Microelectronics Journal 45 (2014) 59–70

Contents lists available at ScienceDirect

Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

Memristor-based combinational circuits: A design methodology

for encoders/decoders
Ioannis Vourkas, Georgios Ch. Sirakoulis n
Laboratory of Electronics, Department of Electrical and Computer Engineering, Democritus University of Thrace, Panepistimioupoli, Kimmeria, Building B,
Room 122, GR-671 00 Xanthi, Greece

art ic l e i nf o a b s t r a c t

Article history: The crossbar architecture is viewed as the most likely path towards novel nanotechnologies which are
Received 15 May 2013 expected to continue the technological revolution. Memristor-based crossbars for integrating memory
Received in revised form units have received considerable attention, though little work has been done concerning the imple-
30 September 2013
mentation of logic. In this work we focus on memristor-based complex combinational circuits.
Accepted 7 October 2013
Particularly, we present a design methodology for encoder and decoder circuits. Digital encoders are
Available online 20 November 2013
found in a variety of electronics multi-input combinational circuits (e.g. keyboards) nowadays, converting
Keywords: the logic level ‘1’ data at their inputs into an equivalent binary code at the output. Their counterparts,
Crossbar digital decoders, constitute critical components for nanoelectronics, mainly in peripheral/interface
Decoding
circuitry of nanoelectronic circuits and memory structures. The proposed methodology follows a
Encoding
CMOS-like design scheme which can be used for the efficient design and mapping of any 2n
n
Memristors
Nanoelectronics (n
2n) encoder (decoder) onto the memristor-based crossbar geometry. For their implementation, a
hybrid nano/CMOS crossbar type with memristive cross-point structures and available transistors is
elaborated, which is a promising solution to the interference between neighboring cross-point devices
during access operation. Circuit functionality of the presented encoder/decoder circuits is exhibited with
simulations conducted using a simulator environment which incorporates a versatile memristor device
model. The proposed design and implementation paradigm constitutes a step towards novel computa-
tional architectures exploiting memristor-based logic circuits, and facilitating the design and integration
of memristor-based encoder/decoder circuits with nanoelectronics applications of the near future.
& 2013 Elsevier Ltd. All rights reserved.

1. Introduction Crossbars offer several benefits including a regular pattern, which

Moving beyond today's silicon integrated chip technology
requires shrinking circuits to the scale of a few nanometers, while
novel devices and architectures will also likely be needed to satisfy
the growing demands for high performance memory and logic
applications. Programmable crossbar circuits [1] constitute a key
architecture proposed for integrated nanoscale electronics. A cross-
bar comprises two parallel planes separated by a thin chemical
layer [2]. Each plane contains a set of parallel and uniformly-spaced
nanowires which are perpendicular to wires in the other. The region
where two wires cross is a junction which may either be configured
as an electronic device or left unconfigured, so that the two crossing
wires do not interact electrically. Configuration of an individual
junction may be done electrically by placing different voltages on
the horizontal and vertical nanowires that define the junction.
n
Corresponding author. Tel.: þ 30 254 10 795 47; fax: þ 30 25 410 795 40.
E-mail addresses: ivourkas@ee.duth.gr (I. Vourkas),
gsirak@ee.duth.gr (G.Ch. Sirakoulis).
makes manufacturing relatively straightforward, flexibility of being
built using a wide range of substances and processes, good defect-
tolerance and the highest possible device density [1–3].
Recently, there have been many alternatives proposed for
implementing the cross-point devices in the crossbar. One such
alternative is the memristor which is based on a theoretical device
formulated by Chua [4]. The first “modern” practical implementa-
tion of this device was realized and demonstrated by the Hewlett–
Packard Laboratories [5]. Their version of the Titanium Dioxide
(TiO2) substrate memristor is the most generally recognized
memristor type. In this work, besides their nonlinear and analog
nature [6], we exploit the memristors as two-state switches rather
than analog devices, without loss of generality. These unique
devices may allow for new nanoelectronic architectures providing
nonvolatile, dense, fast, and power-efficient electronic applica-
tions, including memory [7–9], synaptic computing [10,11], phase
shift oscillators [12,13] as well as logic [14,15], though memristor-
based logic circuits have not received much attention up to now.
In the present work we focus on the design of complex
memristor-based combinational logic circuits. We particularly

0026-2692/$ - see front matter & 2013 Elsevier Ltd. All rights reserved.
http://dx.doi.org/10.1016/j.mejo.2013.10.001
60 I. Vourkas, G.Ch. Sirakoulis / Microelectronics Journal 45 (2014) 59–70
present a design and implementation methodology for the effi-
cient mapping of digital encoders/decoders onto the crossbar
architecture. A digital encoder is a multi-input combinational logic
circuit that converts the logic level ‘1’ data at its inputs into an
equivalent binary code at its output. Encoders can be used to
reduce the number of wires needed in a particular circuit or in
applications that have multiple inputs. Their complementary
circuits, namely digital decoders, constitute critical components
for nanoelectronics [16]. They are especially suitable for nanoscale
crossbars because they allow a small number of conventional
microscale CMOS wires to control a large number of nanoscale
wires and devices. Thus, they result in a robust interface to the
nanocircuitry which provides significant protection from manu-
facturing mistakes [17]. Another important target application for a
decoder circuit is as a subsystem in nanoscale crossbar memory
systems [18]. It is shown here that any 2n
n (n
2n) encoder
(decoder) circuit can be efficiently implemented using a hybrid
nano/CMOS crossbar, where the cross-point devices are consid-
ered to be configurable memristors, accompanied by auxiliary
CMOS switches which facilitate better device access operation. The
methodology presented here employs a CMOS-like design scheme
[19] which uses the programmable resistance of memristors for
the computation of logic functions with voltage as the state
variable and, unlike other logic methods (such as stateful logic),
the computational process comprises only a single step. Charac-
teristic examples of memristor-based digital encoder and decoder
circuits, implemented under the proposed design method, are
presented, and their functionality is exhibited with simulations
conducted with a simulator environment which we developed
using the Java programming language [20]. This simulation tool
incorporates a versatile memristor device model [21] and supports
the design of memristor-based circuits on nanoscale crossbar
structures. The demonstrated simulation results confirm the
efficiency and the fine application of the proposed methodology.
This work contributes to memristor-based combinational logic
circuit design and motivates for further research on new design
strategies that comply with emerging technologies and with the
oncoming scale-down of the electronic circuits. The presented
methodology, exploiting the favorable performance merits of
memristors, concerning their non-volatility, switching speed, area
and energy dissipation [22,23], could be a promising candidate to
be used in future electronic systems design.
2. The memristor: basic properties and device modeling
There had been experimental clues to the memristor's exis-
tence all along the last two centuries. Scientists have been
publishing in the literature experimental results with “strange”
voltage characteristics, where one sees clearly memristance,
though such a material property had always been shadowed by
other effects that were of primary interest [24]. In the absence of
an application, there was no particular need to seek memristive
behavior anyway. In 1971, nonlinear-circuit-theorist Leon Chua
predicted that there should be a fourth element: the memristor
(concatenation of “memory resistor”), joining the resistor, the
capacitor, and the inductor [4]. Such a device would provide a
relationship between flux linkage and charge, likewise a resistor
gives between voltage and current, exhibiting its unique proper-
ties primarily at the nanoscale. A few years later, Chua and Kang
[25] introduced to the scientific community the generic properties
of a broad generalization of the memristor to an interesting class
of nonlinear dynamical devices called memristive devices. The
reason why memristors are substantially different from the other
fundamental circuit elements is that, when you turn off the
voltage to the circuit, they still remember how much voltage
was applied before and for how long; thus presenting a memory of
their past. That is an effect that can not be duplicated by any circuit
combination of resistors, capacitors, and inductors, which qualifies
the memristor as a fundamental circuit element. Currently, there is
a growing variety of systems that exhibit memristive behavior, as
academia and industry keep on with their research and prototyp-
ing [26]. Among them, molecular and ionic thin film memristive
systems primarily rely on different material properties of thin film
atomic lattices that exhibit hysteresis under the application of
charge. In experimentally realizable systems, memristive devices
with threshold voltages seem to be the norm rather than the
exception, and electronic conduction is in most cases dominated
by an effective tunneling barrier-width that varies with the
applied voltage.
Although there has been no direct connection between a model
and the physical properties of memristor yet, many scientists are
working towards the formulation of appropriate descriptive mod-
els [27–31] that will lead to better understanding of its behavior
and will facilitate simulation and incorporation of memristors in
electronics system design. In our previous work [21] we developed
a novel memristor device model which explains the device's
memristive behavior primarily attributing the switching effect to
an effective tunneling distance modulation. In specific, it is a
threshold-type switching model of a two-terminal voltage-con-
trolled electrical device that exhibits memristive behavior, and its
general definition is given by the following relations:
IðtÞ ¼ GðL; tÞV M ðtÞ ð1Þ
L_ ¼ f ðV M ; tÞ: ð2Þ
where L defines the tunnel barrier width and also the state
variable of the system, indicating the internal memristor state. G
is the conductance of the device and parameters I and VM
represent current and applied voltage, respectively. This model is
based on the assumption that the switching rate of L is small (fast)
below (above) a threshold voltage (VSET or VRESET), which is viewed
as the minimum energy required to impose a change on the
physical structure of the device. It also allows for assuming
asymmetric threshold voltages to be applied to the SET and RESET
operations, i.e. |VSET| a|VRESET|, which implies the existence of
different tunneling distance change rates. Such behavior can be
attributed to the interaction of the external applied field, the
internal field of the concentrated defects (e.g. mobile ions, vacan-
cies, etc.), and the diffusion, all acting in the same or in the
opposite directions according to the applied voltage bias [5,32].
The time derivative of the state variable in (2) is interpreted as the
speed of movement of the tunnel barrier due to the applied
voltage, and function f captures the highly nonlinear response of
the memristor. The simulation results from the response of a
single memristor under ac voltage bias according to the used
model are illustrated in Fig. 1. Model parameter values are used as
given in {a, b, c, m, fo, Lo, VSET, VRESET}¼ {5
106, 0, 0.1, 82, 310, 5,
3 V,  1.5 V} and the resulting resistance ratio is β¼ ROFF/RON E102
with ROFF E200 kΩ and RON E2 kΩ.We note here that when {a, b}
40 then a positive (negative) voltage applied to the top terminal
with respect to the bottom terminal, denoted by the black thick
line, always tends to increase (decrease) the memristance. How-
ever, setting b equal to zero imposes no state change in the
memristor unless a certain voltage threshold is exceeded. It has
been demonstrated that the model represents well the complex
switching behavior of memristor, exhibiting I–V responses quanti-
tatively consistent with other widely used published models.
Hence it can be used to provide accurate enough circuit simula-
tions for a wide range of memristor devices and voltage inputs.
 I. Vourkas, G.Ch. Sirakoulis / Microelectronics Journal 45 (2014) 59–70 61

Fig. 1. Simulation results from the response of the memristor model [21] to a triangular ac applied voltage, showed in (a). The hysteretic current–voltage (I–V) characteristic
of a device with (VRESET, VSET) ¼(  1.5V, 3 V) is demonstrated in (b) and the corresponding change of the resistance (memristance) with time and with the applied voltage is
shown in (c) and (d), respectively. Threshold values are highlighted using red dotted-lines in (a) and (d) to facilitate comprehension of the response of the device to the
applied voltage. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)

3. Memristor-based combinational logic circuit design

In this Section we describe a design strategy for memristor-

based combinational logic circuits which is based on well-known
logic design principles from the CMOS Very Large Scale Integration
(VLSI) technology. Work on memristive logic has so far focused on
stateful logic [12], where Boolean functions are computed using
material implication and reset operations. A major disadvantage of
the memristive implication logic is the necessity to perform
lengthy sequences of stateful logic operations in order to synthe-
size a given Boolean function. Unlike stateful logic, the computa-
tional process here comprises only a single step, and the logical
state is represented as a voltage, even though resistance is nor-
mally used to represent the logical state of individual memristors.
The computational result is independent of the initial state of the
memristor devices which are utilized only for logic computation
and not for storing a logical state.
According to the CMOS VLSI circuit design theory, for every logic Fig. 2. Conventional CMOS circuit design method compared to a CMOS-like
function F(x) implementation there is a specific formation for the nanoscale design concept comprising appropriately polarized memristor devices.

employed Field Effect Transistors (FETs) in the circuit. Fig. 2 gen-

erally shows how appropriately polarized memristors can be used
to replace existing FETs, maintaining the well understood CMOS
design methodology and resulting in the same circuit functionality;
i.e. delivering complementary digital logic comprising two-state
switching devices. In conventional CMOS the word “complemen-
tary” refers to the fact that the typical digital design style uses
complementary and symmetrical pairs of p-type and n-type FETs for
the implementation of logic functions. In the proposed memristor-
based design scheme the word “complementary” similarly implies
the use of complementary and symmetrical pairs of memristors;
only in this case complementation refers to the use of the same kind
of devices but with opposite polarization. Consequently, assuming
that memristors work as two-state switches, the overall circuit
functionality remains similar to that of the CMOS-based logic
circuits. More specifically, forward polarized memristors (FPMs)
are used in the n-MOS area and reversely polarized memristors
(RPMs) in the p-MOS area. The RPMs, corresponding to p-type FETs,
are initially found in the ROFF state. Thus a negative applied voltage
62 I. Vourkas, G.Ch. Sirakoulis / Microelectronics Journal 45 (2014) 59–70

changes their state from ROFF to RON, i.e. closes the switch, likewise
happens with p-type FETs. On the contrary, a positive voltage pulse
either restores their state from RON to ROFF or leaves them
unchanged in ROFF, i.e. the switch is opened. As far as FPMs are
concerned, which correspond to n-type FETs, they are initially found
in the RON state. So, a negative applied voltage changes their state
from RON to ROFF, though a positive voltage pulse either restores
their state from ROFF to RON or leaves them unchanged in RON. In
other words, positive (negative) voltage turns the switch on (off),
just as n-type FETs work. The input logic signals are represented
using positive voltage for logic ‘1’ and negative voltage for logic ‘0’.
Similar to the standard combinatorial logic using CMOS, the
implemented logical function is determined every time by the
topology of the circuit, which consequently consists of an equivalent
ohmic resistance for the upper and another one for the lower part of
the CMOS-like design. Therefore the output voltage VOUT is always a
fraction of the supply voltage VDD, being dependent on the voltage
divider across the two parts of the memristor-based circuit, with
voltage values close to VDD corresponding to logic ‘1’ and values
close to zero (Gnd) corresponding to logic ‘0’. The delay of the logic
operations is the time required for the memristors to be fully
switched. The delay time is also dependent on the applied voltage
level. A relatively low voltage level increases the delay time and it is
possible that a memristor does not switch completely, since the
input voltage is not applied for sufficient time or it is too low. In
such a case different output voltage levels might occur, making
difficult to distinguish between them. Therefore, in order to
guarantee a stable and correct operation, appropriate programming
and reading voltage pulses need to be selected based on the
switching characteristics of individual devices.
It should be mentioned that throughout this work the mem-
ristors, which directly replace FETs, are deliberately considered as
three-terminal devices within logic circuits for representation
purposes. In fact, each input wire in the memristor-based circuit
design corresponds to the set of crossbar nanowires which form
the junction where the specific memristor is located. Thus, apply-
ing an input signal to a horizontal input circuit line corresponds to
the application of an appropriate voltage (positive or negative) to
the aforementioned crossbar nanowires which will affect the
internal state of the target memristor. In the following Section
we describe analytically what a three-terminal memristor device
stands for and also how memristor-based combinational circuits,
designed under the CMOS-like paradigm, can be appropriately
mapped onto the crossbar geometry.
or the memristor array was integrated directly on top of underlying
CMOS circuitry [37].
In the present work, in addition to the presented circuit design
strategy, we investigate possible implementation architectures for
the presented logic circuits, elaborating the hybrid transistor–
memristor crossbar type. First of all, the geometry of the mem-
ristor-based combinational circuits should be appropriately altered
in order for them to better fit in an array-like structure, like the
crossbar. Extending the logic circuit design concept proposed in
[19], here FPMs and RPMs (instead of FETs) that receive the same
input signal are placed in the same horizontal line and the circuit
output is always taken from the lower part of the circuit. In Fig. 3a
the CMOS-like memristive circuit which implements a 2-input
NAND universal logic gate is presented in detail in order to
underline the fundamental properties of the proposed design
paradigm. The circuit consists of both memristors (crossbar plane)
and auxiliary FETs (CMOS plane) which are driven by appropriate
selection lines. The CMOS switches not only remove the current
sneak-paths, but also facilitate correct access operation to multiple
memristors receiving the same input voltage bias. In this particular
circuit there are four switches, named M1–M4, which determine
the logic gate function providing the option for either application
of input (i.e. programming) signals which affect the internal state
of memristors, or for reading the circuit output with VDD and Gnd
voltages, or for idle operation, where all switches are set to
floating position. The duration and amplitude of the input voltage
pulses, here denoted as 7Vo, should be selected according to the

4. Hybrid memristor–transistor nano/CMOS crossbar

Several researchers have reported on memristive circuits with a

simple cross-point type array based on various materials, including
binary metal oxides [22,23,33]. However, such circuits suffer from
leakage current paths, generally referred as the sneak-path problem
[34]. Hybrid crossbars with different cross-point devices, like the
transistor–memristor (1T–1M) combination, have been proposed as
a possible solution. This approach comprises a memristor device
connected with a select transistor in series in every cross-point. The
select transistor controls the location of the switching element to be
accessed, ensuring reliable circuit operation. Yakopcic et al. [35]
describe a 1T–1M circuit structure designed so that each of the
memristors could be accessed individually without disrupting other
devices, whereas Kim et al. [36] employ a 1T–1M structure to Fig. 3. (a) Analytical example of a circuit implementation of a two-input NAND
describe the development of a resistive random access memory logic gate, based on the CMOS-like design paradigm, illustrated in detail to facilitate
(ReRAM). Word, bit, and source lines for random access operation, better understanding of the sequence of the applied voltages. Appropriate switches
are used to demonstrate that reading the output or applying input signals (here A
i.e. three signal lines, are necessary to properly access the cross- and B) is done with application of the corresponding voltages. (b) A summary of all
point devices. In such implementations, the switching devices were appropriate voltages (switch positions) needed to be applied to the corresponding
either integrated along with memristors on the same substrate [36], devices during all possible circuit operation phases.
 I. Vourkas, G.Ch. Sirakoulis / Microelectronics Journal 45 (2014) 59–70
switching response of individual memristors, so as to exceed the
VSET and VRESET threshold values and thus cause the device
memristance to completely switch in either direction (i.e. from
OFF to ON and vice versa). However, the VDD amplitude should be
appropriately selected so that the corresponding voltage drop
never exceeds the threshold voltages of any of the invoked
memristors. In this way the internal state of memristors remains
unaffected during read-out regardless of the current flow from VDD
to Gnd. Moreover, with their memory function being nonvolatile,
memristors do not require power to refresh their states, even if the
chip power is turned off, i.e. when set in idle operation.
Generally, in a complementary logic circuit whose output is
described by a logic function which involves a particular input
signal, this signal will apply to at least a pair of anti-parallel
oriented memristors. The exact number of FPMs and RPMs cannot
be formerly defined because a specific logic function has many
different CMOS-like implementations. Regarding the aforemen-
tioned logic circuit, in Fig. 3b we provide information relative to
the positions of the switches and the logic values applied to the
selection transistors for every possible circuit operation phase.
Additionally, in order to facilitate understanding of the applied
voltage sequence, which ensures no main leakage paths in such
memristor-based logic circuits, we also provide in Fig. 4 a flow
chart where all operation details of the proposed memristive logic
circuits are summarized. With the appropriate driving circuit
(which is beyond the scope of this paper), VDD and Gnd voltages
are supposed to be applied only in order to read the circuit output.
In the circuit snapshot of Fig. 3a, the actual demonstrated positions
of the switches are chosen so that the input signal B can be applied
to the lower pair of devices, by simultaneously driving appro-
priately the line-selection signals. Furthermore, it can be seen that
Fig. 4. A flow chart explaining the applied signal sequence and all operation details
of the proposed memristive logic circuits.
63
the total number of access transistors is smaller than the number
of used memristors. Having one transistor for each memristive
device results redundant in the proposed circuit architecture;
indeed, in all circuit branches the devices immediately connected
to the output line can be accessed using a single transistor, thus
the total circuit area is smaller than when using a full 1T–1M type
crossbar. This explains the notation e.g. Sel(AþB) which refers to a
transistor used for both signals A and B. In this approach, for a
single input signal change each time, e.g. for an input sequence
from (A, B) ¼(0, 1) to (A, B)¼ (1, 1), the circuit output is updated in
only a single step, whereas for multiple simultaneous signal
changes the output response delay is multiplied by the number
of the changed input signals. Pulsing details provided in Fig. 3b
infer that no more than one input voltage can be applied at the
same time, unless more switching access elements are introduced
in the vertical lines to isolate the groups of devices found in
different horizontal lines; this practically is an extension of the
above implementation method.
Therefore, the necessary transistors need not be at every cross-
point of the array but can be found alternatively in the CMOS
driving circuitry domain. The development of the presented
hybrid transistor–memristor crossbar architecture adds no signifi-
cant complexity to similar architectures found in the literature and
it is feasible with today's fabrication technologies. Likewise in [36],
there is the option of integrating the driving CMOS components on
the same substrate with memristor crossbars. On the other hand,
memristors could be fabricated directly above the CMOS plane
with an array of vias providing electrical connectivity between the
CMOS and the memristor layer. Various hybrid nanocrossbar
/CMOS architectures have been proposed in which the function-
ality of memristive switches is compensated by the CMOS com-
ponents, thus exhibiting beneficial characteristics without creating
any area overhead [37–39]. The visualization of the aforemen-
tioned implementation concepts is shown for clarity in Fig. 5.
Hereinafter, for readability reasons we sometimes omit the
supplementary transistors, using the compact three-terminal rep-
resentation in the presented memristor-based combinational
circuits implementing digital encoders and decoders. Based on the
previous detailed description, the overall concept regarding the
physical implementation of the three-terminal devices is summar-
ized in Fig. 6. It is shown that the extra terminal of each memristor,
where the input signal is normally shown to be applied, is always
the gate terminal of an available access transistor used to appro-
priately interact with it, without necessarily inferring 1T–1M corres-
pondence.
5. Digital encoder/decoder circuit design
In this Section we adopt the CMOS-like design paradigm to
describe the particular design of programmable and scalable
memristor-based digital encoder/decoder circuits, built on recon-
figurable, hybrid nano/CMOS crossbar arrays that incorporate
memristive cross-points and auxiliary access transistors. In order
to define the location and orientation of the programmable
memristors following the CMOS-like design [19], we defined a
logic tile consisting of interconnected two-dimensional arrays
which comprise configurable memristive nodes and supporting
routing junctions that facilitate the propagation of internal signals
to the outside of the tile. The redundant data paths of the crossbar
structure, as illustrated in Fig. 5, enable alternate routes through
the interconnections, resulting this way in highly defect-tolerant
circuits. Each memristive logic circuit may be presented with
two wires for each input (whenever necessary), i.e. one wire
representing the input value and the other its complement. The
64 I. Vourkas, G.Ch. Sirakoulis / Microelectronics Journal 45 (2014) 59–70
Fig. 5. Visualization of the implementation concept for the proposed hybrid transistor–memristor crossbar architecture. Schematic (a) shows how memristors could be
fabricated directly above the CMOS plane with an array of vias providing electrical connectivity between the CMOS and the memristor layer. On the other hand, the driving
CMOS components could be integrated on the same substrate with memristor crossbars, as illustrated in (b).
Fig. 6. The physical implementation of the three-terminal devices, which were
deliberately chosen to represent two-terminal memristors here. In fact, the third
terminal is the gate terminal of an available access transistor, used to form the
memristor–transistor pairs, which is always driven by appropriate selection lines.
complemented signals are always considered to be readily pro-
duced by external circuitry connected to the crossbar.
The presented methodology comprises a few straightforward
steps for the circuit designer to follow, ranging from the circuit's
definition to its final mapping and implementation on a hybrid
crossbar structure. The steps are as follows:
(1) Define the encoder/decoder circuit's inputs and outputs and
assign a logic variable to each of them.
(2) Extract the corresponding logic functions for each encoder/
decoder circuit output, according to the truth table.
(3) For each one of the extracted logic functions, e.g. Fi(x), find its
complement F ′i ðxÞ and the expression Fi(x').
(4) Design the encoder/decoder circuit according to the paradigm
summarized in Fig. 1. For sum-of-products function represen-
tations, each product term is implemented with a single
vertical chain of memristors and the final sum is created by
wired-ORing the existing products.
(5) Map the designed circuit on the hybrid crossbar structure by
selective configuration of the cross-point junctions.
The listed steps form a complete methodology which should
provide the circuit designer with the ability to efficiently design
and implement memristor-based digital encoder/decoder circuits
on hybrid nano/CMOS crossbar architectures, comprising memris-
tive cross-points and also auxiliar CMOS switches in the periph-
eral/driving circuitry.
5.1. Digital encoder
Encoders are commonly used multi-input combinational cir-
cuits which produce an encoded output according to the signals in
their input lines. Generally, an n-bit digital encoder has 2n input
lines and n output lines. The output lines generate the binary
equivalent of the input line whose value is at the moment set to
logic ‘1’. In order to describe the circuit, every output is first
represented by a logic function of the input variables. Then, each
function can be implemented with memristors by decomposing it
into two sets of minterms, i.e. one set for the RPMs and another for
the FPMs, and by selective configuration of junctions in the
crossbar structure.
Fig. 7 summarizes the proposed methodology for the design of
a particular digital encoder. More specifically, in Fig. 7a the first
methodical steps are included. The block diagram of a 4
2 digital
encoder is shown, where inputs and outputs are assigned a
variable name, and also the output functions are extracted. The
input variables are defined as X0, X1, X2, and X3, whereas the
output variables are F1 and F0, respectively. The circuit's truth table
in Fig. 7b includes all of the four cases which guarantee a correct
input to the circuit, except for the case when all inputs are set to
logic ‘0’. In this case both outputs are left at logic ‘0’, which is the
same with the case of having the input X0 set to logic ‘1’. The truth
table is used to extract the logic functions for each one of the
circuit's outputs. The extracted logic expressions F ′i ðxÞ and F i ðx′Þ
are coincidentally both functions of only the complement input
variables. Thus, only the complement input signals appear in the
circuit design presented in Fig. 7c, where the RPMs and FPMs are
found in the upper (or left) and lower (or right) part of the
compact (analytical) circuit, respectively. The aforementioned
extracted logic expressions, in their most compact form, coinci-
dentally do not include the variable X0 since it does not affect the
circuit output. This is why in this case the corresponding input
signal is omitted in the circuit design. In this particular circuit
schematic, both the compact and the analytical circuit versions are
presented. Memristors receiving the same input signal are colored
correspondingly and the connection lines are similarly colored in
order to facilitate visual correspondence with the circuit definition
in the interface of the developed simulation tool, demonstrated
later in Fig. 9a. In this specific circuit snapshot, the actual positions
of the switches allow interaction with the blue colored devices,
associated with input signal X ′2 . Following the same methodology,
 I. Vourkas, G.Ch. Sirakoulis / Microelectronics Journal 45 (2014) 59–70
Fig. 7. (a) Block diagram of a 4
2 encoder, (b) its truth table, and (c) the corresponding compact and analytical CMOS-like circuit design with appropriately polarized
memristors instead of FETs. Devices associated with the same input signals are colored correspondingly.
any 2n
n digital encoder circuit can be designed and implemen-
ted in hybrid transistor–memristor based crossbar architectures.
5.2. Digital decoder
Decoders constitute circuits which activate only one of their
outputs by presenting logic ‘1’ to the corresponding wire, accord-
ing to the input combination. A circuit with n inputs normally has
2n outputs, i.e. one for every possible input set, and each one of
them can be described by a logic function representation of the
input variables.
Fig. 8 also summarizes the proposed methodology, though this
time for the design of a particular memristor-based digital
decoder. The block diagram of a 2
4 decoder, along with its
truth table and the particular circuit diagram are shown. Only the
compact circuit schematic is demonstrated here since the more
analytic version follows by analogy from the previously presented
examples. Both devices and connection lines are colored accord-
ingly to comply with the schematic of Fig. 10a. There are two
circuit inputs, defined as X and Y, and four output logic functions
representing the four minterms composed of the input variables,
denoted as m0, m1, m2 and m3, respectively. Each function Fi(X, Y) is
found according to the truth table and is then used in order to find
its complement F ′i (X, Y), and the expression Fi(X′, Y′) derived by
replacing all variables in the initial function with their comple-
ments. The circuit is then designed according to the CMOS-like
paradigm, with reversely and forward-polarized memristor
devices. Following the proposed methodic design strategy, any
n
2n memristor-based digital decoder circuit can be designed
and implemented on a hybrid crossbar array.
6. Simulation results
In this Section we demonstrate functionality of the presented
circuits providing the results from the simulations conducted with
a simulation environment that we built using the Java program-
ming language [20], and which utilizes the memristor device
model [21] summarized earlier in Section 2. The simulator
65
incorporates a user friendly interface which facilitates the creation
of logic computations with memristor-based circuits on hybrid
array-like nano/CMOS architectures.
The software interface comprises nanowires which are distrib-
uted into different quadrants of adjustable dimensions to facilitate
the design and simulation of rather complex circuits. Each quad-
rant is considered to possess different electrical properties due to
the chemical properties of the interlayer used in that region. The
array representation which is found in the simulator's interface is
illustrated in Figs. 9 and 10a as well, where configured junctions
determine the implementation of a 4
2 binary encoder and a
2
4 decoder, respectively. All of the remaining available junctions
are maintained unconfigured. For readability reasons we choose to
simulate the relatively small circuits which were presented earlier
in this work, though larger circuits can be designed and simulated
as well by the simulation environment. Particularly, in order to
accommodate the definition of the proposed circuit geometry, the
logic tile consists of quadrants with configurable routing switches
(the lower gray colored ones) and others where a junction can be
configured to be either an RPM (upper left pink quadrants) or an
FPM (upper right blue quadrants). A particular input signal may be
brought in on any of the horizontal nanowires and it applies to all
of the configured memristors found in the same horizontal line,
whereas VDD and Gnd signals are always taken from the dark gray
quadrants located at the top and are used to determine the circuit
output depending on the internal state of the invoked memristors.
According to the literature, the thickness of the critical oxide film
of memristors located at the cross-points varies between 5 and
30 nm [5,6]. In all conducted simulations we strictly defined in the
memristor model the value margin of the tunnel barrier width to
vary between 1 and 5 nm, which is likely to be observed experi-
mentally. Assuming the previously mentioned set of values assigned
to the model fitting parameters as it was described in Section 2, in
all simulations we consider a ROFF/RON ratio of approximately two
orders of magnitude which is large enough to characterize the
discrete conducting states of the memristors. In order to decide on
the applied pulse properties, we focus on the particular I–V
characteristic of individual memristors and the demonstrated
threshold values, shown in Fig. 1; we thus choose to apply read
66 I. Vourkas, G.Ch. Sirakoulis / Microelectronics Journal 45 (2014) 59–70
Fig. 8. (a) Block diagram of a 2
4 decoder, (b) its truth table, and (c) the corresponding compact CMOS-like circuit design with appropriately polarized memristors instead
of FETs. Devices associated with the same input signals are colored correspondingly.
pulses of VDD ¼1 V and input (write) pulses of Vo ¼ 74 V. VDD
supply is thus kept below the threshold voltages to avoid affecting
the internal state of the memristors while reading the circuit output.
The memristance change of a single memristor induced by an input
pulse with time is shown in Fig. 9b, where it can be noted that the
resistance change is completed after almost 60 μs for the aforemen-
tioned set of parameters values. Appropriate adjustment of the
parameters of the model, depending each time on the character-
istics of the actual device that is being simulated, as well as properly
applied voltage produces faster or slower switching times. In our
simulations the applied input pulses were chosen to be 80 μs-wide
so as to guarantee complete state transition and thus facilitate
better distinction during the read-out phase in the corresponding
graphs demonstrated in Figs. 9c and 10b. A logic ‘0’ (logic ‘1’) input
signal always corresponds to a negative (positive) voltage pulse
applied to the specific set of nanowires which form the target cross-
point junction. Through the user interface, crossbar junctions can be
selectively configured in order to appropriately map circuits com-
prising memristors on the array-like architecture, where the access
transistors are omitted for readability reasons but are considered
present in the respective physical implementation. In order to
access correctly the appropriately polarized memristors in a hor-
izontal line, as discussed in Section 4 in detail, the supplementary
CMOS switches are supposed to be biased in such a way that all
unaddressed memristors are kept unaffected by the input voltages.
Reading pulses are applied here at each simulation step in order to
better demonstrate the changes to the memristor states and,
therefore, to the output of the simulated logic circuits. Using the
developed environment, we have successfully simulated all the
presented memristor-based encoder/decoder circuits.
More specifically, in Fig. 9 the simulation results for a 4
2
digital encoder, designed with memristors on a hybrid nano/CMOS
array-based geometry, are presented. Configuration of the selected
cross-points is demonstrated in Fig. 9a, where colored lines are
used to highlight the separate circuits that implement each of the
output functions in correspondence with the circuit schematics of
Figs. 7 and 8. In the particular horizontal line where the comple-
ment of input signal X0 applies, there are no configured junctions
since this particular variable is not found in the extracted Boolean
functions which describe the circuit outputs. The simulation
begins with the logic combination (X3, X2, X1) ¼(0, 0, 0) (the
inverted signals are only showed in Fig. 9c). These three initial
positive pulses maintain RPMs and FPMs unaffected at ROFF and
RON states, respectively. Therefore, looking back in Fig. 7c, the
equivalent resistance of the upper circuit branches (RPM area)
results ROFF/2 (ROFF||ROFF) whereas for the lower branch (FPM area)
it is only 2
RON (RON þRON). Hence when VDD is applied there is a
much higher voltage drop on the upper resistive part of the circuit
compared to that of the lower part, based on the high enough
resistance ratio ROFF/RON. This is why both F1 and F0 output voltage
levels are very low. However, when a negative pulse is applied to
X ′3 input, the involved memristors change their states from OFF to
ON and vice versa. Then the equivalent resistance of the upper
branches results almost equal to RON (ROFF||RON) and for the lower
branch it is almost equal to ROFF (RON þROFF). As a consequence, the
corresponding voltage drop on the lower part of the voltage
divider is higher this time. Since this particular signal is involved
in both output circuits, both F1 and F0 are found close to VDD, as
expected. Similarly, since signal X ′2 affects only F1 and signal X ′1 is
involved only in F0, respectively, then a particular change in each
 I. Vourkas, G.Ch. Sirakoulis / Microelectronics Journal 45 (2014) 59–70 67

Fig. 9. Simulation results for a 4
2 digital encoder. (a) The corresponding configuration of the simulator's logic tile. Yellow dots are configured junctions and black dots are
unconfigured cross-points. (b) The memristance change of a single memristor induced by an input pulse with time. (c) The output response of F0 (green) and F1 (red), for all
valid input variations of the complement signals X ′3 (red), X ′2 (green) and X ′1 (blue). The applied voltages are appropriately selected to exceed the threshold values VRESET and
VSET. The time gap between the input signal transitions, where the circuit outputs should be read, is highlighted using the vertical dotted-lines. (For interpretation of the
references to color in this figure legend, the reader is referred to the web version of this article.)

of the aforementioned signals induces a corresponding change
only to the output related with it, as can be seen in the circuit
response of Fig. 9c. Each of the input signals is sequentially set to
logic ‘1’ and logic ‘0’ to create all valid input combinations. The
corresponding binary output code can be observed in the deliber-
ately left time gap between consecutive input signal transitions,
which is particularly marked between the vertical black dotted-
lines in the output graphs of Fig. 9. Both outputs are kept at logic
‘0’ when all input signals are also found at logic ‘0’. The threshold
voltage levels, i.e. VRESET and VSET, as well as the VDD level are
denoted with horizontal red dotted-lines to facilitate comprehen-
sion of the circuit response.
Fig. 10 presents the simulation results for a 2
4 digital
decoder designed with memristors. The adjustable size of the
crossbar array can be noticed in the representation shown in
Fig. 10a, which comprises a larger area for the FPMs to accom-
modate the different number of used cross-point devices. Likewise
in Fig. 9, colored lines are used to highlight the corresponding
signals found in the respective graph shown in Fig. 10b. Each signal
transition is always followed by the corresponding change of its
complement. In the output response graphs, attention should be
paid only after the complement of a particular signal completes its
transition, i.e. again within the deliberately marked time gap. The
simulation begins with the logic combination (X, Y)¼(0, 0) and the
consecutive input signal transitions follow a two-bit width Gray-
like code sequence, where only one input signal changes each
time, to finally return to the initial combination. This is done
purposely to demonstrate that the circuit always returns to its
initial state. The notation and the employed colors are the same
with the ones in Fig. 8 to facilitate visual correspondence with the
circuit diagram. It should be noticed that there are periods where
more than one output signals are found at logic ‘1’. Nevertheless,
this takes place only before the complement signals complete
their transition, because transitions of every input signal and its
complement are not simultaneously applied each time to the
respective inputs of the circuit. This is why such cases should
68 I. Vourkas, G.Ch. Sirakoulis / Microelectronics Journal 45 (2014) 59–70

Fig. 10. Simulation results for a 2
4 decoder. (a) The corresponding configuration of the simulator's logic tile. Yellow dots are configured junctions and black dots are
unconfigured cross-points. (b) The output response of F0 (red), F1 (green), F2 (blue) and F3 (magenta) for all possible input variations of the signals X (red) and Y (blue).
The time gap between the input signal transitions, where the circuit outputs should be read, is highlighted using the vertical dotted-lines. (For interpretation of the
references to color in this figure legend, the reader is referred to the web version of this article.)

not be taken into consideration. It can be seen that in each of the
denoted gaps only one of the decoder outputs is found at logic ‘1’
(i.e. high voltage level) whereas the rest of the outputs remain low,
as expected. Regarding the frequency of the input and output
signals, we should mention that there is no particular relation
between them; the input pulse widths are selected based on the
switching characteristics of individual memristors, whereas the
output signal duration depends only on the time when VDD and
Gnd signals are applied.
7. Advantages and important characteristics
Memristors demonstrate a natural basis for computation that is
different from familiar paradigms, and memristor-based logic
opens new opportunities for the exploration of advanced compu-
ter architectures. Maybe the most recognized logic design concept
so far for memristive devices is the stateful logic, which constitu-
tes an unconventional, sequential computation framework. Such
concept is determined by the device properties, more than any
other previously conceived logic architecture, and has been
considered so far mainly at the level of elementary operations,
but not in the context of large circuits. Furthermore, it is not
immediately clear what kind of computing architectures would in
practice benefit the most from the built-in logic computing
capability offered by memristors. The relatively lengthy computa-
tional sequences involved in memristive stateful (implication)
logic require the computing to be as parallel as possible.
To this end, the proposed hybrid underlying architecture can
successfully accommodate the presented logic circuits, and thus it
addresses some manufacturability issues which might be a possible
solution to fitting memristors into nowadays circuits. Although cas-
cadability between separate circuits is not supported, given that
circuit inputs require negative voltage pulses as well, which do not
appear in any circuit output, the suggested CMOS-like circuit
architecture with memristive elements is capable of universal
computation; the design of all fundamental digital logic operations
and thus of any Boolean function is possible. In [40] a multi-input
implication operation was introduced with complementary repre-
sentation of variables, showing that up to 2n 1 þ1 computational
steps were required for the synthesis of an n-input Boolean function
in stateful logic circuits. Compared to stateful logic, our complemen-
tary logic approach is also sequential but achieves a significant
reduction in the computation steps needed. In specific, the computa-
tion steps equal the number of the circuit's input signals plus (if
needed) the number of their complementary version, thus reaching a
maximum of 2n for an n-input arbitrary Boolean function, given that
the input's complements are considered readily available. In this way,
a significant reduction in computation steps is achieved. In terms of
circuit area, the exact number of memristors cannot be formerly
defined because a specific logic function has many different imple-
mentations. Particularly, for the set of universal logic gates {NAND,
NOR, NOT} the number of memristors is {4, 4, 2} [21], thus the
proposed design scheme proves slightly more costly than stateful
logic; e.g. 3 devices were used for a 2-input NAND operation in [12].
However, it significantly simplifies the circuit design procedure
because the same design principles from CMOS VLSI are applied.
 I. Vourkas, G.Ch. Sirakoulis / Microelectronics Journal 45 (2014) 59–70
Moreover, unlike other circuit design technologies where simulta-
neous application of all input signals is necessary, in memristor-
based logic we do not consider parallel processing of input signals.
This is because each time a particular input signal is applied to a
group of memristors, these specific devices need to be isolated using
proper voltages at their terminals and at the respective selection
lines as well. However, parallel processing of input signals is not
essential for the overall function of the presented circuits; read-
ing the circuit output only implies the application of VDD and Gnd
voltages without the need of interaction with the memristors.
During operation of the presented logic circuits, the current
flowing directly to the ground depends on the individual memristor
characteristics (RON, ROFF) and the voltage used to read the circuits
output (VDD). According to the device characteristics mentioned in
the literature [26], [41], we believe that flowing current might be in
the range of a few nA, which is nowadays comparable to SOI CMOS
leakage current levels. The actual performance of such a logic-in-
crossbar array paradigm, especially in terms of processing speed
and energy consumption, will strongly depend on device material
selection and operation schemes. The devices themselves are
capable of fast (nanoseconds) and low-energy (picojoules) switch-
ing. The delay of the logic gates is the time required for the
memristive devices to be fully switched. The time required to
change the state of a memristor which is directly connected to a
voltage source, i.e. (write) from ‘0’ to ‘1’ and ‘1’ to ‘0’, was previously
derived in [8] and it was found that it depends on the voltage drop
across the memristor and its physical parameters. Higher voltage
pulses switch the junction much more quickly, thus reducing
switching energy. The power consumed during logic operations is
dependent on the resistance of all memristive devices involved in
the computational process. Certainly, real switching times as given
by exhaustive lab experiments [42] reach o10 ns and thus make
resistance switching devices competitive to currently available
devices. A sub-nanosecond switching of tantalum oxide memristive
devices [43] provides at the moment the best estimate for the
duration of logic computations.
Regarding the performance of the presented logic circuits in
terms of other basic circuit properties like area and operation
speed, it should be noted that the size of a typical memristor is
relatively small; hence memristor-based circuits may be smaller
than circuits comprising only CMOS transistors. Integrating mem-
ristors and CMOS devices for performing logical operations may
prove beneficial since memristors can be fabricated within the
metal layers, thus the integration saves physical area and therefore
the possible logic density increases. Consequently, in terms of area
and speed, memristor-based combinational circuits can be proved
to be very competitive, even though memristor circuit technology
is still at an early stage, also exhibiting comparable power
consumption with conventional circuit technologies. Such char-
acteristics qualify memristor as a promising candidate to be used
in future electronic systems' design.
8. Conclusions
This work focuses on memristor-based combinational logic
circuits, particularly presenting a design methodology for digital
encoder and decoder circuits. Encoders are commonly used in
nowadays electronic devices and decoders are especially impor-
tant for nanocircuitry mainly concerning memory systems. Fol-
lowing a simple yet effective circuit design methodology,
consistent with CMOS-based design, we showed how any 2n
n
(n
2n) digital encoder (decoder) circuit can be successfully
designed using appropriately polarized memristors. Additionally,
we investigated in suitable hardware implementations and pro-
posed an elaborated memristor-based hybrid nano/CMOS crossbar
69
structure, where the presented memristive combinational circuits
can be effectively mapped. We proved the fine application of the
design methodology by exhibiting circuit functionality with simu-
lations of encoder/decoder circuits, conducted with a simulation
tool which incorporates a versatile memristor device model and
facilitates the creation of logic computations with the use of
memristor-based circuits. This work constitutes a step forward,
towards novel emerging technologies which are expected to
dominate the electronic industry in the near future. This new
straightforward design methodology for memristor-based com-
plex combinational circuits offers considerable flexibility to system
architects, in order to carry out the challenging task of integrating
completely all-in-one memory and logic systems on novel nanoe-
lectronic architectures. Accurate SPICE simulations will be part of
our future work on the development of memristive applications
and particularly on the logic circuit design.
Acknowledgment
This work was supported in part by a scholarship from the
BODOSSAKI Foundation in Greece.
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