c.

2)

library ieee; architecture EBLM of comparador is

use ieee.std_logic_1164.all;
entity comparador is
port (A,B: IN std_logic_vector(3 downto 0);
Amay,Bmay,eq: out std_logic);
end comparador;
begin
Amay<='1' when A>B else '0';
Bmay<='1' when B>A else '0';
eq<='1' when A=B else '0';
end EBLM;

QUARTUS

ISE

WINCUPL
d.1)

VHDL

library ieee; P(0)<= B(2) XOR A(2) XOR A(1) XOR A(0);
use ieee.std_logic_1164.all; P(1)<= B(1) XOR A(3) XOR A(1) XOR A(0);
entity comparador is P(2)<= B(0) XOR A(3) XOR A(2) XOR A(0);
port (A: IN std_logic_vector(3 downto 0);
C: out std_logic_vector(6 downto C(0) <= '1' WHEN P="001" ELSE '0';
0)); C(1) <= '1' WHEN P="010" ELSE '0';
end comparador; C(2) <= '1' WHEN P="011" ELSE '0';
architecture EBLM of comparador is C(3) <= '1' WHEN P="100" ELSE '0';
signal B:std_logic_vector(2 downto 0); C(4) <= '1' WHEN P="101" ELSE '0';
signal P:std_logic_vector(2 downto 0); C(5) <= '1' WHEN P="110" ELSE '0';
begin C(6) <= '1' WHEN P="111" ELSE '0';

B(2)<= A(2) XOR A(1) XOR A(0);

B(1)<= A(3) XOR A(1) XOR A(0); end EBLM;
B(0)<= A(3) XOR A(2) XOR A(0);

QUARTUS (El detector de bits con error no reconoció ningún error en los bits del 1 al 7)

ISE
WINCUPL

e) DECODIFICADOR 5211 A BCDN Y 631-1 A BCDN

VHDL

library ieee; "0111" when "1011",

use ieee.std_logic_1164.all; "1000" when "1110",
entity comparador is "1001" when "1111",
port (A,B: IN std_logic_vector(3 downto 0); "0000" when others;
F,G: out std_logic_vector(3 downto with B select
0)); G<= "0000" when "0000",
end comparador; "0001" when "0010",
architecture EBLM of comparador is "0010" when "0101",
begin "0011" when "0100",
with A select "0100" when "0110",
F<= "0000" when "0000", "0101" when "1001",
"0001" when "0001", "0110" when "1011",
"0010" when "0100", "0111" when "1010",
"0011" when "0101", "1000" when "1101",
"0100" when "0111", "1001" when "1111",
"0101" when "1000", "0000" when others;
"0110" when "1010", end EBLM;
QUARTUS
ISE