AEC Manual 17ECL37-1 PDF

DON BOSCO INSTITUTE OF TECHNOLOGY
Kumbalagodu, Mysore Road, Bangalore - 560 074
DEPARTMENT OF
ELECTRONICS & COMMUNICATION ENGINEERING
(ACADEMIC YEAR 2018-19)
LABORATORY MANUAL
SUBJECT:
ANALOG ELECTRONIC CIRCUITS LAB
SUB CODE: 17ECL37 SEMESTER: III

[As per Choice Based Credit System (CBCS) scheme]
WAYANAMAC EDUCATION TRUST
VISION
Don Bosco group of institutions shines brighter each day with a vision to achieve
a world class status in providing exceptionally excellent higher education in the
field of Management, Technology and Applied Sciences entrenched with Human
Values.
MISSION
With a mission to provide refined high quality technical education and training to
aspiring students, we at Don Bosco, strive to impart exclusively valuable,
academic knowledge relating to an array of professional fields undertaken.
Our persistent efforts will evidently create and develop future technocrats and
proficient business leaders who will confidently attend to improve the quality of
life for the current generation.
DON BOSCO INSTITUTE OF TECHNOLOGY
VISION
To become a world-class centre in providing globally relevant higher education in
the field of management, technology and applied science embedded with human
values.
MISSION
To foster an intellectual and ethical environment in which both skill and spirit
will thrive so as to impart high quality education, training, and service with an
international outlook. To create and develop technocrats and business leaders who
will strive to improve the quality of life.
DEPARTMENT OF ELECTRONICS & COMMUNICATION
VISION
To impart value based technical education and train students through continuous
improvement in effectiveness and efficiency of – teaching, learning and associated
processes and to collaborate with industry, foreign universities and institutions for
academic exchange program for faculty and students.
MISSION
To provide an excellent inter-active learning opportunity for all students and staff
to develop knowledge and skills essential in enlightening the individual‟s ability to
think vitally and utilize all concepts of Electronics & Communication Engineering
in detail to meet the technological challenges of tomorrow and to refine knowledge
and understanding through research and creative activities.
PROGRAMME EDUCATIONAL OBJECTIVES:
 Program Educational Objective 1: To prepare students for graduate and

postgraduate programs and to succeed career in Electronics & Communication
Engineering related fields.
 Program Educational Objective 2: To provide students with a foundation in

fundamental engineering principles together with in-depth disciplinary
knowledge or solid foundation in mathematical, scientific and engineering
fundamentals required to succeed in technical profession
 Program Educational Objective 3: To train students with a broad-based

scientific and engineering knowledge so as to comprehend, analyze, design, and
create innovative products and solutions for the real life problems.
 Program Educational Objective 4: To inculcate in students professional and

ethical attitude with a strong character and to uphold the spiritual and cultural
values, effective communication skills, teamwork, multidisciplinary approach,
and ability to relate engineering issues to broader social context.
 Program Educational Objective 5: To provide student with an academic

awareness of advanced technological growth leading to life-long learning
needed for - a successful professional career, excellence and leadership
PROGRAMME OUTCOMES:
At the end of the B.E program, students are expected to have developed the following
outcomes.
1. Engineering Knowledge: Apply the knowledge of mathematics, science,
engineering fundamentals, and an engineering specialisation to the solution of
complex engineering problems.
2. Problem analysis: Identify, formulate, research literature, and analyse complex
engineering problems reaching substantiated conclusions using first principles
of mathematics, natural sciences, and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering
problems and design system components or processes that meet the specified
needs with appropriate consideration for the public health and safety, and the
cultural, societal, and environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge
and research methods including design of experiments, analysis and
interpretation of data, and synthesis of the information to provide valid
conclusions.
5. Modern Tool Usage: Create, select, and apply appropriate techniques,
resources, and modern engineering and IT tools including prediction and
modelling to complex engineering activities with an understanding of the
limitations.
6. The Engineer and Society: Apply reasoning informed by the contextual
knowledge to assess societal, health, safety, legal, and cultural issues and the
consequent responsibilities relevant to the professional engineering practice.
7. Environment and Sustainability: Understand the impact of the professional
engineering solutions in societal and environmental contexts, and demonstrate
the knowledge of need for sustainable development.
8. Ethics : Apply ethical principles and commit to professional ethics and
responsibilities and norms of the engineering practice.
9. Individual and Team Work: Function effectively as an individual, and as a
member or leader in diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities
with the engineering community and with society at large, such as, being able
to comprehend and write effective reports and design documentation, make
effective presentations, and give and receive clear instructions.
11. Project Management and Finance: Demonstrate knowledge and
understanding of the engineering and management principles and apply these to
one„s own work, as a member and leader in a team, to manage projects and in
multidisciplinary environments.
12. Life-long learning: Recognise the need for, and have the preparation and
ability to engage in independent and life-long learning in the broadest context
of technological change
DON BOSCO INSTITUTE OF TECHNOLOGY, KUMBALAGODU, MYSORE ROAD, BANGALORE 560074
COURSE SYLLABUS AS GIVEN BY VTU
ANALOG ELECTRONICS LABORATORY

[As per Choice Based Credit System (CBCS) scheme]
SEMESTER – III (EC/TC)
Laboratory Code: 17ECL37 CIE Marks 40
Number of Lecture 01Hr Tutorial(Instructions) + SEE Marks 60

Hours/Week: 02 Hours Laboratory
RBT Level L1, L2, L3 Exam Hours 03
CREDITS – 02
Course objectives: This laboratory course enables students to get practical experience in design,
assembly, testing and evaluation of
 Rectifiers and Voltage Regulators.
 BJT characteristics and Amplifiers.
 JFET Characteristics and Amplifiers.
 MOSFET Characteristics.
 Power Amplifiers.
 RC-Phase shift, Hartley, Colpitt‟s and Crystal Oscillators.
NOTE: The experiments are to be carried using discrete components only.
Laboratory Experiments:
1. Design and set up the following rectifiers with and without filters and to determine ripple factor and
rectifier efficiency: (a)Full Wave Rectifier (b) Bridge Rectifier.
2. Conduct experiment to test diode clipping (single/double ended) and clamping circuits
(positive/negative).
3. Conduct an experiment on Series Voltage Regulator using Zener diode and power transistor to
determine line and load regulation characteristics.
4. Realize BJT Darlington Emitter follower with and without Boot strapping and determine the gain,
input and output impedances.
5. Design and set up the BJT common emitter amplifier using voltage divider bias with and without
feedback and determine the gain - bandwidth product from its frequency response.
6. Plot the transfer and drain characteristics of a JFET and calculate its drain resistance, mutual
conductance and amplification factor.
7. Design, setup and plot the frequency response of Common Source JFET/MOSFET amplifier and
obtain the bandwidth
8. Plot the transfer and drain characteristics of n-channel MOSFET and calculate its parameters, namely;
drain resistance, mutual conductance and amplification factor.
9. Set up and study the working of complementary symmetry class B push pull power amplifier and
calculate the efficiency.
10. Design and set up the RC-Phase shift Oscillator using FET, and calculate the frequency of output
waveform.
11. Design and set-up the following tuned oscillator circuits using BJT, and determine the frequency of
oscillation.
(a) Hartley Oscillator (b) Colpitts Oscillator
12. Design and set-up the crystal oscillator and determine the frequency of oscillation.
Course Outcomes: On the completion of this laboratory course, the students will be able to:
 Test circuits of rectifiers, clipping circuits, clamping circuits and voltage regulators.
 Determine the characteristics of BJT and FET amplifiers and plot its frequency response.
 Compute the performance parameters of amplifiers and voltage regulators
 Design and test the basic BJT/FET amplifiers, BJT Power amplifier and oscillators.
Department of ECE Page 6 17ECL37 Analog Electronic Circuits Lab Manual
Conduct of Practical Examination:

 All laboratory experiments are to be included for practical examination.
 Students are allowed to pick one experiment from the lot.
 Strictly follow the instructions as printed on the cover page of answer script for breakup of
marks.
 Change of experiment is allowed only once and Marks allotted to the procedure part to be made
zero.

LAB CYCLE
CYCLE -1
1. Wiring and Testing for the performance of BJT –Crystal Oscillator for f0 > 100 KHz
2. . Testing of Half wave, Full wave and Bridge Rectifier circuits with and without Capacitor
filter. Determination of ripple factor, regulation and efficiency
3. Testing of diode clipping (single/double ended) and clamping circuits
(positive/negative).
4. Wiring of a Current series feedback(Common Emitter) amplifier with and without feedback
to determine the gain- bandwidth product from its frequency response
5. Wiring of BJT Darlington Emitter follower and determination of the gain, input and output
impedances with and without bootstrap.
6. Testing of Series voltage regulator using Zener diode and power transistor to determine line
and load regulation characteristics.
CYCLE -2
7. Testing of a transformer less Class – B push pull power amplifier and determination of its
conversion efficiency.
8. Wiring and Testing for the performance of BJT – Hartley & Colpitt‟s Oscillators for RF range
f0 > 100 KHz.
9. Conduct an experiment to Plot the transfer and drain characteristics of n-channel
MOSFET and calculate its parameters, namely; drain resistance, mutual conductance
and amplification factor
10. Conduct an experiment to Plot the transfer and drain characteristics of a JFET and calculate
its drain resistance, mutual conductance and amplification factor.
11. Wiring of RC setup to plot the frequency response of Common Source JFET/MOSFET
amplifier to obtain the bandwidth.
12. Wiring and Testing for the performance of RC Phase shift Oscillator using JFET for f0 <10
KHz

CONTENT LIST
SL. PAGE
EXPERIMENT NAME
NO. NO.
1. Crystal Oscillator 5
2. Rectifiers 7
3. Clipping and Clamping Circuits 11
4. Common Emitter Feedback amplifier 16
5. Darlington Emitter follower 22
6. Series Voltage Regulator 27
7. Class – B push pull power amplifier 30
8. RF Oscillators 34
9. Characteristics of Junction Field Effect Transistor 38
10. Common Source JFET Amplifier 40
11. Characteristics of MOSFET 45
12. Phase Shift Oscillator 47
ADD-ON EXPERIMENTS
13. BJT-RC Phase Shift Oscillator 50

Series and Parallel resonance
14. 54
15. Network Theorems 56

EXPERIMENT NO: 1
CRYSTAL OSCILLATORS
AIM: To design and test for the performance of BJT-Crystal Oscillators for fo= 2.0MHz.
COMPONENTS/APPARATUS REQUIRED: Transistor SL 100, Crystal – 2MHz, Resistors

470Ω, 1KΩ 10KΩ 10K pot and 33 KΩ; Capacitors 0.1µf - 2nos, Power supply, CRO,
Connecting wires etc.
CIRCUIT DIAGRAM:
DESIGN: (NOTE: In all BJT oscillator experiments design procedure for amplifier part
remains same)
BJT- Amplifier:
Design: Let VCC = 12V; ICQ = 4mA; VE = (1/10) VCC to (1/5) VCC; VCEQ= = 6V;
hFE = 100. (This is the normal working value for SL100 transistor)
To find RE: Let us choose VE = 2 V
RE = VE / IE VE / IC =2 V/ 4 mA =500  (Use nearest value 470Ω) RE =470Ω
To find RC:
Write KVL For the collector loop to get: VCC = ICRC + VCEQ + VEQ
RC = (VCC – VCEQ– VEQ) / ICQ = 4.0 V/ 4mA =1.0K Thus RC= 10K
Assume R2=10kΩ.
VB = VE + VBE = 2 + 0.6 = 2.6V (SL100 is a Silicon Transistor)
To Find R2
VB= Vcc*R2
R1+R2
Use R1 = 33K. (Nearest available value)
CE = CC =0.1µF (Arbitrary, any value which gives a reactance < 10 Ω at Crystal frequency may
be used)
{Reactance of a Capacitor XC = (1/2πfC); For C = 0.1 µF, XC = 0.8Ω at 2 MHz}
PROCEDURE:
1. Wire the circuit as per the circuit diagram shown.

2. Switch on the Power Supply and before inserting the crystal check the D.C conditions
by removing the coupling capacitor CC1 or CC2.
3. Insert the crystal and the coupling capacitors and obtain the output waveform on the
CRO. If the o/p is distorted (may be an arbitrary wave form) connect a 10- KΩ
Potentiometer between emitter and RE- CE combination (i.e. Between E and A terminals)
as shown in the second circuit and adjust the pot to get perfect SINE wave.
4. Measure the period of oscillation and calculate the frequency of oscillation.
5. Compare with frequency marked on the crystal.
OBSERVATIONS: Table 1: D.C. Conditions:

Parameter VRC VCE VE VBE VB
Assumed 4.0V 6V 2.0V 0.6V 2.6V
Practical
RESULT: Write your comment on the result obtained.
Viva Questions:
1) What is Piezo-electric effect?
2) Write an equivalent circuit of the crystal.
3)By what name the oscillator you have studied is known? What is the other type of crystal
oscillator?
4) Write some applications of crystal oscillators.

EXPERIMENT NO: 02
RECTIFIER CIRCUITS
AIM: Wiring and testing for the performance of half wave, full wave and bridge rectifiers with
and without a Capacitor filter and to determine ripple factor, regulation and efficiency of each
circuit.
COMPONENTS/APPARATUS REQUIRED: Center tapped transformer 12 – 0 – 12 or any

other as available, BY126/127 / IN4007 diodes – 4 nos, Resistors – 10Ω - 2nos, Load box or
DRB, Multimeter, Connecting wires and Bread board/Spring board with spring terminals
FULL WAVE RECTIFIER:

CIRCUIT DIAGRAM (Note: IN4007 diodes indicated. Use the diode available in your lab)
Without filter
m
A
Vdc
/Va
c
Note:Connect Ammeter in Series and voltmeter in parellel with R L to measure Idc,Vdc,Vac
With filter
„C‟
Note:Connect Electrolytic Capacitor in Parellel with RL

Bridge Rectifier
Without filter
m
A
Vdc
Note:Connect Ammeter in Series and voltmeter in parellel with R L to measure I/Va
dc,Vdc,Vac
c
With filter
„C‟
Note:Connect Electrolytic Capacitor in Parellel with RL
Waveform:
Calcualtions( Same for both with and Without CenterTap)
Without Filter
Ripple Factor

=Vac/Vdc
Efficiency
= Pdc/Pac
Pdc=Vdc*Idc
Pac=Vrms*Irms
Vrms=Vm/√2 ( Vm to be taken from CRO)
Irms=Vrms/RL
With Filter
= Vac/Vdc
Vac=Vr(p-p) / 2√3 (Vr(p-p) from wavefrom on CRO)
Vdc=Vm-Vr(p-p) / 2
Result Tabular Column:
Full Wave Rectifier FWR with Filter

Quantity
Theoretical Practical Theoretical Practical

%
E%
Bridge Rectifier Bridge R with Filter

Quantity
Theoretical Practical Theoretical Practical

%
E%

Viva Questions:
1) What is a rectifier
2) Why do you need a rectifier?
3) What is the meaning of ripple?
4) What are the different filter configurations available to remove these ripples?
5) What is a metal rectifier? Where do you use them?
6) What is the value of ripple factor for a Full wave rectifier? Is this different for a Bridge
rectifier?
7) What is the value of efficiency for a Full wave rectifier? Is this different for a Bridge
rectifier?
8) What happens if you interchange the input – output terminals in a Bridge rectifier?
Explain.
9) Write the equation for the ripple factor of a full wave rectifier with C – filter.
10) Write the equation for Vdc of a full wave rectifier with C – filter.

EXPERIMENT NO: 03
CLIPPING AND CLAMPING CIRCUITS
(A) CLIPPING CIRCUITS

AIM: To wire and test different types of Clipping Circuits and also to obtain their transfer
characteristics.
COMPONENTS/APPARATUS REQUIRED: Diodes – IN 4007 , Resistors - 10KΩ, Power
Supply, Signal generator, CRO, Connecting wires and Bread board/Spring board with spring
terminals
CIRCUIT DIAGRAM:
1. Diode Shunt Clipping above Vref (reference voltage) or Positive Peak Clipping Circuit.
Fig.1 Circuit Diagram of Diode Shunt clipper, Input – output Waveforms and Transfer Characteristic
Forward Resistance of Diode, Rf =100 Ω; Reverse Resistance of Diode, Rr =1MΩ
DESIGN:
The output to be clipped above 2 V, So Vo (max) = +2 V
From the Fig.1 observe that when the diode is ON V o (max) = V + Vref
Where V is Diode Cut-in Voltage which is equal to 0.6 V for IN4007 (Silicon diode)
So Vref = Vo (max) – V
= 2 – 0.6 = 1.4 V Vref = 1.4 V
Select the input amplitude more than 2Volts.
R  R f .Rr  100 10 6  10K Thus R = 10 KΩ
2. Diode Series Clipping below Vref (reference voltage) or Negative Peak Clipping Circuit.
Fig.2 Circuit Diagram of Series Clipper, Input – output Waveforms and Transfer
Characteristic

3. CLIPPING TWO INDEPENDENT LEVEL OR SLICER
Fig.3 Circuit Diagram, Input – output Waveforms and Transfer Characteristic

DESIGN: For clipping the signal below 2 Volt and above 4 Volt levels
1] Vo max = 4 V, i.e. Vo max = VR1 + V; VR1 = Vo max – V= 4 – 0.6 VR1 = 3.4 V
2] Vo min = 2 V i.e. Vo min = VR2 – V; VR2 = Vo min + V = 2 + 0.6 VR2 = 2.6 V
As computed earlier, R = 10 KΩ
4. DOUBLE ENDED CLIPPER TO GENERATE A SYMMETRICAL SQUARE WAVE
Fig.4 Circuit Diagram, Input –output Waveforms and Transfer Characteristics

DESIGN: To generate a symmetrical square wave V0 = ± 4 Volts,
Vo max = VR1 + V; VR1= 4 – 0.6; VR1 = 3.4 V
Vo min = V  VR2= - 4 V =  0.6 VR2 ; VR2 =4  0.6 V; VR2 = 3.4 V
Procedure
1) Connect the circuit as shown .
2) With Vin and Vref set to proper values ,verify the waveform on CRO using X –channel
as I/p and Y-Channel as O/p.
3) Ensure Vin is>> Vref for proper clipping levels
4) For Transfer Characteristics Use X-Y mode in CRO

Viva Questions:
1. What is the need for clipping circuits?
2.Where are the used?
3. Which types of clippers are frequently used – Series clippers or Shunt clippers? Explain the
reasons in any case.
4. Draw circuits to have the following transfer characteristics. Draw the output waveforms for
a sine wave input.

(B) CLAMPING CIRCUITS

AIM: To design and implement different clamping circuits.
COMPONENTS/APPARATUS REQUIRED: Diodes – IN 4007 , Resistors - 10KΩ, Capacitor
1.0 µF, Power Supply, Signal generator, CRO, Connecting wires and Bread board/Spring board
with spring terminals
I ) POSITIVE PEAK CLAMPER :
Clamper to clamp the positive peak at +3v.
CIRCUIT DIAGRAM:
Design: From the circuit of the clamper

Vo,max = Vref + V ; V = 0.6V (Silicon diode)
Vref = Vo,max - V
To clamp the positive peak of a square wave of 10 V (P – P) at +3V we need
Vref = 3 – 0.6 = 2.4 V
Let f = 1KHz.  T = 1msec. Let R = 10K (You have alredy designed this for a clipper)
For the circuit to perform satisfactorily RC = 10T
Therefore C = 10T / R = 10*1ms / 10KΩ  C = 1.0 µF
PROCEDURE:
1. Wire the circuit as shown in the figure.
2. Set Vref = 2.4V from the D.C. source.
3. Apply a square wave of frequency 1KHz and amplitude 10V (P-P) as input.
4. Display the input waveform on channel-1 and output waveform on channel-2.
5. Compare the output waveform with the expected waveform by keeping in DC mode.

II) NEGATIVE CLAMPER :

Clamper to clamp the Negative peak at – 3V.
CIRCUIT DIAGRAM:
Design: From the circuit of the clamper

Vo,max = Vref – V ; V = 0.6V (Silicon diode)
Vref = Vo,max + V, Vo,max= – 3V
Vref = – 3 + 0.6 = – 2.4V to clamp the negative peak at – 3V
Let f = 1KHz.  T = 1msec. R = 10K
R and C are computed as before.
Procedure:
1. Circuit is rigged up as shown in the figure above.
2. The reference voltage from the D.C. source is set to 3.6v.
3. A square wave at 1KHz and 10v (p-p) is applied as input.
4. Display the input waveform on channel-1 and output waveform on Channel-2.
5. Compare the output waveform with the expected waveform by keeping in DC mode.
Results:
Viva Questions:
1) What is the necessity of clamping circuits?
2) Where are they used?
3) Suppose a „Square wave form of 100Hz is used in place of Vref,sketch the output of the
clamping circuitwhen the input is a 10KHz square wave.
4) Explain the operation of the positive clamper. Specifically, starting at t = 0, draw the output
waveform till it settles to the final form.
5) How is the settling time of the clamper determined?

EXPERIMENT NO: 04
BJT CE FEEDBACK AMPLIFIER
AIM: To design and set up the common emitter amplifier under voltage divider bias with and
without feedback and determine the gain-bandwidth product from its frequency response.
COMPONENTS/APPARATUS REQUIRED: Transistors SL100 – 1, Resistors - 100Ω , 390,

10K, 33K, 1K, Capacitors- 100F,0.47F,0.22F, DRB, Multimeter, Connecting wires
and Bread board/Spring board with spring terminals
CIRCUIT DIAGRAM:
COMMON EMITTER AMPLIFIER WITH AND WITHOUT FEEDBACK
DESIGN: Transistor used: SL100. Let VCC = 12V

VEQ = 0.1VCC to 0.2VCC = 1.2 to 2.4V. Let VE = 2V; VCEQ 0.5VCC= 6V; Let ICQ = 4mA.
hFE = 100. (This is the normal working value for this device for IC = 1mA to 10mA)
To find RE:
Given VEQ = 2V. Therefore RE = VEQ / IEQ  VEQ / ICQ =500
Split RE into two parts RE1 = 100 and RE2 = 390
To find RC:
Writing KVL for the Collector loop we get, VCC = ICQRC + VCEQ + VEQ
 RC = (VCC – VCEQ – VEQ) / ICQ = 4V/4mA=1K. Use RC = 1 K
To Find R1 and R2: Assume R2=10KΩ,
VBQ = VEQ + VBEQ = (2 + 0.6)V= 2.6V.
To Find R2
VB= Vcc*R2
R1+R2

Use R1 = 33K. (NCAV: Nearest Commercially Available Value)

To find CC1, CC2 and CE:
Input coupling capacitor CC1 ≥ 1 / (2Ri f1),
Here f1 is the Lower Half Power frequency or Lower 3dB frequency or Lower Cut-off
frequency of your amplifier. Let f1= 500Hz.
Ri =R1||R2||hie. With hie2.5KΩ, we get Ri=1.8857KΩ or Ri=1.9KΩ
Therefore CC1 ≥ 0.168F. Use CC1 = 0.22 F (Next Nearest available single component)
With this coupling capacitor, the expected Lower cut-off frequency will be, f1= 383Hz.
Let Input Coupling capacitor alone decide f1
Output coupling capacitor:
Let RL = 10 KΩ (This represents the Terminating Resistance OR Input Resistance of the next
stage).
CC2 will be chosen to be at least ten times larger than the value obtained for f1 so that it does
not contribute to f1. Thus, CC2 ≥ 10{1 / (2(RC + RL) f1)} = 10/2π x11 K x 0.5K =0.29F
Use CC2 = 0.47F (NCAV)
Note: Any value larger than 0.29F available in the lab may be used for CC2
Emitter bypass capacitor, CE:

XCE will be chosen to have a very small value, say RE/10 at fE ≤ f1/10
CE≥ (1 / (2 R fE), fE ≤ f1/10=50Hz, where R =RE/10= 49; this gives CE =68.085F;
Use CE =100F (Next higher value available in the lab)
Note: A lower value of 47F may be used. This gives XCE=6.8  at f1 (R=68  at 50 Hz in
place of 47) which is around RE/6.9 and the by-pass may be regarded perfect.
I). Connect the bypass capacitor CE between “A” and Gnd point  Amplifier without
feedback
II). Connect the bypass capacitor CE between “B” and Gnd point  Amplifier with current
series feedback. 𝛽 = Vf/Vo =RE1/RC= 0.1
PROCEDURE:
1. Wire the circuit as per the given circuit diagram, first for “A” and then repeat for “B”
2. Switch on the D.C. power supply and check the D.C. conditions without any input
signal and record in table below:
Table: D.C. Conditions
Assumed 4.0V 6 V 2V 0.6 V 2.6 V
Practical
3. Select sine wave input and set the input signal frequency ≥10f 1 (Say = 10 KHz. This
will be a convenient „Mid – frequency‟).
4. Observe the input wave form and output wave form on a dual channel CRO.

5. Adjust the input amplitude such that the output waveform is just undistorted (or in the
verge of becoming distorted). Measure the amplitude of the Input Signal now. This
amplitude is the Maximum Signal Handling Capacity of your amplifier.
6. Decrease the input voltage to a convenient value such that the output is undistorted. Say
100mV. Measure the corresponding o/p voltage. Calculate mid-band gain,
AM = Vo (p-p) / Vin (p-p).
7. Keeping the input voltage constant, go on reducing the frequency until the output voltage
reduces to 0.707 times its value at 10 KHz. The frequency at which this happens gives
you the Lower Cut-off frequency (f1).
8. Keeping the input voltage constant, go on increasing the frequency until the output
voltage decreases to 0.707 times its value at 10 KHz. The frequency at which this
happens gives you the Upper Cut-off frequency (f2).
Thus you have pre-determined f1 and f2. Find the amplifier band width, BW = f2 – f1
9. Determine Gain Bandwidth product (GBW product) which is a Figure of Merit of
your amplifier as GBW = AM x BW.
10. Now repeat the experiment by recording values of output voltage versus frequency
keeping the input voltage at a constant value convenient to you. You should take at
least 5 readings below f1 and 5 readings above f1, at least 5 readings in the mid band,
at least 5 readings below f2 and 5 readings above f2.
11. Plot graphs of AV versus Frequency, f and /or M, dB versus Frequency, f on a semi
log graph paper. From the graph determine: Mid –band - gain, Lower and Upper
Cut-off frequencies and Band width. Compute the GBW product and verify with
answer obtained earlier.
12. Repeat the procedure for the feedback amplifier separately but draw the frequency
response graph on the same graph sheet.
13. Find the Input and Output impedances of the amplifiers with and without feedback
following the procedure given under Darlington Emitter Follower.
14. Verify the relationships between A, Ri and Ro with and without feedback
EXPECTED FREQUENCY RESPONSE GRAPH:

Vi=------mv
Tabular Column:
Without feedback With feedback
Freq(in Freq(in
Sl.No. Vo Av=20Log(Vo/Vi) Sl.No. Vo Av=20Log(Vo/Vi)
Hz) Hz)
1 100hz 1 100hz
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 2M 10 2M
Results:
without feedback
f1=-------------Hz
f2=--------------Hz
BW=(f2-f1)Hz.
GBW= AM x BW.
With feedback
f1=-------------Hz
f2=--------------Hz
BW=(f2-f1)Hz.
GBW= AM x BW.

Viva Questions:
1) What is an amplifier?
2) What kind of bias should be applied for the transistor to act as an amplifier?
3) What are the bias conditions for transistor to be in (a) Saturation region? (b) Cut – off
region? (c) Active region?
4) What is early effect? Is it an advantage or a disadvantage?
5) Mention different types of transistor biasing methods.
6) Which biasing method provides stabilization against variations in ICO, β, VBE?
7) What is bias compensation?
8) What is the major drawback of self biasing circuit?
9) What are the different methods of coupling amplifier stages?
10) What is the advantage of RC Coupling?
11) Where do you use transformer coupling?
12) Write an expression for the mid – band voltage gain for a single stage RC coupled
amplifier.
13) What is the approximate mid – band voltage gain of your amplifier? Does this tally with
practical value? Justify.
14) Which are the components that affect the lower cut – off frequency?
15) Which are the components that affect the upper cut – off frequency?
16) Does the Emitter by – pass capacitor have any effect on the cut – off frequencies? Which
cut – off frequency will it affect?
17) Write an expression for the voltage gain of the amplifier in the low frequency region in
terms of mid-band gain and lower cut – off frequency
18) Write an expression for the voltage gain of the amplifier in the high frequency region in
terms of mid-band gain and upper cut – off frequency.
19) What are the merits and de-merits of the R – C Coupled amplifier?

EXPERIMENT NO: 05
DARLINGTON EMITTER FOLLOWER
AIM: To determine experimentally Zi, Zo, Voltage gain, AV and the Current gain Ai of a
Darlington Emitter Follower With and Without Bootstrapping.
COMPONENTS/APPARATUS REQUIRED: SL100, Resistors - 680 Ω, 1KΩ(3) and

1MΩ(pot), Capacitors 0.47µf(2), 10µf, Power Supply, 10Hz – 2MHz Signal generator, CRO,
Connecting wires and Bread board/Spring board with spring terminals
CIRCUIT DIAGRAM:
Fig. 1
DESIGN:
Let VCC = 12 V D.C.; IC2 ≈ IE2 = 6mA, hfe1 = 50, hfe2 = 100;
(For SL100 transistor 40 < hfe < 300; For Ic=2mA to 10 mA working value of hfe = 100)
Choose VCE2 = VCC / 2 = 12/2 = 6V; Thus, VCE2 = 6V

IB2=IC2/hfe2=6000/100=60μA = IC1 ; IB1 = IC1/hfe1= 60/50 = 1.2μA
To Find RE
RE = (VCC – VCE2)/IE2 =6V / 6mA = 1000 Ω Use RE = 1 KΩ
Assume R3 = 1K. (Intentionally). Then R3IB1 = 1.2 mV

To find R1 :
VAG = VAB1 + VBE1 + VBE2 + VE2

= R3IB1 + VBE1 + VBE2 + VE2
=1.2 mV + 0.7 V + 0.7 V + 6V
=7.4012 V
With R2 = 1 K, IR2 = VAG/R2 = 7.4012 mA=7401.2 μA
There fore, IR1 = IR2 + IB1 =7401.2 + 1.2 = 7402.4 μA
R1= (Vcc-VAG)/IR1 = 12-7.4012/7402.4 μA =621.258Ω
Use R1 = 680 Ω (Nearest single value
component)
Choose CC1 = CC2 = 0.47 μF. (Arbitrary, as we are not interested in frequency response).
PROCEDURE:
A] To measure Voltage Gain

1) Connect the circuit as shown in the Fig.1
2) Switch on the power supply and set VCC = +12 V.
3) Measure the DC Voltages using CRO or Multimeter and record.
VCE1 VBE1 VCE2 VBE2 VE2

Assumed 6V 0.7V 6V 0.7V 6V
Obtained
4) Apply a sine wave voltage from the Function Generator.
5) Observe the o/p Vo. Measure and record Vi and Vo. Compute and enter the voltage gain,
AV=Vo/Vi in the table.
VOLTAGE GAIN WITH BOOTSTRAP
Vi
Vo
AV
Record Vi, Max, The maximum input you can apply for undistorted output as the “Maximum
Signal handling capacity” of the Emitter follower
6) Repeat the experiment after disconnecting the capacitor CB in branch AB, i.e.; just
remove the Bootstrapping capacitor, CB. Now you have taken away the Bootstrapping.
Without CB you are testing the „Darlington Emitter Follower without
Bootstrap‟

VOLTAGE GAIN WITHOUT BOOTSTRAP
Vi
Vo
AV
B] To measure Input Impedance Zi:

1) Connect the circuit as shown in Fig 3 below.
2) Set the DRB to minimum (0 Ω). Apply a10 KHz sine wave signal of amplitude 1V (p-p)
or any suitable value to get an undistorted output.
3) Measure Vo (p-p). Let Vo = Va (say) with DRB value = 0
4) Increase DRB value in steps till Vo = Va/2.
The corresponding DRB value gives Zi.
5) Repeat the experiment by disconnecting CB, the bootstrapping capacitor.
6) Compare the two input impedance values you have measured.
Fig. 3
C] To measure output impedance, Zo:
1) Connect the circuit as shown in Fig.4.

2) Set the DRB to its maximum resistance value. Apply a 10 KHz sine wave of amplitude
1V (p-p) or any suitable value to get undistorted output
3) Measure Vo (p-p), Vo = Vb without DRB connection or DRB value at Max.
4) Decrease DRB value in steps till Vo = Vb/2. The corresponding DRB value gives Zo.
In this part of the experiment, it is likely that the o/p wave form may get
distorted as the DRB value is decreased. Then, Vi has to be set to a lower
value and the steps to be repeated. Note carefully that the answer will be wrong
if you take readings with distorted output.
5) Repeat the experiment by disconnecting the Bootstrapping capacitor.

Fig. 4
RESULTS:
1] Voltage Gain with Boot Strap. : ……..
2] Voltage Gain with Boot Strap. : …….
3] Input Impedance, Zi, with Bootstrap. : ……….
4] Input Impedance, Zi, without Bootstrap. : ………..
5] Output Impedance, Z0, with Bootstrap. : ………..
6] Output Impedance, Z0, without Bootstrap. : ……….
7]Current Gain, Ai, With Bootstrap. : ………..
8] Current Gain, Ai, Without Bootstrap. :
Vi = Zi × Ii, Vo =Zo × Io  Ai = (Io/Ii) = AV × (Zi/Zo)
Viva Questions:
1. Why do you need high input impedance?

2. What is the input impedance of an ordinary emitter follower?
3. Indicate the methods by which you can increase the input impedance of the emitter
follower.
4. How can you increase the forward short circuit current gain of the emitter follower?
5. State Miller‟s theorem. How does this theorem help you in your circuit?
6. Draw the AC equivalent circuit of the Boot strapped emitter follower and show how the
effect of the bias resistors is altered.

EXPERIMENT NO: 06
SERIES VOLTAGE REGULATOR
AIM: To design and build a Series voltage regulator using Zener diode and power transistor and
to determine line and load regulation characteristics.
COMPONENTS/APPARATUS REQUIRED:Power transistors (2N3055 1 Nos), Zener Diode

IN4738A (8.2V) or IN4742A (12V), 0 – 30 V variable power supply, One Auto ranging
multimeter, One Decade Resistance Box, 100K and one 100  resistors
CIRCUIT DIAGRAM:
SIMPLE SERIES REGULATOR (EMITTER FOLLOWER REGULATOR):
VZ= 8.2 V; IZmin = 1.0 mA; For 2N3055 (Silicon) 𝛽 = 20 - 70, ICmax= 15A, PDmax = 115W
VIN=153V
Design: VOUT= VZ - VBE= 8.2 – 0.7 = 7.5V
VCEmax= 18 – 7.5 = 10.5V, ICmax = 115/10.5 = 10.9A
Let the load current vary from 2.5mA to 250mA. ie. ILmin = 2.5 mA and ILmax= 250mA
For ILmax= 250mA, with hFE=20, IB = 250/20 =12.5mA
R = (VINmin – VZ)/ IR, IR= IBmax + IZmin=12.5+1 = 13.5mA, R = 3.8/13.5 = 281 USE R =
270
(If not available use 220, 0.5W)
Wattage of R: PR= (VR,max)2/R= 9.82/220= 0.437W  ½ W resistor is sufficient.
Range of RL: (7.5V/250mA) to (7.5V/2.5mA) = 30 to 3K Vary RL in the range 50 to
2.5K
Wattage of load resistors: 50 - 1.125W – Use 50 - 1.5W all other resistors should have
wattage appropriately (7.52/RL). If you have a 5K pot of 2W rating it will be good.

Operation: If the output voltage increases, the decreased base-emitter voltage causes transistor to
conduct less, thereby reducing the output voltage. Consequently, the output voltage is maintained
at a constant level.
PROCEDURE:
1). Wire the circuit as shown in the figure.
2). Measure and record the values of V0 and RL keeping Vin = 15V
RL 2.5K 2.0K 1.5K 1K 800 500 250 100 50

V0
I0=V0/RL
[Alternatively you can connect an ammeter in series with the load and note down the output
voltage and load current readings directly]
Plot a graph of V0 Vs I0.
Load regulation is calculated as below:
Regulation1 = (VNL – VFL)/VFL. This is called “Up Regulation”
Regulation2 = (VNL – VFL)/VNL. This is called “Down Regulation”
3). Adjusting RL so as to maintain output current constant, Tabulate the following and find “Line
regulation”. (Here you will need an ammeter in series with RL)
Line Regulation:

I0=Constant (Say 20mA)

VIN 12V 13V 14V 15V 16V 17V 18V
V0
Percentage of line regulation=

Results:
Viva Questions:
1. Explain the concept of Zener breakdown?

2. How depletion region gets thin by increasing doping level in Zener diode?
3. State the reason why an ordinary diode suffers avalanche breakdown rather than Zener
breakdown?
4. Give the reasons why Zener diode acts as a reference element in the voltage regulator circuits.
5. What type of biasing must be used when a Zener diode is used as a regulator?
6. Justify the use of zener diode in a stabilization circuit?
7. How will you differentiate if it is Zener or avalanche breakdown when you are given two
Zener diodes of rating 6.2 v and 24V?
8. What is the drawback of Emitter follower regulator?
9. What are the advantages of the Series feedback regulator?
10. Can you redraw your circuit to include short circuit protection and overload protection?
11. What are shunt regulators? What are their merits and demerits?
12. What is the general nature of the conventional regulator used in all practical applications?

EXPERIMENT NO: 7
CLASS –B PUSH PULL POWER AMPLIFIER
AIM: To set up and study the working of complementary symmetry class B push pull power
amplifier and calculate efficiency. (To wire and determine the conversion efficiency of class B,
transformer less push pull power amplifier).
COMPONENTS/APPARATUS REQUIRED: Complementary symmetry transistors SL100

and SK100, Resistors – 47KΩ - 2nos, 4.7KΩ - 1no, 1KΩ - 2nos, 10KΩ pot - 1no,0.01µF – 2 nos,
Load box or DRB, Multimeter, Connecting wires and Bread board/Spring board with spring
terminals
CIRCUIT DIAGRAM:
V
10Ω
Fig 1 Circuit Set Up

Note: Idc can also be directly measured by connecting ammeter in series with VCC.
Brief theory of Transformer - less Class B Push-Pull Amplifier

One of the main disadvantages of the Class B amplifier circuit is that it uses balanced
center-tapped transformers in its design, making it expensive to construct. However, there is
another type of Class B amplifier called a Complementary-Symmetry Class B Amplifier that
does not use transformers in its design. Therefore it is transformer less, using instead
complementary or matching pairs of power transistors. As transformers are not needed, this
makes the amplifier circuit much smaller for the same amount of output. Also there are no stray
magnetic effects or transformer distortion to affect the quality of the output signal. A
"transformer less" Class B amplifier circuit is given in Fig 1.

The Class B amplifier circuit above uses complimentary transistors for each half of the
waveform and while Class B amplifiers have a much high efficiency than the Class A types, one
of the main disadvantages of class B type push-pull amplifiers is that they suffer from an effect
known commonly as Crossover Distortion. Remember from Basic knowledge of Transistors that
it takes approximately 0.7 volts (measured from base to emitter) to get a bipolar transistor to start
conducting. In a pure class B amplifier, the output transistors are not "pre-biased" to an "ON"
state of operation.
This means that the part of the output waveform which falls below this 0.7 volt window
will not be reproduced accurately as the transition between the two transistors (when they are
switching over from one to the other), the transistors do not stop or start conducting exactly at the
zero crossover point even if they are specially matched pairs. The output transistors for each half
of the waveform (positive and negative) will each have a 0.7 volt area in which they will not be
conducting resulting in both transistors being "OFF" at the same time. Fig 2 and Fig 3 illustrate
the reason and concept of crossover distortion.
Fig 2 Nonlinear Characteristic of Class B Operation
Fig 3 Illustrating Cross-over distortion

PROCEDURE:
1. Wire the circuit as in Fig 1.
2. Adjust the 10K pot to get VCE1 = VCE2 = 5 V
3. Measure and record VBE1 and VBE2
4. Give a sine wave input of frequency 1 KHz and observe the output.
5. Determine the output impedance of the amplifier and record. (Say 60)
6. Vary RL in the range 30Ω to 80Ω in steps. (Take 5 readings on either side of R0)
7. For each value of RL adjust the signal amplitude to get “Maximum Un – distorted
Output”
8.For each RL setting, Record RL, Idc, Vo peak to peak and compute the conversion efficiency as
shown in the table.
9. Plot a graph of  vs. RL and determine the optimum load and maximum efficiency
TABULAR COLUMN
Sl. RL Idc mA= Vo( Pdc Po  Remarks

No
In Ω P- =VccIdc =[V0(P-P)2]/8RL =(Po/Pdc)100 %
P)
(V/10Ω)
in
V
1 30
2 40
3 50
4 60
5 70
6 80
Fig 5. Efficiency versus Load graph
Results:

Viva Questions:
1. What are power amplifiers?
2. How are power amplifiers different from conventional Voltage or Current amplifiers?
3. Define the efficiency of a power amplifier.
4. What are the efficiencies of R-C Coupled Class A, Single ended Class A and Class B
power amplifiers?
5. What are the disadvantages of Class B power amplifiers with center tapped
transformer?
6. What is cross –over distortion? What is the reason for this distortion?
7. How this distortion can be eliminated? Explain.
8. What are „complimentary symmetry‟ transistors?
9. Is the transformer-less Class B Power amplifier advantages compared to Push-pull
amplifiers with center tapped transformer? If so write the merits and de-merits of both
10. Is this kind of power amplifiers used in the present VLSI era?
11. Write the applications of Power amplifiers.
12.What are „Class – C‟ power amplifiers? Where are they used?

EXPERIMENT NO: 8
RF OSCILLATORS
Note: All LC oscillators are RF Oscillators (≥ 100 KHz).
A) BJT HARTLEY OSCILLATOR
AIM: To design and test a Hartley Oscillator for a given frequency using BJT
COMPONENTS/APPARATUS REQUIRED: Transistor SL 100, Resistors 470Ω, 1KΩ 10KΩ

and 33 KΩ; Capacitors 0.1µf - 3nos, Discrete inductances 100 µH – 2 nos, Capacitor 470 pF –
2nos, Power supply, CRO, Connecting wires etc.
CIRCUIT DIAGRAM:
DESIGN:
BJT- Amplifier: Same as given in Common Emitter Amplifier.

1
Tank Circuit Design: Oscillator Frequency f = Leq. = L1 + L2
2 Leq .C.
Assume f = 500 KHz. With L1 = L2 =100μH, we get Leq. = L1 + L2 = 200μH
Leq.C=1/(2πf)2=(π)-2 x10-12
This gives C = {1/ (π)2 x 200μH} pF 500pF
Use C = 470 pF (Nearest available value) Use C = 470 pF
For this capacitance value f = 518.6 KHz
Table 1: D.C. Conditions


Assumed 4.0V 6V 2.0V 0.6V 2.6V
Practical
PROCEDURE:
1. Wire the circuit as per the circuit diagram shown.
2. Switch on the Power Supply and check the D.C conditions by removing the coupling capacitor
CC1 or CC2.
3. Connect the coupling capacitors and obtain an output waveform on the CRO. If the o/p is
distorted (may be an arbitrary wave form) connect a 10- KΩ Potentiometer between emitter and
RE- CE combination(i.e. Between E and A terminals) as shown in the second circuit and adjust to
get perfect SINE wave.
4. Measure the period of oscillation and calculate the frequency of oscillation.
5. Compare the measured frequency with re-computed theoretical value for the component values
connected
Results:

B) BJT COLPITTS OSCILLATOR
AIM: To design and test a Colpitt‟s Oscillator for a given frequency using BJT
COMPONENTS/APPARATUS REQUIRED: Transistor SL 100, Resistors 470Ω, 1KΩ 10KΩ

and 33 KΩ; Capacitors 0.1µf - 3nos, Discrete inductances 100 µH – 2 nos, Capacitor 470 pF –
2nos, Power supply, CRO, Connecting wires etc.
CIRCUIT DIAGRAM
Fig 3 Circuit Diagram of Colpitt‟s Oscillator
DESIGN: Design of the amplifier part is as in Crystal Oscillator or you can use the same
circuit values of Hartley Oscillator
1 CC
Tank Circuit Design: Similar to Hartley Oscillator f  Where Ceq  1 2
2 LCeq C1  C2
Given Oscillation frequency f =1 MHz
Assume C1=C2 = 470 pF  Ceq= 235 pF =2.35 F

1
Then, L   119 µH
4 2 ( f 2 )C
Use L = 100 µH (Nearest available value single component)
For this value of L, f = 1.04 MHz
PROCEDURE: Follow the procedure of the Hartley Oscillator experiment.
Results:
Viva Questions:
1. What is an oscillator? What kind of feedback is used in oscillator circuits?

2. What are the conditions to be satisfied in order to produce oscillations? What are these
conditions called?
3. Write other versions of Hartley oscillator circuits.
4. Which version of the circuit is used in communication applications?
5. What are Relaxation Oscillators?
6. Why LC oscillators are not suitable for Audio frequencies?
7. Write the AC equivalent of the crystal oscillator. Use the equivalent circuit of the crystal.
8. What kind of oscillator you can visualize for the crystal oscillator? Hartley or Colpitt‟s or any
other?

EXPERIMENT NO: 09
CHARACTERISTICS OF A JUNCTION FIELD EFFECT TRANSISTOR
AIM: To plot the input and output characteristics of a JFET and calculate its parameters, namely;
drain dynamic resistance, mutual conductance and amplification factor.
COMPONENTS/APPARATUS REQUIRED: JFET PF5102, 100 Resistor, and DC Power

Supply 0 – 30V, 2 Numbers and Connecting wires and Bread board/Spring board with spring
terminals.
CIRCUIT DIAGRAM:
PROCEDURE: Make the circuit connections as shown in the figure.
(a) Drain Characteristics:
1). Adjust the reading of V2 to +0.5V (Interchange the polarity of the power supply V GG), 0V
(Short the gate terminal to ground), –1V, –2V and – 3V. For each setting, keep it constant.
2). Vary VDD supply and adjust the supply such that V1 is as indicated in the table below and
record the corresponding readings of ID.
3). Enter the second row for ID as indicated. Plot a graph of ID Vs VDS.
VGS = V2 = Constant (0.5V, 0V, - 1V, - 2V, - 3V)

V1(VDS, V) 0.1 0.15 0.2 0.25 0.3 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
ID, mA
V1(VDS, V) 2 2.4 2.8 3.0 3.4 3.6 3.8 4.0 5.0 6 8 10 12

ID, mA
(b). Transfer Characteristics:
1). Set VDS = 6V. That is, adjust the reading of V1 to 6V.
2). Record the readings of V2 and corresponding ID.
VDS = V1 =6V Constant (Repeat for VDS = 9V and VDS = 12V)

V2(VGS, V) 0 –0.2 –0.4 –0.6 –0.8 –1.0 –1.2 –1.4 –1.6 –1.8 –2.0
ID, mA
V2(VGS, V) –2.2 –2.4 –2.6 –2.8 –3.0 –3.2 –3.4 –3.6 –3.8 –4.0
ID, mA
NOTE: The readings given above are on the assumption that the pinch-off voltage is –4V.
For the drain characteristics, take at least 3 readings before and after the pinch-off starts
so that you will get a smooth graph.
For the transfer characteristics, continue increasing |V2| till drain current becomes ZERO.
The values indicated on the graphs below are not exact. They are only for illustration.
EXPECTED GRAPHS:
a) Drain Characteristics b) Transfer Characteristics
From the graphs determine gm = (ID/VGS)|VDS = Constant and rd =(ID/VDS)|VGS = Constant

NOTE: The procedure is general. You can do the experiment with any JFET.
For example you can Use PF5102 N-channel JFET manufactured by Fairchilds company.
Results:

EXPERIMENT NO: 10
COMMON SOURCE JFET AMPLIFIER
AIM: To design, setup and plot the frequency response of Common Source JFET amplifier,
and obtain the band width.
COMPONENTS/APPARATUS REQUIRED: JFET – PF5102, Resistors - 180 Ω, 1KΩ,
10KΩ and 1MΩ, Capacitors 47µf, 0.1µf and 0.047µf, Power Supply, 10Hz – 3MHz Signal
generator, CRO, Connecting wires and Bread board/Spring board with spring terminals.
CIRCUIT DIAGRAM:
Fig 4 (a) FET RC Coupled Amplifier (b) Base Diagram of the FET
DESIGN:
Given VDD=12V
VDS=VDD/2=6V
From data sheet of PF5102
Idssmin=4mA
Idssmax=20mA
Vgsmax=-1.6V
Vgsmin=-0.7V
Yoss=25umho
Therefore select Idss=10mA and Id=1mA (select one point on load line)

PROCEDURE:
a) To Run Frequency response:
1. Wire the circuit as per the given circuit diagram.
2. Switch on the D.C. power supply and check the D.C. conditions without any input
signal and record in table below:
Parameter VDD VRD VDS VS VGS

Assumed 12V 4.35V 6 V 1.65V -1.65V
Practical 1.65V
3. Select sine wave input and set the input signal frequency ≥10f1 (Say = 10 KHz. This will
be a convenient „Mid – frequency‟).
4. Observe the input wave form and output wave form on a dual channel CRO.
5. Adjust the input amplitude such that the output waveform is just undistorted (or in the
verge of becoming distorted). Measure the amplitude of the Input Signal now. This
amplitude is the Maximum Signal Handling Capacity of your amplifier.

6. Decrease the input voltage to a convenient value such that the output is undistorted.
Say 100mV. Measure the corresponding o/p voltage. Calculate mid-band gain, AM = Vo
(p-p) / Vin (p-p).
7. Keeping the input voltage constant, go on reducing the frequency until the output
voltage reduces to 0.707 times its value at 10 KHz. The frequency at which this happens
gives you the Lower Cut-off frequency (f1).
8. Keeping the input voltage constant, go on increasing the frequency until the output
voltage decreases to 0.707 times its value at 10 KHz. The frequency at which this
happens gives you the Upper Cut-off frequency (f2).
9. Thus you have pre-determined f1 and f2. Find the amplifier band width, BW = f2 – f1
10. Determine Gain Bandwidth product (GBW product) which is a Figure of Merit of your
amplifier as GBW = AM x BW.
11. Now repeat the experiment by recording values of output voltage versus frequency
keeping the input voltage at a constant value convenient to you. You should take at least
5 readings below f1 and 5 readings above f1, at least 5 readings in the mid band, at least 5
readings below f2 and 5 readings above f2.
12. Plot graphs of AV versus Frequency, f and /or M, dB versus Frequency, f on a semi
log graph paper. From the graph determine: Mid –band - gain, Lower and Upper Cut-
off frequencies and Band width. Compute the GBW product and verify with answer
obtained earlier.
Vin (P-P) = ……..Volts (Constant)
Frequency
100 200 300 350 400 450 500 600 800 1K
In Hz
VO(P-P)
in Volts
AV
M, dB
(AV in dB)
Frequency
2K 3K 5K 8K 10K 20K 30K 50K 100K 200K
In Hz
VO(P-P)
in Volts
AV
M, dB
(AV in dB)
requency
300K 500K 800K 1M 1.5M 1.8M 2M 2.5M 2.8M 3M
In Hz

VO(P-P)
in Volts
AV
M, dB
(AV in dB)
AV= VO (P-P)/Vin (P-P) (It is a ratio of two voltages. No units); M = 20log (AV), dB
Expected Graphs:
Plot of Voltage Gain AV versus frequency
Results:

Viva Questions:
1) What are the classifications of Field effect transistors?
2) Write the symbols for an N – Channel JFET and a P – Channel JFET.
3) What are the advantages of Field effect transistors?
4) What decides the maximum signal handling capacity of the FET RC coupled amplifier?
5) Re – design your amplifier by first choosing |VGS| = |VS| = 0.5 |Vp| and then compute IDQ
using
6) What are the advantages of potential divider bias circuit for JFET‟s?
7) What other kinds of bias circuits you know for JFET‟s? Draw them and illustrate.
8) What decides the output resistance of the RC Coupled amplifier?

EXPERIMENT N0. 11
CHARACTERISTICS OF A MOSFET
AIM: To plot the input and output characteristics of n-channel MOSFET and calculate its
parameters, namely; drain dynamic resistance, mutual conductance and amplification factor.
COMPONENTS/APPARATUS REQUIRED: MOSFET IRF840, 100 Resistor, and 2

Numbers of DC Power Supply 0 – 30V, and Connecting wires and Bread board/Spring board
with spring terminals.
CIRCUIT DIAGRAM:
PROCEDURE:
Some specifications: VGS (TH) = 2V to 4V, IDS max = IDS (ON) = 8 A. (VGS=10V), BVDSS = 500V
(VGS=0, IDS=250A) (For detailed specifications make a GOOGLE search)
Transfer Characteristics:
1. Connections are made as shown in the figure.
2. Initially both VGG and VDD are kept at zero position

3. By varying the VDD, set VDS = 5V.
4. Now increase VGS by varying VGG gradually and note down the corresponding meter readings
as shown in the table.
5. Note down the minimum value of VGS for which drain current starts flowing and record VTH =
6. Repeat for VDS = 10V and 15V.
7. Plot the graph of ID Vs VGS
.Drain Characteristics
1. Connections are made as shown in the figure
2. Initially both VGG and VDD are kept at zero position
3. By varying VGG set VGS to some value (slightly greater than the Threshold voltage determined
from the transfer characteristics) Say 3.0V
4. Now increase VDS by varying VDD gradually and note down the corresponding meter readings
as shown in the table.
5. Repeat the steps 3 and 4 for VGS=3.2V and VGS = 3.4V
6. Plot the graph of ID Vs VDS
.

TABLE – Transfer Characteristics

VDS = V1 = 5V (10V, 15V)
VGS =V2, V 1.0 2.0 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.8 4.0 4.2 4.5
ID, mA
. . TABLE – Drain Characteristics

VGS = V2 = 3.0 (3.2V, 3.4V)
VDS =V1, V 0.2 0.4 0.6 0.8 1.0 1.5 2.0 3.0 5.0 10 12 15 18 20
ID , mA
EXPECTED GRAPHS:
Drain Characteristics Transfer Characteristics

From the graphs determine gm = (ID/VGS)|VDS = Constant and rd =(ID/VDS)|VGS = Constant
Results:

VIVA QUESTIONS:
1. What are MOSFET‟s?
2. What is the difference between MOSFET and BJT?
3. What are the types of MOSFET?
4. What is the difference between depletion mode and enhancement mode MOSFET‟s?
5. How does n-drift region affect MOSFET?
6. How MOSFET‟s are suitable for low power high frequency applications?
7. What are the requirements of gate drive in MOSFET?
8. What is rise time and fall time?
9. What is pinch off voltage?
10. In which region the MOSFET is used as a switch?
11. Which parameter defines the transfer characteristics?
12. Why MOSFET‟s are mainly used for low power applications?
13. How MOSFET is turned off?
14. What are the advantages of vertical structure of MOSFET?
15. What are the merits of MOSFET?
16. What are demerits of MOSFET?
17. What are the applications of MOSFET?

EXPERIMENT NO: 12
PHASE SHIFT OSCILLATOR
AIM: To design and setup the RC-Phase shift Oscillator using JFET, and calculate the frequency
of output waveform. (To design and test a JFET-RC Phase Shift Oscillator for a given frequency)
COMPONENTS/APPARATUS REQUIRED: Junction FET BF862, Resistors 27Ω, 1KΩ and

56KΩ - 3 nos. and a 10K pot; Capacitors 100µf, 1000 pf - 3nos, Power supply, CRO, Connecting
wires etc.
CIRCUIT DIAGRAM:
QUICK REFERENCE DATA FOR BF862

UNIT
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX.
VDS drain-source voltage -- -- 20 V

VGSoff gate-source cut-off voltage - 0.3 - 0.8 - 1.2 V
IDSS drain-source current 10 -- 25 mA
Ptot Total Power Dissipation Ts<900C --- --- 300 mW
|yfs| Transfer Admittance 35 45 -- mS
o
Tj Junction Temperature -- -- 150 C
Design: For RC Phase Shift Oscillator using FET, Barkhuasen Criterion gives:
1) |A|  29 and 2) Hz
To satisfy (1), we need A =  56 with , where . Usually RD will be small

(1 K to 10K) and to achieve the desired gain, we need an FET that has a large gm.
BF862 satisfies this condition with minimum gm = 35 mS. So BF862 is chosen.
If BFW10/11 is used, its gm is of the order of 3.5 mS and working gm will be still smaller and a
single stage amplifier will give the desired gain with R D  15K. This requires large value of VDD
greater than the gate break down voltage. Therefore a single stage amplifier is not possible. So a
Three stage amplifier circuit will be needed.
Let VDD = 12V, ID = 1mA

IDSS varies from sample to sample.
A convenient value would be (IDSSMin +IDSSMax)/2 = (10+25)/2 = 17.5 mA
Thus choose IDSS = 18 mA. Further, use Vp = - 0.8 V
Compute RS using
Choose RS = 560 (Nearest Commercially Available Value – NCAV)
Choose VDSQ = VDD/2 = 6V. Then VRD = VDD – VDS – VS = 12 – 6 – 0.56 = 5.44 V
RD = VRD/ID = 5.44 V/ 1 mA = 5.44 K. Choose RD = 5.6 K (NCAV)
Let and Let f = 1 KHz
Then Choose CS = 47 F (NCAV)
For the feedback network:
Let R = 5.6K. Then Choose C = 0.01F (NCAV)
With this choice of components, the frequency of oscillation will be
PROCEDURE:
1). Make the circuit connections for the base amplifier portion only and measure the Q – conditions
and record.
VDD VDS VS VRD ID=VRD/RD

Design Values 12V 6V 0.6V 5.6V 1mA
Measured Values
2] Switch on the D.C. power supply and check for the Q-conditions by disconnecting feedback
connection (Just remove the pot and leave it open).
3]. Connect the 1K / 10K pot between A and D (or between B and G) and adjust to get a sine wave
form on the CRO. (You can connect the pot in series with bypass capacitor, CS, as shown in the
diagram and try)
4] Measure the frequency of oscillation and compare with the theoretical value.
RESULT:

Viva Questions:
1) Draw the circuit of a Phase Lag Oscillator. Write / derive the design equations.
2) In the circuit you have studied, what is the phase shift provided by each stage? Do the practical
values match with theoretical values?
3) Draw the circuit diagram of a four stage phase lead oscillator and test its performance.
4) Write the circuit diagram of a Wien Bridge oscillator and explain its working.
5) What is the operating range of RC phase shift oscillators.
6)What is the phase shift produced by each stage ?
7)What is the difference between FET and BJT phase shift oscillator.

ADDON EXPERIMENTS
EXPERIMENT NO 1
AIM: To design and test a BJT-RC Phase Shift Oscillator for a given frequency
COMPONENTS/APPARATUS REQUIRED: Transistor BC107, Resistors 470Ω, 1KΩ 10KΩ

and 33KΩ, 3.3KΩ - 2nos and a 10K pot; Capacitors 100µf, 0.047 µf - 3nos, Power supply, CRO,
Connecting wires etc.
CIRCUIT DIAGRAM:
DESIGN: Let the required frequency of oscillation f = 500Hz

Amplifier Design: (Same as before but you are using a different transistor)
Let VCC = 12 V, For BC107, For IC = 4mA, hie=2.5K Ω and hFE= 150 (working value)
IB=IC/hfe=4000/150=26.67μA
To Find RE Let VE ≤ VCC/5 =2.0 V,
 RE = VE / IE = VE / IC = 2 / 4mA = 500Ω (IE ≈ IC). Use RE = 470 Ω
To Find RC VCE = VCC / 2 = 12 / 2 = 6 V and
Use RC = 1KΩ
To find R1 and R2: From the base circuit in the above figure,
We know VB = VBE +VE = 0.6 + 2 = 2.6 V;
With R2 = 10 KΩ , I2=VB/R2 =2.6/10K =0.26mA =260μA; I1=I2+IB= 260+26.67=286.67μA
R1=(VCC – VB)/ I1 =9.4V/ 286.67μA =32.79 KΩ Use R1 = 33 KΩ
To find By-pass capacitor CE:

RE
Let, X CE  at the given frequency (500 Hz),
100

1 RE 106
=>   4.7;  CE  F  67.726F
2fC E 100 2  500  4.7
Use CE=100 µF (Electrolytic)
Phase Shifting Circuit Design: The Oscillator circuit given here has a phase lead network.
Frequency of Oscillation of the Phase Shift Oscillator is given by
1 1 RC
f  . , where k  , and
2RC (6  4 k ) R
29
hFE  4k  23  ; R  Ri  Rx
k
Transistor Selection (A very important step):
Look at the circuit. We need Rx + Ri = R, which means value of R ≥ Ri.
For the component values of the circuit and with hie=2.5KΩ, Ri = hie||R1||R2 1.9 KΩ
So R > 1.9 KΩ. Use R=3.3KΩ
For this value for R, k= (1/3.3)=0.3 and we have hFE>121.2
Use a transistor that has hFE, min>121.2.
SL100 has hFE, min=50. Hence it cannot be used.
BC107 has its hFE in the range 120< hFE<480. That is its hFE, min =120
Hence use BC107 transistor.

Design of Phase shifter Capacitor:
Using the formula for frequency of oscillation and for f = 500 Hz, we get
1 1
C .  0.0359µF
2Rf (6  4 k )
Use C=0.047µF nearest available value in the Lab
For this capacitance value of f = 382 Hz
PROCEDURE:
1] Connect the circuit as shown in Fig. (1).

2] Switch on the D.C. power supply and check for the Q-conditions by disconnecting feedback
connection (Just remove the pot and leave it open).
3] Connect the Parameter VRC VCE VE ICQ VBE VB feedback circuit.

Observe the Assumed 4.0V 6 V 2V 4 mA 0.6 V 2.6 V output Vo on
Practical
CRO. Adjust the pot to get an
undistorted sine wave output on the CRO.
4] Measure the frequency of the output wave.
5] Compare the measured frequency with theoretical value.
6] With respect to output at point P, observe the waveforms at point Q, R and S on the CRO.
Measure and record the Phase shifts at Q, R and S with respect to P
For this, adjust the „Variable Knob‟ at the right end of the CRO such that the Peak to
Peak distance along X – axis for the o/p at P is some convenient value. This gives the Period „T‟
of the wave form in an unknown scale. One period means 360 degrees. Measure and record the
no. of divisions along X- axis (Time axis) for one period – „a‟. Now without altering anything get
the display of other wave form in the second channel. Measure the distance between the peaks of
these two wave forms – „b‟. Then the phase shift between the two wave forms is given by (b/a)
x360 degrees. For example, Let the distance between the two peaks of the first wave form be
adjusted to 6 divisions along the x – axis. Then distance between the peaks of the two wave
forms at P and Q respectively should be equal to1 division so that the phase shift between these
two wave forms is 600.
The wave form display on the CRO may be like the one shown in the figure above. Observe that
the wave form at Q reaches its maximum value first before the waveform at P reaches its
maximum value. The delay is 600. Q leads P by 600 or P lags behind Q by 600. By this method
you can verify whether the phase angle is Leading or Lagging. The phase sift network provides

overall 1800 and the remaining 1800 will be provided by the transistor in CE configuration to
satisfy the Barkhuasen criterion.
Alternatively, Put the CRO in X-Y mode with input to the First Channel being o/p at P. You
will get the elliptical patterns as shown below.
Compute the Phase shift using the formula  = Sin-1(B/A)

Here, you will not be able to identify whether the wave form in the other channel is Lagging or
Leading the P-wave form.
7]. Repeat the design for a different value of frequency (in Audio range only).
Compare the generated frequency with theoretical value.
RESULT: Write your comment on the result obtained
Viva Questions:
1) Draw the circuit of a Phase Lag Oscillator. Write / derive the design equations.
2) In the circuit you have studied, what is the phase shift provided by each stage? Do the practical
values match with theoretical values?
3) Draw the circuit diagram of a four stage phase lead oscillator and test its performance.
4) Write the circuit diagram of a Wien Bridge oscillator and explain its working.

EXPERIMENT NO: 02
SERIES AND PARALLEL RESONANCE
AIM: To wire series and parallel resonant circuits and determine their Resonance frequency f0,
band width and Quality factor.
COMPONENTS/APPARATUS REQUIRED: Resistors 22Ω, 47Ω 100Ω and 150Ω, Capacitor
0.22µf, Inductor 4.7 mH, Signal generator, CRO, Connecting wires etc.
CIRCUIT DIAGRAMS
DESIGN: (For both circuits) Resonant frequency is given by f0=1/ (2π√LC)

Givenf0=5 KHz. Assume C=0.22μF, this gives L=4.6mH
Choose L=4.7mH (Commercially available)
You can also use a Decade Inductance Box in place of the fixed discrete inductance.
PROCEDURE:
1. Make the circuit connections as shown in figures.
2 Set the signal generator to 2V peak to peak or any convenient value you want and vary the
frequency from 1 KHz to 10 KHz.(Also, predetermine fo, f1 and f2, see step 6)
3. Note down the corresponding output amplitude.
4. Plot the graph of frequency versus voltage
5. From the graph, noted down resonant frequency „fo‟.
6. Measure lower half power frequency „f1‟and upper half power frequency „f2 „.(These are the
frequencies at which the o/p amplitude is 0.707 times the maximum o/p for Series resonance and
1.414 times the minimum o/p for Parallel resonance)
7. Compute, Bandwidth BW = f2 – f1 = ….Hz.
8. Compute the Q factor, Q = f0/ (f2 – f1).
9. Repeat the experiment for R= 47 Ohms,100 Ohm and 150 Ohm and comment on the result.
TABULAR COLUMN:

Series resonance Parallel resonance

VS = volts VS = volts
f in Hz Vo in Volts f in Hz Vo in Volts
FREQUENCY RESPONSE:
RESULT: Write your comment on the result obtained.
Viva Questions:
1. Where actually the resonant circuits are used in communication engineering?

2. Which circuit is used practically – Series or Parallel?
3. What will be the order of practical Q – factor?
4. Write an equation for the equivalent resistance of a parallel resonant circuit at resonance in
terms of Capacitance, Coil Inductance and Coil Resistance.
5. Derive equations for f0, f1, f2 and Q.

EXPERIMENT NO: 03
NETWORK THEOREMS
A). THEVININ‟S THEOREM
AIM: To state and verify Thevinin‟s Theorem
Statement: Any linear, bilateral and passive network can be replaced across any two terminals of
interest by a single voltage source, Vth, called the Thevinin‟s voltage in series with an impedance
Zth, called the Thevinin‟s impedance. The voltage V th is the „open circuit voltage‟ across the
terminals of interest. (Voltage measured across the terminals of interest by disconnecting the
component connected across that terminal pair) and Zth is the impedance measured looking back
across the terminals of interest (after removing the component connected across that terminal
pair) after replacing all voltage sources and current sources by their internal impedances.
Alternatively, short circuit the terminal pair of interest and measure the short circuit
current, IN, through the short circuit. Then Zth = Vth / IN. Further, if we connect this impedance in
shunt with a current source having value IN, we get the “Norton‟s Equivalent” circuit. IN is called
the Norton‟s Current.
COMPONENTS/APPARATUS REQUIRED: Resistors - 100Ω - 8nos, 1KΩ - 8nos, 1.5KΩ -

1no, DC Power Supply, Multimeter, Ammeter 0 – 10mA, Connecting wires and Bread
board/Spring board with spring terminals
VERIFICATION OF THEVININ‟S THEOREM FOR A „T „NETWORK:
PROCEDURE:

All circuit setups needed are given in Figures 1 to 4
1) Measure IL, as indicated in Fig 2. If ammeter is not available, measure VL, the voltage across
the terminals A – B with load resistor connected. Find IL = VL/RL
2) Then open AB terminal and measure Vth as shown in Fig 3
3) From Fig 4, Measure Ith and find Rth as Vth/Ith . V= 10V is the supply voltage.
4) Draw the Thevinin‟s equivalent Circuit as shown in Fig 5. Measure I L and compare with the
value measured in step 1. If both answers are same you have verified Thevinin‟s theorem. For
your verification, the values have been calculated and shown in the diagram.
Take the two circuits given below and repeat the procedure. In both cases, make a prior numerical
computation and verify your answers.


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DON BOSCO INSTITUTE OF TECHNOLOGY

Kumbalagodu, Mysore Road, Bangalore - 560 074

ANALOG ELECTRONIC CIRCUITS LAB

SUB CODE: 17ECL37 SEMESTER: III

DON BOSCO INSTITUTE OF TECHNOLOGY

 Program Educational Objective 1: To prepare students for graduate and

 Program Educational Objective 2: To provide students with a foundation in

 Program Educational Objective 3: To train students with a broad-based

 Program Educational Objective 4: To inculcate in students professional and

 Program Educational Objective 5: To provide student with an academic

COURSE SYLLABUS AS GIVEN BY VTU

ANALOG ELECTRONICS LABORATORY

Number of Lecture 01Hr Tutorial(Instructions) + SEE Marks 60

Conduct of Practical Examination:

Department of ECE Page 7 17ECL37 Analog Electronic Circuits Lab Manual

Department of ECE Page 8 17ECL37 Analog Electronic Circuits Lab Manual

3. Clipping and Clamping Circuits 11

4. Common Emitter Feedback amplifier 16

5. Darlington Emitter follower 22

6. Series Voltage Regulator 27

7. Class – B push pull power amplifier 30

9. Characteristics of Junction Field Effect Transistor 38

10. Common Source JFET Amplifier 40

11. Characteristics of MOSFET 45

12. Phase Shift Oscillator 47

13. BJT-RC Phase Shift Oscillator 50

15. Network Theorems 56

Department of ECE Page 9 17ECL37 Analog Electronic Circuits Lab Manual

COMPONENTS/APPARATUS REQUIRED: Transistor SL 100, Crystal – 2MHz, Resistors

1. Wire the circuit as per the circuit diagram shown.

OBSERVATIONS: Table 1: D.C. Conditions:

RESULT: Write your comment on the result obtained.

Department of ECE Page 11 17ECL37 Analog Electronic Circuits Lab Manual

COMPONENTS/APPARATUS REQUIRED: Center tapped transformer 12 – 0 – 12 or any

FULL WAVE RECTIFIER:

Note:Connect Electrolytic Capacitor in Parellel with RL

Department of ECE Page 12 17ECL37 Analog Electronic Circuits Lab Manual

Calcualtions( Same for both with and Without CenterTap)

Department of ECE Page 13 17ECL37 Analog Electronic Circuits Lab Manual

Vrms=Vm/√2 ( Vm to be taken from CRO)

Vac=Vr(p-p) / 2√3 (Vr(p-p) from wavefrom on CRO)

Result Tabular Column:

Full Wave Rectifier FWR with Filter

Bridge Rectifier Bridge R with Filter

Department of ECE Page 14 17ECL37 Analog Electronic Circuits Lab Manual

Department of ECE Page 15 17ECL37 Analog Electronic Circuits Lab Manual

CLIPPING AND CLAMPING CIRCUITS

(A) CLIPPING CIRCUITS

Forward Resistance of Diode, Rf =100 Ω; Reverse Resistance of Diode, Rr =1MΩ

Department of ECE Page 16 17ECL37 Analog Electronic Circuits Lab Manual

3. CLIPPING TWO INDEPENDENT LEVEL OR SLICER

Fig.3 Circuit Diagram, Input – output Waveforms and Transfer Characteristic

Fig.4 Circuit Diagram, Input –output Waveforms and Transfer Characteristics

Department of ECE Page 17 17ECL37 Analog Electronic Circuits Lab Manual

Department of ECE Page 18 17ECL37 Analog Electronic Circuits Lab Manual

(B) CLAMPING CIRCUITS

Design: From the circuit of the clamper

Department of ECE Page 19 17ECL37 Analog Electronic Circuits Lab Manual

II) NEGATIVE CLAMPER :

Design: From the circuit of the clamper

Department of ECE Page 20 17ECL37 Analog Electronic Circuits Lab Manual

BJT CE FEEDBACK AMPLIFIER

COMPONENTS/APPARATUS REQUIRED: Transistors SL100 – 1, Resistors - 100Ω , 390,