An Operational Amplifier Architecture with a Single Gain Stage and Distor- [1MI1.

04]
tion Cancellation Preprint 3231

WURCER, Scott;
Analog Devices Semiconductor, Wilmington, Massachusetts, United States

Presented at
the 92nd Convention
1992 March 24-27
Vienna
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AN AUDIO ENGINEERING SOCIETY PREPRINT

 An Operational Amplifier Architecture with a Single
Gain Stage and Distortion Cancellation
Scott Wurcer
Senior Staff Engineer
Analog Devices Semiconductor
804 Woburn Street
Wilmington,MA 01887
USA
Abstract
Amplifiers with a single high gain stage are attractive for their simplicity
and excellent power/performance tradeoff, but their typically higher distortion
has limited their use in the audio field. Presented here will be a low-power single
-stage IC amplifier architecture that enables passive cancellation of distortion
(THD <-120dB @ 20kHz, 7V rms, RI = 600Ct). Classical output stage distortion
as well as nonlinear capacitive effects are addressed.

Introduction
It is now more than 20 years since activity started in the field of integrated
circuit (IC) op amps. Many of the basic circuit architectures and most of the
theory remains useful to this day. The now ubiquitous 741 and its descendents fall
in to the class of two-stage "pole-split" [1] amplifiers and still account for tens of
millions of sockets every year. Their basic slew-rate and bandwidth limitations
have been addressed in various ways [2,3,4], with the majority of high slew, wide
band applications going to BiFET or simple degenerated bipolar designs. On the
other hand, the requirements of high DC precision and low noise have been met
by the three-stage op amp introduced around 1969 [5], refined in 1980 [6], and
refined again in 1986 [7]. The now generic audio industry standard 5534 is
descended from this line, adding an all NPN output stage to compensate for the
poor PNP performance normal to a vintage 1975 bipolar process.

The original demand for the work presented here came from the automatic
test equipment (ATE) industry ; after all, it is their burden to test the
performance of today's high end systems. The requirements here are a
combination of the DC precision of the three-stage op amp and the speed and
dynamic characteristics of the single-stage amplifier. Current-feedback amplifiers
offer excellent performance with respect to speed but the DC precision
requirements eliminated them from consideration here. This combination of
requirements also make this work Of interest to the audio community.
 The amplifier architecture* described here is based on the single stage
folded-cascode amplifier, Figure 1. Described as early as 1971 [4], this general
circuit configuration has become very common in CMOS as well as bipolar IC
design. The simplicity of the signal path tends to give maximum bandwidth,
limited only by the speed of the process itself. When realized in a complementary
bipolar, (CB) process, employing either junction or dielectric isolation, the
circuit of Figure 1 can have a unity gain stable crossover (f_) in excess of 50
MHz. In a decompensated configuration, gain bandwidth products over 750MHz
are readily achieved. These amplifiers have become very popular for general
purpose video speed design, where dynamic ranges on the order of 60dB are the
norm, but they have drawbacks when the system requirements include extremely
wide dynamic range (>120dB) and very low THD+N, some of the main concerns
in audio design.

Problems to Overcome
One of these drawbacks is limited DC open-loop gain (Aol). At first one
might discount the the need for extremely high DC open-loop gain citing the fact
that in a closed-loop system the open-loop gain at a given frequency is what really
matters. For instance in the circuit of Figure 1, at best the Aol will be limited by
the parallel combination of the DC output resistances of Q4 and Q6 to
approximately 10,000. Of course if this gain is perfectly linear it will cause only
a benign inaccuracy in the value of closed-loop gain. Unfortunately, this is
usually not the case. This approximation is arrived at by simply linearizing beta
and Early voltage around a particular operating point. In reality changes in Aol
of 5-10% in producing several volts of swing into a modest load are common.
Even in a unity gain inverter a change of 10,000 to 11,000 in Aol over an output
swing of +10 to -10 volts limits THD to worse than -100dB. With 18 and even
20 bit performance required in many applications, the linearity of Aol will
remain a factor. One solution is to boost gain by adding an integrator stage
(Figure 2) and converting this to a two-stage amplifier, Cc now serving as the
pole-splitting capacitor. Referring to the numerator of equation 44 in [1],
Zl-gm(Q12) ''" (1)
Co
gm(Q12)'_> gm(Ql'2) '** (2)
Cc Cc
it can be seen that there is a right plane zero in the amplifier's transfer function at
(1) which is no longer insignificant unless it lies well beyond fp. (equation 2).
Phase margin therefore is severely compromised in this situation. Since Q1 and

* Pat Pending

2
Q2 idle at 900gA here, this would imply that Q12 run at 10mA or more, which is
not practical.

The second drawback, and a primary performance issue in audio

applications is distortion, a fundamental dynamic range limiter. I will not discuss
THD and IMD separately but rather remind the reader that in general
nonlinearity in an amplifier's transfer function will cause both THD and,IMD the
relationship between the two being one of proportion. Using the circuit of Figure
I, I will introduce the concept of referred to input (RTI) and referred to output
(RTO) distortion. In a simple analysis there are three major sources of distortion
producing nonlinearity: 1) in the voltage to current conversion of the first stage
(gm), 2) the nonlinear impedance, both real and imaginary (capacitive), at the
gain node (B), 3) the nonlinearity in the output stage transfer function. It is
important to note that 1 and 3 for bipolar are inherent in the logarithmic nature
of transistors, while 2 can be affected by process or architectural limitations. For
the discussion here, RTI distortion consists of only component 1, RTO
components 2 and 3.

The differential current flowing out of a differential pair of undegenerated

bipolar transistors (Io), as related to the differential input voltage (Vin), has the
form:
[-

Vinq
Io = Ib [tan
0Io _ Ibq
gm= 3vin 2kT ... (4)
When linearized around the origin one gets the familiar result, equation (4). As
the current needed to charge Cc increases with frequency so does the input error
signal (3) must then be solved exactly (usually by a power series) to arrive at the
voltage to current transfer of the first stage. What is called the slew-limit is
reached when either Q1 or Q2 takes all the available current (I1).

Some component of Cc will consist of junction capacitance usually a strong

function of bias voltage. This will generate nonlinearity in the displacement
current in Cc. This current depends on the rate of change of the output voltage,
and therefore is a component of RTO distortion. The voltage from node B to the
output is a function of the base to emitter voltage (Vbe) of Q8-Q11. The change in
their Vbes with output voltage or current constitutes an error in the input to
output voltage transfer of the output stage. In a closed-loop application, this
voltage must be corrected by displacement current in Cc. The functional form of
the displacement current in Cc is related to the derivative of the hyperbolic
tangent function, when the output devices are bipolar transistors, as is the case
here. The resulting error voltage reflected to the input is a series of inverted
cusps, one at each zero crossing of the output. Thus the origin of the term
crossover-distortion. The magnitude of these is related to the standing current in
the output stage, with a reduction in distortion achieved by increasing this
current.

Distortions Defined
! have applied a set of values (Table 1) to the circuit of Figure 1 for use in
two common applications, a differential receiver (noise gain = 2) and a high gain
preamp (noise gain = 101) to show the effects of these three distortion
components. Figures 4a and 4b show distortion (by simulation) relative to a 10V
p-p output signal into a 600fl load, plotted vs. frequency. As would be expected,
the distortion at the output of the gain of 100 circuit is larger by a factor of 34dB
(101/2). Also, because slew-limiting is modeled in even this simple case, slew-
induced distortion is manifested as a dramatic increase in RTI distortion as is
clearly shown, here at just over 400kHz.

I1 = 1.8mA
I2,I3 = 2.3 mA
I5,16 = 500gA
Cc = 50pF

Table 1 Values for Simulating Circuit in Figure 1

Several other principles are shown here. Before slew limiting the RTI
distortion increases at 60dB per decade of frequency. This occurs because as the
differential input voltage increases in magnitude at 20dB per decade, the third
harmonic component (dominant here) increases at three times this rate
(log(x)3=3.1og(x)). The RTO errors, on the other hand, since they are constant
vs. output level, get reflected back to the input in proportion to the impedance of
Cc or at 20dB per decade of frequency.

The 100MHz bandwidth of this amplifier gives a maximum RTI distortion

of -110dB, even under these fairly harsh conditions. So it is reasonable to say that
RTI distortion can usually be dealt with by having sufficient gain-bandwidth
product at frequencies of interest, while maintaining a sufficient margin of safety
with respect to slew-rate (a factor of three seems adequate). The previously
mentioned 5534 and [7] are in this category.

The RTO distortion is another matter. From Figure 4b one can estimate
that fp. would have to be on the order of 3GHz in order to use "raw" feedback to
keep THD under -110dB at 20kHz at a gain of 100. Even at a gain of 2 a 100MHz
f_ is required to meet this same level of performance. Of course the bias levels in
the output stage could be increased, but this would mean wasted power when
maximum performance is not needed.

A New Circuit Architecture

The solution to both the RTI and RTO performance issues is found in a
combination of a new circuit architecture together with one of today's wideband
CB processes. The new amplifier, Figure 3a, was developed to deal with most of
these dynamic range limiting issues. With some imagination, one can find all of
the elements of a three-stage low-noise amplifier here: a resistively loaded first
stage (Q5-6,R1-2), a current mirror loaded second stage (Q9-10,Q15-17) and an
integrator (Q18-19). But now there is just one output node, B (Figure 3b), and
the amplifier acts as if there is a single gain stage. Frequency compensation
consists of a single capacitor (Cc) to ground, f_ being set at 100MHz. It is easy to
show that the signal transfer (Figure 3b) from the collectors of Q3 to Q4 to node
B does not have the right plane zero (equation 1), but now it appears at node C.

Some additional frequency shaping (beyond 15Mhz) is employed (R3 and

C1). There are two major reasons for the inclusion of R3 and C1 in this
realization. First, this particular amplifier was designed to achieve an input
referred noise of 0.gnVpdHz. The large geometries required for the input devices
causes loss of phase in the first stage. Secondly 100MHz is just beyond the safe
region for f_ in this process. This pole-zero network forces the amplifier to
actually crossover at -32MHz with about 30 degrees of phase margin.

As was previously mentioned this amplifier has an input referred voltage

noise of 0.9nVpJHz. A side benefit of the single-stage topology is that the input
noise of the amplifier is flat with respect to frequency out to beyond 1MHz, a
result difficult to achieve in a three-stage amplifier. Figure 6 compares this
amplifier to the 5534 in this respect.

In Figure 3b, driving node C forces nodes A, B, and C, as well as the

output to all track each other closely. The Aol is then limited by the matching of
the output resistances of Q3 and Q4 rather than by their absolute values. The
loading of node B by the output buffer has been reduced by employing a triple-
Darlington configuration (Figure 3a) with input devices, Q20 and Q26,
bootstrapped to the output. Their operating points are therefore independent of
output voltage and loading is ~ betas3' RI or 2>°_910
_ for RI = 60092 The matching
of like devices (NPN to NPN or PNP to PNP) with equivalent geometries is the
great forte of IC technology and an Aol of >5o106 is typical here. Another benefit
of nodes A and B tracking is the elimination of the distortion due to the junction
capacitance at these nodes. This error becomes common-mode and is cancelled by
the inherent symmetry of the circuit.

Q5 and Q6 (Figure 3a) are operated undegenerated for low noise and are
cascoded by Q3 and Q4 for high common mode rejection ratio. Although not
shown here, input bias current compensation is used to reduce DC errors due to
source resistance. DC performance is summarized in Table 2.

Vos 251xV
Ib 250nA
PSRR 126dB
CMRR 126dB
Aol 134dB
Noise @ lkhz 0.9nV/x/Hz
Noise 0.1-10Hz 50nV p-p

Table 2 Summary of DC Performance

Distortion Cance!llttion
At high closed-loop gains, RTO distortion still needs to be dealt with. In a
general purpose IC op amp an output stage with sufficient standing current to
drive 60011 with RTI limited distortion was not considered practical in a general
purpose IC op amp. Explicit error correction [8] in the output stage or the use of
nested-feedback [9] depart from the simplicity of the basic amplifier topology. A
key observation leads to the result that the output stage induced distortion can be
substantially reduced by the addition of a single capacitor to the basic circuit. As
was previously mentioned, the RTO distortion is due mainly to displacement
current in Cc caused by modulation of the voltage from node B to the output. An
equivalent displacement current if injected into node A will, by the action of the
current-mirror (Q5-6), cancel the effects of the current in Cc.

The addition of Cn, Figure 3b, achieves just such a result. Node A roughly
follows the output, the difference being the same troublesome output error
voltage. Cn therefore has only the error induced displacement current flowing in
it and no signal current. In this way Cn effects cancellation of the output error
while not appearing in the signal path. A side benefit of this is that the effects of
dynamic output impedance are also cancelled. Figures 7a and 7b show this for an
amplifier connected in a closed-loop gain of 1000 with its output current ramped
from +10mA to -10mA. The addition of Cn causes almost complete cancellation,
Figure 7b, yielding a nearly load independent output voltage. Figure 8a shows the
distortion cancellation at work. The amplifier is connected as in figure 4b
(Gain=100) with a 7V rms into 600gl output at 20kHz. The distortion cancellation
achieves a 24dB improvement, to ~-105dB THD, where the RTI limit is ~-110dB.
Figure 8b shows the reduction in output impedance for the same conditions.

Conclusion
Presented here is a new amplifier architecture, with properties that make it
less susceptible to the most common distortion producing mechanisms. Also
presented are performance results for a fully integrated embodiment of this
amplifier. Further work should include the extension of these ideas to discreet
power amplifier design where the possibility exists for new levels of performance
from low feedback designs.
References
[1] Solomon, J., "The Monolithic Op Amp: A Tutorial Study," IEEE J. Solid-
State Circuits, vol. SC-9, pp. 314-332, Dec. 1974.

[2] Solomon, J., et al, "A Self Compensated Monolithic Operational Amplifier
with Low Input Current and High Slew Rate," ISSCC Digest of Tech. Papers, pp.
14-15, 1969

[3] Hearn, W., "Fast Slewing Monolithic Operational Amplifier," IEEE J. Solid-
State Circuits ,vol. SC-6, pp. 20-24, Feb. 1971

I4] Gray, P., Meyer, R., "Recent Advances in Monolithic Operational Amplifier
Design," IEEE Trans. Circuits Syst., vol. CAS-21, pp. 317-327, May 1974.

[5] Erdi, G., "Instrumentation Operational Amplifier with Low Noise, Drift, Bias
Current," Northeast Res. Eng. Meeting Res. Tech Papers, Oct. 1972

_6] Erdi, G., et al, "Op amps Tackle Noise and for Once, Noise Loses,"
Electronic Design, pp. 65-71 Dec. 1980

C7] Erdi, G., Cakhnokhi, Y. "A Bipolar Op Amp with a Noise Resistance Less
Than 50_," ISSCC Digest of Technical Papers, pp. 14-15, Feb. 1986

C8] Hawksford, M. "Reduction of Transistor Slope Impedance Dependent

Distortion in Large Signal Amplifiers," J. Audio Eng. Society, vol. 36, pp. 213-
222, Apr. 1988

[9] Cherry, E. M., Cambrell, G.K., "Output Resistance and Intermodulation

Distortion of Feedback Amplifiers," J. Audio Eng. Society, vol. 30, pp. 178-191,
Apr. 1982
 Q3 _..__ QIO

+IN -IN _ I_

_ QII

I1 Q$ I4

· Vss

Figure 1 Simplified Schematic of Folded-Cascode Amplifier

" /
/
'_
_/
__/
'_T_7/
/ //J
vc
f-d--r,,
_'°

Figure 2 Folded-Cascode with Integrator

10
 R1 R2 I2 R34 _ [_VCC

1,1K 1.1K 7.63K I4

Figure 3a Complete Schematic (Signal Path) of this Amplifier

11
 : R2 R11
Cn 15

Q3
_'_Q4 _ _1_ Q7 Qlp

+IN

1 Q Q7 QII

_ ' w _ _ VSS

Figure 3b Simplified Schematic of this Amplifier

12
 2k_ 2k_

4a 4b

Figure 4 Test Circuits for Distortion Data in Figure 5

13
10' / -5534-

8- _f ' _ ThisAmplifier-

0 i
Oe+O 1e+6 2e+6
frequency,Hz

Figure 6 Noise vs. Frequency

14
 011 .....L[ ![__:.L_]JII[[]LJ'I'LH...... ..... II .L.:L._
[_LU.I:_
l ILl
.........
L.....__LL._L_EL.]:_XLI. J.Z].]LLLLLLEEEY_ Y----EEttXtZXt]X: .ttttLt_.LtEt]ttttEtXtt.:t/..tZE]E]XtlL
L ..:_._.........L.._..:I_____.L_LLI_____.I
......................
L.LLL.........__. L:_._.L_I__ 1.:L:I._I. I..........
I__..,/II._.L_I.I..LI

......................... .[------,_:_.s .............

c- : i'_'_'_::_::_-'
:::::::::::::::::::::::::::::::::::
l ...__L_l._]. I H '................
.................
I-'-J--']-_ I'-Z ...........
I_
_ -100 _., ,_....__
-'"'--:-'""__':t'_ '['.(_ I 1 LIlII I /T 1...111111
'_ [ [_ [ ] J....J, 1-," _:""__i I ] L,2z¢1'{ ............ .._...I.......... L...l...,.Ll...IJ_
::::::::::::::::::::::::::::::::::::::::: _ ..
,..............
[:.:__:_L
L.]_:._J ;:;].__.[._.JI_.....:J ;;;L;.J[_;:'J3.._lJJ;];J]JJ.EJ :
.........
_]:::'F]:]] :;::J::--l":
.._..._.;;!;...I
"-'-i-'-t-'"i'_ ] I .l.,.......... , I , LI..LI ............
'...................-_'3'3'_FI
-200 03 104 05 10 6
Frequency, Hz

Figure 5a Distortion of circuit in Figure 4a

15
 o_ [ I illlll ___J I I I Illll I I l_llllil
========================================
::::::::::::::::::::::::-
L__l I [ I lll[] ___L_Z_I I 1111[ L_J_,,( IIIII1
I.........
ZX.._Z[ZIZ[[][]X[IZZ:
...........
I-_Z[]Z]Z[X][[[[ZZiZ]_-1-_'-iIii--]ii]ii[ii[11
....
[ I I IIII

_ ' .....[w-t
ZZiiIZ-JlZ[][H[I[Y'"'J_TZY
1_illlL__',-i '_'j]'"j['"'lJ[[[[..._
Ill_l ....................
....................
;__..]]]
_-
_1 m ..........
*..........
3-
._s,_l- I1'] Illlll ' 'l'" I Illllll I I"1 I1111'1
_o3 10 4 10 5 10 6
Frequency, Hz

Figure 5b Distortion of circuit in Figure 4b

16
Figure 7 a
Upper trace - Error signal at Output without
Cn 50mV/div.
Lower trace - Current Into Output 10mA/div.

17
Figure 7 b
Upper trace - Error signal at Output with
Cn 50mV/div.
Lower trace - Current Into Output 10mA/div.

18
 RANGE: -27 dBV STATUS: PAUSED
A:MAG RHS:lO0
354.8
mVPms
......... : ......... :......... i ......... :......... '..................................................

dB
/OlV

35. -18
tlVrms
START: 0 Hz SW: 954.85 Hz STOP: _00 000 Hz
B: STORED RHS: lO0
354. S
mVrms
............................. i.....................................................................

dB

35. ,18 .
uVrms L_ i
START: 0 Hz BW' 954.85 Hz STOP: _00 OOO Hz
X: 60000 Hz Y: 46.69 mVrms

Figure 8 a
Upper trace - Distortion without Cn
Bottom= .135.4dB
Lower trace - Distortion with Cn
Bottom= .135.4dB

19
 RANGE: -39 dBV STATUS; PAUSED
A: MAS RMS: 50
3i6.2
uVrms

5 ................. ' ' · ·

dB

3. i62
START: i OOO Hz BW: 250 Hz STOP: 101 000 Hz,
0: STORED RMS: 50

uVrms

5 ..........
dB
IDIV

3. _62
START: i 000 Hz BW: 250 Hz STOP: 10_ 000 Hz
X: _O00O Hz Y: 29.89 uVrms

Figure 8 b
Upper trace - Output Impedance with Cn
Bottom = .024gl
Lower trace - Output Impedance without Cn
Bottom = .024f_

20