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ISSCC 2019 / SESSION 1 / PLENARY / 1.3
1.3 Integration of Photonics and Electronics
Meint Smit,
with Kevin Williams, Jos van der Tol
Institute for Photonic Integration (formerly COBRA Institute),
Eindhoven University of Technology, Eindhoven, The Netherlands
Preamble
The market for photonic integrated circuits (PICs) is rapidly
growing. Photonic integration which is now the dominant
technology in high-bandwidth and longdistance
telecommunications is increasingly applied to shorter distances
within data centers. Now, it is set to become also dominant in many
other fields: PICs offer compelling performance advances in terms
of precision, bandwidth, and energy efficiency. To enable uptake in
new sectors, the availability of highly standardized (generic)
photonic-integration-platform technologies is of key importance, as
this separates design from technology, reducing barriers for new
entrants. Another major challenge is low-cost energy-efficient
integration of photonics with the electronic circuitry that is used for
driving and controlling the photonic IC and processing its
information. Today, the major platform technologies are indium
phosphide (InP)-based monolithic integration and silicon (Si)-
based photonics. InP technology offers integration of the full suite
of photonic components, including lasers, optical amplifiers, and
highperformance modulators. While Si photonics offers better
compatibility with CMOS process facilities, it lacks the most
important photonic building blocks: lasers and optical amplifiers. In
this paper, we describe the current status and directions for future
developments of InP-based generic integration, and we compare
the potential of InP photonics and Si photonics for integration with
controlling electronics. In what follows, we will focus in Section 1
on similarities and differences between InP and Si photonics. In
Section 2, we will give a concise overview of the present status of
this technology and how it compares with Silicon photonics. In
sections 3 and 4 we will discuss membrane-based technologies
which support efficient integration with electronics.
1.0 Introduction: Similarities and Differences
Between Photonic and Electronic
Integration
From the beginning, in the first publications on integrated photonics
(known then as “integrated optics”), it was assumed that photonic
integration would follow the same path as microelectronic
integration [1, 2]. Indeed, at this early stage, we see a lot of
similarities. Figure 1.3.1 shows a clear exponential increase of
photonic-chip complexity (measured as the number of components
integrated on a single chip), similar to Moore’s Law in electronics
[3].
Today, the most sophisticated circuits including lasers, modulators,
detectors, and multiplexers have more than 1,500 components on
one chip [4]. Currently, the number of components per chip is
constrained by electrical connectivity and thermal management.
For the future, membrane technologies, addressed later in this
paper, offer a route to the size and energy reductions required for
higher-density integration.
1.1 Semiconductor Integration Technology
Figure 1.3.2 highlights some of the milestones which have been
reached in both electronic and photonic integration. Their
development follows largely the same path, with a delay of about
30 years for photonics. The starting point for microelectronic
integration was the invention of the transistor [5, 6], a compact
February 18, 2019 / 10:40 AM
semiconductor amplifier which replaced the bulky vacuum tube.
For photonic integration it was the invention of the semiconductor
laser, which replaced the bulky gas and doped-glass solid-state
lasers [7]. In the early years both the transistor and the
semiconductor laser were used as discrete components. In 1958
Jack Kilby succeeded to integrate a circuit containing several
transistors in a silicon substrate [8]. Later, other technologies were
explored, but in the eighties CMOS became dominant. In photonics
a first integrated circuit consisting of a laser integrated with a
modulator was reported in 1987 [9].
1.2 Generic Integration Technologies
In the early years of both microelectronic and photonic integration
design and technology development were closely connected, and
chip designs were technology specific. With increasing circuit
complexity, this close connection between design and technology
became increasingly difficult. Correspondingly, an important step
in the development of semiconductor integration technology was
the introduction of generic integration processes, technologies that
allowed for decoupling of design and technology by offering chip
designers a small set of well-defined standardized building blocks
with which they could design a broad range of application-specific
circuits. This approach to microelectronics, first introduced by
Carver Mead and Lynn Conway [10], caused a revolution in IC-
design and opened the way to CMOS-VLSI. An important
advantage of designing with standardized building blocks is that
they enable reuse of components and sub-circuits that are made
available to designers through a so-called process design kit
(PDK). Another advantage is that a number of designs from various
designers can be combined on a so-called multi-project wafer
(MPW), which leads to a large reduction in the costs of prototyping.
In photonics, this approach was pioneered by the COBRA research
institute, now known as the Institute for Photonic Integration, at TU
Eindhoven [11]. Later, in 2008, it was adopted by the ePIXnet
Network of Excellence [12], which brought Europe the world’s first
photonic MPW runs in indium phosphide (InP) and silicon
photonics.
Today, InP-based monolithic integration and Si photonics are the two
major integration technologies in photonics. In both of these access to
MPW runs is currently offered by industrial and semi-industrial foundries.
The advantage of Si Photonics is that it is produced in a CMOS foundry,
which provides a wellcontrolled and rapidly scalable fabrication
environment. As the substrates for Si are significantly larger than those
for InP, the potential for scaling of Si to high volumes seems superior.
But, Si photonics is lacking light sources and amplifiers which limits its
potential for large scale integration. To resolve this, work on integration
of InP-based light sources and amplifiers on silicon substrates is
underway, but formidable manufacturing challenges remain. Overall, InP-
based monolithic integration currently offers the most comprehensive
range of photonic functionality with high-energy-efficiency quantum-well
lasers and modulators, as well as optical amplifiers, detectors, and a
range of passive components for creating interferometers, combiners,
and modulators. An important milestone on the road to mature integration
technology is the reduction of killer-defect density to a level < 1 /cm 2, for
silicon electronics this milestone was reached in 1987, and for InP
photonics 23 years later, in 2010 [13].
1.3 Differences Between Electronic and Photonic
Integration Technology
Although microelectronic and photonic integration show a lot of
similarities, there are also marked differences. Photonic building blocks
are larger and active building blocks, such as optical amplifiers and
modulators, operate at much higher power levels than transistors.
However at the sub-system level, the electronic amplifiers currently
DIGEST OF TECHNICAL PAPERS • 29
operate with three to four times more power than the photonic devices to output ports, such that they comply with standard packaging and
which they are connected. The footprints for the basic active components test equipment. This adds to lowering access barriers even further
themselves are comparable. As well, the electronic-driver areas are often to make PIC technology part of the mainstream semiconductor
dominated by passive components such as resistors, capacitors, and the industry.
input/output connections, and furthermore, photonic circuits include
redundant chip area for cross-talk mitigation, waveguide bends, and PDK development in both InP-based as well as other material
electrical connections. A more appropriate basis for comparison of high- systems such as silicon photonics started from photonic design
performance active photonic devices is with RF and analog electronics. software because of the different requirements that PICs impose on
There is also an important difference in terms of operational capacity and the mask-layout and simulation software (for example, with a need
technology maturity; the higher wafer throughputs in electronic circuit for smooth curves and optical simulations). Today, it can be
manufacturing enables a faster manufacturing learning curve when observed that photonic design is being integrated into traditional
introducing new technology nodes. electronic design automation (EDA) software such as tools from
Mentor, Cadence, and Synopsys. These EDA vendors offer a large
Nanophotonic technology offers an order-of-magnitude power- pool of capabilities which are also relevant for PICs. With increasing
dissipation-level reduction as well as footprint reduction [14,15]. Both complexity of PIC designs, the need for verification with design-rule
become critical as designs become thermally-constrained. While checking (DRC), and layout versus schematic (LVS) is becoming
photonics will not scale to the same component densities seen in CMOS mandatory, and not all current PDA tools provide such functionality.
electronics, the application of membranebased technologies creates a A remaining challenge is the need to address co-simulation of
roadmap to the level of tens of thousands of components per chip, as electronics and photonics as is required in lasers, detectors, high-
indicated in Figure 1.3.1. This raises new challenges in terms of speed modulators, and modulator drivers.
mechanical, thermal, and electrical design.
2.2 Present-Day Capabilities of Photonic InP
2.0 Generic InP-Based Integration Technology Foundries
An extensive description of InP-based generic integration technology is The example shown in Figure 1.3.5, a widely tunable laser,
given in [16]. Here, we will provide a brief overview of this technology illustrates many of the present capabilities of available InP foundry
including some recent progress. Figure 1.3.3 shows a relationship platforms. It consists of a ring resonator with a semiconductor optical
between generic electronic and photonic integration technology. amplifier (SOA), for providing gain, and three cascaded asymmetric
Electronic circuits are composed of a very small set of basic building Mach-Zehnder interferometer (AMZI) filters, for providing
blocks: transistors, capacitors, and resistors, and electrical wavelength selection. The three Mach-Zehnder filters each consist
interconnection lines. In photonics, we can do something similar. Light of two so-called multi-mode interference (MMI) couplers and two
has an amplitude, a phase and a polarization. These properties can be electro-optic phase modulators. The filters have periodic
wavelength responses with a ratio 1:2:4, which can be shifted with
manipulated with an optical amplifier, a phase modulator, and a the phase modulators. By appropriate control of the phase shifters,
polarization converter, respectively. With a process in which we can the laser wavelength can be tuned over more than 70nm, as shown
integrate these basic building blocks with waveguides and passive at the bottom right of the figure. The laser signal is coupled out of
components, we can realize a large variety of circuits, including the ring with an MMI power splitter. In total, the laser consists of 15
pulsed and tunable lasers, transmitters and receivers, and a variety building blocks: an SOA, 7 phase shifters, and 7 MMI couplers.
of sensor-readout circuits. Output power can be increased by including a booster output
amplifier. The overall size of the laser is 1.5×3.5 mm2; 4 of them will
In 2008, TU Eindhoven started providing external designers with
fit into a MPW-cell of 4×5 mm2.
open access to its generic foundry process in the framework of the
ePIXnet network of excellence, which had adopted a foundry model Several hundreds of different MPW cell designs have already been
for photonics [12]. In the next decade, a number of large R&D processed by the two InP foundries in more than 30 MPW runs, with
projects (EuroPIC, PARADIGM, MEMPHIS) worked on transferring PIC designs for telecommunications, data communications,
the foundry approach from the university to an industrial microwave-photonic applications, fiber sensor readouts, metrology,
environment. Presently, two European foundries provide medical diagnostics, gas sensing, and automotive applications.
commercial access to InP-based generic photonic integration
processes. Thus far, they are the only open-access generic InP- These foundries provide optical amplifiers with 70 to 90cm -1 gain and
foundries in the world providing pre-specified building blocks in a user defined length, various types of tunable lasers, electro-optical
Process Design Kits. Figure 1.3.4 shows the basic building blocks phase modulators for 20Gb/s operation, thermo-optic and current
which are available on these photonic integrated circuit (PIC) injection modulators, high responsivity photodetectors (with low
platforms. dark currents and >30GHz bandwidth), high and low confinement
waveguides (with losses < 2dB/cm), and a variety of passive
2.1 Process Design Kits (PDK) devices: wavelength demultiplexers, MMI couplers and reflectors,
A PDK for photonic integrated circuits is very similar to those for spotsize converters, and polarization converters. A more detailed
traditional CMOS, containing information about the fabrication description of the building blocks available in the InP foundries in
process, design rules, mask layers, models for simulation, and 2018 is provided in the JePPIX1 roadmap 2018 [17].
predefined components. But, due to the nature of integrated
Recent innovations include the introduction of 192nm scanner
photonic components, many of the predefined components come in
lithography for precision waveguide fabrication [18] in low-excess-loss
the form of sophisticated modules for generating the mask-layout.
(< 0.2dB) arrayed waveguide gratings [19]. High accuracy methods to
These are somewhat comparable to parameterized cells (PCells) as
automate in-line measurements for gain [20], loss [21], and intra-cavity
used in electronics, but more advanced as these modules can be
reflections [22] have been devised to enable both process optimizations
optically defined and take material and process properties from the
and statistically representative component models. High speed
PDK to generate and optimize these components. Further, photonic
electroabsorption modulators have now been demonstrated, with
PDKs contain templates for packaging and testing of the designed
55GHz bandwidth [23], and 112Gb/s operation with polarization
PICs. These templates define the electrical and optical input and
multiplexed electroabsorption modulators [24]. In the future,

1
JePPIX is the Joint European Platform for Photonic Integration of Components and InP and TriPleX-based Photonic Integration are cooperating on the establishment
Circuits, a consortium in which Europe’s key players in of an open-access foundry infrastructure (www.jeppix.eu).

30 • 2019 IEEE International Solid-State Circuits Conference 978-1-5386-8531-0/19/$31.00 ©2019 IEEE


improvements of platform capabilities are envisaged through enhanced
efficiency, precision, and bandwidth of building blocks, and introducing
statistical performance data into the PDK.
3. Wafer-Scale Integration of Photonics and
Electronics
As InP integrated photonic circuits increase in complexity, the wiring
density between photonic and electronic components and thermal
loading become more critical. Semiconductor lasers are typically a few
hundreds microns long for widely tunable lasers, with the possibility of
reducing to 100μm within integrated circuits [25]. Techniques to create
shorter electrically pumped lasers and light sources with lower energy
consumption are addressed in section 4. Eliminating non-functional area
is attractive for increasing functionality, but leads to challenges in terms
of optical, electronic [26], and thermal [27] crosstalk, as well as optical,
electrical, and thermal connectivity. A broad range of strategies have
been identified for chip and wafer scale connection, and the integration
of photonic and electronic circuits. These range from the full embedding
of a subset of key photonic functions into electronics, through to 3D
integration, hybrid integration, and heterogeneous integration. Figure
1.3.6 illustrates a few of the approaches that are being explored.
The conceptually simplest approach from the electrical perspective is to
integrate electronics and photonics without the light source in one chip
(Figure 1.3.6d), with hybrid connection to an InP laser as depicted in
Figures 1.3.6e and 1.3.6f. Hybrid integration is defined here as the
assembly of pre-fabricated chips, involving either a sub-micron
alignment requirement for chip to substrate assembly, or the use of
larger chips incorporating mode adaptation. The red circles indicate the
positions were accurate alignment and efficient coupling is needed. In
this approach, high-speed RF connections between modulators,
detectors, and drivers can be combined within the same chip. However,
this does not address the challenges associated with photonic
connection and impairments introduced with imperfect interfaces in the
photonic circuits, and there are open questions on how scalable such
approaches will be with many light sources and amplifiers per chip. 3D
integration using through-silicon vias offers two dimensional grids of
bond pads and a route for thousands of electrical connections, but the
use of large bond pads limits component density on the photonic side,
and potentially on the electronic side, as well. Many of the proposed
solutions using Si waveguides use dielectric claddings, which will
obstruct heat removal.
Heterogeneous integration offers a highly scalable route to combine
photonics and electronics, and can be implemented at the wafer scale.
Figure 1.3.6g shows an example in which InP dies with an unprocessed-
active-layer stack are bonded on top of a processed silicon photonics
layer. The InP substrate is removed after bonding, and the active
components (lasers or optical amplifiers) can be processed at the wafer
scale. Because the processing is accurately aligned to the underlying
silicon photonics layer, so are the lasers. However, vertical coupling
between the active InP and the passive silicon layer introduces losses
and potentially reflections, as well. Adding electronics as a third layer in
this scheme increases the complexity of processing and is further down
the roadmap.
An alternative approach is heterogeneous integration by top-down
bonding of processed InP wafers or dies on CMOS wafers, removing
the InP substrate and wafer scale processing of the electrical
interconnections with vias through the optical and thermal-isolating
bonding layer, without the need for enlarged bond pads, saving surface
area. The approach is called IMOS (InP Membrane On Silicon), as
depicted in Figures 1.3.6h and 1.3.6i. In this arrangement, doublesided
cooling is required to transfer heat from both the photonic and the
electronic layer. The difference with Figure 1.3.6g is that the photonic
circuit is not partitioned between an active InP and a passive silicon layer
which must be processed separately. All optical interfaces are
1
implemented within the monolithic photonic circuit and can, therefore,
exhibit low loss and low reflection. The electrical connections can be
reduced to the micron-scale thickness of the InP integrated photonic
membrane and the bonding layer, thus reducing parasitic capacitance
and increasing energy efficiency.
Membrane-based photonic integrated circuits offer a powerful
means to create a photonic plane over an electronic control plane
as the substrate can be removed to reduce parasitics, enabling
thermal and electrical vias, and ensuring the most intimate heatsink
connections. As processing of the light source and full photonic
functionality is separated from the electronics, the photonic circuits
can be created without compromising the electronics. Similarly, the
electronic fabrication flow is not compromised by the photonics.
Co-designed photonics and electronics is anticipated to enable a
step change in both efficiency and function. The shorter connections
between detectors and amplifiers enable lower parasitic loss [28]
and energy efficiencies through the removal of impedance matching
networks. The closer placement of electronic and photonic chips
already allows for higher numbers of electronic connections and
functions, such as digital to analog conversion to be performed in
the optical domain [29, 30]. So far these techniques have been
studied for single elements and devices, enabling connections
between co-designed chips which are placed in close proximity, but
larger circuits implementing on-chip multiplexing will require more
electrical connections. One example is sensor and communication
chips which increasingly employ multiple wavelength channels.
While this is straight forward to implement from a photonic
perspective, there are considerable challenges from an electronic
perspective due to higher levels of control complexity and crosstalk.
Figure 1.3.9 shows a cross-section for the methods under
development. A polymer layer (Benzocyclobutene (BCB)) is used for
the purposes of both planarization and adhesion, but also provides
optical, thermal, and electrical isolation. Creating vias for electrical
signal routing and thermal management requires the removal of the
substrate. This photonic-electronic integration, also known as
photronic integration, uses processed PIC wafers and ASIC wafers.
Si BiCMOS wafers provide mechanical support for the InP wafer
membrane which is several microns in thickness.
In this approach, the full suite of generic building blocks is available,
requiring no re-engineering of the photonics. Similarly no bespoke
processes are required from the electronics, offering a “zero-
change” integration approach. The fabrication challenges are
therefore primarily at the interface, creating fine pitch vias. Design
challenges address the re-engineering of co-designed circuits to
take full advantage of circuit-level design freedom. With such
intimate integration, we can avoid the use of transmission lines,
resistive terminations, and uncontrolled inductances, for example,
from bond wires, avoiding the capacitance of bondpads. The
heterogeneously integrated combination of stateof-the-art industry-
sourced photonics and electronics is expected to deliver
considerable speed and energy improvements over co-packaged
systems. Moreover, it offers the possibility of creating “smart
photonic building blocks”, such as lasers and modulators which are
integrated with monitor diodes and electronic control circuitry,
maintaining the building blocks at the correct operating point despite
variations in temperature and fabrication process parameters.
4. Silicon-Based Nanophotonic InP-Membrane
Platform (IMOS)
Further innovation is feasible by moving to a nanophotonic
integration platform. This enables the monolithic combination of the
new functions achievable with sub-wavelength photonic
DIGEST OF TECHNICAL PAPERS • 31
 components with the full range of active devices such as lasers,
amplifiers, and efficient modulators and detectors. This technology
evolution is captured in Figure 1.3.10 and described below.
The membranes used in the photronics approach have the same
micron-scale waveguide features as used in current manufactured
PIC products. However,
removing the substrate creates considerably more design flexibility
for future technology nodes. As can be seen from Figures 1.3.9
and 1.3.10, the photonic waveguides can now be completely clad
between low index materials such as BCB, SiOx, SiNx, or even air.
This enables far tighter confinement of light, so that the
waveguides and the components based on them can become
much smaller, as illustrated in Figure 1.3.10. This enables a higher
integration density, and offers the potential for new forms of mode
adaptation, and the introduction of precision surface gratings for
coupling light in and out of the PIC.
A nanophotonic IMOS-node might become the successor of the
microphotonics IMOS-node described in the previous section. It will
support higher integration densities and better energy efficiency for
short-range communications as is required in data centers. An important
difference with the microphotonic IMOS technology is that we can no
longer build on mature InP-foundry technology, as the thin (200 to
300nm) membranes require complete redevelopment of the foundry
process, and all of its building blocks. At TU Eindhoven, we are working
on development of a nanophotonic IMOS technology [15].
Figure 1.3.11 shows an example of a laser developed in this platform
[31]. It uses short photonic crystal reflectors for creating the laser
resonator. The laser shown is a few hundred microns long, but
optimalization of the gain stack will allow for efficient lasers which are
an order-of-magnitude smaller and significantly more efficient than
current InP lasers. They are expected to produce more than 100μW
output power, which is sufficient for high-speed short-range
communication.
Optical wireless is a particularly promising application domain for IMOS
technology, as wireless transceivers can benefit from the combination
of highperformance active components, such as lasers and detectors,
as well as from precision beam forming enabled by nano-photonic
gratings. A novel integrated optical wireless receiver/transmitter has
recently been presented [32] where the device is realized on an InP
membrane platform where active and passive components are
integrated monolithically (Figure 1.3.12). It can be reconfigured to either
receiver mode or transmitter mode, by simple control of the operation
mode of a photodetector (short SOA). In receiver mode, 17.4Gb/s
orthogonal frequency division multiplexing (OFDM) signal transmission
was demonstrated in an indoor optical wireless system, illustrating the
potential of this concept. Array integration of high density surface
emitters in combination with precision, high-speed control of light (in
terms of amplitude and phase) offers opportunities for dynamic beam
forming in communications, ranging, and imaging.
5.Conclusion
While photonic integration has a long history which lags that of
microelectronics by thirty years, there is increasing evidence that the
technology is set to follow the similar trajectory in the coming years.
With the recent establishment of generic foundry technologies and the
enabled multi-project wafer services, comparisons with microelectronics
are both timely and instructive. The application of generic
methodologies to the main platforms has allowed separation of design
innovation and technology development which enables a broader
uptake of the technology and diversity in circuit innovation. Continued
pressure on performance motivates the development of new
technologies for higher speed, higher precision, and energy efficiency.
32 • 2019 IEEE International Solid-State Circuits Conference
Circuits produced with wafer-scale technologies will benefit from large-
scale manufacturing methods. We have highlighted promising new
technologies to introduce photonicelectronic integration, and to
transition to integrated nanophotonics for high density and richer
functionality.
Acknowledgements
The authors acknowledge support from the NWO Research School for
Integrated Nanophotonics, the EC H2020 WIPE project and the NWO
Photronics project. A. Meighan, M. Spiegelberg and T. de Vries are
acknowledged for the photronics experiments and the photograph of the
first membrane attachment of InP to Silicon BiCMOS. V. Pogoretskyi is
acknowledged for processing a first IMOS MPW wafer.
ISSCC 2019 / SESSION 1 / PLENARY / 1.3
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DIGEST OF TECHNICAL PAPERS • 33

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ISSCC 2019 / February 18, 2019 /
10:40 AM

Electronics Photonics

Invention of key component (transistor/semiconductor laser) 1947 1969

Semiconductor integration technology 1958 1987

Generic integration technology (MPWs*) 1979 2008

2
Killer-random-defect densities reported < 1/cm 1987 2010

Figure 1.3.2: Important milestones in the development of electronic

Figure 1.3.1: Moore’s Law for photonics. and photonic integration. *multi-project wafer

Figure 1.3.3: Basic building blocks in generic electronic and

photonic integration technology. Figure 1.3.4: Building blocks on open-access InP PIC platforms.

DIGEST OF TECHNICAL PAPERS • 29

Figure 1.3.5: Circuit layout of a widely tunable laser and a photo Figure 1.3.6: Examples of hybrid and heterogeneous integration of
micrograph of an array of lasers fabricated in one of the JePPIX photonic and electronic ICs.
foundry processes (@SMART Photonics).
ISSCC 2019 / SESSION 1 / PLENARY / 1.3 February 18, 2019 / 10:40 AM

Optical connections Electronic Thermal connections Scaling potential

connections
Monolithic Si Off-chip laser Ultrahigh density Silicon heatsink Embedded in
electronic photonic no amplifiers electronics
integration
3-D integration Off-chip laser Bond pad limited Silica insulator Assembly
technology no amplifiers challenges

Hybrid integration Optical vias at the Bond pad limited Silica insulator Assembly
Chips on carrier assembly interface challenges
Heterogeneous InP and On-chip laser High density InP heatsink Energy
electronics integration and amplifiers efficient InP
optoelectronics

Figure 1.3.8: InP photonic wafer attachment to a Si electronic wafer

Figure 1.3.7 an illustrationtwo
of were
wafers,
co-
nP and a Si (left) to enable intimate, high density interconnection of an InP
is
designed and bonded on topanofI each other.
BiC MOS, which membrane over Silicon BiCMOS (right).

30 • 2019 IEEE International Solid-State Circuits Conference 978-1-5386-8531-0/19/$31.00 ©2019 IEEE

 1

Figure 1.3.9: Photronics integration: the heterogeneous integration Figure 1.3.10: Transitioning from photronics to integrated nano-
of generic InP integrated photonics with microelectronics shown in photonics to enable order-of-magnitude reduction in waveguide
cross-section. cross-sections.

Figure 1.3.11: A photonic crystal reflector laser realized in the IMOS Figure 1.3.12: Integrated reconfigurable optical wireless
platform. left: the optical amplifier; bottom right: the laser(left) and transmitter/receiver: Left: The transparent SOA gate (in transmitter
the photonic crystal reflectors (right); top right: spectra for two mode) / photodetector (in receiver mode) integrated with grating-
pumping currents. based optical antenna. Right: Zoom in picture of the SOA/detector.

DIGEST OF TECHNICAL PAPERS • 31