The MIPS Instruction-Set Architecture

[H&P §2.12] The MIPS instruction set illustrates four underlying

principles of hardware design:

1. Simplicity favors regularity.

2. Smaller is faster.
3. Good design demands compromise.
4. Make the common case fast.

The MIPS instruction-set architecture has characteristics based on

conclusions from previous lectures.

• It is a load-store architecture that uses general-purpose

registers.
• It has only two addressing modes, displacement and
immediate, but can synthesize other important modes from
them.
• It supports 8-, 16-, 32-, and 64-bit integers, and 32- and 64-
bit IEEE 754 floating-point numbers.
• It has an orthogonal set of instructions to manipulate these
data types.
• It has separate comparison and branching instructions.
(This is an example of making the common case fast.)

MIPS has thirty-two 64-bit general-purpose registers, named R0, R1,

… , R31.

R0 always contains 0 (loading it with another value has no

effect).

It has 32 floating-point registers, which can hold either single-

precision (32-bit) or double-precision (64-bit) values.

This is an example of smaller is faster—using a single register set

would make register-address fields larger and make accesses take
longer.
© 2002 Edward F. Gehringer ECE 463/521 Lecture Notes, Fall 2002 1
Figures from CAQA used with permission of Morgan Kaufmann Publishers. © 2003 Elsevier Science (USA)
 Addressing modes
Displacement and immediate modes both have 16-bit fields.

How can we synthesize other important addressing modes?

› Register indirect:
› Direct:
› Scaled:

› Memory indirect:

Like the PowerPC, MIPS can select either Big Endian or Little Endian
byte ordering.

Memory is byte addressable with a 64-bit address.

MIPS instruction formats

Simplicity favors regularity … so all MIPS arithmetic instructions have
exactly three operands.

For example,
DADD R3, R1, R2 Regs[R3] ← Regs[R1] + Regs[R2]
DSUB R3, R1, R2 Regs[R3] ← Regs[R1] – Regs[R2]

Good design demands compromise … so instructions are fixed length

(32 bits). This requires different instruction formats. This table gives
a summary of the three formats.

Format 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Comments

R op rs rt rd shamt funct Arithmetic
Transfer, branch,
I op rs rt address/immediate
immediate
J op target address Jump

Lecture 13 Advanced Microprocessor Design 2

Let’s take a look at each of these formats in more detail.

An R-type instruction has this format.

6 5 5 5 5 6
Opcode rs rt rd shamt funct
ALU op Operand 1 Operand 2 Result Shift amt. add, sub, etc.

This format is used for both arithmetic and boolean operations. In

general, the shamt field is 0 for arithmetic operations, and the rs field
is 0 for logical operations.

An I-type instruction has this format.

6 5 5 16
Opcode rs rt Immediate

Load/Store Source Destination Immediate

register register [rt ← rs op immediate]

Conditional Comparand Comparand PC-relative offset

branch 1 2 [if rs rel rt then branch]

A J-type instruction has this format.

6 26
Opcode Offset
Jump Target address4..29
[& link]
Jump Register JR function
register to jump to code

MIPS instructions
Here are a few MIPS instructions. The text has another list, and a
comprehensive list (for MIPS IV) can be found at
techpubs.sgi.com/library/manuals/2000/ 007-2597-001/pdf/007-2597-
001.pdf

© 2002 Edward F. Gehringer ECE 463/521 Lecture Notes, Fall 2002 3

Figures from CAQA used with permission of Morgan Kaufmann Publishers. © 2003 Elsevier Science (USA)
Arithmetic instructions
Instruction Example Meaning Comments
Add ADD R1,R2,R3 R1←R2+R3
Subtract SUB R1,R2,R3 R1←R2–R3
Add immediate ADDI R1,R2,10 R1←R2+10 Adds a constant
Add unsigned ADDU R1,R2,R3 R1←R2+R3 No trap on o’flo.
Add immed uns’d ADDIU R1,R2,10 R1←R2+10

Logical instructions
Instruction Example Meaning Comments
And AND R1,R2,R3 R1←R2&R3
Or OR R1,R2,R3 R1←R2|R3
And immediate ANDI R1,R2,10 R1←R2&10 and with a constant
Shift left logical SLL R1,R2,10 R1←R2<<10 Shift left by constant
Shift right logical SRL R1,R2,10 R1←R2>>10 Shift right by constant

Load/store
Instruction Example Meaning Comments
Load word LW R1,10(R2) R1←Mem [R2+10] Memory to register
Store word R1,10(R2) Mem[R2+10] ←R1 Register to memory
SW
Load upper Load constant into
LUI R1,10 R1←10×216
immed. upper 16 bits of word

Conditional branch
Instruction
Branch on equal
Branch on not equal
Set on less than
Example Meaning
BEQ R1,R2,10 if (R1==R2) goto PC+4+10
BNE R1,R2,10 if (R1!=R2) goto PC+4+10
SLT R1,R2,R3 if (R2<R3) R1←1; else R1=0

Lecture 13 Advanced Microprocessor Design 4

16-bit signed offset is shifted left two places and added to the
program counter. (The program counter is pointing to the next
sequential instruction.)

Unconditional jump
Instruction Example Meaning Comments
Jump J 1000 goto 1000 Jump to target address
Jump register JR R31 goto R31 For switch or procedure return
R31←PC+4;
Jump and link JAL 1000 For procedure call
goto 1000
Jump and link R31←PC+4;
JALR R1 For procedure call
register PC←R2

Floating-point
Instruction Example Meaning Comments
Add double ADD.D F1,F2,F3 F1←F2+F3 64-bit operation
Subtract single SUB.S F1,F2,F3 F1←F2–F3 32-bit operation
Multiply paired MUL.PS Two 32-bit operations
F1←F2×F3
single F1,F2,F3 simultaneously

Let’s take a look at how frequently these instructions are used. Here
are frequencies for five SPECint2000 programs.

© 2002 Edward F. Gehringer ECE 463/521 Lecture Notes, Fall 2002 5

Figures from CAQA used with permission of Morgan Kaufmann Publishers. © 2003 Elsevier Science (USA)
Below are frequencies for five SPECfp2000 programs.

Compare these
frequencies with
the frequencies
for integer
programs.

Why are there

more loads than
stores?

What differences
do you see in
instruction
frequencies?

Lecture 13 Advanced Microprocessor Design 6

Sample MIPS program
# sumit.asm
# Simple routine to sum N integers to demo a loop.
# Author: R.N. Ciminero
# Revision date: 10-06-93 Original def.
# See Patterson & Hennessy pg. A-46 for system services.

.text
.globl main
main:
li $v0,4 # load code for print_string
la $a0, msg1 # address of string to print
syscall # print string
li $v0,5 # load code for read_int
syscall # input N
move $t0,$v0 # save
li $t1, 0 # initialize counter (i)
li $t2, 0 # initialize sum
loop: addi $t1, $t1, 1 # i = i + 1
add $t2, $t2, $t1 # sum = sum + i
beq $t0, $t1, exit # if i = N, continue
j loop
exit: li $v0, 4 # output msg2
la $a0, msg2
syscall

li $v0,1 # output sum

move $a0, $t2
syscall
li $v0,4 # output lf
la $a0, lf
syscall
li $v0,10 # exit
syscall
.data
msg1: .asciiz "\nNumber of integers (N)? "
msg2: .asciiz "\nSum = "
lf: .asciiz "\n"

Output
Number of integers (N)? 5
Sum = 15
© 2002 Edward F. Gehringer ECE 463/521 Lecture Notes, Fall 2002 7
Figures from CAQA used with permission of Morgan Kaufmann Publishers. © 2003 Elsevier Science (USA)
Comments on the program
In MIPS, registers have names as well as numbers. Some of the
register names that are used in this program are—

Register Number Usage

name
$v0 2 Expression evaluation and function results
$a0 4 Argument 1
$t0 8 Temporary (not preserved across call)
$t1 9 Temporary (not preserved across call)
$t2 10 Temporary (not preserved across call)

li $t1, 0 # initialize counter (i)

Temporary register $t1 contains the count.
li $t2, 0 # initialize sum
Temporary register $t2 contains the sum.
loop: addi $t1, $t1, 1 # i = i + 1
Increment the counter by one.
add $t2, $t2, $t1 # sum = sum + i
Add the counter to theum.
beq $t0, $t1, exit # if i = N, continue
If the counter equals the number of integers, then exit the loop.
j loop
Else perform the summation again.
exit: li $v0, 4 # output msg2
Statement to execute upon leaving the loop.
[All contents copyright © 1995 Ronald N. Ciminero. Used with
permission.]

Lecture 13 Advanced Microprocessor Design 8