Journal of

Nanoelectronics and Optoelectronics

Copyright © 2019 by American Scientific Publishers Vol. 14, pp. 1–7, 2019
All rights reserved.
Printed in the United States of America www.aspbs.com/jno

ARTICLE

Enhancing Frequency Performance of Underlap

Tunnel Field-Effect Transistor for
Analog/RF Applications
Shikhar Gupta∗ and Ashutosh Nandi

In this paper, a silicon n-channel double gate tunnel field-effect transistor (TFET) with source/drain underlap
is demonstrated. As spacer dielectric material is an important parameter to decide the device analog/RF
performance, we use dual- spacer material in the underlap region of TFET to enhance the analog/RF perfor-
mance of the device. It is observed that air as an outer spacer material further enhances the performance of
the device. A thorough analysis, with the help of comprehensive device simulation, on the device analog/RF
performance with Air as an outer spacer material in dual- spacer underlap TFET is reported in this paper.
It is examined that the intrinsic gain of dual-Air spacer dielectric is almost unaltered (≈71 dB); whereas
frequencies like cut-off frequency (fT ) and maximum oscillation frequency (fMAX ) are enhanced by 1.5 times
and 1.25 times respectively as compared to conventional dual- spacer dielectric material. This results in a
higher percentage improvement in the gain-frequency product (GFP), transconductance frequency product
(TFP) and gain transconductance frequency product (GTFP) of the device.
Keywords: TFET, Underlap, Tunneling Length, Dual-.

1. INTRODUCTION of channel side. When a positive gate supply voltage is

As the MOSFETs are scaled to smaller dimensions, the
switching speed, packing density and fabrication cost is
improving. However, several limitations such as leakage
current, short-channel effect (SCEs) and high power con-
sumption are cropping up as major issues [1]. Lower
power supply voltage leads to reduced power density.
However, with the reduction of the supply voltage, there
is a risk of a decrease in the on-current which degrades
the ION /IOFF ratio. For better switching, the ION /IOFF should
be high, and the sub-threshold slope (SS) should be low.
However, at room temperature, the SS of conventional
MOSFETs cannot be reduced below 60 mV/dec. Tunnel-
FET is an alternative approach for low power circuit
design because of its low off current (IOFF  and lower
sub-threshold slope (SS). TFETs are the gated reverse
biased p–i–n diode. This reverse bias voltage shifts the
valence band of source side nearer to the conduction band
Department of Electronics and Communication Engineering, National
Institute of Technology, Kurukshetra 136119, Haryana, India
∗
Author to whom correspondence should be addressed.
Email: shikhar.gupta2@gmail.com
Received: 1 June 2018
Accepted: 28 November 2018
applied in the channel region, empty electron state is
formed, and band-to-band tunneling (BTBT) of electrons
from the valence band of the source to the conduction band
of the channel takes place. As the positive bias is applied
at the drain terminal, these electrons are then conveyed to
the drain terminal [2]. Due to the BTBT mechanism on
the source-channel interface, it can achieve sub-threshold
slope (SS) below 60 mV/dec at room temperature, low
off-current (IOFF  and improved SCEs. The band bend-
ing occurs in the small tunneling region rather than whole
channel region, as it offers low threshold voltage roll-
off. Further, the OFF-state leakage current in TFET is
very low in the range of A/m, which makes it entic-
ing for ultralow power applications [3]. In spite of the
several advantages, TFET has its own flaws, such as low
on-state current (ION , ambipolarity, high gate-drain capac-
itances, experiences delayed saturation, which is harmful
to the analog applications. In order to increase the ION
of TFET, various techniques such as double-gate (DG)
TFET [4], strained silicon TFET [5], III–V hetero-junction
TFETs [6], carbon nanotube TFET [7], double material
gate [8], low- spacer [9], high- gate dielectric [10] are
practiced. Another way to increase the drain current is
to enhance the p–i–n junction electric field which can

J. Nanoelectron. Optoelectron. 2019, Vol. 14, No. xx 1555-130X/2019/14/001/007 doi:10.1166/jno.2019.2528 1

Enhancing Frequency Performance of Underlap TFET for Analog/RF Applications
be achieved by using the drain underlap structure [11].
In underlap architecture of TFET, the RF performance in
terms of cut-off frequency (fT  and maximum oscillation
frequency (fMAX  of device increases. With the increase
in the underlap length of the device, fMAX of the device
increases [11]. Dual- spacer underlap device is a better
alternative for enhancing digital performance, improving
SCEs, and controlling direct source to drain tunneling [12].
By shifting the lateral electric field at the gate edge toward
the drain, the analog performance of dual- spacer based
device is enhanced [13]. In dual- spacer, the inner gate
side-wall spacer is high- dielectric and the outer spacer
is a low- dielectric. Reducing the outer spacer dielectric
constant of the dual- spacer, the analog performance of
the device can be further enhanced. In the Section 1 of
this paper, therefore, we have focused on the analog per-
formance of dual- spacer underlap double gate silicon
tunnel-FET with air as an outer spacer dielectric mate-
rial. The device structure and methodology used for sim-
ulation are discussed in Section 2 of the paper, Followed
by the device physics and performance study aspects in
Section 3. Section 4 describes the result and analysis and
finally, Section 5 concludes the paper.
2. DEVICE STRUCTURE AND
SIMULATION SETUP
The schematic cross-sectional view of TFET with symmet-
rical Source/Drain underlap is shown in Figure 1. Encased
Air-gap spacer is formed by the selective deposition of
carbon on the gate stack side-wall, followed by the SiN
deposition and reactive ion etching (RIE), which results
in encapsulation of carbon region by SiN. Finally, oxy-
gen plasma is used to remove the deposited carbon and
forming air spacer encased between SiN and gate side-
wall [14]. The fixed gate length of 20 nm is used through-
out the analysis. The Source/Drain underlap length (LU 
is set to 10 nm. The dual- spacer is optimized for 7 nm
high- inner material and 3 nm of low- outer material.
In conventional dual- structure, HfO2 is considered as
inner high- material, whereas SiO2 is considered as outer
low- material. Doping has been optimized in order to
maximize the on-state current and minimize the off-state
Fig. 1. A cross-sectional view of dual-gate tunnel FET with source/drain underlap.
2 J. Nanoelectron. Optoelectron., 14, 1–7, 2019
Gupta and Nandi
current. In tunnel-FET, the source is made up of p-type
and drain is of n-type. To reduce the ambipolarity of
the tunnel FET, the doping concentration of the source
and drain should be asymmetric. The p-type source is
doped with 1 × 1020 cm−3 , the intrinsic channel is doped
with 1 × 1016 cm−3 and the n-type drain is doped with
5 × 1018 cm−3 [15]. The thickness of the active silicon
layer where the channel is formed (tSi  is kept as 8 nm.
SiO2 is used as gate dielectric throughout the simula-
tion procedure. The polysilicon gate has several disadvan-
tages in nanoscale devices such as gate depletion, high
gate resistance and sheet resistance, and penetration of
dopant ions from doped poly-silicon gate [16]. To elim-
inate these adverse effects and enhance the performance
of gate, an aluminum metal gate with work-function
of 4.3 eV is used. Cut-off frequency (fT  is deter-
mined from current gain (h21  through an extrapolation
of 20 dB/decade slope, whereas maximum oscillation fre-
quency (fMAX , indicating the maximum available power
gain, is derived from Mason’s unilateral gain through an
estimation of 20 dB/decade slope [17]. A dual-gate TFET
with Source/Drain underlap is simulated using Sentaurus
TCAD mixed mode device simulator with different under-
lap lengths [18]. The band-to-band tunneling model with a
nonlocal path is used in the simulation setup, to imitate the
tunneling phenomena [19]. The Wentzel-Kramer-Brillouin
(WKB) approximation model along with two side disper-
sion model is responsible to capture tunneling across all
possible junctions and interfaces [19]. In this article, we
have used effective tunneling mass of electrons (me  =
0.19 and that of holes (mh  = 0.16 [20]. Furthermore,
Old Slotboom bandgap narrowing mobility model, band to
band Auger recombination model and Shockley-Read-Hall
recombination/generation model are also included in the
simulation setup [21–23]. The various analog/RF figure-
of-merit (FOM) of all the considered devices are extracted
at 1 A/m drain current targeting high gain subthreshold
to weak inversion region of operation.
3. EFFECT OF TUNNELING PATH
Tunneling path in tunnel-FET is the physical path between
two equi-energy points; one on the conduction band and
Gupta and Nandi Enhancing Frequency Performance of Underlap TFET for Analog/RF Applications

another on the valence band, where band-to-band tunnel- As the GBT BT increases, Itun of the device increases, which
ing (BTBT) is probably afforded. The tunneling path is an in-turn enhances the drain current of the device. Subse-
important factor for calculating the tunneling current. The quently, the analog performance of the device in terms of
lateral electric field is dominated over gate electric field transconductance (gm , intrinsic voltage gain (AV  and unit
in tunneling region. Therefore, the main contributor to the gain cut-off frequency (fT  are enhanced.
average electric field (Eavg  in the tunneling region is the
laeral electric field. The Eavg anticipates the tunneling path
which is defined as [24] 4. EFFECT OF DUAL- SPACER IN
UNDERLAP TFET
Eavg = Eg /qlpath (1) In tunnel-FET, spacer fringing field engineering can boost-
where lpath and q indicate the tunneling path and charge up the performance of the device. The coupling of the
of electron respectively. The band energy diagram of the fringing field to the source-channel interface can be en-
tunnel-FET and tunneling paths are shown in Figure 2. l1 is hanced by using a dual- spacer with high- dielectric as
the shortest tunneling path and l2 is the longest tunneling an inner spacer and low- dielectric as an outer spacer in
path. The difference between l1 and l2 is the effective tun- underlap structure [26]. With the use of a dual- spacer
neling path (lpath ) of the tunnel FET. It is clearly seen from in the underlap region, the tunneling length of the device
Eq. (1) that with the reduction in lpath of the device, the
average electric field of the device increases. The band-to-
band generation rate (GBT BT ) of carriers is the function of
the electric field at the tunneling junction and is defined
as [18]
GBT BT = AEavg /E0 P exp−B/Eavg  (2)
where E0 indicates the normalizing electric field (with a
value of 1 V/cm), P indicates the coefficient whose values
for direct tunneling and indirect or phonon-assisted tun-
neling are 2 and 2.5 respectively [19]. The model param-
eters A has value 4 × 1014 cm−3 s−1 and B has value 1.9 ×
107 V/cm [18]. We are considering indirect tunneling in
this paper. As in equation (2), the band-to-band generation
rate (GBT BT  of the carrier increases with increase in Eavg .
By integrating the GBT BT over the effective tunneling vol-
ume, the tunneling current is calculated. The tunneling
current (Itun  per unit width is given as [25]
 Fig. 3. Tunneling length of TFET for different spacer dielectric
Itun = q GBT BT dy dx (3) material.

Fig. 2. Energy band diagram along the channel obtained at VGS and Fig. 4. Drain current of underlap DG-TFET for different spacer dielec-
VDS = 2 V. tric, plotted in logarithmic scale.

J. Nanoelectron. Optoelectron., 14, 1–7, 2019 3

Enhancing Frequency Performance of Underlap TFET for Analog/RF Applications
Fig. 5. Energy band diagram of underlap DG-TFET across the channel
of device.
is reduced. Figure 3 shows the tunneling length of the
device for various spacer dielectrics. It is observed from
the figure that as spacer dielectric increases, the tunneling
length of the device decreases. A sequential reduction in
tunneling length is observed with the use of Air as outer
spacer dielectric (Dual-Air . Subsequently, the increase in
GBT BT results in higher drain current of the device.
Figure 4 shows the on-state current of different spacer
dielectric underlap double gate tunnel-FET plotted on log-
arithmic scale. It is revealed from the figure that the
drain current of the underlap TFET is maximum for the
dual-Air spacer instead of conventional high- or low-
spacer. Madan et al. [15] have reported that to constrain
the ambipolarity effect, source and drain are doped asym-
metrically. Figure 5 shows the variation of conduction
Fig. 6. Effect of asymmetric doping on the ambipolar behavior of the
device.
4 J. Nanoelectron. Optoelectron., 14, 1–7, 2019
Gupta and Nandi
Fig. 7. Subthreshold Slope for different spacer dielectric material.
band energy and valence band energy for both symmetri-
cally doped (NS = ND = 1 × 1020 cm−3  and asymmetri-
cally doped (NS = 1 × 1020 cm−3 and ND = 5 × 1018 cm−3 
DG-TFET. It is observed that the improvement in barrier
width at the drain end helps in restricting the ambipolar
conduction of the device. Figure 6 shows the reduction
in ambipolar behavior of device due to asymmetric dop-
ing. Subsequently, Figure 7 shows the variation of SS
with different spacer dielectric. It is observed that the SS
of the device improves with the increase in the spacer
dielectric of the underlap region due to enhanced electro-
static integrity of the device [27]. SS of the device further
reduces with the use of Dual-Air spacer dielectric. Hence
the proposed device has better switching characteristics
than the conventional high- DG-TFET.
Figure 8 shows the variation of transconductance (gm 
and output conductance (gds  for different spacer dielectric.
Fig. 8. Variation of gm and gds for various spacer dielectric, at
1 A/m.
Gupta and Nandi Enhancing Frequency Performance of Underlap TFET for Analog/RF Applications

length and spacer dielectric. They play an important role

in overall device capacitances. These fringe capacitances
can be reduced further by the use of low-spacer in the
underlap region. The variation of intrinsic device capac-
itance (cgg  and gate-drain capacitance (cgd  for various
spacer dielectrics is shown in Figure 9. Dual- spacer in
the underlap region reduces the capacitances cgg and cgd .
By opting for dual-Air spacer dielectric in the source/drain
underlap region, cgd and cgg are reduced by 6.5% and
11.7% respectively. cgd is a strong limiting agent for cal-
culation of maximum oscillation frequency (fMAX . For
a high value of fMAX , cgd should be low. The intrinsic
gain (AV  and cut-off frequency (fT  is formulated as:

AV = gm /gds (4)

Fig. 9. Variation of cgd and cgg for various spacer dielectric, extracted fT = gm /2Cgg (5)
at 1 A/m.
Figure 10 elucidate that with the use of a dual- spacer
The gm decides the current driving capability of the device. in the underlap region, the AV and fT is improved.
Because of increase in the drain current (due to an increase
in tunneling current) the transconductance (gm  of the
device increases. Subsequently, the output conductance
(gds  of the device also enhanced with the use of a
dual- spacer in the underlap region. However, with the
use of Air as an outer low- spacer in the dual- struc-
ture, gds slightly deteriorates. This deterioration in gds
doesn’t pose any serious threat because of higher percent-
age improvement in gm . From analog perspective, high
transconductance is preferred for large gate transport effi-
ciency. The increase in transconductance will lead to the
improvement in electrostatic integrity (EI). It is exam-
ined that transconductance of device enhances with the use
of dual-Air dielectric in the spacer region instead of the
dual- or high- spacer dielectric.
In underlap devices, the parasitic outer and inner fringe
capacitance of the device depends upon the underlap

Fig. 11. Variation of (a) maximum oscillation frequency (fMAX ) and

Fig. 10. Variation intrinsic gain (AV ) and unity cut-off frequency (fT ) TFP (b) GFP and GTFP for various spacer dielectric, extracted at
for various spacer dielectric, extracted at 1 A/m. 1 A/m.

J. Nanoelectron. Optoelectron., 14, 1–7, 2019 5

Enhancing Frequency Performance of Underlap TFET for Analog/RF Applications
This improvement is further enhanced by the use of Air as
outer low-. The AV changes nominally with the dual-Air
spacer, but the fT enhances substantially because of the
reduction of cgg . Mallikarjunarao et al. [28] have observed
the gate capacitance (cgg  and the maximum cut-off fre-
quency (fT  about 1.9 fF/m and 460 MHz, whereas, in
this manuscript, we have observed the cgg and fT about
0.22 fF/m and 10.35 GHz respectively at 1 A/m cur-
rent level. The maximum oscillation frequency (fMAX  is
 proportional to fT and inversely proportional to
directly
the gds + 2fT cgg [29].
It is observed from the Figure 11 that, opting dual-Air
spacer dielectric in underlap region, fMAX of the device
increases, because of improvement in fT and cgg . Fur-
thermore, the fMAX of the device improved remarkably
with the use dual-Air spacer dielectric in the underlap
region when compared with conventional dual- structure.
Transconductance frequency product (TFP), gain band-
width product (GFP) and gain transconductance frequency
product (GTFP) are an important parameter for the RF per-
formance [30]. In high-speed circuit design, the TFP main-
tains equilibrium between power and bandwidth. GTFP
helps the designer to determine the best region of opera-
tion with gain, transconductance, and frequency. The TFP,
GFP and GTFP of the device is enhanced by 99%, 61%
and 114% with the use of dual-Air instead of dual- as
spacer dielectric in the underlap region.
T F P = gm /ID  × fT (6)
GF P = gm /gds  × fT (7)
GT F P = gm /ID  × g m /gds  × fT (8)
5. CONCLUSION
A thorough study of the analog performance of the sym-
metric underlap TFET with different spacer dielectric
is presented in this work. It is discovered that use of
dual-Air spacer instead of dual- and/or high- spacer
in the underlap region, enhance the drain current of the
device. This enhancement in drain current further enhances
the transconductance and analog/RF performance of the
device. The gain of the device remains almost unaltered
from 88 dB when the dual- spacer is replaced by a dual-
Air spacer, but the fT , fMAX and other RF FOM of the
device are enhanced remarkably. Dual-Air can target fT
and fMAX in excess of 3.4 GHz and 21.5 GHz respec-
tively. Similarly, TFP, GFP and GTFP are objected to be in
excess of 77 GHz/V, 13.9 THz and 292 THz/V. Therefore,
the dual-Air spacer dielectric based underlap TFET is an
attractive option for the high-frequency application.
References and Notes
1. Tayal, S. and Nandi, A., 2018. Optimization of gate-stack
in junctionless Si-nanotube FET for analog/RF applications.
Materials Science in Semiconductor Processing, 80, pp.63–67.
6 J. Nanoelectron. Optoelectron., 14, 1–7, 2019
Gupta and Nandi
2. Mehta, J.U., Borders, W.A., Liu, H., Pandey, R., Datta, S.
and Lunardi, L., 2016. III–V tunnel FET model with closed-
form analytical solution. IEEE Transactions on Electron
Devices, 63(5), pp.2163–2168.
3. Khaveh, H.R.T. and Mohammadi, S., 2016. Potential and drain
current modeling of gate-all-around tunnel FETs considering
the junctions depletion regions and the channel mobile charge
carriers. IEEE Transactions on Electron Devices, 63(12),
pp.5021–5029.
4. Chattopadhyay, A. and Mallik, A., 2011. Impact of a spacer
dielectric and a gate overlap/underlap on the device perfor-
mance of a tunnel field-effect transistor. IEEE Transactions on
Electron Devices, 58(1), pp.677–683.
5. Nayfeh, O.M., Chleirigh, C.N., Hennessy, J., Gomez, L., Hoyt,
J.L. and Antoniadis, D.A., 2008. Design of tunneling field-
effect transistors using strained-silicon/strained-germanium
type-II staggered heterojunctions. IEEE Electron Device Let-
ters, 29(9), pp.1074–1077.
6. Wang, L., Yu, E., Taur, Y. and Asbeck, P., 2010. Design of
tunneling field-effect transistors based on staggered hetero-
junctions for ultralow-power applications. IEEE Electron Device
Letters, 31(5), pp.431–433.
7. Appenzeller, J., Lin, Y.M., Knoch, J., Chen, Z. and Avouris, P.,
2005. Comparing carbon nanotube transistors-the ideal
choice: A novel tunneling device design. IEEE Transactions on
Electron Devices, 52(12), pp.2568–2576.
8. Saurabh, S. and Kumar, M.J., 2011. Novel attributes of a
dual material gate nanoscale tunnel field-effect transistor. IEEE
transactions on Electron Devices, 58(2), pp.404–410.
9. Anghel, C., Chilagani, P., Amara, A. and Vladimirescu, A.,
2010. Tunnel field effect transistor with increased ON cur-
rent, low-k spacer and high-k dielectric. Applied Physics Let-
ters, 96(12), p.122104.
10. Boucart, K. and Ionescu, A.M., 2006. Double Gate Tunnel
FET with Ultrathin Silicon Body and High-k Gate Dielectric.
Solid-State Device Research Conference, 2006. ESSDERC
2006. Proceeding of the 36th European, September, IEEE.
pp.383–386.
11. Virani, H.G., Adari, R.B.R. and Kottantharayil, A., 2010. Dual-k
spacer device architecture for the improvement of performance
of silicon n-channel tunnel FETs. IEEE Transactions on Elec-
tron Devices, 57(10), pp.2410-2417.
12. Nandi, A., Saxena, A.K. and Dasgupta, S., 2012. Impact
of dual-k spacer on analog performance of underlap Fin-
FET. Microelectronics Journal, 43(11), pp.883–887.
13. Nandi, A., Saxena, A.K. and Dasgupta, S., 2013. Design
and analysis of analog performance of dual-k spacer under-
lap N/P-FinFET at 12 nm gate length. IEEE Trans. Electron
Devices, 60(5), pp.1529–1535.
14. Sachid, A.B., Huang, Y.M., Chen, Y.J., Chen, C.C., Lu, D.D.,
Chen, M.C. and Hu, C., 2017. FinFET With encased air-gap
spacers for high-performance and low-energy circuits. IEEE
Electron Device Letters, 38(1), pp.16–19.
15. Madan, J. and Chaujar, R., 2016. Interfacial charge analysis of
heterogeneous gate dielectric-gate all around-tunnel FET for
improved device reliability. IEEE Transactions on Device and
Materials Reliability, 16(2), pp.227–234.
16. Gupta, S. and Nandi, A., 2017. Effect of air spacer on ana-
log performance of underlap tri-gate FinFET. Superlattices and
Microstructures, 109, pp.693–701.
17. Tayal, S. and Nandi, A., 2017. Analog/RF performance anal-
ysis of channel engineered high-k gate-stack based junction-
less trigate-FinFET. Superlattices and Microstructures, 112,
pp.287–295.
18. Sentaurus Device User Guide. 2016.
19. Acharya, A., Dasgupta, S. and Anand, B., 2017. A Novel
${{V}}_{\textsf {DSAT}}$ Extraction Method for Tunnel FETs
Gupta and Nandi Enhancing Frequency Performance of Underlap TFET for Analog/RF Applications
and Its Implication on Analog Design. IEEE Transactions on
Electron Devices, 64(2), pp.629–633.
20. Kao, K.H., Verhulst, A.S., Vandenberghe, W.G., Soree, B.,
Groeseneken, G. and De Meyer, K., 2012. Direct and indi-
rect band-to-band tunneling in germanium-based TFETs. IEEE
Transactions on Electron Devices, 59(2), pp.292–301.
21. Tayal, S. and Nandi, A., 2018. Effect of high-k gate dielectric
in-conjunction with channel parameters on the performance
of FinFET based 6T SRAM. Journal of Nanoelectronics and
Optoelectronics, 13(5), pp.768–774.
22. Tayal, S. and Nandi, A., 2018. Performance analysis of junc-
tionless DG-MOSFET-based 6T-SRAM with gate-stack config-
uration. IET Micro & Nano Letters, 13(6), pp.838–841.
23. Tayal, S. and Nandi, A., 2018. Enhancing the delay perfor-
mance of junctionless silicon nanotube based 6T SRAM. IET
Micro & Nano Letters, 13(7), pp.965–968.
24. Bagga, N. and Sarkar, S.K., 2015. An analytical model for tun-
nel barrier modulation in triple metal double gate TFET. IEEE
Transactions on Electron Devices, 62(7), pp.2136–2142.
25. Prabhat, V. and Dutta, A.K., 2016. Analytical surface poten-
tial and drain current models of dual-metal-gate double-gate
J. Nanoelectron. Optoelectron., 14, 1–7, 2019
tunnel-FETs. IEEE Transactions on Electron Devices, 63(5),
pp.2190–2196.
26. Virani, H.G., Gundapaneni, S. and Kottantharayil, A., 2011.
Double dielectric spacer for the enhancement of silicon
p-channel tunnel field effect transistor performance. Japanese
Journal of Applied Physics, 50(4S), p.04DC04.
27. Gundapaneni, S., Ganguly, S. and Kottantharayil, A., 2011.
Enhanced electrostatic integrity of short-channel junctionless
transistor with high-k spacers. IEEE Electron Device Let-
ters, 32(10), pp.1325–1327.
28. Ranjan, R., Pradhan, K.P. and Sahu, P.K., 2016. Dielectric
engineered symmetric underlap double gate tunnel FET (DGT-
FET): An investigation towards variation of dielectric materi-
als. Superlattices and Microstructures, 96, pp.226–233.
29. Tayal, S. and Nandi, A., 2017. Effect of FIBL in-conjunction
with channel parameters on analog and RF FOM of Fin-
FET. Superlattices and Microstructures, 105, pp.152–162.
30. Gupta, S. and Nandi, A., 2018. RF performance enhancement
in underlap Tri-Gate FinFET. In 2018 2nd International Confer-
ence on Inventive Systems and Control (ICISC) IEEE, January,
pp. 760–762.
7