Vous êtes sur la page 1sur 2

CTS activities Experiment 1 Experiment 2

Drive strengths 2,4,8 All


Cells BUFF BUFF

NBUFFX2_RVT,
Inputs NBUFFX2_RVT, NBUFFX4_RVT,
Clock cell names NBUFFX4_RVT, NBUFFX8_RVT,
NBUFFX8_RVT NBUFFX16_RVT,
NBUFFX32_RVT

Total number of clock cells 0+586+344 0+586+344


Insertion Delay (Longest path delay) 4.5113 4.5113
Max Global skew (Max ID - Min ID) 2.0858 2.0858
Clock Tree power (report_power) 2.23E+03 2.22E+03
Congestion Vertical utilization 9.21% 9.13%
(report_congestio
Outputs n) Horizontal utilization 12.28% 12.16%
Timing Setup violations 17 16
(clock_opt) Hold violations 143 144
inst Count 7083 7116
Buf/Inv Count 1844 1874
No.of Levels 281(1+216+64) 281(1+216+64)
Experiment 3 Experiment 4 Experiment 5 Experiment 6
2,4,8 All 2,4,8 All
INV INV BUFF & INV BUFF & INV

NBUFFX2_RVT,
NBUFFX4_RVT,
NBUFFX8_RVT,
INVX0_RVT, NBUFFX2_RVT, NBUFFX16_RVT,
INVX1_RVT, NBUFFX4_RVT, NBUFFX32_RVT,
INVX2_RVT, INVX2_RVT, NBUFFX8_RVT, INVX0_RVT,
INVX4_RVT, INVX4_RVT, INVX2_RVT, INVX1_RVT,
INVX8_RVT INVX8_RVT, INVX4_RVT, INVX2_RVT,
INVX16_RVT, INVX8_RVT INVX4_RVT,
INVX32_RVT INVX8_RVT,
INVX16_RVT,
INVX32_RVT

0+586+344 0+586+344 0+586+344 0+586+344


4.5124 4.5113 4.5112 4.511
2.0866 2.0858 2.0857 2.0858
2.22E+03 2.23E+03 2.22E+03 2.22E+03

9.44% 9.37% 9.17% 9.21%


12.86% 12.49% 12.23% 12.30%
16 17 17 16
143 143 143 144
7612 7682 7072 7054
2391 2458 1845 1820
281(1+216+64) 281(1+216+64) 281(1+216+64) 281(1+216+64)

Vous aimerez peut-être aussi