Spring 2006

Project Overview

Verification of a I2C Master Core

By
Arkady Vaisman
Ilia Nudelman

Supervised by Yotam Lahav

 Agenda
• Project Goals
• What is Functional Verification?
• I2C Protocol - General Overview
• The DUT (Design Under Test)
• Verification Plan
• The Env Architecture
• Challenges we cope with.
 Project Goals
Development of a complete functional
(dynamic) verification environment for the
I2C master core chip.

• The environment will be written in the "e"

language and will include tests for all
functionality of the protocol.
What is Functional Verification ?
• Functional verification, is the task of
verifying that the logic design conforms to
specification.
• This is a complex task, and takes
the majority of time and effort Does this
proposed
in most large electronic design do what
is intended?
system design projects.
 I2C Protocol

• A two-wire bi-directional serial bus that provides a simple

and efficient method of data exchange between devices.
• The interface defines 3 transmission speeds:
- normal: 100kbps (used in our DUT)
- fast: 400kbps
- high speed: 3.5Mbps
 I2C Protocol (Cont)

Features:
• Master Transmitter Mode — Serial data output via SDA. Clock is generated.
• Master Receiver Mode — Serial data is received via SDA. Clock is generated.
• Slave Transmitter Mode — Serial data is transmitted via SDA. Clock is received.
• Slave Receiver Mode — Serial data and clock are received via SDA and SCL.
• SCL is the Transaction dynamic clock.
• Management Flow — Own address and General Call address detection.

Configuration:
• 7-bit addressing format.
• Fixed data width of 8 bits.
• Data transfer in multiples of bytes.
The DUT (Design Under Test)
• The DUT is a HCA (Host Channel Adapter)
chip block.
• The DUT can be used simultaneously as a
I2C Master and as a I2C Slave.
• The I2C protocol is used for setting the chip
initial configurations.
 Verification Plan
• The Verification Plan describes
approaches and methods for system
verification and testing.
• The Plan contains following parts:
– I2C as Master Good Flow.
– I2C as Master Bad Flow.
– I2C as Slave Good Flow.
– I2C as Slave Bad Flow.
– Management Flow.
 The DUT - InterFaces
• The DUT has main 3 Interfaces:
Outside
1) I2C Bus I/F the chip

2) Slave Transactions I/F - CrSpace Inside

the chip
3) Master Transactions I/F - GW
 I2C Env Structure
HCA Slave
YU - I/F

CrSpace Watcher

Master
Master
BFM
Master 2 HCA
BFM I C GW
BFM Master
GW
SDA
DUT I/F
clk

SCL

Bus Watcher Master Watcher

Score Board
TA Builder (TA Level)
 Challenges we cope with
There are 2 main Challenges:

1) Working with 2 Clock Domains -

Multiple abstraction levels.

2) Synchronization between 3 protocols:

a. I2C – main communication.
b. YU CrSpace – Slave Transactions.
c. GW – Master transactions.
Questions…