HARDWARE/SOFTWARE DIGITAL SYSTEM DESIGN

LAB REPORT EXPERIMENTATIONS 4 & 5

Ammar Ahmed
Hernan Dellamaggiora
WET Master
Experiment 4: Automate

Behavior

We defined three states: “Pause”, “Incrementation”, and “Decrementation”. When having clock rising and BTNC
is “1” the system goes to “Incrementation” counting upwards, when it reaches its max tmr value (9) goes straight
to the initial value (0) and keep counting upwards. When it´s in “Incrementation” if BTND goes to “1” , then the
system goes to “Decrementation”, when it reaches its min tmr value (0) goes straight to the max tmr value (0).
While “Decrementation” if BTNC goes to “1” the system goes to Pause and also if BTNU goes to “1” while
“Decrementation” then the system goes to “Incrementation”.

The behavior of signals generated during both states are:

Incrementing
10
9
8
7
6
5
4
3
2
1
0
0 2 4 6 8 10 12 14 16

Decrementing
10
9
8
7
6
5
4
3
2
1
0
0 2 4 6 8 10 12 14 16
Synthesis results: RTL Schematic
- COMMAND UNIT AND OPERATIVE PART

General state flow of the program, there are three states Pause, Incrimination and decrementation.

OPERATIVE PART

Below diagram shows the part where the clock Is divided. The division of the clock only for the visual on the
fpga board. The tmrCntr_Max value is defined in the program, counter is incremented to this value and when the
tmrCntr is equal to tmrCntr_Max value then it is again set to zero.
The below mentioned diagrams represents the calculation of the tmrVal. The tmrVal is enabled through the
selection of state. The condition of tmrCntr would be either BTNC pressed or BTNU, in this case the state
would be incrementation, and BTND (for the state decrementation). Each of which will defined the clock enable
of the trmVal Reg. In the second diagram the incremented or decremented valued is calculated which is then
send to the control unit which further displays it on the seven segment display.
This part shows the calculation of the state value after the pressing of the either of the BTNC, BTNU and BTND
button. The value of the state is stored in the Etat Register.
 COMMAND UNIT
The command unit of the program is simply dependent upon the input, after the input it decides the value and
store it in the state register. This value is then further used to make up counting if the state is Incrementation and
down counting if the state is Decrementation.
Resources used in Exp. 4:
Experiment 5: Development of a VHDL solution
Describe in VHDL the behavior of a Signal Generator, generating a cycle of signal generation.

VHDL code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.all;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity automate is
Port ( SW : in std_logic_vector(15 downto 0);
LED : out std_logic_vector(15 downto 0);
BTNC, BTNL, BTNU, BTNR, BTND : in std_logic;
CLK : in std_logic;
SSEG_AN : out std_logic_vector (3 downto 0);
SSEG_CA : out std_logic_vector (7 downto 0) );
end automate;

architecture Behavioral of automate is

constant TMR_CNTR_MAX : std_logic_vector(26 downto 0):= "101111101011110000100000000";
constant TMR_VAL_MAX : std_logic_vector(3 downto 0):="1001";
constant TMR_VAL_MIN : std_logic_vector(3 downto 0):="0000";
constant counter_2_MIN : std_logic_vector(3 downto 0):="0000";
constant counter_2_MAX : std_logic_vector(3 downto 0):="1001";
signal counter_2 : std_logic_vector (3 downto 0) := (others=>'0');
signal tmrCntr : std_logic_vector (26 downto 0) := (others=>'0');
signal tmrVal : std_logic_vector (3 downto 0) := (others=>'0');

type DefEtat is (Pause, Incrementation, Decrementation, High, Low);

signal Etat : DefEtat;
begin
LED <= SW;

with SW(1 downto 0) select

SSEG_AN <= "1110" when "00",

"1101" when "01",
"1011" when "10",
"0111" when "11",
"1111" when others;

with tmrVal select

SSEG_CA <= "01000000" when "0000",
"01111001" when "0001",
"00110100" when "0010",
"00110000" when "0011",
"00011001" when "0100",
"00010010" when "0101",
"00000010" when "0110",
"01111000" when "0111",
"00000000" when "1000",
"00010000" when "1001",
"11111111" when others;

timer_counter_process : process(CLK)
begin
if rising_edge(CLK) then
if tmrCntr = TMR_CNTR_MAX then
tmrCntr <= (others => '0');
else
tmrCntr <= tmrCntr+1;
end if;
end if;
end process;

timer_state_process : process(CLK)
begin
if rising_edge(CLK) then
case Etat is
when Pause =>
tmrVal <= (others => '0');
if BTNC= '1' then
Etat <= Incrementation;
 end if;
when Incrementation =>
if BTND='1' then
Etat <= Decrementation;
elsif tmrCntr = TMR_CNTR_MAX then
if tmrVal = TMR_VAL_MAX then
Etat <= High;
--
else
tmrVal <= tmrVal+1;
end if;
end if;

when High =>

if tmrCntr = TMR_CNTR_MAX then

if tmrVal = TMR_VAL_MAX then
if counter_2 = counter_2_MAX then
Etat <= Decrementation;
else
counter_2 <= counter_2+1;
end if;
end if;
end if;

when Low =>

if tmrCntr = TMR_CNTR_MAX then

if tmrVal = "0000" then
if counter_2 = counter_2_MIN then
Etat <= Incrementation;
--
else
counter_2 <= counter_2-1;
end if;
end if;
end if;

when Decrementation =>

if BTNC='1' then
Etat <= Pause;
elsif BTNU='1' then
Etat <= Incrementation;
elsif tmrCntr = TMR_CNTR_MAX then
if tmrVal = "0000" then
Etat <= Low;
--
else
tmrVal <= tmrVal-1;
end if;
end if;
when others =>
end case;
end if;
end process;

end Behavioral;

We defined two new states: “High” and “Low” and we keep “Incrementation” and “Decrementation” in
comparison to experience 4. When BTNC is “1” the system goes to “Incrementation”, when it reaches its max
value (7) and counter then it goes to the state “High”, stays in that state and initiates counter_2 which counts till
it max. value. When reaches the max value, then goes to “Decrementation”, when it reaches its min value and
counter (4), then it goes to the state “Low” and stays in that state and initiates counter_2 which counts till it min.
value and when it reaches, then goes to the “Incrementation” state, and the cycle starts again.
The signal generated is:

Signal Generator
8
7
6
5
4
3
2
1
0
0 2 4 6 8 10 12 14 16

- We run the simulation: we set BTNC as “1”

- Then the system goes to the “Incrementation” state. When it reaches its max value and counter then it goes to
the state “High”, stays in that state and initiates counter_2 which counts till it max. value.
Implementing on the FPGA board, the “High” state is shown:

- When reaches the max value, then goes to “Decrementation”, when it reaches its min value and counter, then it
goes to the state “Low” and stays in that state and initiates counter_2 which counts till it min. value.
Implementing on the FPGA board, the “Low” state is shown:
Synthesis results: RTL Schematic
Resources used in Exp. 5: