Superlattices and Microstructures 120 (2018) 828e836

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Superlattices and Microstructures

journal homepage: www.elsevier.com/locate/superlattices

Graphene-based Field Effect Diode

Abolfazl Sotoudeh, Mina Amirmazlaghani*
Nano Electronics Lab(NEL), Shahid Rajaee Teacher Training University, Tehran 1678815811, Iran

a r t i c l e i n f o a b s t r a c t

Article history: One of the major problems with Graphene transistors is the small On/Off current ratio. In
Available online 6 February 2018 spite of introducing various methods to improve this problem, like patterning the Gra-
phene layer or using the Graphene nanoribbons, this issue still limits the use of Graphene
keywords: transistors. Here, we present a new Graphene-based, 4-terminal device and discuss its
Graphene application as a Graphene-based transistors. The proposed structure is a Filed Effect Diode
Field effect diode
(FED) in which Graphene acts as the channel. In the structure of Graphene-Field Effect
Field effect transistor
Diode (G-FED), two gates are located over the channel and biased oppositively to elec-
On/off current ratio
trically induce n or p regions in Graphene layer. As the Off current of G-FED is limited to
only the leakage current of a reverse-biased diode, the On/Off current ratio is large in
comparison with the comparable Graphene Filed effect Transistor (G-FET). We have
measured the current-voltage curves of G-FED as well as the carrier concentration and
energy band diagram in both On and Off states. It has been observed that G-FED perfor-
mance is similar to a silicon-based FED with rectifying characteristics. We have demon-
strated that the On/Off current ratio obtained for the G-FED is about 100 while this value is
less than 15 for the G-FET with the same dimensions. Additionally, the G-FED has the same
fabrication process as the G-FET and no difficulty is needed for patterning the Graphene
layer to get the high On/Off current ratio. This demonstration reveals the great potential of
Graphene-based Field Effect Diode in digital nanoelectronics applications as well as analog
mixers.
© 2018 Elsevier Ltd. All rights reserved.

1. Introduction

Graphene is a two-dimensional material formed by the combination of carbon atoms [1,2]. Andre Geim et al. produced this
material for the first time in 2004 at the University of Manchester [3]. Graphene is a semiconductor with a band gap of zero, in
which the electrons act like massless Dirac fermions and show very high mobility (100.000 cm2/V$S) [4]. This material as a
single atomic layer is a good conductor of electrical current [4,5]. In addition, the Fermi energy level, and hence the electron
and hole concentration, can be changed in Graphene by applying the electric field [4e6]. Accordingly, this material can play a
functional role in the electronic and optoelectronic devices [7e9].
One of the most important components in the electronics industry is transistor. Minimization of the transistor size has
been continued to advance the silicon-based electronics devices. However, various scientific and technical issues have limited
this advancement. Graphene-based technology is an alternative to overcome such limitations in silicon technology [9e11].
Graphene-based transistors have been proposed to take advantage of the peculiar electrical properties of Graphene in the

* Corresponding author.
E-mail address: m.mazlaghani@srttu.edu (M. Amirmazlaghani).

https://doi.org/10.1016/j.spmi.2018.01.010
0749-6036/© 2018 Elsevier Ltd. All rights reserved.
 A. Sotoudeh, M. Amirmazlaghani / Superlattices and Microstructures 120 (2018) 828e836 829

electronics industry [9e29]. Field effect transistors (FETs) manufactured using Graphene as an active element can play a
significant role in the evolution of the next generation of electronic components [9e29]. Graphene can also be used as an
electrode (source and drain) as well as the channel layer in any type of FET structure [5], [9,10]. Graphene on a SiO2 substrate
has shown a high rate of mobility (10000 cm2/V.s) [30,31]. Therefore, faster and smaller transistors with lower energy
consumption and higher thermal dissipation than the silicon transistors can be achieved using Graphene [9e11], [13e16].
One of the major problems with Graphene transistors is the low On/Off current ratio [17]. Different methods have been
reported to improve this feature [14,15], [17e29]. The absence of a band gap causes effectively that there is no strong
saturation behaviour in Graphene transistors. It also causes a low On/Off current ratio, for which the values reported are 2.4
[14], 3 [15], as well as about 5 for single layer top-gated Graphene-FET [19], at room temperature. One reported method to get
a higher On/Off current ratio is patterning the Graphene channel, according to which the On/Off ratio obtained has been
reported equal to 7 [20]. Creating a band gap in Graphene by changing its physical structure leads to transistors with higher
On/Off ratio. Some of these structural modifications are the use of Graphene nanoribbons, Graphene shaping, and the use of
multi-layer Graphene. For example, Graphene-based transistors obtained by the use of the Graphene nanoribbons lead to the
On/Off ratio of 106 [21], as well as the ratio of 107 [22] and 2✕103 at room temperature [25]. Creating nano holes in Graphene
layer can also increase the On/Off current ratio to 2✕103 in [29]. On the other hand, applying a perpendicular electric field can
create a band gap up to a few hundred milli-electron volts in bilayer Graphene. This effect results to an On/Off current ratio as
high as 100 at room temperature and 103 at cryogenic temperature for double-gate bilayer Graphene field effect transistor
[18,19]- [27]. Although the proposed methods have advantages, but they continue to suffer from such limitations as
complexity in the fabrication process. Despite many efforts conducted and different methods presented in this area, there is
still a need for an efficient and simple structure of Graphene-based transistor.
In this paper, a new structure of a Graphene-based transistor has been designed and simulated. This structure is able to
supply less Off-current than the Graphene transistors presented so far and consequently provides high On/Off current ratio.
The proposed structure is a Graphene-based Field Effect Diode (G-FED) consisting of a Graphene channel, in which the carrier
concentration can be modulated by the two gates over the Graphene channel. To compare the On/Off current ratio, a G-FET
with the comparable size is also designed and presented. The current-voltage graphs have been drawn and the carrier
concentration has been measured in both On and Off modes. The G-FED shows an on/off current ratio of about 100. This value
is about one order of magnitude larger than the On/Off current ratio of a comparable G-FET. Considering the simple structure
of G-FED along with the higher On/Off current ratio, this device can be a good functional component in Graphene-based
circuits.

2. Field effect diode (FED)

Fig. 1 shows the structure of a Silicon-based FED. The FED is a field effect component that has been formed to control the
current by two gate terminals [32e41]. The FED construction is similar to the MOSFET construction, except that it has two
upper gates. Another difference is related to the type of source and drain impurities. In FED, the source and the drain im-
purities are unlike each other. In addition, by applying voltages with opposite polarities on the gates, a separate electron and
hole concentration is created inside the thin semiconductor channel.
Applying enough negative and positive voltages to drain-gate (GD) and source-gate (GS) induce p and n regions under the
drain-gate (GD) and source-gate (GS), respectively. Looking from drain to source the p-pn-n structure is created via field effect
that is considered as On-state of the device. The ppnn sequence from drain to source lets the current flow, as in a conventional
p-n diode. Reversing the polarity of voltages applied to drain-gate (GD) and source-gate (GS) creates p-np-n structure from
drain to source which is considered as Off-state. In this state, the reverse biased “np” diode inside the channel precludes the

Fig. 1. Schematic of Field Effect Diode (FED) structure. In this device, two top gates are biased oppositely to induce n or p regions in the channel between drain
and source. Applying negative voltage to GD and positive voltage to GS creates p-region and n-region from drain to source, respectively. In this state, the structure
works like a traditional p-n junction. Inverting the sign of gate voltages induce n-region and p-region under GD and GS, respectively. In this mode, the reversed
bias n-p diode through the channel precludes the current flow from drain to source.
830 A. Sotoudeh, M. Amirmazlaghani / Superlattices and Microstructures 120 (2018) 828e836

Table 1
ON and OFF modes of Field Effect Diode as a function of gate voltages.

State VGD VGS Structure

On e þ ppnn
Off þ e pnpn

current flow from drain to source and limits the Off current of the device to only the saturation current of a reverse biased
diode. Table 1 demonstrates On and Off operation modes of FED by applying voltages to its gates. Other operation modes can
also be considered for FED which are discussed in more details in [32,36]. Due to the exponential current-voltage relation and
the absence of pinch-off phenomenon in the channel of FED, this component provides high On-current, low Off-current, low
output resistance and high speed [32e35], [37]. The reported simulation results show that the On/Off current ratio in the 3D
structure of FED is 5 orders of magnitude larger than a comparable SOI-MOSFET [34,35]. Large-signal and small-signal
modelling of FED illustrates that a new high-speed digital family can be implemented based on this device [33]. For
example, SRAM cells based on FED can work much faster than MOSFET structures [37]. Large current handling of FED makes
this device also a good candidate for design of high frequency analog circuits [32]- [35]- [41]. The main idea of this paper is to
present Graphene-based FED (G-FED) as a new Graphene transistor which can be used instead of G-FET to improve the
performance of the Graphene-based transistor in the new emerging Graphene-based electronics.

3. Graphene-based Filed Effect Diode (G-FED)

The ability to control the electronic properties of materials by applying an external voltage has expanded in modern
electronics. In many cases, it is the electric field effect that allows a change in the carrier concentration and, consequently, a
change in electrical current of a semiconductor component [42,43]. In the case of Graphene, the electric field of an isolated
gate can change the Fermi energy level [44]. This feature leads to design of field effect devices based on Graphene, such as
Graphene-Field Effect Transistor (G-FET). On the other hand Graphene has no energy band gap and its intrinsic sheet carrier
density is large in comparison with semiconductors at ambient condition [4]. These two features makes the Graphene carriers
not to be changed very significantly by the external electric field. This is exactly the reason why G-FETs are not as efficient as
semiconductor FETs. Actually, there is no significant electrical difference between On and Off states of G-FETs, and On/Off
current ratio is less than 10 without channel patterning or without using Graphene nanoribbons or multilayer graphene. In this
section, we simulate Graphene-based FED (G-FED) and we expect that this device provide clearer difference between On and
Off characteristics in comparison with G-FETs.
Using TCAD-3D simulator, we have simulated a G-FED structure with channel length of 85nm. Fig. 2 a demonstrates the
structure of the simulated G-FED. As is shown, Graphene is deposited on a SiO2 substrate and two gates are placed over its
channel. The gates are isolated from channel by using a thin oxide layer. To compare the electrical characteristics of G-FED
with G-FET, a 3D structure of G-FET is also designed and simulated. Fig. 2 b shows the structure of the simulated G-FET. The
geometrical parameters of the simulated G-FED and G-FET are stated in Table 2. To characterize Graphene in TCAD simulator,

Fig. 2. a) Three-dimensional structure of the Graphene-based field effect diode (G-FED). b) 3D structure of Graphene Field Effect Transistor (G-FET). In the above
structures, Graphene acts as the channel.

Table 2
Structural parameters for G-FED and G-FET

Symbol GFED GFET

Channel Length 85 nm 85 nm
Device Width 18 nm 18 nm
Device Length 175 nm 175nm
Gate-oxide Thickness 5 nm 5 nm
Space between GD and GS 5 nm ———
Bulk oxide Thickness 3 nm 3 nm
 A. Sotoudeh, M. Amirmazlaghani / Superlattices and Microstructures 120 (2018) 828e836 831

Table 3
Physical parameters for Graphene definition.

Physical Parameter Graphene

Energy band gap at 300 K, (EG300). 0
Electron and hole mobility (mun, mup). 10000 cm2/v.s
Permittivity 6.9
Electron and hole intrinsic volume density at 300 K, (NC300 and NV300). 1e17 cm3
Electron and hole lifetimes, Schockley-Read-Hall recombination (Taun0, Taup0). 1e-14 s

Fig. 3. a) The graph of electron and hole volume density from drain to source in G-FED in On state, the “pn” region in the middle is created by electric field of gate
voltages. The sequence of ppnn from drain to source (from right to left) is considered as On state which can conduct current by applying a positive drain voltage.
b) The graph of the electron and hole volume concentration from drain to source in the G-FED in OFF mode, the induced “np” region in the channel precludes the
current flow from drain to source in Off state.

we have defined its physical characteristics like energy band gap [4], carrier mobility [28] [30,31], intrinsic carrier concen-
tration [45], recombination parameters [46], electron affinity [8] [47], permittivity [48], refraction index and extinction co-
efficient in the simulator environment as a new material [48e50]. The physical parameters of the simulated Graphene sheets
are stated in Table 3. The following physical models are incorporated for simulation of G-FED and G-FET: Band gap Narrowing
(BN), Concentration Dependent (CD), Parallel Electric Field Dependence (PEFD), Shockley-Read-Hall, Lombardi (CVT), Fermi-
Dirac model, Concentration Dependent and Selberherr's model.
As in Table 1, applying enough positive voltage to drain-gate and enough negative voltage to source-gate creates hole
and electron inversion layers, respectively. The sequence of “ppnn” from drain to source is created which corresponds to
On-state of G-FED. Fig. 3 a demonstrates the carrier density from the drain to source contact inside the channel. Electrons
are in black and holes in red clearly showing the two separately “doped” regions in the channel. Fig. 4 a shows the energy
band diagram at steady state inside the channel for On state. For better understanding, a graphical linear dispersion
relation for Graphene is added to the calculated band diagram. As shown, in the channel and under the drain-gate, the
Graphene carriers are located below the Dirac point in energy-momentum curve, which corresponds to p-doped region.
On the other hand, the Graphene carriers are accumulated over the Dirac point under the source-gate in the channel.
Consequently, looking from drain to source the energy band diagram of a p-n junction can be observed. The built-in
potential of the induced p-n junction is calculated 0.34V at ±1.5V biases applied to gates. A rectifying behaviour is ex-
pected from such a potential barrier.
It is worth noting that any change in the applied voltage to the gates, results in variation in the height of potential
barrier or built-in potential of the induced p-n junction. Hence, the gate voltages can control the current flow from
drain to source. The energy band diagram and the built-in potential of G-FED are shown for four different gate
voltages in Fig. 4 c.
73. According to the second state of Table 1 and Fig. 3 b, the application of a negative voltage to the source-gate causes the
holes to accumulate under the surface and form the p-region, as well as, the application of a positive voltage to the drain-gate
leads to the accumulation of electrons under the surface and formation of n-region. Looking from drain to source the “pnpn”
structure is induced in Graphene channel. This structure is considered as the Off-state of G-FED and does not have the ability
to transmit the current due to the reversed “np” junction in the middle. Fig. 4 b demonstrates the energy band diagram of G-
FEF in Off-state. As can be seen, the energy band diagram from darin to source corresponds to a reverse biased diode. We
expect that G-FED provide very small current from drain to source in this state. We check the current-voltage characteristic
curves in the next section.
832 A. Sotoudeh, M. Amirmazlaghani / Superlattices and Microstructures 120 (2018) 828e836

Fig. 4. a) The energy band diagram at steady state inside the channel for On state. For better understanding, a graphical linear dispersion relation for Graphene is
added to the calculated band diagram. As shown, in the channel and under the drain-gate, the Graphene carriers are located below the Dirac point in energy-
momentum curve, which corresponds to p-doped region. On the other hand, the Graphene carriers are accumulated over the Dirac point under the source-gate in
the channel. Consequently, looking from drain to source (right to left) the energy band diagram of a p-n junction can be observed. b) The energy band graph of the
G-FED in Off state. c) The energy band diagram of G-FED in On-state for four different gate voltages. As can be seen, the height of the built in barrier potential can
be changed and tuned by gate voltages. This results in a controllable current flow in G-FED.

4. Results and discussion

DC current-voltage characteristics of G-FED are obtained and the relevant linear and semi-logarithmic results are provided
in Fig. 5. Fig. 5 a shows the drain current with respect to the drain voltage VDS. The drain current on a log plot with respect to
VDS is demonstrated as the inset of this figure. The linear portion of the plot is indicative of the exponential behaviour of the p-
n junction and for an ideal diode has to exhibit a 60mV/decade slope, which is roughly what this plot reveals (about 55 mV/
decade). The roll-off at higher voltages is due to well-known high injection phenomenon present in p-n diodes [42,43], [52].
To ensure the effect of this phenomenon in G-FED, we calculated the (I-V) characteristic curve at different temperatures from
50 K to 400 K. Since the intrinsic carrier concentration in Graphene decreases with temperature reduction [45], this mea-
surement can help to see the effect of high-level injection phenomenon in Graphene-based devices at higher temperatures.
Fig. 5 b shows the (I-V) characteristic curves of G-FED from 50 K to 400 K. The semi-logarithmic plot is shown as the inset of
this figure. As can be seen, at low temperatures the (I-V) characteristic curve has almost a perfect exponential shape in
 A. Sotoudeh, M. Amirmazlaghani / Superlattices and Microstructures 120 (2018) 828e836 833

Fig. 5. a) Current-voltage curve of the G-FED, The rectifying behaviour can be observed in this plot. The drain current on a log plot with respect to VDS is
demonstrated as the inset of this figure. b) the (I-V) characteristic curves of G-FED from 50 K to 400 K. The semi-logarithmic plot is shown as the inset of this
figure. As can be seen, at low temperatures, the (I-V) characteristic curve has a better exponential shape in comparison with the (I-V) curves at high temperatures.
c) The (I-V) characteristic curve for different voltages applied to gates from 0.6V to 1.5V for G-FED. Increasing the absolute value of gate voltages result in raising of
the built-in potential of the induced p-n junction and consequently better rectifying behaviour. The corresponding energy band diagram is demonstrated in Fig. 4
c.

comparison with the (I-V) curves at high temperatures. In other words, the high level injection has great effect on current
saturation at higher temperatures in comparison with cryogenic temperatures. This is mainly due to the decrease of Graphene
carriers by lowering the temperature [45]. The semi-logarithmic (I-V) curve provides a better understanding of this effect.
As explained in previous sections, the current of G-FED can be controlled by the applied voltage to its gate terminals. Fig. 5
c demonstrates the (I-V) characteristic curve for different voltages applied to gates from 0.6V to 1.5V. Increasing the absolute
value of gate voltages result in raising of the built-in potential of the induced p-n junction and consequently better rectifying
behaviour. The corresponding energy band diagram is demonstrated in Fig. 4 c in the previous section.
The graph below shows the On and Off current of the G-FED at room temperature. By applying a positive and negative
electrical potential difference to the gates, FED can be turned on or off, so that it is in the ON mode and directs when the drain-
gate is negative (-1.5) and the source-gate is positive (þ1.5). Alternatively, when the drain-gate is positive (þ1.5) and the
source-gate is negative (-1.5), the structure is inverse and it does not direct, that is, the component is turned off. The On/Off
current ratio is approximately 100 in the G-FED at room temperature and under VGS ¼ -VGD ¼ ±1.5V and VDS ¼ 1.5V. The On/
Off current ratio of G-FED is also calculated as a function of different drain voltages and shown in Fig. 6 b.
To compare the On/Off current ratio of the simulated component with that of Graphene transistor, a G-FET structure (see
Fig. 2b) with the same size and parameters is designed and simulated. Fig. 7 a demonstrates the (ID-VDS) curve of G-FET for
different gate voltages. The On and Off current of the Graphene transistor (G-FET) at room temperature is illustrated in Fig. 7 b.
By applying the 1.5V gate voltage, the transistor will be in ON mode, and by applying the zero gate voltage, the transistor will
be in OFF mode. The On/Off current ratio is approximately 16 in the G-FET and under VG ¼ 1.5V. This value is close to the
practical results for On/Off current ratio like 2.4 [14], 3 [15], 5 [19], 7 and 10 [20]. The On/Off current ratio of G-FET is calculated
as a function of drain voltage and shown in Fig. 6 b.
It is worth to note that the small current handling of G-FED in Off-mode in comparison with G-FET, shows the good
potential of this device for digital applications. On the other hand, the nonlinear relation between drain current and drain
voltage in G-FED makes this device a good candidate for mixing the electrical signals. As described in the previous sections,
this nonlinear relation can also be controlled by gate voltages. In other words, two top gates can be fed by two signals with
834 A. Sotoudeh, M. Amirmazlaghani / Superlattices and Microstructures 120 (2018) 828e836

Fig. 6. a) Logarithmic graph of the drain current in both On and Off states as a function of drain voltage for G-FED.b) The On/Off current ratio of G-FED and G-FET
at different drain voltages. The average value of Ion/Ioff is calculated about 100 for G-FED while the average value of Ion/Ioff is calculated about 16 for G-FET.

Fig. 7. a) The (I-V) characteristic curve for different voltages applied to gates from 0.6V to 1.5V for G-FET, as can be seen the drain current of the simulated G-FET
saturates by increasing the drain voltages and the current cab be controlled by the gate voltages, like traditional Si-based MOSFETs. b) Logarithmic graph of the
drain current in both On and Off states as a function of drain voltage for G-FET.

different frequencies and the mixed signal can be get in drain electrode. In comparison with regular p-n mixer, G-FED does not
suffer from isolation or coupling circuits which are needed in regular p-n mixers. Implementation of different analog and
digital application of G-FED is the research subject of our group and the results can be published as another paper.

5. Conclusion

83. This paper presents a report on the structure of the Graphene-based field effect diode. Then, the features of the on/off
current ratio of this component have been investigated. Given that the on/off current ratio is not optimal in the Graphene
transistors, we have presented in this paper a component that has an appropriate on/off current ratio, which is based on the
structure of the field effect diode (FED). Here, both the Graphene field effect diode and the Graphene transistor structures
have been analyzed in the same dimensions and conditions. The on/off current ratio obtained for the Graphene field effect
diode has been equal to 100 and it has been 16 for a Graphene transistor. In the telecommunications, there are some com-
ponents that are made of high-mobility materials due to being used in high-frequency applications. Now, if Graphene is used
in the structure of the field effect diode, it seems that we will have a high-frequency material as well as a structure that is
suitable for high frequency applications. Graphene-based telecommunication mixers can be mentioned as an example such
structures.

Acknowledgment

This work was supported by Shahid Rajaee Teacher Training university under contract number of 28240.

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