COA Comprehensive Makeup Examination 2014.

Answer Key
Section A
1. Then the processor needs access to main memory for executing instructions twice every
microsecond.( once every .500µs). The DMA module is transferring characters at a rate of 2400
characters per second, or one every 417 μs. The DMA therefore "steals" every 417th clock cycle.
which means two instructions are lost which normally could have been executed.
This slows down the processor approximately by (2/834) *100= 0.24%.

2. Average CPI = 2*0.25 + 1 *0.4 + 2* 0.15 + 3*0.2 = 1.8

MIPS rate = ( f/cpi*106)= 555 MIPS
Execution time of the program =(Ic * CPI /f) secs = 360 µs.

3. a. Immediate addressing. Operand is 12 which will be there in the address field.

b. Direct addressing. Operand will be in the contents of address 12 ie M[12]
c. Indirect addressing. Operand will be the value in the address pointed by M[12]
d. Register indirect addressing. Operand will be in the address pointed by register 12.
ie M[R12]

Section B
4. At 16 MHz, the processor has a clock period of 0.0625 μs, so that an instruction cycle

takes 12 × 0.0625 = 0.75 μs. = 750 ns. To check status requires one input-type instruction to

read the device status register, plus at least one other instruction to examine the

register contents. If the device is ready, one output-type instruction is needed to

present data to the device handler. The total is 3 instructions, requiring 2.25 μs.

5. F[i]= x[i] + y[i] - z[i]

The typical ALP in 8086 based architecture can be
Mov Bx, 6000h to hold x
mov si, 7000h to hold y
mov di, 8000h to hold z
mov dx, 9000h to hold result f
mov cx, 400h count initialized
repeat mov al, byteptr [si]
sub al, byteptr [di] al will hold the he result
add al, byteptr[bx]
 mov byteptr[dx], al
inc si
inc di
inc bx
inc dx
loop repeat
hlt

Note that each operands can be fitted in one page ( since a page will hold 1023 bytes)
The total pages accessed will be 5 . four for operands x, y, z, f and one for instruction .

6. a. The clock period is 1/F secs. Read Latency of Dram is X secs. Therefore
minimum number of wait cycles is next integer to X/(1/F) .
for example if it turns out to be2.34 then wait cycles will be 3.
b. the Read signal begins to rise early in T2. To insert two clock
cycles, the Ready line can be put in low at the beginning of T2 and kept low for 250 ns.

7. a. 1 10000011 11000000000000000000000

IEEE 32 bit format consisting of 8 bit exponent and 24 bit mantissa.

1 10000011 11000000000000000000000
exponent is 83h= 131 ; since it is in excess 127 form ,the power is 4.
mantissa is 0.75.
hence number is - 1.11 * 24 = -1.75 * 16= -28d.

b. 0 01111110 10100000000000000000000
exponent is 7eh = 126; hence power is -1.
mantissa is 0.625
hence it is 1.101 * 2-1 = 1.625/2= 0.81d

Section C

8. Restoring Method Division

Dividend : -27, Divisor 13

Quotient =- 2 ; Remainder = -1 ( check for MSB of quotient it should be 1 and for Remainder
it should be 1)
 The minimum number of bits to represent -27 is 6 .
If students are not able to
represent the Dividend and Divisor correctly in binary form , no marks needs to be given.
-27d = E5h = 100101( in 6 bits ) or 1110 0101 ( in 8 bits)
13d = 0Dh =001101( in 6 bits) or 00001101(8 bits).
Apart from this check for correct number of iteration , which depends on the number of bits taken
for the operand etc. Accordingly step marks can be given only when logical flow is there across each
iteration.
Correct answers without the above mentioned operations can be given only zero marks and nothing
more.

9. In the first pass through the loop, the Add instruction is stored at address 4 in

the cache, and its operand (A03C) at address 6. Then the operand is overwritten

by the Decrement instruction. The jnz instruction is stored at address 0. In the

second pass, the value 05D9 overwrites the jnz instruction, then jnz is read

from the main memory and again stored in location 0. The contents of the cache,

the number of words read from the main memory and from the cache, and the

execution time for each pass are as shown below.

After pass No. Cache contents MM accesses Cache accesses Time

1 4 0 40τ

005e jnz

005d add
005d dec

2 2 2 22τ

005e jnz

005d add
005d dec
3. 1 3 13τ

005e jnz
00aa 10d7
005d add
005d dec

Total 7 5 75τ

10. If we assume that the processor processes data before polling for the nextbyte, the cycles spent for
polling are 0.02 ms * 1 GHz - 1000 cycles = 19,000cycles. A polling iteration takes 60 cycles, so 19,000
cycles = 316.7 polls.Since it takes an entire polling iteration to detect a new byte, the cycles spentfor
polling are 317 * 60 = 19,020 cycles. Each byte thus takes 19,020 + 1000 =20,020 cycles. The total
operation takes 20,020 * 1000 = 20,020,000 cycles.

b. Every time a byte comes the processor takes 200 + 1000= 1200 cycles to processthe data. 0.02 ms * 1
GHz - 1200 cycles = 18,800 cycles spent on theother task for each byte read. The total time spent on the
other task is 18,800"1000= 18,800,000 cycles.

11. Throughput Improvement due to pipelining is n , where n is the number of pipeline

stages.

Number of cycles needed to Throughput

execute 1 instruction
4 stage 1.2 – 0.8*20 = 1.04 4/1.04= 3.85

6 stage 1.4- 0.8*0.2- 0.25*0.2= 1.19 6/1.19= 5.04

Thus, the 6-stage pipeline leads to higher performance.

12. (a) The rate of transfer to or from any one disk is 30 megabytes per second.

Maximum memory transfer rate is 4/(10 * 10-9)=400 megabytes per second.

Therefore, 13 disks can be simultaneously flowing data to/from the main memory.

(b) 8K/30M = 0.27 ms is needed to transfer 8K bytes to/from the disk. Seek and
rotational delays are 6 ms and 3 ms, respectively. Therefore, 8K/4 = 2K words are transferred in 9.27 ms.
But in 9.27 ms there are 927 *103 = 927 * 103 memory (word) cycles available. Therefore, over a long
period of time, any one disk steals only (2/927) * 100 = 0.2% of available memory cycles.

13. A 0 100011 010010100 = exponent is 4

B 1 011100 110100111 = exponent is -3
B will be shifted 7 times to the left so as to normalize both the exponents before addition
which means B will be 0.000000101 * 2100 after rounding off the bits
Addition will give 1.010011001 * 2100 .

Largest number is 111111 111111111 = (2- 2-9)* 232

smallest number is -(2- 2-9)* 232 ( Most negative number ).
14. X= (A - B + C * (D*E – F))/ (G+ H*K).

3 operand instruction

0 - Address 2 - Address 3- Address

Push G Mov R0, H Mov R0, H
Push H Mul R0, K Mul R0, R0, K
Push k Add R0, G add R0, R0,G
Mul Mov R1, D Mov R1, D
Add Mul R1, E Mul R1, R1, E
Push B Sub R1, F Sub R1, R1,F
Push A Mul R1, C Mul R1, R1,C
Push C Add R1, A Add R1, R1, A
Push F Sub R1, B Sub R1, R1, B
Push D Div R1, R0 Div R1, R1,R0
Push E Mov X, R1 Mov X, R1
Mul
Sub
Mul
add
sub
div

Pop X