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INTRODUCTION
Internet of Things (IoT) is the next revolution of the internet which brings
profound impact on our everyday lives. IoT is the extension of the Internet to
connect just about everything on the planet. This includes real and physical objects
ranging from household accessories to industrial engineering.
As such these “things” that are connected to the Internet will be able to take actions
or make decisions based on the information they gather from the Internet with or
without human interaction. In addition, they also update the Internet with real-time
information with the help of various sensors.
They communicate through the wireless communication channel which is not
secured and transmit real-time information through the treacherous wireless
medium. In certain applications, confidentiality, authentication, data freshness,
and data integrity might be extremely important. Therefore, encryption of data is
becoming a major concern.
The more popular and widely adopted symmetric encryption algorithm likely to
be encountered nowadays is the Advanced Encryption Standard AES. It is found
at least six times faster than triple DES (data encryption standard). A replacement
for DES was needed as its key size was too small. With increasing computing
power, it was considered vulnerable against exhaustive key search attack.
Triple DES was designed to overcome this drawback but it was found slow. THE
Internet of Things is said to revolutionize the way in which individuals and
organizations interact with the physical world.
1
According to, IoT is regarded as an extension of Internet to the real world of
physical objects, usually associated with “cyber physical system”. Everyday smart
objects could become information-security risks, and the IoT could distribute
those risks more widely than the conventional Internet.
However, it is particularly difficult to support security and privacy in the IoT. One
reason of this is due to the large amount of sensitive data in the network
Military, Health Care, Financial, Among Others.
As the multipliers dominate the hardware resource of the IIR filters, a large
number of multipliers required cause large power dissipation and large area.
An important aspect to be considered with the evolution of internet in the current
information age is secrecy and privacy. Cryptography provides confidentiality and
reliability to data during communication. It is used in different application which
includes e-commerce, wireless communications, cellular networks, online
banking, computerized networks etc.
Since a few decades, digital hardware design technology has become more similar
to software design and has evolved tremendously with the introduction of
reconfigurable platforms like FPGA.
2
like FPGA fills the gap to achieve a balance between hardware and software in
terms of performance and flexibility.
1.2 MODIFICATION:
Thus during the encryption and decryption process, to secure the data around 6
rounds are performed earlier, now thus proposing around 10 rounds to get the
secure information during encryption and also in decryption using aes algorithm.
1.3 ADVANTAGES:
We propose 1-dimensional Substitution Box (S-Box) which is constructed
by formulating a novel equation for constructing a square matrix in affine
transformation phase of MAES.
3
We implement both original AES and MAES algorithms using Verilog and
implement in FPGA Spartan-6.
After analyzing the result of our experiment we conclude that MAES is well
efficient than AES around in terms of area, number of packet transmission
and latency, respectively.
1.4 APPLICATIONS:
In certain applications, confidentiality, authentication, data freshness, and
data integrity might be extremely important.
It is used in Internet of Things (IoT), which is the next revolution of the
internet which brings profound impact on our everyday lives.
It is used in Cryptography.
4
CHAPTER 2
LITERATURE SURVEY
Borghoff, Julia, et al (2006) [3] interprets that block cipher that optimized with
respect to latency when implemented in hardware. Such ciphers are desirable for
many future pervasive applications with real-time security needs. Our cipher,
named PRINCE, allows encryption of data within one clock cycle with a very
competitive chip area compared to known solutions. The fully unrolled fashion in
which such algorithms need to be implemented calls for innovative design choices.
The number of rounds must be moderate and rounds must have short delays in
hardware. At the same time, the traditional need that a cipher has to be iterative
with very similar round functions disappears, an observation that increases the
design space for the algorithm. An important further requirement is that realizing
decryption and encryption results in minimum additional costs. PRINCE is
designed in such a way that the overhead for decryption on top of encryption is
negligible. More precisely for our cipher it holds that decryption for one key
corresponds to encryption with a related key. This property we refer to as α-
reflection is of independent interest and we prove its soundness against generic
attacks.
5
Bogdanov, Andrey et al, (2006)[4] stated that the establishment of the AES the
need for new block ciphers has been greatly diminished; for almost all block
cipher applications the AES is an excellent and preferred choice. However,
despite recent implementation advances, the AES is not suitable for extremely
constrained environments such as RFID tags and sensor networks. In this paper
we describe an ultra-lightweight block cipher. Both security and hardware
efficiency have been equally important during the design of the cipher and at
1570 GE, the hardware requirements are competitive with today’s leading
compact stream ciphers.
Daemen, Joan and Rijmen, Vincent (2007)[5] stated that AES is expected to
gradually replace the present Data Encryption Standard (DES) as the most widely
applied data encryption technology.| The designers of the block cipher presents
Rijndael from scratch. The underlying mathematics and the wide trail strategy as
the basic design idea are explained in detail and the basics of differential and linear
cryptanalysis are reworked. Subsequent chapters review all known attacks against
the Rijndael structure and deal with implementation and optimization issues.
6
top underline its value by presenting a new bloc cipher. PRIDE is optimized for
8-bit micro-controllers and significantly outperforms all academic solutions both
in terms of code size and cycle count
7
CHAPTER 3
MODULE EXPLANATION
9
3.2 ENCRYPTION PROCESS:
1. Add-round key
• The 8 bytes of the matrix are now considered as 64 bits and are XORed to
the 64 bits of the round key as shown 3.3.
• If this is the last round then the output is the ciphertext.Otherwise,in
10
Figure 3.4 S-box Layer Substitution Box
• Is a basic component of symmetric key algorithms which performs
substitution as shown in Figure 3.4. In block ciphers, they are typically used
to obscure the relationship between the key and the cipher
text — Shannon's property of confusion.
• In general, an S-box takes some number of input bits, m, and transforms
them into some number of output bits, n, where n is not necessarily equal
to m. An m × n S-box can be implemented as a lookup table with 2m words
of n bits each as shown in Figure 3.5.
• Fixed tables are normally used, as in the Data Encryption Standard (DES),
but in some ciphers the tables are generated dynamically from the key (e.g.
the Blowfish and the two fish encryption algorithms).
• One good example of a fixed table is the S-box from DES (S5), mapping 6-
bit input into a 4-bit output:
12
• Since sub-processes in each round are in reverse manner, unlike for a Feistel
Cipher, the encryption and decryption algorithms need to be separately
implemented, although they are very closely related.
3.4 APPLICATIONS:
DSP includes subfields like: audio and speech signal processing, Sonar and
radar signal processing, sensor array processing, spectral estimation, statistical
signal Processing, digital image processing, signal processing for
communications, control of systems, Biomedical signal processing, seismic
data processing, etc.
13
Mobile phone:
A mobile phone is a device that can make and receive telephone calls
over a radio link whilst moving around a wide geographic area. It does so
by connecting to a cellular network provided by a mobile phone operator,
allowing access to the public telephone network. In these mobile phones
they want to reduce the area as well as the power. So our adder design is
used to mobile phones.
Satellite application:
Satellites are used for a large number of purposes. Common types
include military and Civilian Earth observation satellites, communications
satellites, navigation satellites weather satellites, and research satellites.
Space stations and human spacecraft in orbit are also satellites.
Satellite orbits vary greatly, depending on the purpose of the satellite, and
are classified in number of ways. Well-known (overlapping) classes include
low Earth orbit, polar orbit, and geostationary orbit.
Satellites are usually semi-independent computer-controlled systems.
Satellite subsystems attend many tasks, such as power generation, thermal
control, telemetry, attitude control, and orbit control. In this control unit,
our adder will be used for some area efficient products.
14
The 16x16 2-dimensional lookup table is formed through the multiplicative
inverse phase and affine transformation phase in the original AES. We are
proposing a new 1-dimensional lookup table as S-Box. It also follows the
same generation process as the original one.
Substitution of one complete byte requires two times substitution from the
S-Box. First four bits of the state byte is replaced first then the remaining
four bits are substituted from the S-Box.
15
Figure 3.7 Original S-Box Generation Process Figure 3.8 Proposed MAES
S-box Generation Process
16
3.5.2 Modified AES S-Box Generation:
17
CHAPTER 4
REQUIREMENTS
INTRODUCTION:
18
budgets, escalating ASIC and ASSP non-recurring engineering costs, spiralling
complexity, and increased risk). To Xilinx, the programmable imperative
represents a two-fold commitment. The first is to continue developing
programmable silicon innovations at every process node that deliver industry-
leading value for every key figure of merit against which FPGAs are measured:
price, power, performance, density, features, and programmability. The second
commitment is to provide customers with simpler, smarter, and more strategically
viable design platforms for the creation of world-class FPGA-based solutions in a
wide variety of industries—what Xilinx calls targeted design platforms.
Base Platform:
The base platform is both the delivery vehicle for all new silicon offerings from
Xilinx and the foundation upon which all Xilinx targeted design platforms are
built. As such, it is the most fundamental platform used to develop and run
customer-specific software applications and hardware designs as production
system solutions. Released at launch, the base platform comprises a robust set of
well-integrated, tested, and targeted elements that enable customers to
immediately start a design. These elements include:
• FPGA silicon
• A host of widely used IP, such as GigE, Ethernet, memory controllers, and PCIe.
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4.1.3 XILINX ISE Design Tools:
Xilinx ISE is the design tool provided by Xilinx. Xilinx would be virtually
identical for our purposes.
There are four fundamental steps in all digital logic design. These consist of:
1. Design – The schematic or code that describes the circuit.
20
4.2 VERILOG –LANGUAGE:
21
A Verilog design consists of a hierarchy of modules. Modules
encapsulate design hierarchy, and communicate with other modules through a set
of declared input, output, and bidirectional ports.
22
4.3 HARDWARE REQUIREMENT
GENERAL
The last 15 years have witnessed the demise in the number of cell-based
ASIC designs as a means for developing customized SoCs. Rising NREs,
development times and risk have mostly restricted the use of cell-based ASICs to
the highest volume applications; applications that can withstand the multi-million
dollar development costs associated with 1-2 design re-spins. Analysts estimate
that the number of cell based ASIC design starts per year is now only between
2000-3000 compared to ~10,000 in the late 1990s. The FPGA has emerged as a
technology that fills some of the gap left by cell-based ASICs. Yet even after 20+
years of existence and 40X more design starts per year than cell-based ASICs, the
size of the FPGA market in dollar terms remains only a fraction that of cell-based
ASICs.
23
This suggests that there are many FPGA designs that never make it into
production and that for the most part, the FPGA is still seen by many as a vehicle
for prototyping or college education and has perhaps even succeeded in actually
stifling industry innovation. This paper introduces a new technology, the second
generation Structured ASIC that is tipped to reenergize the path to innovation
within the electronics industry. It brings together some of the key advantages of
FPGA technology (i.e. fast turnaround, no mask charges, no minimum order
quantity) and of cell-based ASIC (i.e. low unit cost and power) to deliver a new
platform for SoC design. This document defines requirements for development of
Application Specific Integrated Circuits (ASICs). It is intended to be used as an
appendix to a Statement of Work. The document complements the ESA ASIC
Design and Assurance Requirements (AD1), which is a precursor to a future ESA
PSS document on ASIC design.
Structured ASICs:
A new alternative has recently emerged to address the market void between
FPGAs and cell-based ASICs. Analysts term this as the Structured ASIC.
Like the FPGA market, the Structured ASIC market had a flurry of early
entrants many of who have departed the market. Examples include respectable
semiconductor companies like NEC, LSI logic and EDA vendors such as
Simplicity.
24
Turn-around times were still 2-5 months from tape-out to silicon
NREs were still in the range of $150-$250K or more making the technology
difficult to access for mainstream users.
Minimum order quantities were required as wafers could not be shared
amongst projects or customers
Development costs and time were also very high and long respectively, as
designers were expected to undergo rigorous verification down to the
transistor level
Designers transitioning from prototyping devices like FPGAs to first
generation Structured ASICs were still expected to redesign the product into
a completely new device, revisit timing closure and re-qualify the new
device before it production ready.
While some companies still offer first generation Structured ASICs today,
market acceptance has been severely limited as a result of these barriers to entry.
However, these first generation Structured ASICs paved the way for a new
generation that would combine the benefits of both FPGAs and cell-based ASICs.
25
This new generation of Structured ASICs, available from ASICs
Corporation, and named Extreme also removes the barriers of traditional cell
based ASICs and also first generation Structured ASICs. With Extremes
Structured ASICs advantages include:
26
are destined for high-volume systems they have been integrated into high-density
gate arrays. However, gate array NRE costs often are too expensive and gate arrays
take too long to manufacture to be viable for prototyping or other low-volume
scenarios. For these reasons, most prototypes, and also many production designs
are now built using FPDs. The most compelling advantages of FPDs are instant
manufacturing turnaround, low start-up costs, low financial risk and (since
programming is done by the end user) ease of design changes. The market for
FPDs has grown dramatically over the past decade to the point where there is now
a wide assortment of devices to choose from.
A general term that refers to any type of integrated circuit used for
implementing digital hardware, where the chip can be configured by the end user
to realize different designs. Programming of such a device often involves placing
the chip into a special programming unit, but some chips can also be configured
“in-system”. Another name for FPDs is programmable logic devices (PLDs);
although PLDs encompass the same types of chips as FPDs, we prefer the term
FPD because historically the word PLD has referred to relatively simple types of
devices.
Simple PLD:
28
Complex PLD:
29
Logic Capacity- the amount of digital logic that can be mapped into a single
FPD. This is usually measured in units of “equivalent number of gates in a
traditional gate array”. In other words, the capacity of an FPD is measured
by the size of gate array that it is comparable to. In simpler terms, logic
capacity can be thought of as “number of 2-input NAND gates”.
Logic Density - the amount of logic per unit area in an FPD.
Speed-Performance- measures the maximum operable speed of a circuit
when implemented in an FPD. For combinational circuits, it is set by the
longest delay through any path, and for sequential circuits it is the maximum
clock frequency for which the circuit functions properly. In the remainder
of this section, to provide insight into FPD development the evolution of
FPDs over the past two decades is described. Additional background
information is also included on the semiconductor technologies used in the
manufacture of FPDs.
Evolution of Programmable Logic Devices:
31
CHAPTER 5
32
RTL VIEW
34
5.2 IMPLEMENTATION OF ENCRYPTION PROCESS(MAES)
35
RTL SCHEMATIC:
36
37
5.3 IMPLEMENTATION OF BOTH ENCRYPTION AND
DECRYPTION PROCESS (AES)
39
DESIGN SUMMARY (AREA) & TIMING REPORT
40
5.4 IMPLEMENTATION OF BOTH ENCRYPTION AND DECRYPTION
PROCESS (MAES):
41
RTL VIEW AND RTL SCHEMATIC:
43
44
DESCRIPTION AREA TIMING
ANALYSIS ANALYSIS
5.5 CONCLUSION:
This method shows efficiency when encrypted packets are transmitted using the
proposed MAES to the sink node and the number of transmitted packets has
increased. In future, the security issue and space complexity will be considered to
make the proposed modification more applicable.
45
Cryptosystem, especially Elliptic-curve cryptography (ECC) to achieve
comparable efficiency in terms of number of packet transmission and latency with
better security.
46
APPENDIX
1. AES PROGRAM:
//////////////////////////////////////////////
wire [127:0]
round0,round1,round2,round3,round4,round5,round6,round7,round8,
47
round9,round10,round11,round12,round13,round14;
// addroundkey(round 1)
wire [127:0] z,
z1,z2,z4,z5,z6,z8,z9,z10,z12,z14,z15,z17,z18,z19,z23,z24,z25,z27,z28,z29,z30,z3
2,z33,z34,z35,
z36,z40,z41,z42,z43,z44,z45,z46,z47,z48,z49,z50,z51,z52,z53,z54,z55,z56,z57,z5
8,z59,z60,z61,z62,z63,z64,z65,z66;
addroundkey k1 (.a(a),.b(ak),.y(z));
subbyte k2 (.a(z),.c(z1));
shiftrows k3(.a(z1),.y(z2));
mix_columns k4 (.a(z2),.y(round0));
//
addroundkey k5 (.a(round0),.b(ak),.y(z4));
subbyte k6 (.a(z4),.c(z5));
shiftrows k7(.a(z5),.y(z6));
mix_columns k8 (.a(z6),.y(round1));
//
addroundkey k9 (.a(round1),.b(ak),.y(z8));
subbyte k10 (.a(z8),.c(z9));
shiftrows k11(.a(z9),.y(z10));
mix_columns k12 (.a(z10),.y(round2));
//
//
addroundkey k25 (.a(round5),.b(ak),.y(z27));
subbyte k26 (.a(z27),.c(z28));
shiftrows k27(.a(z28),.y(z29));
mix_columns k28 (.a(z29),.y(round6));
//
//////////////////////////////////////////////////////////////////////////////DECR
YPTION
inversemix_columns h26(.a(ciphertext),.y(z40));
inverse_shift_rows h36 (.a(z40),.y(z41));
inverse_subbyte h46 (.a(z41),.c(z42));
inverse_addroundkey h16 (.a(z42),.b(ak),.y(round8));
//////////////////////
49
inversemix_columns h25(.a(round8),.y(z43));
inverse_shift_rows h35 (.a(z43),.y(z44));
inverse_subbyte h45 (.a(z44),.c(z45));
inverse_addroundkey h15 (.a(z45),.b(ak),.y(round9));
////////////////////
inversemix_columns h24(.a(round9),.y(z46));
inverse_shift_rows h34 (.a(z46),.y(z47));
inverse_subbyte h44 (.a(z47),.c(z48));
inverse_addroundkey h14 (.a(z48),.b(ak),.y(round10));
////////////////
inversemix_columns h72(.a(round10),.y(z49));
inverse_shift_rows h73 (.a(z49),.y(z50));
inverse_subbyte h74 (.a(z50),.c(z51));
inverse_addroundkey h71 (.a(z51),.b(ak),.y(round11));
////////////////////////////
inversemix_columns h82(.a(round11),.y(z52));
inverse_shift_rows h83 (.a(z52),.y(z53));
inverse_subbyte h84 (.a(z53),.c(z54));
inverse_addroundkey h81 (.a(z54),.b(ak),.y(round12));
///////////////////////////////
inversemix_columns h92(.a(round12),.y(z55));
inverse_shift_rows h93 (.a(z55),.y(z56));
inverse_subbyte h94 (.a(z56),.c(z57));
inverse_addroundkey h91 (.a(z57),.b(ak),.y(round13));
///////////////
inversemix_columns h204(.a(round14),.y(z61));
inverse_shift_rows h302 (.a(z61),.y(z62));
inverse_subbyte h401 (.a(z62),.c(z63));
inverse_addroundkey h108 (.a(z63),.b(ak),.y(decrypt));
endmodule
2.MAES PROGRAM:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:33:08 03/06/2019
// Design Name:
// Module Name: bothmaes
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module bothmaes(a,ak,ciphertext,decryption);
51
//////////////////////////////////////////////
input [127:0]a; // plaintext
wire [127:0]
round0,round1,round2,round3,round4,round5,round6,round7,round8,
round9,round10,round11,round12,round13,round14;
// addroundkey(round 1)
wire [127:0] z,
z1,z2,z4,z5,z6,z8,z9,z10,z12,z14,z15,z17,z18,z19,z23,z24,z25,z27,z28,z29,z30,z3
2,z33,z34,z35,
z41,z42,z43,z44,z45,z46,z47,z48,z49,z50,z51,z52,z53,z54,z55,z56,z57,z58,z59,z6
0,z61,z62,z63;
addroundkey k1 (.a(a),.b(ak),.y(z));
subbyte_maes k2 (.a(z),.c(z1));
shiftrows k3(.a(z1),.y(z2));
mix_columns k4 (.a(z2),.y(round0));
//
addroundkey k5 (.a(round0),.b(ak),.y(z4));
subbyte_maes k6 (.a(z4),.c(z5));
shiftrows k7(.a(z5),.y(z6));
mix_columns k8 (.a(z6),.y(round1));
//
addroundkey k9 (.a(round1),.b(ak),.y(z8));
subbyte_maes k10 (.a(z8),.c(z9));
shiftrows k11(.a(z9),.y(z10));
52
mix_columns k12 (.a(z10),.y(round2));
//
//
addroundkey k25 (.a(round5),.b(ak),.y(z27));
subbyte_maes k26 (.a(z27),.c(z28));
shiftrows k27(.a(z28),.y(z29));
mix_columns k28 (.a(z29),.y(round6));
//
inversemix_columns h25(.a(round8),.y(z43));
inverse_shift_rows h35 (.a(z43),.y(z44));
inverse_subbyte_maes h45 (.a(z44),.c(z45));
inverse_addroundkey h15 (.a(z45),.b(ak),.y(round9));
////////////////////
inversemix_columns h24(.a(round9),.y(z46));
inverse_shift_rows h34 (.a(z46),.y(z47));
inverse_subbyte_maes h44 (.a(z47),.c(z48));
inverse_addroundkey h14 (.a(z48),.b(ak),.y(round10));
////////////////
inversemix_columns h72(.a(round10),.y(z49));
inverse_shift_rows h73 (.a(z49),.y(z50));
inverse_subbyte_maes h74 (.a(z50),.c(z51));
inverse_addroundkey h71 (.a(z51),.b(ak),.y(round11));
////////////////////////////
wire [127:0] decrypt;
assign decryption = a;
inversemix_columns h82(.a(round11),.y(z52));
inverse_shift_rows h83 (.a(z52),.y(z53));
inverse_subbyte_maes h84 (.a(z53),.c(z54));
inverse_addroundkey h81 (.a(z54),.b(ak),.y(round12));
///////////////////////////////
inversemix_columns h92(.a(round12),.y(z55));
54
inverse_shift_rows h93 (.a(z55),.y(z56));
inverse_subbyte_maes h94 (.a(z56),.c(z57));
inverse_addroundkey h91 (.a(z57),.b(ak),.y(round13));
///
inversemix_columns h102(.a(round13),.y(z58));
inverse_shift_rows h103 (.a(z58),.y(z59));
inverse_subbyte_maes h104 (.a(z59),.c(z60));
inverse_addroundkey h105 (.a(z60),.b(ak),.y(round14));
///////////////
inversemix_columns h204(.a(round14),.y(z61));
inverse_shift_rows h302 (.a(z61),.y(z62));
inverse_subbyte_maes h401 (.a(z62),.c(z63));
inverse_addroundkey h108 (.a(z63),.b(ak),.y(decrypt));
endmodule
55
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