Circuit Symbols of Electronic Components

[Copias de transparencias] [Guiones de prácticas guiadas][Cómo diseñar un ...
] [Tutoriales]
[Placas de prototipado] [Placas de expansión] [Data Sheets] [Application Notes] [Ejecutables] [Miscelánea]
Copias de transparencias
● Temario
❍ Tema 1. Diseño automático
❍ Tema 2. Especificación a nivel lógico de sistemas HW.
❍ Tema 3. Especificación a nivel lógico-RT de sistemas HW usando VHDL.
❍ Tema 4. Análisis de circuitos de nivel lógico.
❍ Tema 5. Técnicas de diseño de nivel lógico.
❍ Tema 6. Batería de diseños
■ Pulsadores, teclados y ratones.
■ Memorias SRAM.
■ Leds, displays, LCDs y monitores.
■ Zumbadores, altavoces y audio CODECs.
■ Comunicación serie: RS-232, USB.
■ Buses I2C, ISA y PCI.
■ Procesado de vídeo.
■ Comunicación ethernet.
❍ Anexo. Material docente en los laboratorios de la Facultad de Informática.
● Temas adicionales
❍ Tema 7. Especificación a nivel RT de sistemas HW.
❍ Tema 8. Especificación a nivel RT-algorítmico de sistemas HW usando VHDL.
❍ Tema 9. Técnicas de diseño de nivel RT.
● VHDL
❍ VHDL'87 completo - Un repaso de las construcciones del lenguaje que presta especial atención a su
utilidad en modelado de sistemas digitales.
❍ VHDL'87, subconjunto sintetizable de nivel RT-lógico - Describe el subconjunto de construcciones VHDL
admisibles por una herramienta de síntesis lógica-RT, cómo se implementan y cómo deben ser
utilizadas para especificar sistemas digitales.
❍ VHDL'87, subconjunto sintetizable de alto nivel - Describe el subconjunto de construcciones VHDL
admisibles por una herramienta de síntesis de alto nivel, cómo se implementan y cómo deben ser
utilizadas para especificar sistemas digitales.
● Técnicas de diseño
❍ Especificación a nivel RT de sistemas HW - Describe las nociones de ASM y cómo usarlo para
especificar circuitos a un alto nivel de abstracción.

❍ Técnicas de diseño de nivel RT - Describe cómo optimizar circuitos a un alto nivel de abstracción.
❍ Fundamentos del diseño hardware - Repaso de nociones de electrónica, diseño hardware básico, etc.
● Synopsys
❍ Synopsys VHDL System Simulator - Arquitectura del simulador: herramientas y comandos.
❍ Synopsys Design Tools - Arquitectura del entorno de síntesis.
❍ Synopsys Design Compiler - Arquitectura del sintetizador de nivel lógico-RT: ciclo de diseño,
herramientas y comandos.
❍ Synopsys Behavioral Compiler - Arquitectura del sintetizador de alto nivel: ciclo de diseño, herramientas
y comandos.
● Xilinx Foundation
❍ Xilinx Foundation - Arquitectura del entorno de síntesis.
Guiones de prácticas guiadas

● Modelado y simulación de sistemas usando SYNOPSYS VHDL System Simulator (versión 1997-08).
● Síntesis lógica usando SYNOPSYS Design Compiler (versión 1997-08).
● Síntesis lógica usando XILINX Foundation (versión 2000-12).
● Síntesis de alto nivel usando SYNOPSYS Behavioral Compiler (versión 2000-12).
Cómo diseñar un ...
(diseños didácticos)
● Eliminador de rebotes (estructura, vhdl).

❍ Diseño didáctico: bouncing (vhdl, ucf placa tipo A-B-C, ucf placa tipo D)
● Interfaz con un teclado PS-2 (estructura, vhdl):

❍ Diseño didáctico: keyboard (vhdl, ucf placa tipo A-B-C, ucf placa tipo D)
● Interfaz con un ratón PS-2 (estructura, vhdl):

❍ Diseño didáctico: mouse (vhdl, ucf placa tipo A-B-C, ucf placa tipo D)
● Interfaz síncrono de SRAM (estructura).

❍ Diseño didáctico: badSRAM (vhdl, ucf placa tipo A-B-C, ucf placa tipo D)
❍ Diseño didáctico: SRAM1 (vhdl, ucf placa tipo A-B-C, ucf placa tipo D)
● Refresco de bancos multiplexados

❍ Diseño didáctico: refresh (vhdl, ucf placa tipo A-B-C, ucf placa tipo D)
● Interfaces con un monitor VGA:

❍ Nociones de temporización (estructura)
■ Diseño didáctico: VGA (vhdl, ucf placa tipo A-B-C, ucf placa tipo D)
❍ Interfaz gráfico monocromo direccionable X-Y (estructura, vhdl).
■ Diseño didáctico: graphic (vhdl, ucf placa tipo A-B-C, ucf placa tipo D)
❍ Interfaz alfanumérico monocromo direccionable X-Y (estructura, vhdl).
■ Diseño didáctico: alphanum (vhdl, ucf placa tipo A-B-C, ucf placa tipo D)
❍ Interfaz alfanumérico monocromo tipo terminal (estructura, vhdl).
■ Diseño didáctico: terminal (vhdl, ucf placa tipo A-B-C, ucf placa tipo D)
● Interfaz con un stereo CODEC (estructura, vhdl).

❍ Diseño didáctico: buzzer (vhdl, ucf placa tipo A-B-C, ucf placa tipo D)
❍ Diseño didáctico: bipper (vhdl, ucf placa tipo A-B-C, ucf placa tipo D)
● Modulación de señales:
❍ Generador de formas de onda (estructura, vhdl).
❍ Generador de frecuencia (estructura, vhdl).
❍ Modulador de pulsos (estructura, vhdl).
● Conversión de código:
❍ Conversores entre códigos binario y Gray (estructura, vhdl).
❍ Conversores entre códigos binario y BCD-8421 (estructura, vhdl).
● Varios:
❍ Multiplicador por constante (estructura, vhdl).
❍ Generador de números pseudo-aleatorios (estructura, vhdl).
Tutoriales
● Foundation Series 2.1i In-Depth Tutorials - Tutorial de XILINX Foundation.
Placas de prototipado
● XS40-010XL Board:
❍ Características.
❍ Manual de usuario (v1.2, v1.3, v1.4).
❍ Manual de usuario de las herramientas software para el manejo de la placa (v1.3).
❍ Manual de usuario de los microcontroladores de la familia 8051 fabricados por OKI Semiconductor.
❍ Manual de usuario del ensamblador cruzado para los microcontroladores de la familia 8051.
❍ Compilador cruzado de C para los microcontroladores de la familia 8051.
● XSA-100 Board:
❍ Manual de usuario (v1.2).
● XStend Board:
❍ Características (v1.x, v2.x).
❍ Manual de usuario (v1.2, v1.3, v1.3.2, v2.0).
● XSV-800 Board

● XSTE5 CSoC Board
● APS - V240
❍ Manual de usuario
❍ Esquemáticos
Placas de expansión
(diseñadas y contruídas por Carlos Roa Romero)
● Teclado numérico:
❍ Esquemático (v1.0).
● Banco de displays 7-segmentos:

● Matriz de leds:
● LCD
❍ Control básico de LCDs.
● Banco de interruptores, pulsadores y leds

● Zumbador y altavoz
Data Sheets
(componentes de las placas de prototipado y de expansión)
● XS40-010XL v1.2 (Xess Corporation):

❍ MSM80C154S - Microcontrolador de 8 bits compatible con el 8051 (OKI Semiconductor).
❍ W24257AK - 32Kx8 SRAM (Winbond Electronics).
❍ XC4010XL - FPGA de 10K puertas (Xilinx).

❍ W78C31B - Microcontrolador de 8 bits compatible con el 8051 (Winbond Electronics).
❍ AS7C256 - 32Kx8 SRAM (Alliance Semiconductor).
❍ DS1075 - Oscilador programable (Dallas Semiconductor).

❍ W78C31B / W78C32B - Microcontrolador de 8 bits compatible con el 8051 (Winbond Electronics).
❍ AS7C256 / AS7C1024 - 32Kx8 / 128Kx8 SRAM (Alliance Semiconductor).
● XSA-100 v1.2 (Xess Corporation):

❍ HY57V281620HCT - 4x2Mx16 SDRAM (Hynix Semiconductor).
❍ AT49F002 - 256Kx8 Flash RAM (Atmel Corporation).
❍ XC2S100 - FPGA de 100K puertas (Xilinx).
❍ XC9572XL - CPLD de 1600 puertas (Xilinx).
● XStend v1.2 (Xess Corporation):

❍ CS4222 - Conversor A/D & D/A estéreo de 20 bits (Cirrus Logic).
● XStend v1.3, v1.3.2 (Xess Corporation):

❍ W24257A - 32Kx8 SRAM (Winbond Electronics).
❍ AK4520A - Conversor A/D & D/A estéreo de 20 bits (Asahi Kasei Microsystems).
● XStend v2.0 (Xess Corporation):

❍ PDIUSBD11 - Interfaz USB con conexión I2C (Philips Semiconductors).
● XSV-800 v1.0 (Xess Corporation):
❍ XCV800 - FPGA de 800K puertas (Xilinx).
❍ XC95108 - CPLD de 2400 puertas (Xilinx).
❍ 28F016S5 - 16Mbit Flash RAM (Intel Corporation).
❍ SAA7113 - Procesador de video de 9 bits, sistemas NTSC, SECAM y PAL (Philips Semiconductors).
❍ BT481A - RAMDAC de 256 entradas y 24 bits de color (Brooktree Corporation).
❍ LXT970A - Transceiver Ethernet PHY (Level One Communications).
❍ PDIUSBP11A - Transceiber USB (Philips Semiconductors).
● XSTE5 CSoC Board (Xess Corporation):

❍ TE505 - System-on-chip formado por un microcontrolador 8032, 2 controladores DMA, 16 Kb de SRAM
interna y un array 512 celdas programables (Triscend Corporation).

❍ part number - 128Kx8 SRAM
❍ AS29F002 - 128Kx8 Flash RAM (Alliance Semiconductor).
● APS - V240 (Associated Professional Systems)

❍ XCV300 - FPGA de 300K puertas (Xilinx).
❍ XC18V04 - PROM de 5Mbit (Xilinx).
❍ XC9572XL - CPLD de 1600 puertas (Xilinx).
❍ IDT71V3558 - 256Kx18 ZBT SRAM síncrona (Integrated Device Technology)
❍ MAX3223 - Transceiber RS-232 (Maxim)
❍ PI6C918W - Oscilador (Pericom)
● Banco de displays 7-segmentos :

❍ 74HC138 - Decodificador inversor 3 a 8.
● Matriz de leds:
❍ 74HC594 - Registro de desplazamiento de 8 bits con salida registrada.
❍ ULN2803 - Array de 8 transistores Darlington.
● LCD
❍ AC162B - LCD alfanumérico 16x2 (Ampire).
❍ KS0066U - Controlador de LCDs matriciales (Samsung Electronics).
❍ HD44580 - Controlador de LCDs matriciales (Hitachi).
Application Notes
● Xess Corporation:
❍ Microcontroller + FPLD Designs with the XS40 & XS95 Boards.
❍ XSV Parallel Port Interface (código fuente).
❍ XSV Flash Programming and Virtex Configuration (código fuente).
❍ XSTOOLs Source Documentation 3.0 (código fuente).
● Familia 4000 de Xilinx:

❍ XAPP 052 July 7, 1996 - Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence
Generators.
❍ XAPP 057 July 7, 1996 - Usign Select-RAM Memory in XC4000 Series FPGAs.
❍ XAPP 094 November 24, 1997 - Metastable Recovery.
❍ XAPP 107 August 6, 1998 - Synopsys/Xilinx High Density Design Methodology Usign FPGA Compiler.
❍ XBRF 014 June 30, 1997 - A Simple Method of Estimating Power in XC4000XL/EX/E FPGAs.
❍ XBRF 015 November, 1997 - Speed Metrics For High-Perfomance FPGAs.
● Familia Virtex de Xilinx:

❍ XAPP 130 March 16, 2000 - Usign the Virtex Block SelectRAM+Features.
❍ XAPP 137 March 1, 1999 - Configuring Virtex FPGAs from Parallel EPROMs with a CPLD.
❍ XAPP 138 February 24, 2000 - Virtex FPGA Series Configuration and Readback.
❍ XAPP 151 February 22, 2000 - Virtex Series Configuration Architecture User Guide.
Ejecutables
● Placas de prototipado:
❍ Test para las placas de prototipado XS40+XStend (v1.2, v1.3).
❍ XStools (v1.5, v2.0.3, v3.0.0, v.4.0, v4.0.2, v4.0.3) - utilidades software para el manejo de las placas de
prototipado XS40 (xsload, xsport, xstest, xsetclk, etc).

❍ XSVTools - utilidades software para el manejo de las placas de prototipado XSV.
● Microcontroladores 8051:
❍ Ensamblador cruzado para los microcontroladores de la familia 8051.
❍ Emulador de los microcontroladores de la familia 8051.
❍ Compilador cruzado de C para los microcontroladores de la familia 8051.
Miscelánea
● Especificaciones de interfaces estándar:
2
❍ I C - Especificación del Inter Integrated Circuit Bus.
❍ USB - Especificación del Universal Serial Bus.
Página creada y modificada por J. M. Mendías / Ultima actualización Nov-04

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LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY debouncer IS
PORT (
rst: IN std_logic;
clk: IN std_logic;
x: IN std_logic;
xDeb: OUT std_logic;
xDebFallingEdge: OUT std_logic;
xDebRisingEdge: OUT std_logic
);
END debouncer;
ARCHITECTURE debouncerArch of debouncer is
SIGNAL xSync: std_logic;

SIGNAL startTimer, timerEnd: std_logic;
BEGIN
synchronizer:
PROCESS (rst, clk)
VARIABLE aux1: std_logic;
BEGIN
IF (rst='0') THEN
aux1 := '1';
xSync <= '1';
ELSIF (clk'EVENT AND clk='1') THEN
xSync <= aux1;
aux1 := x;
END IF;
END PROCESS synchronizer;
timer:
-- espera 50 ms para un reloj a 12.5 MHz
PROCESS (rst, clk)
CONSTANT timeOut: std_logic_vector (19 DOWNTO 0) := "10011000100101101000";
VARIABLE count: std_logic_vector (19 DOWNTO 0);
BEGIN
IF (count=timeOut) THEN
timerEnd <= '1';
ELSE
timerEnd <= '0';
END IF;
IF (rst='0') THEN
count := timeOut;
IF (startTimer='1') THEN
count := (OTHERS=>'0');
ELSIF (timerEnd='0') THEN
count := count + 1;
END IF;
END IF;
END PROCESS timer;
controller:
PROCESS (xSync, rst, clk)
TYPE states IS (waitingPression, pressionDebouncing, waitingDepression, depressionDebouncing);
VARIABLE state: states;
BEGIN
xDeb <= '1';
xDebFallingEdge <= '0';
xDebRisingEdge <= '0';
startTimer <= '0';
CASE state IS
WHEN waitingPression =>
IF (xSync='0') THEN
xDebFallingEdge <= '1';
startTimer <= '1';
END IF;
WHEN pressionDebouncing =>
xDeb <= '0';
WHEN waitingDepression =>
xDeb <= '0';
IF (xSync='1') THEN
xDebRisingEdge <= '1';
startTimer <= '1';
END IF;
WHEN depressionDebouncing =>
NULL;
END CASE;
IF (rst='0') THEN
state := waitingPression;
CASE state IS
WHEN waitingPression =>
IF (xSync='0') THEN
state := pressionDebouncing;
END IF;
WHEN pressionDebouncing =>
IF (timerEnd='1') THEN
state := waitingDepression;
END IF;
WHEN waitingDepression =>
IF (xSync='1') THEN
state := depressionDebouncing;
END IF;
WHEN depressionDebouncing =>
IF (timerEnd='1') THEN
state := waitingPression;
END IF;
END CASE;
END IF;
END PROCESS controller;
END debouncerArch;
NET rst LOC=P37;
NET clk LOC=P13;
NET button LOC=P67;

NET switch LOC=P7;
NET leftDisplay<0> LOC=P3;

NET rightDisplay<0> LOC=P59;

LIBRARY IEEE;
ENTITY ps2KeyboardInterface IS
PORT (
clk: IN std_logic;
rst: IN std_logic;
ps2Clk: IN std_logic;
ps2Data: IN std_logic;
data: OUT std_logic_vector (7 DOWNTO 0);
newData: OUT std_logic;
newDataAck: IN std_logic
);
END ps2KeyboardInterface;
ARCHITECTURE ps2KeyboardInterfaceArch OF ps2KeyboardInterface IS
SIGNAL ldData, validData, lastBitRcv, ps2ClkSync, ps2ClkFallingEdge: std_logic;

SIGNAL ps2DataRegOut: std_logic_vector(10 DOWNTO 0);
SIGNAL goodParity: std_logic;
BEGIN
synchronizer:
PROCESS (rst, clk)
VARIABLE aux1: std_logic;
BEGIN
IF (rst='0') THEN
aux1 := '1';
ps2ClkSync <= '1';
ps2ClkSync <= aux1;
aux1 := ps2Clk;
END IF;
END PROCESS synchronizer;
edgeDetector:
PROCESS (rst, clk)
VARIABLE aux1, aux2: std_logic;
BEGIN
ps2ClkFallingEdge <= (NOT aux1) AND aux2;
IF (rst='0') THEN
aux1 := '1';
aux2 := '1';
aux2 := aux1;
aux1 := ps2ClkSync;
END IF;
END PROCESS edgeDetector;
ps2DataReg:
PROCESS (rst, clk)
BEGIN
IF (rst='0') THEN
ps2DataRegOut <= (OTHERS =>'1');
IF (lastBitRcv='1') THEN
ps2DataRegOut <= (OTHERS=>'1');
ELSIF (ps2ClkFallingEdge='1') THEN
ps2DataRegOut <= ps2Data & ps2DataRegOut(10 downto 1);
END IF;
END IF;
END PROCESS ps2DataReg;
oddParityCheker:
goodParity <=
((ps2DataRegOut(9) XOR ps2DataRegOut(8)) XOR (ps2DataRegOut(7) XOR ps2DataRegOut(6)))
XOR ((ps2DataRegOut(5) XOR ps2DataRegOut(4)) XOR (ps2DataRegOut(3) XOR ps2DataRegOut(2)))
XOR ps2DataRegOut(1);
lastBitRcv <= NOT ps2DataRegOut(0);
validData <= lastBitRcv AND goodParity;
dataReg:
PROCESS (rst, clk)
BEGIN
IF (rst='0') THEN
data <= (OTHERS=>'0');
IF (ldData='1') THEN
data <= ps2DataRegOut(8 downto 1);
END IF;
END IF;
END PROCESS dataReg;
controller:
PROCESS (validData, rst, clk)
TYPE states IS (waitingData, waitingNewDataAck);
VARIABLE state: states;
BEGIN
ldData <= '0';
newData <= '0';
CASE state IS
WHEN waitingData =>
IF (validData='1') THEN
ldData <= '1';
END IF;
WHEN waitingNewDataAck =>
newData <= '1';
WHEN OTHERS => NULL;
END CASE;
IF (rst='0') THEN
state := waitingData;
CASE state IS
WHEN waitingData =>
IF (validData='1') THEN
state := waitingNewDataAck;
END IF;
WHEN waitingNewDataAck =>
IF (newDataAck='1') THEN
state := waitingData;
END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS controller;
END ps2KeyboardInterfaceArch;
NET clk LOC=P13;
NET rst LOC=P37;
NET ps2Clk LOC=P68;

NET ps2Data LOC=P69;


NET clk LOC=P13;
NET rst LOC=P37;
NET switch<1> LOC=P7;

NET led<1> LOC=P41;

NET led<2> LOC=P40;
NET led<3> LOC=P39;
NET led<4> LOC=P38;
NET led<5> LOC=P35;
NET led<6> LOC=P81;
NET led<7> LOC=P80;
NET led<8> LOC=P10;
NET button LOC=P67;

NET leftDisplayPoint LOC=P84;

LIBRARY IEEE;
USE IEEE.std_logic_unsigned.ALL;
ENTITY VGAtiming IS
PORT (
rst: IN std_logic;
clk: IN std_logic;
hSync: OUT std_logic;
vSync: OUT std_logic;
RGB: OUT std_logic_vector(5 DOWNTO 0)
);
END VGAtiming;
ARCHITECTURE VGAtimingArch OF VGAtiming IS
SIGNAL pixelCntOut: std_logic_vector(8 downto 0);

SIGNAL lineCntOut: std_logic_vector(9 downto 0);
SIGNAL blanking, valor: std_logic;
BEGIN
pixelCnt:
PROCESS( rst, clk )
BEGIN
IF (rst='0') THEN
pixelCntOut <= (OTHERS=>'0');
ELSIF(clk'EVENT AND clk='1') THEN
IF (pixelCntOut=396) THEN
pixelCntOut <= (OTHERS=>'0');
ELSE
pixelCntOut <= pixelCntOut+1;
END IF;
END IF;
END PROCESS pixelCnt;
lineCnt:
PROCESS( rst, clk )
begin
IF (rst='0') THEN
lineCntOut <= (OTHERS=>'0');
IF (pixelCntOut=396) THEN
IF (lineCntOut=527) THEN
lineCntOut <= (others=>'0');
ELSE
lineCntOut <= lineCntOut+1;
END IF;
END IF;
END IF;
END PROCESS lineCnt;
hSync <= '0' WHEN (pixelCntOut > 325) AND (pixelCntOut < 373) ELSE '1';
vSync <= '0' WHEN (lineCntOut > 493) AND (lineCntOut < 496) ELSE '1';
blanking <= '1' WHEN (pixelCntOut > 313) OR (lineCntOut > 479) ELSE '0';
valor <= (pixelCntOut(3) XOR lineCntOut(4)) AND NOT blanking;
RGB <= valor & valor & valor & valor & valor & valor;
END VGAtimingArch;
NET rst LOC=P37;
NET clk LOC=P13;
NET vSync LOC=P67;

NET hSync LOC=P19;
NET RGB<5> LOC=P18;

NET RGB<4> LOC=P23;
NET RGB<3> LOC=P20;
NET RGB<2> LOC=P24;
NET RGB<1> LOC=P26;
NET RGB<0> LOC=P25;
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one or more of the following U.S. Patents: 4,642,487; 4,695,740; 4,706,216; 4,713,557; 4,746,822; 4,750,155;
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5,023,606; 5,028,821; 5,047,710; 5,068,603; 5,140,193; 5,148,390; 5,155,432; 5,166,858; 5,224,056; 5,243,238;
5,245,277; 5,267,187; 5,291,079; 5,295,090; 5,302,866; 5,319,252; 5,319,254; 5,321,704; 5,329,174; 5,329,181;
5,331,220; 5,331,226; 5,332,929; 5,337,255; 5,343,406; 5,349,248; 5,349,249; 5,349,250; 5,349,691; 5,357,153;
5,360,747; 5,361,229; 5,362,999; 5,365,125; 5,367,207; 5,386,154; 5,394,104; 5,399,924; 5,399,925; 5,410,189;
5,410,194; 5,414,377; 5,422,833; 5,426,378; 5,426,379; 5,430,687; 5,432,719; 5,448,181; 5,448,493; 5,450,021;
5,450,022; 5,453,706; 5,455,525; 5,466,117; 5,469,003; 5,475,253; 5,477,414; 5,481,206; 5,483,478; 5,486,707;
5,486,776; 5,488,316; 5,489,858; 5,489,866; 5,491,353; 5,495,196; 5,498,979; 5,498,989; 5,499,192; 5,500,608;
5,500,609; 5,502,000; 5,502,440; 5,504,439; 5,506,518; 5,506,523; 5,506,878; 5,513,124; 5,517,135; 5,521,835;
5,521,837; 5,523,963; 5,523,971; 5,524,097; 5,526,322; 5,528,169; 5,528,176; 5,530,378; 5,530,384; 5,546,018;
5,550,839; 5,550,843; 5,552,722; 5,553,001; 5,559,751; 5,561,367; 5,561,629; 5,561,631; 5,563,527; 5,563,528;
5,563,529; 5,563,827; 5,565,792; 5,566,123; 5,570,051; 5,574,634; 5,574,655; 5,578,946; 5,581,198; 5,581,199;
5,581,738; 5,583,450; 5,583,452; 5,592,105; 5,594,367; 5,598,424; 5,600,263; 5,600,264; 5,600,271; 5,600,597;
5,608,342; 5,610,536; 5,610,790; 5,610,829; 5,612,633; 5,617,021; 5,617,041; 5,617,327; 5,617,573; 5,623,387;
5,627,480; 5,629,637; 5,629,886; 5,631,577; 5,631,583; 5,635,851; 5,636,368; 5,640,106; 5,642,058; 5,646,545;
5,646,547; 5,646,564; 5,646,903; 5,648,732; 5,648,913; 5,650,672; 5,650,946; 5,652,904; 5,654,631; 5,656,950;
5,657,290; 5,659,484; 5,661,660; 5,661,685; 5,670,896; 5,670,897; 5,672,966; 5,673,198; 5,675,262; 5,675,270;
5,675,589; 5,677,638; 5,682,107; 5,689,133; 5,689,516; 5,691,907; 5,691,912; 5,694,047; 5,694,056; 5,724,276;
5,694,399; 5,696,454; 5,701,091; 5,701,441; 5,703,759; 5,705,932; 5,705,938; 5,708,597; 5,712,579; 5,715,197;
5,717,340; 5,719,506; 5,719,507; 5,724,276; 5,726,484; 5,726,584; 5,734,866; 5,734,868; 5,737,234; 5,737,235;
5,737,631; 5,742,178; 5,742,531; 5,744,974; 5,744,979; 5,744,995; 5,748,942; 5,748,979; 5,752,006; 5,752,035;
5,754,459; 5,758,192; 5,760,603; 5,760,604; 5,760,607; 5,761,483; 5,764,076; 5,764,534; 5,764,564; 5,768,179;
5,770,951; 5,773,993; 5,778,439; 5,781,756; 5,784,313; 5,784,577; 5,786,240; 5,787,007; 5,789,938; 5,790,479;
Xilinx Development System

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5,838,954; 5,841,296; 5,841,867; 5,844,422; 5,844,424; 5,844,829; 5,844,844; 5,847,577; 5,847,579; 5,847,580;
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Copyright 1991-1999 Xilinx, Inc. All Rights Reserved.

Xilinx Development System

Preface
About the In-Depth Tutorials

These tutorials give a description of the features and additions to
Xilinx’s newest product—Foundation 2.1i. The primary focus of this
guide is to show the relationship between the design entry tools and
the design implementation tools.
This guide should be used as the initial learning tool for designers
who are unfamiliar with the features of the Foundation software.
Additional Resources
For additional information, go to http://support.xilinx.com. The
following table lists some of the resources you can access from this
page. You can also directly access some of these resources using the
provided URLs.
Resource Description/URL
Tutorial Tutorials covering Xilinx design flows, from design entry to verification
and debugging
http://support.xilinx.com/support/techsup/tutorials/index.htm
Answers Current listing of solution records for the Xilinx software tools
Database Search this database using the search function at
http://support.xilinx.com/support/searchtd.htm
Application Descriptions of device-specific design techniques and approaches
Notes http://support.xilinx.com/apps/appsweb.htm
Foundation Series 2.1i In-Depth Tutorials i

Resource Description/URL
Data Book Pages from The Programmable Logic Data Book, which describe device-
specific information on Xilinx device characteristics, including
readback, boundary scan, configuration, length count, and debugging
http://support.xilinx.com/partinfo/databook.htm
Xcell Journals Quarterly journals for Xilinx programmable logic users
http://support.xilinx.com/xcell/xcell.htm
Tech Tips Latest news, design tips, and patch information on the Xilinx design
environment
http://support.xilinx.com/support/techsup/journals/index.htm
Quick Start Guide Contents

This guide covers the following topics.
• Chapter 1, “Schematic-Based Design,” explains many different
facets of a schematic-based Foundation design flow using a
design of a runner’s stopwatch called “Watch”. This chapter also
shows how to use Foundation accessories such as the State
Editor, Project Manager, LogiBLOX, and the HDL Editor.
• Chapter 2, “HDL-Based Design,” guides you through a typical
HDL-based design procedure using a design of a runner’s stop-
watch called “Watch”.
• Chapter 3, “Functional Simulation,” explains how to use the
Logic Simulator to simulate a design before design implementa-
tion to verify that the logic that you have created is correct.
• Chapter 4, “Design Implementation,” describes how to Translate,
Map, Place, Route, (Fit for CPLDs) and generate a Bit file for
designs.
• Chapter 5, “Timing Simulation,” explains how to perform a
timing simulation using the block and routing delay information
from the routed design to give an accurate assessment of the
behavior of the circuit under worst-case conditions.
ii Xilinx Development System

Conventions
This manual uses the following typographical and online document
conventions. An example illustrates each typographical convention.
Typographical
The following conventions are used for all documents.
• Courier font indicates messages, prompts, and program files
that the system displays.
speed grade: -100
• Courier bold indicates literal commands that you enter in a
syntactical statement. However, braces “{ }” in Courier bold are
not literal and square brackets “[ ]” in Courier bold are literal
only in the case of bus specifications, such as bus [7:0].
rpt_del_net=
Courier bold also indicates commands that you select from a
menu.
File → Open
• Italic font denotes the following items.
• Variables in a syntax statement for which you must supply
values
edif2ngd design_name
• References to other manuals
See the Development System Reference Guide for more informa-
tion.
Foundation Series 2.1i In-Depth Tutorials iii

• Emphasis in text
If a wire is drawn so that it overlaps the pin of a symbol, the
two nets are not connected.
• Square brackets “[ ]” indicate an optional entry or parameter.
However, in bus specifications, such as bus [7:0], they are
required.
edif2ngd [option_name] design_name
• Braces “{ }” enclose a list of items from which you must choose
one or more.
lowpwr ={on|off}
• A vertical bar “|” separates items in a list of choices.
lowpwr ={on|off}
• A vertical ellipsis indicates repetitive material that has been
omitted.
IOB #1: Name = QOUT’
IOB #2: Name = CLKIN’
.
.
.
• A horizontal ellipsis “. . .” indicates that an item can be repeated
one or more times.
allow block block_name loc1 loc2 ... locn;
Online Document
The following conventions are used for online documents.
• Red-underlined text indicates an interbook link, which is a cross-
reference to another book. Click the red-underlined text to open
the specified cross-reference.
• Blue-underlined text indicates an intrabook link, which is a cross-
reference within a book. Click the blue-underlined text to open
the specified cross-reference.
iv Xilinx Development System

Contents
Preface
About the In-Depth Tutorials .......................................................... i
Additional Resources ..................................................................... i
Quick Start Guide Contents ........................................................... ii
Conventions
Typographical................................................................................. iii
Online Document ........................................................................... iv
Chapter 1 Schematic-Based Design
Getting Started ............................................................................... 1-2
Nomenclature............................................................................ 1-2
Required Software .................................................................... 1-2
Installing the Tutorial................................................................. 1-2
Tutorial Project Directories and Files ........................................ 1-3
Starting the Project Manager .................................................... 1-3
Copying the Tutorial Files (Optional) ........................................ 1-5
Design Description ......................................................................... 1-5
The Project Manager...................................................................... 1-8
Hierarchy Browser .................................................................... 1-9
Project Manager Functional Tabs ............................................. 1-10
Message Console Window ....................................................... 1-10
Design Entry................................................................................... 1-10
Starting the Schematic Editor ................................................... 1-11
Executing Commands............................................................... 1-12
Hotkeys................................................................................ 1-12
Toolbar Buttons ................................................................... 1-12
Manipulating the Screen ........................................................... 1-13
Creating a Schematic-Based Macro ......................................... 1-14
Foundation Series 2.1i In-Depth Tutorials v

Creating the CNT60 Schematic ................................................ 1-17

Opening the Schematic ....................................................... 1-17
Connectivity—Hierarchy Connectors ................................... 1-17
Project Libraries................................................................... 1-18
Adding Components to CNT60............................................ 1-19
Correcting Mistakes ............................................................. 1-21
Placing the Remaining Components ................................... 1-22
Moving Hierarchy Terminals ................................................ 1-22
Drawing Nets ....................................................................... 1-22
Adding Buses....................................................................... 1-23
Adding Bus Taps ................................................................. 1-25
Saving the Schematic .......................................................... 1-26
Placing the CNT60 Macro.................................................... 1-26
Creating a LogiBLOX Module ................................................... 1-28
Creating a State Machine Module............................................. 1-30
Opening the State Editor ..................................................... 1-31
Adding New States .............................................................. 1-33
Adding a Transition.............................................................. 1-33
Adding a State Action .......................................................... 1-34
Adding a State Machine Reset Condition ............................ 1-35
Adding a Transition Condition.............................................. 1-36
Creating the State Machine Macro ...................................... 1-37
Placing the STMACH symbol .............................................. 1-37
Creating an HDL-Based Module ............................................... 1-38
Using the HDL Design Wizard and HDL Editor ................... 1-39
Using the Language Assistant ............................................. 1-41
Synthesizing the HDL Code and Creating a Macro ............. 1-43
Adding the HEX2LED Component to the Schematic........... 1-43
Specifying Device Inputs/Outputs ............................................. 1-44
Hierarchy Push/Pop............................................................. 1-44
Adding Input Pins................................................................. 1-46
Labeling Nets ............................................................................ 1-47
Assigning Pin Locations............................................................ 1-48
Using Global Buffers ................................................................. 1-50
Completing the Schematic ........................................................ 1-51
Chapter 2 HDL-Based Design
Getting Started ............................................................................... 2-2
Nomenclature............................................................................ 2-2
Required Software .................................................................... 2-2
Installing the Tutorial................................................................. 2-2
Tutorial Project Directories and Files ........................................ 2-3
vi Xilinx Development System

Contents
VHDL or Verilog? ...................................................................... 2-4

Starting the Project Manager .................................................... 2-4
Copying the Tutorial Files (Optional) ........................................ 2-5
Design Description ......................................................................... 2-6
The Project Manager...................................................................... 2-8
Hierarchy Browser .................................................................... 2-9
Project Manager Functional Tabs ............................................. 2-9
Message Console Window ....................................................... 2-10
Design Entry................................................................................... 2-10
Adding Source Files.................................................................. 2-10
Correcting HDL errors............................................................... 2-11
Starting the HDL Editor ............................................................. 2-12
Creating an HDL-Based Module ............................................... 2-12
Using the HDL Design Wizard and HDL Editor ................... 2-12
Using the Language Assistant ............................................. 2-15
Creating a LogiBLOX Module ................................................... 2-17
Running the LogiBLOX Module Selector ............................. 2-17
Instantiating the LogiBLOX Module in the HDL Code.......... 2-21
Synthesizing the Design................................................................. 2-25
The Express Constraints Editor (Foundation Express Only).......... 2-27
Using the Express Constraints Editor (Foundation Express Only). 2-28
Viewing Synthesis Results (Foundation Express Only) ................. 2-32
Chapter 3 Functional Simulation
Starting the Logic Simulator ........................................................... 3-2
Performing Simulation.................................................................... 3-2
Adding Signals ............................................................................... 3-2
Adding Signals Using Probes ................................................... 3-3
Adding Signals Using the Component Selection Window......... 3-5
Deleting a Signal....................................................................... 3-7
Adding Stimulus ............................................................................. 3-8
Stimulating with the Internal Binary Counter............................. 3-9
Stimulating with Keyboard Stimulators ..................................... 3-10
Stimulating with Custom Formulae ........................................... 3-10
Other Sections of the Stimulator Selector................................. 3-12
Running the Simulation .................................................................. 3-12
Saving the Simulation .................................................................... 3-16
Foundation Series 2.1i In-Depth Tutorials vii

Chapter 4 Design Implementation

Project Management ...................................................................... 4-1
Starting Implementation ................................................................. 4-2
Implementing the Schematic Design ........................................ 4-2
Implementing the HDL Design .................................................. 4-3
Implementation Options ................................................................. 4-5
Implementation Template ......................................................... 4-6
Control Files.............................................................................. 4-7
Running Implementation — The Flow Engine................................ 4-8
Viewing Implementation Results .................................................... 4-9
Other Implementation Tools........................................................... 4-11
Chapter 5 Timing Simulation
Invoking Timing Simulation ............................................................ 5-1
Simulating with Script Files ............................................................ 5-2
Creating Script Files — Script Wizard and Script Editor ........... 5-2
Viewing the Script File with the Script Editor ............................ 5-10
Running the Simulation from the Script Editor .......................... 5-11
Viewing the Printed Output File ................................................ 5-13
Closing the Simulator................................................................ 5-13
viii Xilinx Development System

Chapter 1
Schematic-Based Design
This chapter guides you through a typical FPGA schematic-based
design procedure using a design of a runner’s stopwatch called
“Watch”. The design example used in this tutorial demonstrates
many device features, software features, and design flow practices
that you can apply to your own design. The Watch design targets a
SpartanXL device; however, all of the principles and flows taught are
applicable to any Xilinx device family, unless otherwise noted.
For an example of how to design with CPLDs, see the online help by
selecting Help → Foundation Help Contents from the Project
Manager. Under Tutorials, select CPLD Design Flows.
In the first part of the tutorial, you will use the Foundation design
entry tools to complete the design. The design is composed of
schematic elements, a state machine, a LogiBLOX component, and an
HDL macro. After the design is successfully entered in the Schematic
Editor, it is ready for functional simulation with the Foundation
Logic Simulator, implementation with the Xilinx Implementation
Tools, timing simulation.
Note: If you use Verilog or VHDL to create an HDL macro, then you
must have Base Express or Foundation Express and a valid license.
Foundation Series 2.1i In-Depth Tutorials 1-1

This chapter includes the following sections.

• “Getting Started”
• “Design Description”
• “The Project Manager”
• “Design Entry”
Getting Started
The following subsections describe the basic requirements for
running the tutorial.
Nomenclature
In this tutorial, the following terms are used:
• “Spartan family” includes the Spartan and SpartanXL devices.
• “Right-click” means click the right mouse button. Unless
specified, all other mouse operations are performed with the left
mouse button.
Throughout this tutorial, file names, project names, and directory
names (paths) are specified in lower case, and the design is referred
to as “Watch”.
Required Software
The Xilinx Foundation Series package, Version 2.1i, is required to
perform this tutorial. The design requires that you install the
SpartanXL libraries and device files, as well as the XABEL interface.
These options are selected by default in the install program.
Installing the Tutorial

This tutorial assumes that the software is installed in the default
location c:\fndtn\active. If you have installed the software in a
different location, substitute your installation path for
c:\fndtn\active.
1-2 Xilinx Development System

The tutorial projects are optionally installed (as sample projects) in

the c:\fndtn\active\projects directory when you install the Founda-
tion Series software. If you have installed the software, but are not
sure whether the tutorial projects were installed, check for directories
named c:\fndtn\active\projects\wtut*. These directories contain the
various tutorial files.
Note: For detailed instructions, refer to the Foundation Series 2.1i
Installation Guide and Release Notes.
Tutorial Project Directories and Files

During the software installation, the following schematic project
directories are installed.
• c:\fndtn\active\projects\wtut_sc
(incomplete schematic tutorial)
• c:\fndtn\active\projects\watch_sc
(complete schematic tutorial)
The schematic tutorial files are copied into these directories.
The wtut_sc project contains an incomplete copy of the tutorial
design. You will create the remaining files when you perform the
tutorial. As described in a later step, you can copy this project to
another area and perform the tutorial in this new area if desired.
The watch_sc solution project contains the design files for the
completed tutorial, including schematics and the bitstream file.To
conserve disk space, some intermediate files are not provided. Do not
overwrite any files in the solutions directories.
Starting the Project Manager

1. Double click the Foundation Series Project Manager icon on your
desktop or select Start → Programs → Xilinx Foundation
Series 2.1i→ Project Manager from the Start menu.

2. A Getting Started dialog box displays, allowing you to select a

project to open. If you have not opened this tutorial project before
now, click the More Projects... button.
Figure 1-1 Getting Started Dialog Box

3. Browse to the c:\fndtn\active\projects directory in the
Directories list (it should open to this location by default) and
select the wtut_sc project in the Projects list of the Open Project
dialog box. Select Open to open the wtut_sc project.

Copying the Tutorial Files (Optional)

You can either work within the wtut_sc directory as it has originally
been installed, or you can make a copy to work on. Perform the
following steps to make a working copy of the tutorial files.
Whenever copying projects in Foundation, it is important to use the
“Copy Project” feature in the Project Manager to ensure that the
project’s directory structure is kept intact.
1. Select File → Copy Project.
2. Under the Destination section, type Mywatch (or a unique name
of your choice) in the Name field.
3. Click OK.
4. Select File → Open Project.
5. Scroll down in the project list and select Mywatch. Click Open.
6. The Mywatch project may contain two UCF files. If this is the
case, select the wtut_sc.ucf file. Select Document → Remove or
press Del to remove the file from the project. Click Yes to
confirm the removal of the file.
This does not delete the file from disk. It only removes it from the
project so that it is not used during compilation. The file still
exists in the project directory on the disk. If you mistakenly
remove a file from a project, select Document → Add to add it
back.
Design Description
Throughout this tutorial, the design is referred to as Watch.
The design used in this tutorial is a hierarchical, schematic-based
design, meaning that the top-level design file is a schematic sheet
which refers to several other lower-level macros. The lower-level
macros are a variety of different types of modules including
schematic-based modules, LogiBLOX modules, state machine
modules, and HDL modules.
The design begins as an unfinished design. Throughout the tutorial,
you will complete the design by creating some of the modules, and
by completing some others from existing files. After the design is
complete, you will simulate it to verify the functionality.

Watch is a simple runner’s stopwatch. The completed schematic is

shown in the following figure.
Figure 1-2 Completed Watch Schematic

There are three external inputs and three external outputs in the
completed design. The following list summarizes the inputs and
outputs and their functions.

Inputs:
• CLK—System clock for the Watch design.
• STRTSTOP—Starts and stops the stopwatch. This is an active-low
signal which acts like the start/stop button on a runner’s stop-
watch.
• RESET—Resets the stopwatch to 00.0 after it has been stopped.
Outputs:
• TENSOUT[6:0]—7-bit bus which represents the Tens digit of the
stopwatch value. This bus is in 7-segment display format to be
viewable on the 7-segment LED display on the Xilinx
demonstration board.
• ONESOUT[6:0]—similar to TENSOUT bus above, but represents
the Ones digit of the stopwatch value.
• TENTHSOUT[9:0]—10-bit bus which represents the Tenths digit
of the stopwatch value. This bus is one-hot encoded.
The completed design consists of the following functional blocks.
Most of these blocks do not appear yet on the schematic sheet in the
tutorial project since they will be created during this tutorial.
Functional Blocks
• STMACH_A or STMACH_V
State Machine macro. This module uses the Foundation State
Editor to enter and implement the state machine. One is an ABEL
version; the other is a VHDL version.
• CNT60
Schematic-based module which counts from 0 to 59, decimal.
This macro has two 4-bit outputs, which represent the ‘ones’ and
‘tens’ digits of the decimal values, respectively.
• TENTHS
LogiBLOX 10-bit, one-hot encoded counter. This macro outputs
the ‘tenths’ digit of the watch value as a 10-bit one-hot encoded
value.

• HEX2LED
HDL-based macro. This macro decodes the ones and tens digit
values from hexadecimal to 7-segment display format to view on
the FPGA Demonstration Board.
• OUTS1, OUTS2, OUTS3
Schematic-based macros which define the external output pin
assignments for TENSOUT, ONESOUT, and TENTHSOUT
output buses.
The Project Manager

The Project Manager controls all aspects of the design flow.You can
access all of the various design entry and design implementation
tools as well as the files and documents associated with your project.
The Project Manager also maintains revision control over multiple
design iterations.
The Project Manager is divided into three main subwindows. To the
left is the Design Hierarchy Browser which displays the project
elements. To the right is a set of tabs, each one opens a separate
functional window. The third window at the bottom of the Project
Manager is the Message Console and shows status messages, errors,
and warnings, and is updated during all project actions. These
windows are discussed in more detail in the following sections.

Figure 1-3 Project Manager
Hierarchy Browser
The Hierarchy Browser displays the project source files in a
hierarchical tree. Within this display, you can quickly navigate to any
point in your design.
In the Files tab of the Hierarchy Browser, the design source files and
libraries are displayed. Next to each filename, an icon tells you the
file type (schematic, HDL file, state machine, library, text file). If a file
contains lower levels of hierarchy, the icon has a “+” in the lower
right corner. You can expand the tree by clicking this icon. You can
open a file to edit by simply double-clicking the filename in the
browser.

A Versions tab is also available behind the Files tab. This tab displays
a design’s implementation revisions. Because this is a new design
which has not yet been implemented, the Versions tab does not yet
contain any revision information. Versions are discussed in more
detail later in the tutorial during design implementation.
Project Manager Functional Tabs

As mentioned previously, the right-hand side of the Project Manager
contains a series of functional tabs. Briefly, the functions of these tabs
follow.
• Flow—Provides access to tools you use to complete your entire
design, arranged in a flow-chart style to guide you through the
design flow. Status indicators in the lower right corner of each
phase button indicate whether the step has been completed
successfully.
• Contents—Lists contents and date the file selected in the
Hierarchy Browser was last modified.
• Reports—Displays design flow reports.
• Synthesis—Displays all of the HDL macros contained in the
project, and, from this tab, you can update these macros.
You have the option to browse through these tabs to see how the tabs
are updated during the design flow process.
Message Console Window

Errors, warnings, and informational messages are displayed in the
Message Window. Errors are displayed in red, warnings in blue, and
informational messages in black.
Design Entry
In this hierarchical design, you will create various types of macros,
including schematic-based macros, HDL-based macros, state
machine macros, and LogiBLOX macros. You will learn the process
for creating each of these types of macros, and then you will connect
them all together to create the completed Watch design. This tutorial
gives you experience with creating and using each type of design
macro so that you can apply this knowledge to your own design.

Starting the Schematic Editor

There are two different ways to open the Schematic Capture tool.
• From the Flow tab, click the Schematic Capture icon in the
Design Entry phase button. This instructs the Schematic Editor to
open the project’s top level schematic sheet.
• Double click the file name WATCH.SCH in the Files tab.

The Schematic Editor opens with the Watch schematic sheet loaded.
The Watch schematic is incomplete at this point. Throughout the
tutorial, you create the components to complete the design. The
unfinished design is shown in the figure below.

Figure 1-4 Incomplete Watch Schematic

If you need to stop the tutorial at any time, save your work by
selecting File → Save from the pulldown menus.
Executing Commands
There are three ways to execute commands within the Foundation
tools: pulldown menus, hotkeys, and toolbar buttons. In most cases,
this tutorial instructs you to use the pulldown menus.
Hotkeys
You can use the keyboard to execute various commands. These
“hotkeys” are listed next to the commands within the pulldown
menus. Some of the hotkeys are the function keys, some are single
letters, and some require the Ctrl or Alt keys. You cannot customize
them.
Toolbar Buttons
There are also toolbars that are located beneath the pulldown menus
and to the left of the main Schematic Editor window. Hold your
mouse over the buttons to see their function.

Figure 1-5 Schematic Editor
Manipulating the Screen

Under the Display pulldown menu is a series of commands that
modify the viewing area of the Schematic Editor window. Zoom in
the schematic to comfortably view it.

Creating a Schematic-Based Macro

A schematic-based macro consists of a symbol and an underlying
schematic. You can create either the underlying schematic or the
symbol first, and the tools can automatically generate the
corresponding symbol or schematic file, respectively. In the
following steps, you create a schematic-based macro by first creating
the symbol using the Symbol Wizard. A template schematic file is
then created by the tools, and you complete the schematic with the
appropriate logic. The created macro is then automatically added to
the project’s library.
The macro you will create is called CNT60. CNT60 is a binary counter
with two 4-bit outputs, which represent the Ones and Tens values of
the stopwatch. The counter counts from 0 to 59, decimal.
1. Select Tools → Symbol Wizard. The Design Wizard opens.
The Design Wizard guides you through the process of creating a
macro symbol. It also creates a “skeleton” file based on the pins
you define and the type of macro (schematic, ABEL, VHDL, or
state machine). The State Editor and the HDL Editor (described
later in this tutorial) also use the Design Wizard.
2. Click Next.
3. In the Symbol Name field, type CNT60. In the Contents section,
select Schematic. This tells the tool that the underlying file for
the symbol is a schematic.

Figure 1-6 Symbol Wizard - Contents Page

4. Click Next.
5. Click New to create a new pin. In the Name field, type CE. Check
that the direction of the pin is set to Input.
6. Repeat Step 5 for input pins CLK and CLR.
7. Repeat Step 5 for output bus pins LSBSEC[3:0] and MSBSEC[3:0].
To create a bus pin, type the name of the bus in the Name field
(that is, LSBSEC), and then use the up/down arrows in the Bus
field to set the bounds of the bus (that is, 3:0). Check that the
Direction of the pin is set to Output.

Figure 1-7 Symbol Wizard - Ports Page

8. Click Next.
Note: In the Comments section, you can type text that appears on the
symbol when it is placed. You can also define a longer comment that
only appears in the SC Symbols window when you place
components.
9. Click Next and then click Finish.
The symbol is created and placed in the project library and can be
accessed from the SC Symbols toolbox. The Symbol Wizard
automatically creates and opens a schematic sheet with I/O
terminals corresponding to the defined symbol pins.
Note: If the schematic is not automatically created, the most likely
cause is that Empty was selected in step 4. Repeat steps 1-9, and click
Yes or OK when prompted to overwrite the existing symbol.

Creating the CNT60 Schematic

You have now created the symbol for CNT60 with the help of the
Symbol Wizard. The next step is to create the underlying
corresponding schematic for this macro. You can then reference this
macro symbol by placing it on a schematic sheet.
Opening the Schematic

1. If the CNT60 schematic is not open, select File → Open. The
Open Sheet dialog box opens. Click Browse, select cnt60.sch
from the files list, then click OK.
2. Zoom in or out until all of the Hierarchy Connectors are clearly
visible. The hierarchy connectors represent connections between
this schematic sheet and the pins of the corresponding symbol.
Figure 1-8 CNT60 Schematic Hierarchy Connectors
Connectivity—Hierarchy Connectors
Hierarchy Connectors logically connect the CNT60 symbol and its
underlying schematic. The name of each pin on the symbol must
have a corresponding connector in the underlying schematic.

The Symbol Wizard automatically places hierarchy connectors on the

schematic. If you need to add hierarchy connectors manually, you
can use the Hierarchy Connector icon in the vertical toolbar.
When you save a macro, the Schematic Editor checks the hierarchy
connectors against the corresponding symbol. If there is a
discrepancy, you can let the software update the symbol
automatically, or you can modify the symbol manually. Hierarchy
connectors should only be used to connect signals between levels of
hierarchy. Never use hierarchy connectors on top-level schematic
sheets.
Project Libraries
When you create a new project in Foundation, three libraries are
automatically added to the project: the appropriate device family
library based on the target family you have chosen (for example,
SpartanXL), the project library (with the same name as the project),
and the SIMPRIMS library (for simulation). All libraries which are
part of the project are listed in the Files tab of the Project Manager.
You can double click on any of these libraries to see the contents of
the library.
Figure 1-9 Project Libraries

The device family library (SpartanXL for this project) contains all of
the Xilinx Unified Library components for the given family. A
complete description of all of these components can be found in the
Xilinx Libraries Guide.
The project library (WTUT_SC for this project) is a writable library
containing user-created macros. Any macro you create in this project
is automatically placed in this library.

Additionally, you can copy macros from other libraries into this
project library and vice versa using the Schematic Symbols Library
Manager which you can open with the Tools → Utilities menu
in the Project Manager.
To facilitate simulation with the Foundation Logic Simulator, the
SIMPRIMS is added to the project. This library contains the
simulation models for the Xilinx devices.
You can add more libraries to the project by choosing File →
Project Libraries from the Project Manager. After you add a
library to the project, you can use any component from that library in
the current project.
Adding Components to CNT60

Components from all of the libraries (except SIMPRIMS) for the given
project are available from the SC Symbols toolbox to place on the
schematic. The available components listed in this toolbox are
arranged alphabetically within each library.
1. From the menu bar, select Mode → Symbols or click the Symbols
Toolbox button in the vertical toolbar on the left side of the
Schematic Editor.
This opens the SC Symbols window and displays the libraries

and their corresponding components.

Figure 1-10 SC Symbols Toolbox

2. The first component you will place is an AND2, a 2-input AND
gate. You can select this component by either scrolling down the
list and selecting it or by typing AND2 in the bottom of the SC
Symbols Window. Then move the mouse back into the schematic
window.
In the SC Symbols window, when the AND2 component is
selected, a description of the component appears in the bottom of
the window.
3. Move the symbol outline to the location shown in the following
figure and click the left mouse button to place the object.

Figure 1-11 Completed CNT60 Schematic

Note: The preceding schematic illustrates the completed CNT
schematic. Use this figure as a reference for drawing nets and buses
in the following subsections.
Correcting Mistakes
If you make a mistake when placing a component, you can easily
move or delete the component.
1. Press the Esc key on the keyboard to exit the Symbols Mode.
2. Select the component you want to move or delete. Make sure that
no other components are selected (clicking on a blank area of the
schematic deselects everything).
3. Click and drag to correctly place the component, or press the Del
key on the keyboard or the Cut icon in the toolbar to delete the
component.

Placing the Remaining Components

Follow the steps listed previously in the “Adding Components to
CNT60” section to place the CD4CE, OR2, CB4RE, INV, and AND4
components on the schematic sheet as shown in the “Completed
CNT60 Schematic” figure. For a detailed description of the
functionality of each of these components, refer to the Xilinx Libraries
Guide.
Moving Hierarchy Terminals

To make the schematic easier to draw and clearer to read, move some
of the hierarchy connectors which were automatically created by the
Symbol Wizard. Follow these steps to relocate the hierarchy
connectors as shown in the “Completed CNT60 Schematic” figure.
1. With the mouse cursor in point/select mode, select the CLR
hierarchy connector, and drag it to the lower left area of the
schematic sheet. If the mouse cursor is not in point/select mode,
Press the Esc key on the keyboard to get into this mode.
2. To move the bus hierarchy terminal MSBSEC[3:0], select and
drag an area surrounding the entire bus hierarchy terminal and
label it, so that both the bus and the label are highlighted in red.
With the bus and label highlighted, click on the terminal again,
and drag the entire unit down to the lower right area of the sche-
matic sheet. Release the mouse to place the terminal, and then
click anywhere else on the schematic sheet to deselect the bus
and label.
Drawing Nets
You use the Draw Wires icon in the vertical toolbar to draw wires
(also called nets) between the various components on the schematic.
Use Nets to physically connect single bits together.
Signals can also logically be connected by naming multiple segments
identically. In this case, the nets do not need to be physically
connected on the schematic to make the logical connection. In the
CNT60 schematic, you will draw nets to connect the components
together. Do not yet worry about drawing the nets for the LSBSEC
and MSBSEC buses. These nets will be drawn in the next section.
Follow these steps to draw a net between the AND2 and the CB4RE
components on the CNT60 schematic.

1. Click the Draw Wires icon in the vertical toolbar.
2. Click the source symbol pin (output pin of the AND2), then click
on the destination pin (CE pin on the CB4RE). The net will
automatically be drawn between the two pins.
Note: You can specify the shape of the net by moving the mouse in
the direction you want to draw the net and then single-clicking to
create a 90-degree bend in the wire.
Draw the nets to connect the remaining components as shown in the
“Completed CNT60 Schematic” figure. To draw a net between an
already existing net and a pin, click once on the component pin and
once on the existing net. A junction point will be drawn on the
existing net.
You should now have all the nets drawn except those connected to
the LSBSEC and MSBSEC buses. You will draw these in the next
section.
Adding Buses
Sometimes it is convenient to draw a set of signals as a bus rather
than as several separate wires. You have the option to group signals
in the form of a bus and “tap” this bus off to use each signal
individually. In this CNT60 schematic, you will create two buses,
each comprised of the 4 output bits of each counter. These buses will
be named LSBSEC[3:0] and MSBSEC[3:0], and they will also be
connected to hierarchy connectors to connect them to the CNT60
symbol.
Add buses to the schematic as follows.
1. Select Mode → Draw Buses or click the Draw Buses button in the
vertical toolbar to get into the Draw Buses mode.
2. The CNT60 schematic has some bus “stubs” connected to

Hierarchy Connectors which represent the symbol pins on the
CNT60 macro symbol as defined with the Symbol Wizard.

Click the end of the LSBSEC[3:0] stub, then move the mouse to a
new position. Click to make a corner in the bus.
3. Terminate the bus by either double clicking with the left mouse
button, or single-clicking with the right mouse button. This opens
the Add Bus Terminal/Label dialog box where you can define
the bus name, width, and the type of terminal you want to use.
4. In the Add Bus Terminal/Label dialog box, change the Terminal
Marker type to None by choosing this selection from the
pulldown menu. This sets the type of terminal for the point
where you are terminating the bus. Do not change any of the
other settings. Click Bus End (the bus name and width were
defined with the Symbol Wizard, so it is unnecessary to redo this
here).
Figure 1-12 Creating Bus Ends

5. Repeat Steps 2 through 4 for the MSBSEC[3:0] bus.
6. If you make a mistake, press the Esc key on the keyboard to exit
the Draw Buses mode. Then click the bus you want to delete so
that it is highlighted. Press Del to remove the bus.

7. After adding the two buses, press Esc or right-click to exit the
Draw Buses mode.
Adding Bus Taps

Next, you add nets to attach the appropriate pins from the CB4RE
and CD4CE counters to the buses. Use Bus Taps to tap off a single bit
of a bus and connect it to another component. The Schematic Capture
tool can automatically name the bus taps incrementally as they are
drawn.
You have the option to enlarge the view of the schematic to make it
easier to draw the nets.
1. Select Mode → Draw Bus Taps or click the Draw Bus Taps button
in the vertical toolbar. The cursor changes, indicating that you are
now in Draw Bus Taps mode.
2. Click the LSBSEC[3:0] bus label.

The status bar at the bottom of the window displays the message
Expand Bus Tap: LSBSEC3. This tells you that the next bus tap
drawn will be labeled LSBSEC3.
Note: The default is to start at 3 and decrement as bus taps are
drawn. You can use the up and down arrow keys to change which
bus bit will be tapped first.
3. Click the Q3 output pin of the CD4CE component to draw the
bus tap. The net is automatically drawn and labeled. The status
bar now reads Expand Bus Tap: LSBSEC2.
4. Click next on each of the other output pins of the CD4CE
component. The bus taps will be drawn and labeled
incrementally.
Note: If the bits are not automatically being labeled incrementally,
check that you clicked the bus name (label) before clicking the
counter output pins.
Note: If the nets appear disconnected, try selecting Display →
Redraw to refresh the screen.

If there is an error with the labeling of the bus taps, double click
the bus tap net to edit the label.
5. Repeat Steps 1 through 4 for the MSBSEC[3:0] bus.
6. Press Esc twice or right-click to exit the Draw Bus Taps mode.
7. Complete the schematic by drawing the nets to connect the
MSBSEC bus taps to the INV and AND4 components. If
necessary, refer to the “Drawing Nets” section for guidance.
8. Compare your CNT60 schematic again with the “Completed
CNT60 Schematic” figure to ensure that all connections are
properly made.
Saving the Schematic

The CNT60 schematic is now complete.
Save the schematic by selecting File → Save or clicking the Save
icon in the horizontal toolbar.
All errors, warnings, and informational messages are displayed in the

Message Window in the Project Manager. If any errors are issued,
resolve them and save the schematic again.
Placing the CNT60 Macro

So far, you have created the CNT60 macro. The next step is to place
this macro on the top-level Watch schematic sheet, where it may then
be connected to other components in the design.
1. Open the Watch schematic sheet. If the Watch schematic is
already open, you will see a tab at the bottom of the Schematic
Capture tool where you can select that sheet.
2. If the Watch schematic is not open, select File → Open, select
the Watch sheet, and click OK.
3. Open the SC Symbols Toolbox to display a list of all the available
design components. As mentioned before, you can select the
Symbols Toolbox icon to open the SC Symbols Toolbox.

4. Near the bottom of the SC Symbols Toolbox, there is a header

with the name of the project representing the current project
library. Beneath this, find the newly created CNT60 macro in this
list. Select this component.
5. Place the CNT60 macro as shown below.
Figure 1-13 Placing the CNT60 Macro

6. Press Esc to exit the Symbols mode. The cursor now returns to
the standard “point and select” mode.
Notice that the SC Symbols window remains open. With this
window open, you can quickly place additional symbols without
having to click on the Symbols Toolbox icon again. If you want to
close the SC Symbols window, click the ‘-’ button in the upper
left corner of the window.
7. Do not yet worry about connecting nets to the pins of the CNT60
symbol. You will do this later in the tutorial after you add the
other components to the Watch schematic.

Creating a LogiBLOX Module

LogiBLOX is a graphical interactive design tool that you use to create
high-level modules such as counters, shift registers, RAM, and
multiplexers. You can customize and pre-optimize the modules to
take advantage of the inherent architectural features of the Xilinx
FPGA architectures, such as Fast Carry Logic for arithmetic functions
and on-chip RAM for dual-port and synchronous RAM.
In this design, you create a LogiBLOX module called Tenths. Tenths
is a 10-bit one-hot encoded counter. It counts the tenths digit of the
stopwatch’s time value. To better see the digit when it is downloaded
on the FPGA Demonstration Board, the encoding is set to one-hot.
The series of LED lights displays the Tenths digit, where one light is
on for each count of the tenths digit.
You use the LogiBLOX Module Selector GUI to select the type of
module you want to create, as well as the specific features of the
module. You may invoke this GUI from either the Project Manager,
the Schematic Editor, or the HDL Editor. The operation of the tool is
the same regardless of where you invoke it.
1. From within the Schematic Editor, select Tools → LogiBLOX.
2. Fill in the Logiblox Module Selector with the following settings:
• Module Name: Tenths
Defines the name of the module.
• Module Type: Counters
Defines the type of module.
• Bus Width: 10
Defines the width of the data bus. You either choose from the
pulldown menu, or type in a value.
• Operation: Up
Defines how the counter will operate. This field is dependent
on the type of module selected.
• Style: Maximum Speed
Defines the type of optimization strategy for the module.
This dictates how the layout of the module is defined.

• Encoding: One Hot

Defines the register encoding for the module.
• Async Val: 0000000001
Defines the value of the module on power-up and reset.
3. “Check” or “uncheck” the appropriate boxes on the module
diagram so that only the following pins are used.
Q_OUT, Clock Enable, Async Control, Terminal Count
Figure 1-14 LogiBLOX Module Selector

4. Click OK. The module is created and automatically added to the
project library. Additionally, it will be automatically attached to
the cursor to immediately place on the schematic.

Note: If you do not want to place the symbol at this time, you can
press the Esc key on the keyboard to get out of the Place Symbol
mode. You can then select it at any time from the SC Symbols
Toolbox to place on the schematic.
5. Place the newly created Tenths component on the Watch
schematic sheet, as shown below. You will connect this symbol to
the rest of the schematic later in the tutorial. The symbol is
labeled “L1” on the schematic sheet.
Figure 1-15 Placing the Logiblox TENTHS component

6. Save the schematic by selecting File → Save. Close the Sche-
matic Editor.
Creating a State Machine Module

With the Foundation State Editor, you graphically create finite state
machines. You draw states, inputs/outputs, and state transition
conditions on the diagram using a simple windows GUI. Transition
conditions and state actions are typed into the diagram in
appropriate VHDL, Verilog, or ABEL syntax. The State Editor then
synthesizes the diagram into either VHDL, Verilog or ABEL code.
The resulting HDL file is finally synthesized to create a netlist and/or
macro for you to place on a schematic sheet.

For this tutorial, a partially complete state machine diagram is

provided. In the next section, you complete the diagram and
synthesize the module into a macro to place on the Watch schematic.
Both a VHDL and an ABEL version of the State Machine diagram
have been provided for you.
If you have a Foundation Express package, you can use either the VHDL or
ABEL version. If you have a Foundation Standard or a Foundation Base
package, then you must use the ABEL version of the diagram.
Opening the State Editor

To invoke the State Editor, click the State Editor button in the Flow
tab of the Project Manager.
A dialog box prompts you to select a document. Click Existing

Document, click OK, and then select STMACH_V.ASF (VHDL) or
STMACH_A.ASF (ABEL) to open the partially completed stopwatch
state machine.
The unfinished State Machine diagram is shown below.

Figure 1-16 Incomplete State Machine Diagram

• The circles represent the various states.
• The purple underlined expressions are the transition conditions,
defining how you move between states.
• The boxes containing expressions attached to each state are
output actions for each state, defining how the outputs behave in
each state.
In the State Machine diagrams, the transition conditions and the state
actions are written in proper HDL syntax, either VHDL or ABEL.
In the following section, you add the remaining states, transitions,
actions, and also a reset condition to complete the state machine.

Adding New States

Complete the state machine by adding a new state called CLEAR.
1. Click the State icon in the vertical toolbar.
The state bubble is now attached to the cursor.

2. Place the new state on the left-hand side of the diagram as shown
below. Click the mouse to place the state bubble.
3. The state is given a default name, in this case S1. Double click the
S1 in the state bubble, and change the name of the state by typing
CLEAR. The name of the state is for your use only; it does not
affect the synthesis, and so you can name it whatever you want.
Figure 1-17 Adding the CLEAR State

You can change the shape of the state bubble by clicking the bubble
and dragging in the direction to “stretch” the bubble.
Adding a Transition
A transition defines the movement between states of the state
machine. Transitions are represented by arrows in the State Editor.
You will be adding a transition from the CLEAR state to the ZERO
state in the following steps. Because this transition is unconditional,
there is no Transition Condition associated with it.
1. Click the Transition icon in the vertical toolbar.

2. Click first on the CLEAR state, then on the ZERO state to draw
the transition arrow. The arrow’s shape can be manipulated by
clicking it and then dragging the mouse.
Figure 1-18 Adding State Transition
Adding a State Action

A State Action dictates how the outputs should behave in a given
state. There are three types of state actions: Entry Action, State
Action, and Exit Action. These determine if the outputs should act
upon entry to, existence in, or exit from a given state, respectively.
You will add two state actions to the CLEAR state, one to drive the
CLKOUT output to 0, and one to drive the RST output to 1.
1. Click the State Action icon in the vertical toolbar.
2. Move the mouse over the diagram so that the small round ball at
the end of the pointer is over the CLEAR state. After you are in
this position, click the mouse to place the State Action box.
3. When a cursor appears, type the following state action:
• For ABEL:
clkout = 0;
rst = 1;
• For VHDL:
clkout <= ‘0’;
rst <= ‘1’;

4. Click in an empty space in the diagram to exit out of state action

entry mode. The State Action should now appear in a black box
next to the CLEAR state.
You have the option to click and drag the State Action to move it.
Figure 1-19 Adding State Actions
Adding a State Machine Reset Condition

Using the State Machine Reset, you specify a reset condition for the
State Machine. The state machine initializes to this specified state and
enters the specified state whenever the reset condition is met. In this
design, you add a Reset condition which sends the state machine to
the CLEAR state whenever the RESET signal is asserted.
1. Click the Reset icon in the vertical toolbar.
2. Place the Reset triangle onto the diagram near the CLEAR state,
as shown in the diagram below.
3. The cursor is automatically attached to the transition arrow for
this Reset. Move the cursor to the CLEAR state, and click the state
bubble.
Figure 1-20 Adding Reset

Adding a Transition Condition

Add the Transition Condition to the Reset. Transition Conditions are
applied to all transitions, not only Reset transitions, in the same way.
Transition Conditions are attached to the transition arrows, and
describe the required condition for the movement between states.
Add a transition condition which tells the state machine to reset to
the CLEAR state whenever the signal RESET is high.
1. Click the Condition icon in the vertical toolbar.
2. Click the transition arrow which was drawn between the Reset
triangle and the CLEAR state.
3. When the cursor appears, type in the following condition:
• For ABEL:
reset
• For VHDL:
reset = ‘1’
4. Click in an empty space in the diagram to exit the Draw
Condition mode. The condition should now appear underlined
and in purple text.
Figure 1-21 Adding Reset Transition Condition

5. Save your changes by selecting File → Save.

Creating the State Machine Macro

You will now synthesize the state machine and a macro will be
created that you can place on the Watch schematic. The macro
symbol will automatically be added to the project library. The
synthesis process encompasses the creation of the HDL code from the
state machine diagram and the synthesis of the HDL code by either
the Foundation Express (VHDL) or XABEL (ABEL) compiler.
Additionally, you have the option to use the State Editor to create a
symbol for the state machine which you can place on the schematic.
1. Select Project → Create Macro. This synthesizes the design
as well as creates the macro symbol and adds the symbol to the
SC Symbols toolbox.
2. To view the HDL code which the State Editor produced, select
Tools → HDL Editor.
3. Close the State Editor by clicking the X in the upper right corner
of the window.
Placing the STMACH symbol

You can now place the STMACH state machine macro on the Watch
schematic. If it is not already opened, open the Schematic Editor.
Open the SC Symbols Toolbox to view the list of available library
components. You should now be able to locate the STMACH_A or
STMACH_V macro in this list. (If the SC Symbols Toolbox was
already open, and you do not see the STMACH macro, select File
→ Update Libraries.) Select the appropriate symbol, and add it to
the Watch schematic as shown below. Do not worry about drawing
the wires to connect this symbol. You will connect the entire
schematic later in the tutorial.

Figure 1-22 Placing the State Machine Macro

Save the schematic.
Creating an HDL-Based Module

With Foundation you can create modules from HDL code. The HDL
code is synthesized by either the Express compiler (for VHDL or
Verilog), or the XABEL compiler (for ABEL), and a symbol is
generated which you can place on the schematic.
Note: If you use Verilog or VHDL to create an HDL macro, then you
must have Base Express or Foundation Express and a valid license.
You will create an HDL module from scratch. This macro serves to
convert the two 4-bit outputs of the CNT60 module into 7-segment
LED display format.

Using the HDL Design Wizard and HDL Editor

The HDL Wizard is very similar to the Symbol Wizard that you used
to create the CNT60 macro earlier.You enter the name and ports of
the component and the HDL Wizard creates a “skeleton” HDL file
which you can complete with the remainder of your code.
1. From the Flow tab in the Project Manager, click the HDL Editor
button.
2. A dialog box opens, asking if you want to create an empty HDL

file, select an existing HDL file, or use the HDL Wizard to create a
new file. Click the radio button next to Use HDL Design Wizard
and click OK.
3. Follow the instructions from the Wizard. When you are
prompted for a preferred HDL language, choose one.
Note: You must have a Base Express or Foundation Express package
in order to use VHDL or Verilog.
4. When you are prompted for a file name, type HEX2LED and click
Next.
5. The HEX2LED component will have a 4-bit input port named
HEX, and a 7-bit output port named LED. To enter these ports,
click the New button in the Ports dialog box. Select Input as the
direction and type HEX in the Name field. Then, click the arrow
next to the Bus field to select 3:0, which is the width of the bus.
In the Name field, you should now see HEX[3:0], and a
corresponding pin should appear on the symbol diagram on the
left.

Figure 1-23 HDL Wizard

6. Repeat the previous step for the LED[6:0] output bus. Be sure to
set the direction to Output.
If you use ABEL, set the outputs to combinatorial instead of the
default (registered). To set the outputs, make sure the LED[6:0]
pin is highlighted and click the Advanced ... button. In the
Advanced Port Settings dialog box, click the radio button next to
Combinatorial.
7. Click Finish to complete the Wizard session. A “skeleton” HDL
file now appears in the HDL Editor.

Figure 1-24 Skeleton HDL File

In the HDL Editor, the ports are already declared in the HDL file, and
some of the basic file structure is already in place. Keywords are
printed in red, comments in green, and values are gray. This color-
coding enhances readability and recognition of typographical errors.
Using the Language Assistant

Use the templates from the Language Assistant for commonly used
HDL constructs, as well as synthesis templates for commonly used
logic components such as counters, D flip-flops, multiplexers, and
global buffers. You can add your own templates to the Language
Assistant for components or constructs you use often.
1. To invoke the Language Assistant, select Tools → Language
Assistant from the HDL Editor pulldown menu.

2. The Language Assistant is divided into three sections: Language

Templates, Synthesis Templates and User Templates. To expand
the view of any of these sections, click the ‘+’ next to the topic.
Click any of the listed templates to view the template in the right
hand pane.
3. Use the template called HEX2LED Converter located under the
Synthesis Templates heading. Locate this template, preview it in
the right hand pane by clicking the template. This template
provides source code to convert a 4-bit value to 7-segment LED
display format.
Figure 1-25 HDL Language Assistant

4. Before adding this template to your HDL file, be sure that the
cursor in the HDL Editor is positioned below the line with the
comments “<<enter your statements here>>” for VHDL. For
Verilog, enter code after the “// Add your code here” line. For
ABEL, add the template below the line “<<add your equations
here>>”. When you use the template, the code is placed
wherever the cursor is currently positioned in the HDL Editor.
5. To add the HEX2LED Converter template code, click the Use
button in the Language Assistant while the HEX2LED Converter
template is selected. The code is automatically placed in the HDL
file.
6. Close the Language Assistant by clicking the X in the upper right
corner of the window.

7. (Verilog only) After the “//add your declarations here”

statement and before the HEX2LED converter that you just
added, add the following line of code to the HDL file to allow an
assignment.
reg LED;
8. You now have complete and functional HDL code and can check
the syntax using Synthesis → Check Syntax.
9. After you successfully complete the syntax check, save the file by
selecting File → Save from the HDL Editor.
Synthesizing the HDL Code and Creating a Macro

Synthesize the code and create a macro symbol which may be placed
on the schematic.
1. From within the HDL Editor, select Project → Create Macro.
The code is synthesized, and a symbol is created and placed in
the project library.
2. Close the HDL Editor by clicking the X in the upper right corner
of the window.
Adding the HEX2LED Component to the Schematic

You are now ready to place the HEX2LED macro on the Watch
schematic. Open the Schematic Editor if it is not already open. Open
the SC Symbols Toolbox (refer to the “Adding Components to
CNT60” section) to view the list of available library components. You
should now be able to locate the HEX2LED macro in this list. Select it,
and add it to the Watch schematic as shown in the next figure.
This component will be placed on the Watch schematic sheet in two
separate instances. To duplicate the component in the schematic,
click the left mouse button while the pointer is on the placed symbol,
and then click again to place the duplicate symbol.
Note: The Symbols Toolbox icon must still be depressed on the
vertical toolbar to enable this feature to automatically duplicate a
symbol.
Again, do not worry about drawing the wires and buses to connect
this macro. You will connect the entire schematic later in the tutorial.

Figure 1-26 Placing the HEX2LED Component
Specifying Device Inputs/Outputs

When specifying device I/O on a schematic sheet, use components
from the Xilinx Unified Library to represent the input/output pads
and buffers in the device. The SpartanXL library, which is attached to
this Foundation project, contains primitive components for these,
such as IPAD, OPAD, IBUF, OBUF, and IOPAD. You can place I/O
components on any level of hierarchy in a Foundation schematic.
However, it is recommended that the pad and the buffer (that is,
IPAD/IBUF) reside on the same level of hierarchy. In other words, do
not split up the pad and the buffer between levels of hierarchy.
Hierarchy Push/Pop
Descend into a lower-level of hierarchy to view the underlying file.
You will be pushing down into the OUTS1 macro, which is a
schematic-based user-created macro.
1. To push down into OUTS1, click the Hierarchy Push/Pop button.
The mouse cursor changes to the letter “H”. Double click the
OUTS1 symbol.

In the OUTS1 schematic, you see a series of output buffers

(OBUF) and output pads (OPAD). These represent output pins
on the SpartanXL device. Each of these pads has a LOC=P__
attribute attached to them. This attribute assigns each of the pins
to a particular pin on the target device. You will add more pins
with LOC attributes in the next section.
Figure 1-27 OUTS1 Schematic Macro

The OUTS2 and OUTS3 macros are similar to OUTS1, except that
the pins have been locked to different device I/O.
2. “Pop” back out of the OUTS1 component. You can do this in one
of two ways. Either click the Hierarchy Push/Pop icon, then
double click in an empty space in the OUTS1 schematic, or click
the Watch tab at the bottom of the Schematic Capture tool to
return to the top-level Watch schematic sheet.

Adding Input Pins

Add three more input pins to the Watch schematic, called CLK,
RESET and STRTSTOP.
1. Add an IPAD and an IBUF for each of the two input pins, RESET
and STRTSTOP. Add an IPAD and a BUFG for the input clock
signal, CLK. To add these components, click the SC Symbols icon
in the vertical toolbar to open the SC Symbols Toolbox. Browse to
locate the IPAD, IBUF, and BUFG components in the SpartanXL
library. Drop these on the schematic as shown below.
2. Draw a net between each IPAD/IBUF pair and the IPAD/BUFG
input. If necessary, refer to the section on drawing nets (see the
“Drawing Nets” section) for instruction.
Figure 1-28 Placing CLK, RESET and STRTSTOP I/O

Components

Labeling Nets
It is important to label nets and buses for several reasons. It aids in
debugging and simulation, as you will more easily trace nets back to
your original design. Any nets which remain unnamed in the design
will be given machine-generated names which will mean nothing to
you later in the implementation process. Naming nets also enhances
readability and aids in documenting your design.
Label the three input nets you just drew. When naming input and
output pins, it is advisable to label the net between the pad and the
buffer. This name is carried through the entire design flow including
place and route. If you label only the output of the buffer (in the case
of an input pin) or input of the buffer (in the case of an output pin),
you will not be able to easily trace your I/O pins in implementation
tools and reports.
1. Double click the RESET net.
2. In the Net Name field, type RESET as shown below.
Figure 1-29 Labeling Nets

3. Click OK.
4. Repeat Steps 1 through 3 for the STRTSTOP and CLK pins. You
have the option to click and drag the new attributes to better
place them on the schematic.

Figure 1-30 Labeled Nets
Assigning Pin Locations

Xilinx recommends that you let the automatic placement and routing
program, PAR, define the pinout of your design. Pre-assigning
locations to the pins can sometimes degrade the performance of the
place and route tools. However, it is usually necessary, at some point,
to lock the pinout of a design so that it can be integrated into a PCB
(Printed Circuit Board).
Define the initial pinout by running the place-and-route tools
without pin assignments, then locking down the pin placement so
that it reflects the locations chosen by the tools. In this design, you
assign locations to the pins in the Watch design so that the design can
function in a Xilinx demonstration board. Because the design is
simple and timing is not critical, these pin assignments will not
adversely affect the ability of PAR to place and route the design.
Specify pin locations by attaching a LOC parameter to a pad
component. Assign a LOC parameter to the pad associated with the
RESET signal on the Watch schematic as follows.
1. Double click the IPAD connected to the net labeled RESET. The
Symbol Properties dialog box opens.
2. In the Parameters section, add a new parameter with these
values:
Name: LOC
Description: P28
This step assigns the RESET signal to pin P28 of the target device.

Figure 1-31 Assigning Pin Locations

3. Click Add. The parameter appears in the list box.
Notice the two black dots to the left of the parameter. This
indicates that both the Name field and the Description field of the
parameter will be displayed on the schematic. You can double
click on the parameter to change the number of dots shown.
• One dot—only the Description field will show on the
schematic
• Zero dots—neither the Description field nor the Name field
will appear on the schematic.
This function only affects what is displayed on the schematic; in
all cases, the parameter has the same effect on the tools.
4. Click Apply. You see the parameter next to the IPAD.
5. Click OK to close the window.
6. Repeat Steps 1 through 5 to assign the STRTSTOP input pin to
pin P18.

Note: You may click and drag the attributes to position them where
you wish on the schematic.
Figure 1-32 STRTSTP Pin Assignment
Using Global Buffers

All Xilinx devices contain a set of Global Buffers which provide low-
skew distribution of high fanout signals. The number and type of
global buffers differ depending on the Xilinx device family you
target. Consult the Xilinx Libraries Guide for more information
regarding the various types of global buffers available.
In the Watch design, you will use a BUFG component from the
SpartanXL library to drive the clock signal. The signal on the output
of the BUFG is the buffered clock signal which will drive all the
clocks in the system
Draw a net between the output of the IPAD and the input of the
BUFG that you created earlier.
Figure 1-33 BUFG Connection

Completing the Schematic

Complete the schematic by wiring the components you have created
and placed, adding any additional necessary logic, and labeling nets
appropriately. The following steps guide you through the process of
completing the schematic, or you may want to use the completed
schematic shown below for guidance. Each of the actions in this
section has been discussed in detail in earlier sections of the tutorial.
If you need to review these sections, you may return to them. The
finished schematic is shown in the following figure as a guide.
Figure 1-34 Completed Watch Schematic

1. Draw a net (see the “Drawing Nets” section) between the BUFG
and the CLK pin of the STMACH state machine macro. Label this
net CLK_INT.
2. Draw a net (see the “Drawing Nets” section) between the IBUF of
the RESET input and the RESET pin of the STMACH state
machine macro.
3. Place an INV (inverter) component (see the “Adding
Components to CNT60” section) from the SpartanXL library
between the IBUF of the STRTSTOP input and the STRTSTOP pin
of the STMACH state machine macro. Draw nets (see the
“Drawing Nets” section) to connect the INV to the both the IBUF
and the STMACH state machine macro.
4. Place an AND2 component (see the “Adding Components to
CNT60” section) to the left of the CNT60 macro.
5. Draw a net (see the “Drawing Nets” section) to connect the
output of the AND2 with the CE pin of the CNT60 macro.
6. Draw a net (see the “Drawing Nets” section) to connect the
TERM_CNT pin of the TENTHS macro to one of the inputs to the
AND2.
7. Draw a hanging net (see the “Drawing Nets” section) from the
CLKOUT pin of the STMACH macro. To terminate a hanging
wire, double click.
8. Press Esc to get back into point/select mode and then label the
net you drew in Step 7 CLKEN_INT.
9. Draw a hanging net at the CLK_EN input pin of the TENTHS
macro. Label this net CLKEN_INT (see the “Labeling Nets”
section).
10. Draw a hanging net (see the “Drawing Nets” section) at the other
input of the AND2 component. Label this net CLKEN_INT again
(see the “Labeling Nets” section).
11. Draw a hanging net (see the “Drawing Nets” section) from the
RST output pin of the STMACH macro. Label this net RST_INT.
12. Draw two more hanging nets (see the “Drawing Nets” section),
also named RST_INT, from the ASYNC_CTRL pin of the
TENTHS macro and from the CLR pin of the CNT60 macro.

13. Draw two hanging nets (see the “Drawing Nets” section), each
named CLK_INT, from the CLOCK pin of the TENTHS macro
and from the CLK pin of the CNT60 macro.
Note: Remember that nets are logically connected if their names are
the same, even if the net is not physically drawn as a connection in
the schematic. This method is used to make the logical connection of
the RST_INT, CLKEN_INT and CLK_INT signals.
14. Draw buses (see the “Adding Buses” section) to complete the
schematic. Label them as shown on the preceding schematic
diagram.
The schematic is now complete!
15. Save the design by selecting File → Save.


Chapter 2
HDL-Based Design
This chapter guides you through a typical HDL-based design
procedure using a design of a runner’s stopwatch called Watch. The
design example used in this tutorial demonstrates many device
features, software features and design flow practices which you can
apply to your own design. This design targets an SpartanXL device;
however, all of the principles and flows taught are applicable to any
Xilinx device family, unless otherwise noted.
For an example of how to design with CPLDs, see the online help by
selecting Help → Foundation Help Contents from the Project
Manager. Under Tutorials, select CPLD Design Flows.
In the first part of the tutorial, you use the Foundation design entry
tools to complete the design. The design is composed of HDL
elements and a LogiBLOX macro; you will synthesize the design
using the Express tools.
Then, you will functionally simulate the design using the Foundation
Logic Simulator. In the third part, you will implement the design
using the Xilinx Implementation Tools. The simulation,
implementation, and bitstream generation are described in
subsequent chapters.
• “Getting Started”
• “Design Description”
• “The Project Manager”
• “Design Entry”
• “Synthesizing the Design”
• “The Express Constraints Editor (Foundation Express Only)”

• “Using the Express Constraints Editor (Foundation Express

Only)”
• “Viewing Synthesis Results (Foundation Express Only)”
Getting Started
The following subsections describe the basic requirements for
running the tutorial.
Nomenclature
In this tutorial, the following terms are used:
• “Spartan family” includes the Spartan and SpartanXL devices
only.
• “Right-click” means click the right mouse button. Unless
specified, all other mouse operations are performed with the left
mouse button.
Throughout this tutorial, file names, project names, and directory
names (paths) are specified in lower case, and the design is referred
to as Watch.
Required Software
The Xilinx Foundation Series package, Version 2.1i, is required to
perform this tutorial. The design requires that you have installed the
SpartanXL libraries and device files and are licensed for Foundation
Express or Base Express. You must also have the Watch projects
which are installed with the Sample Designs or which may be
downloaded from http://support.xilinx.com.
Note: A Foundation Express license is required to access the Express
Constraints GUI.
Installing the Tutorial

This tutorial assumes that the software is installed in the default
location c:\fndtn. If you have installed the software in a different
location, substitute your installation path for c:\fndtn.
The tutorial projects are optionally installed (as sample projects) in
the c:\fndtn\active\projects directory when you install the

HDL-Based Design
Foundation Series software. If you have installed the software, but

are not sure whether the tutorial projects were installed, check for
directories named c:\fndtn\active\projects\wtut*. These directories
contain the various tutorial files.
Note: For detailed instructions, refer to the Foundation Series 2.1i
Install and Release Document.
Tutorial Project Directories and Files

During the software installation, the WTUT_VHD and WTUT_VER
directories are created within c:\fndtn\active\projects, and the
tutorial files are copied into these directories. These directories
contain complete and incomplete versions of the design, done in
VHDL and Verilog, respectively. You will complete the design in the
tutorial. However, solutions projects with all completed input and
output files are also provided. The following table lists the associated
project.
Table 2-1 Tutorial Project Directories
Directory Description
WTUT_VHD Incomplete Watch Tutorial - VHDL
WTUT_VER Incomplete Watch Tutorial - Verilog
WATCHVHD Solution for Watch - VHDL
WATCHVER Solution for Watch - Verilog
The WATCHVHD and WATCHVER solution projects contain the

design files for the completed tutorials, including HDL files and the
bitstream file.To conserve disk space, some intermediate files are not
provided. Do not overwrite any files in the solutions directories.
The WTUT_VHD and WTUT_VER projects contain incomplete
copies of the tutorial design. You will create the remaining files when
you perform the tutorial. As described in a later step, you have the
option to copy the Watch project to another area and perform the
tutorial in this new area if desired.
VHDL or Verilog?
This tutorial has been prepared for both VHDL and Verilog designs.
This document applies to both designs simultaneously, noting
differences where applicable. You will need to decide which HDL

language you would like to work through the tutorial when you open
the project.
Starting the Project Manager

1. Double click the Foundation Series Project Manager icon on your
desktop or select Programs → Xilinx Foundation Series →
Xilinx Foundation Project Manager from the Start menu.
2. A Getting Started dialog box opens. You can select a recently

opened project from this box. If have not opened this tutorial
project before now, click the More Projects... button.
Figure 2-1 Getting Started Dialog Box

HDL-Based Design
3. In the Directories list, browse to c:\fndtn\active\projects. In the

Projects list, open WTUT_VHD or WTUT_VER by double
clicking.
Copying the Tutorial Files (Optional)

You can either work within the project directory as it has been
installed from the CD, or you can make a copy to work on. To make a
working copy of the tutorial files, begin with an opened project and
perform the following steps.
Note: Whenever copying projects in Foundation, it is important to
use the “Copy Project” feature in the Project Manager to ensure that
the project’s directory structure is kept intact.
1. Select File → Copy Project.
2. Under the Destination section, type “wtch_hdl” in the Name
field.
3. Click OK.
4. Select File → Open Project.
5. Scroll down in the project list and select the wtch_hdl project
name. Click Open.
6. The wtch_hdl project will contain two UCF files. If this is the
case, select wtut_vhd.ucf or wtut_ver.ucf. Select Document →
Remove or press Del to remove the file (wtut_ver.ucf or
wtut_vhd.ucf). Click Yes to confirm the removal of the file.
This does not delete the file from the disk. It merely removes it
from the project so that it is not used during compilation. The file
still exists in the project directory on the disk. If you mistakenly
remove a file from a project, select Document → Add to add it
back.
Design Description
The design used in this tutorial is a hierarchical, HDL-based design,
meaning that the top-level design file is an HDL file that references
several other lower-level macros. The lower-level macros are either
HDL modules or LogiBLOX modules.

The design begins as an unfinished design. Throughout the tutorial,

you complete the design by generating some of the modules from
scratch and by completing some others from existing files. When the
design is complete, you simulate it to verify the design’s
functionality.
Watch is a simple runner’s stopwatch. There are three external
inputs, and three external output buses in the completed design. The
system clock is an externally generated signal. The following list
summarizes the input lines and output buses.
Inputs:
• STRTSTOP —Starts and stops the stopwatch. This is an active
low signal which acts like the start/stop button on a runner’s
stopwatch.
• RESET—Resets the stopwatch to 00.0 after it has been stopped.
• CLK—Externally generated system clock
Outputs:
• TENSOUT[6:0]—7-bit bus which represents the Ten’s digit of the
stopwatch value. This bus is in 7-segment display format
viewable on the 7-segment LED display on the Xilinx
demonstration board.
• ONESOUT[6:0]—Similar to TENSOUT bus above, but represents
the One’s digit of the stopwatch value.
• TENTHSOUT[9:0]—10-bit bus which represents the Tenths’ digit
of the stopwatch value. This bus is one-hot encoded.
The completed design consists of the following functional blocks.
• STATMACH
State Machine module.
• CNT60
HDL-based module which counts from 0 to 59, decimal. This
macro has 2 4-bit outputs, which represent the ones and tens
digits of the decimal values, respectively.
• TENTHS
Logiblox 10-bit, one-hot encoded counter. This macro outputs the
tenths digit of the watch value as a 10-bit one-hot encoded value.

HDL-Based Design
• HEX2LED
HDL-based macro. This macro decodes the ones and tens digit
values from hexadecimal to 7-segment display format for
viewing on the FPGA Demonstration Board.
• SMALLCNTR
A simple Counter.

The Project Manager

The Project Manager controls all aspects of the design flow. Through
the Project Manager, you can access all of the various design entry
and design implementation tools. You can also access the files and
documents associated with your project. The Project Manager
maintains revision control over multiple design iterations.
The Project Manager is divided into three main subwindows. To the
left is the Design Hierarchy Browser which displays the elements
included in the project. To the right is a set of tabs, each one brings up
a separate functional window. The third window at the bottom of the
Project Manager is the Message Console and shows status messages,
errors, and warnings and is updated during all project actions. These
windows are discussed in more detail in the following sections.
Figure 2-2 Project Manager

HDL-Based Design
Hierarchy Browser
In the Files tab of the Hierarchy Browser, design source files and
libraries are displayed. Next to each filename is an icon which tells
you the file type (HDL file, state machine, schematic, library, text file,
for example). If a file contains lower levels of hierarchy, the icon has a
+ to the left of the name. HDL files have this + to show the entities
(VHDL) or modules (Verilog) within the file. You can expand the tree
by clicking this icon. You can open a file to edit by double clicking the
filename in the browser.
A Versions tab is also available behind the Files tab. Since this is a
new design which has not yet been implemented, the Versions tab is
empty. This tab is discussed in more detail later in the tutorial during
design implementation.
Project Manager Functional Tabs

As mentioned previously, the right-hand side of the Project Manager
contains a series of functional tabs. The functions of these tabs
follows:
• Flow—Provides access to tools you use to complete your entire
design, arranged in a flow-chart style to guide you through the
design flow. Status indicators in the upper right corner of each
phase box indicate whether the step has been completed
successfully.
• Contents—Lists the contents and date of the last modification of
the file selected in the Hierarchy Browser.
• Reports—Accesses design flow reports.
You have the option to browse through these tabs at this time, and at
any time during the tutorial to see how the tabs are updated during
the design flow process.

Message Console Window

Errors, warnings, and informational messages are displayed in the
Message Window. Errors are displayed in red, warnings in blue, and
informational messages in black.
Information about synthesis results are displayed under the HDL
Errors, HDL Warnings, and HDL Messages tabs. Because the HDL
messages, errors and warnings are associated with a specific file or
version, you must select a synthesis version (functional structure or
optimized structure) or a specific file in the Files or Version tab to see
messages.
Design Entry
In this hierarchical design, you will examine HDL files, correct syntax
errors, create an HDL macro, and add a LogiBLOX module. This
tutorial gives you experience with creating and using each type of
design macro so that you can apply these procedures to your own
design.
Adding Source Files

You must add HDL files to the project before they can be synthesized.
Four HDL files have already been added to this project, but have not
yet been analyzed. Use Synthesis → Analyze All Source Files
to update these files.
Now add the remaining HDL file to the project. Select Synthesis →
Add Source Files and select SMALLCNTR.VHD or
SMALLCNTR.V from the project directory.
This file will be analyzed when it is added to the project. HDL files
that have been added to the project always have one of four status
indicators associated with the file. These indicators are:
• A red question mark means the file has been modified and needs
to be re-analyzed. Right-click the file and select Analyze.
• A red X means errors have been found. Select this file and
examine the errors under the HDL Errors tab. Errors are also
given in the HDL Editor.

HDL-Based Design
• A red exclamation point means warnings have been issued.

Select the file and examine the warnings under the HDL
Warnings tab. Many warnings can be safely ignored.
• A green check means that the file is up-to-date with no errors or

warnings.
Correcting HDL errors

The SMALLCNTR design contains a syntax error that must be
corrected. The red “x” next to the filename indicates an error was
found during analysis. The Project Manager reports errors in red and
warnings in blue in the console.
Note: To open help on Express errors or warnings, select the error or
message in the HDL Error or Warning tab, then press the F1 key.
1. Open SMALLCNTR.VHD or SMALLCNTR.V in the HDL Editor
by double clicking the file name in the Files tab of the Hierarchy
Browser.
2. Correct any errors in the HDL source file. The comments next to
the error explain this simple fix.
3. Select File → Save to save the file.
4. Re-analyze the file by selecting Synthesis → Check Syntax, in
the HDL Editor or by right-clicking the HDL file in the Project
Manager and selecting Analyze.

Starting the HDL Editor

There are three different ways to open the HDL Editor tool.
• From the Flow tab, click the HDL icon within the Design Entry
phase button.
• Double click an HDL file in the Files tab.

• Right-click an HDL file in the Files tab and select Edit.
If you need to stop the tutorial at any time, save your work by
selecting File → Save from the menus.
Creating an HDL-Based Module

With Foundation, you can easily create modules from HDL code. The
HDL code is connected to your top-level HDL design through
instantiation and compiled with the rest of the design.
You will create a new HDL module. This macro serves to convert the
two 4-bit outputs of the CNT60 module into a 7-segment LED display
format.
Using the HDL Design Wizard and HDL Editor

You enter the name and ports of the component in the HDL Wizard
and the Wizard creates a “skeleton” HDL file which you can
complete with the remainder of your code.

HDL-Based Design
1. From the Flow tab in the Project Manager, click the HDL Editor
button.
2. A dialog box opens, asking if you want to create an empty HDL
file, select an existing HDL file, or use the HDL Wizard to create a
new file. Click the radio button next to Use HDL Design Wizard
and click OK.
3. Follow the instructions from the Wizard. When you are
prompted for a preferred HDL language, choose whichever one
you want, VHDL or Verilog.
4. When you are prompted for a file name, type HEX2LED and click
OK.
5. The HEX2LED component has a 4-bit input port named HEX and
a 7-bit output port named LED. To enter these ports, first click the
New button in the Ports dialog box. Select Input as the direction
and type HEX in the Name field. Then, click the arrow next to the
Bus field to select 3:0, which is the width of the bus. In the Name
field, you should now see HEX[3:0], and a corresponding pin
should appear on the symbol diagram on the left.
Figure 2-3 HDL Wizard

6. Repeat the previous step for the LED[6:0] output bus. Be sure that
the direction is set to Output.

7. Click Finish to complete the Wizard session. A “skeleton” HDL

file now displays in the HDL Editor.
Figure 2-4 Skeleton VHDL File

HDL-Based Design
Figure 2-5 Skeleton Verilog File

In the HDL Editor, the ports are already declared in the HDL file, and
some of the basic file structure is already in place. Keywords are
printed in red, comments in green, and values are gray. This color-
coding enhances readability and recognition of typographical errors.
Using the Language Assistant

You use the templates in the Language Assistant for commonly used
HDL constructs, as well as synthesis templates for commonly used
logic components such as counters, D flip-flops, multiplexers, and
global buffers. You can add your own templates to the Language
Assistant for components or constructs you use often.
1. To invoke the Language Assistant, select Tools → Language
Assistant from the HDL Editor pulldown menu.
2. The Language Assistant is divided into three sections: Language
Templates, Synthesis Templates, and User Templates. To expand
the view of any of these sections, click the + next to the topic.
Click any of the listed templates to view the template in the right
hand pane.

3. Use the template called HEX2LED Converter located under the

Synthesis Templates heading. Locate this template and preview it
in the right hand pane by clicking the template. This template
provides source code to convert a 4-bit value to 7-segment LED
display format.
Figure 2-6 Language Assistant

4. Before adding this template to your HDL file, be sure that the
cursor in the HDL Editor is positioned below the line with the
comments “<<enter your statements here>>” for VHDL. For
Verilog, enter code after the “// Add your code here” line. When
you use the template, the code is placed wherever the cursor
currently is in the HDL Editor.
5. To add the HEX2LED Converter template code, click the Use
button in the Language Assistant while the HEX2LED Converter
template is selected. The code is automatically placed in the HDL
file.
6. Close the Language Assistant by clicking the X in the upper right
7. (Verilog only) After the “//add your declarations here”
statement and before the HEX2LED converter that you just
added, add the following line of code to the HDL file to allow an
assignment.
reg LED;

HDL-Based Design
8. You now have complete and functional HDL code and can check
the syntax using Synthesis → Check Syntax.
9. After you successfully complete the syntax check, save the file by
selecting File → Save from the HDL Editor.
10. Add this HDL file to your current project by selecting Project
→ Add to Project.
11. Exit the HDL Editor.
Creating a LogiBLOX Module

LogiBLOX is a graphical interactive design tool you use to create
high-level modules such as counters, shift registers, RAM and
multiplexers. You can customize and pre-optimize the modules to
take advantage of the inherent architectural features of the Xilinx
FPGA architectures, such as Fast Carry Logic for arithmetic
functions, and on-chip RAM for dual-port and synchronous RAM.
In this section, you create a LogiBLOX module called Tenths. Tenths
is a 10-bit one-hot encoded counter. It counts the tenths digit of the
stopwatch’s time value. The encoding is set to one-hot counter so that
the digit is easily viewed on the FPGA Demo Board when
downloaded. A series of LED lights display the Tenths digit, where
one light will be on for each count of the tenths digit.
Running the LogiBLOX Module Selector

You select the type of module you want in the GUI of the LogiBLOX
Module Selector dialog box as well as the specific features of the
module. You can invoke this GUI from either the Project Manager,
the HDL Editor, or the Schematic Editor. The operation of the tool is
the same regardless of where you invoke it.
1. If you have closed the HDL Editor, open STOPWATCH.VHD or
STOPWATCH.V.
2. From within the HDL Editor, select Tools → LogiBLOX.
3. The Setup window opens if this is your first call to the LogiBLOX
module generator. If the Setup window does not open, click the
Setup button. Enter the following items.
a) Under the Device Family tab, use the pulldown to select
SpartanXL.

b) Under the Options tab, select VHDL Template or Verilog

Template, depending on the language you are using.
c) If you plan to simulate with an HDL simulator, select
Behavioral VHDL Netlist or Structural Verilog netlist,
depending on the HDL simulator you want to use.
4. Click OK when you have defined all of the options.
Figure 2-7 LogiBLOX Setup for VHDL Designs

5. Fill in the LogiBLOX Module Selector with the following settings.
• Module Type: Counters
Defines the type of module.
• Module Name: Tenths
Defines the name of the module.
• Bus Width: 10
Defines the width of the data bus. You either choose from the
pulldown menu, or type in a value.
• Operation: Up
Defines how the counter will operate. This field is dependant
on the type of module you select.

HDL-Based Design
• Style: Maximum Speed

Defines the type of optimization strategy for the module.
This dictates how the layout of the module is defined.
• Encoding: One Hot
Defines the register encoding for the module.
• Async Val: 0000000001
Defines the value of the module on power-up and reset.
6. Check or uncheck the appropriate boxes on the module diagram
so that only the following pins are used.
• Async. Control
• Clock Enable
• Q_OUT
• Terminal Count

Figure 2-8 LogiBLOX Module Selector

7. Click OK. The module is created and automatically added to the
project library.
A number of files are added to the project directory. These files
follow:
• TENTHS.NGC
This file is the netlist that is used during the Translate phase
of implementation.
• TENTHS.VHI or TENTHS.VEI
This is the instantiation template that is used to incorporate
the LogiBLOX module in your source HDL.

HDL-Based Design
• TENTHS.VHD or TENTHS.V
This is the HDL file to be used only for functional simulation.
Do not attempt to synthesize this file. Also do not add this
file to the Foundation project.
• TENTHS.MOD
This file stores the configuration information for the Tenths
module.
• LOGIBLOX.INI
This file stores the LogiBLOX configuration for the project.
Instantiating the LogiBLOX Module in the HDL Code
VHDL Flow
1. Open STOPWATCH.VHD in the HDL Editor.
2. Place your cursor after the line that states:
“-- Place the LogiBLOX Component Declaration for Tenths here”
Select Edit → Insert File and choose Tenths.vhi. The VHDL
template file for the LogiBLOX instantiation is inserted.
The Component Declaration does not need to be modified.
3. Highlight the inserted code from “--Component Instantiation” to
“TERM_CNT=>);”. Select Edit → Cut.

Figure 2-9 VHDL Component Declaration of LogiBLOX Module

4. Place the cursor after the line that states:
“--Place the LogiBLOX Component Instantiation for Tenths
here.”
Select Edit → Paste to place the instantiation here.
Change “instance_name” to “XCOUNTER”.
5. Edit this instantiated code to connect the signals in the Stopwatch
design to the ports of the LogiBLOX module. The completed code
looks like the following.

HDL-Based Design
Figure 2-10 VHDL Component Instantiation of LogiBLOX

Module
6. Save the design and close the HDL Editor.
Verilog Flow
1. Open STOPWATCH.V in the HDL Editor.
2. Place your cursor after the line that states:
“-- Place the LogiBLOX Module Declaration for Tenths here”
This line is at the end of the file.
Select Edit → Insert File and choose Tenths.vei. The Verilog
template file for the LogiBLOX instantiation is inserted.
The Component Declaration does not need to be modified.
Note: Alternatively, the remaining module declaration can be placed
in a new Verilog file (name it TENTHS.V) and added to the project.
Be careful not to overwrite the Verilog simulation model, also named
TENTHS.V, if one has been created. This module declaration is
required to define the port directions of the ports of the LogiBLOX
module.

3. Highlight the inserted code from “Tenths instance_name” to

“.TERM_CNT=());”. Select Edit → Cut.
Figure 2-11 Verilog Module Declaration of LogiBLOX Module

4. Place the cursor after the line that states:
“--Place the LogiBLOX Component Instantiation for Tenths
here.”
Select Edit → Paste to place the instantiation here.
Change “instance_name” to “XCOUNTER”.
5. Edit this code to connect the signals in the Stopwatch design to
the ports of the LogiBLOX module. The completed code is shown
in the following figure.

HDL-Based Design
Figure 2-12 Verilog Component Instantiation of LogiBLOX

Module
6. Save the design and close the HDL Editor.
Synthesizing the Design

Now that the design has been entered and analyzed, the next step is
to synthesize the design. In this step, the HDL files are translated into
gates and optimized to the target architecture.
1. Set the global synthesis options by selecting Synthesis →
Options. Set the Default Frequency to 50MHz, and check the
Export Timing Constraints box. Click OK to accept these values.
2. Click the + next to STOPWATCH.VHD (or STOPWATCH.V).
This shows the entities (or modules) within the HDL file. Some
files may have multiple entities (or modules).
3. Right click the entity named “stopwatch” and select
Synthesize.
This step can also be done by clicking the Synthesis button under
the flow tab. Select the stopwatch entity or module by using the
pulldown in the Top Level field. Be sure that the Version Name
field has an entry.

4. Complete the Target Device fields with this information:

• Family: SpartanXL
• Device: S05XLPC84
• Speed Grade: -5
5. Check the boxes labeled Edit Synthesis/Implementation
Constraints and View Estimated Performance after Optimization.
Selecting the Edit Synthesis/Implementation Constraints box
automatically opens the Express Constraints Editor after
synthesis is complete.
Selecting the View Estimated Performance after Optimization
box automatically opens the Optimized dialog box which
displays the results of the synthesis and optimization.
Figure 2-13 Synthesis/Implementation Window

6. Click Run. Express synthesizes the design and opens the Express
Constraints Editor.

HDL-Based Design
Note: The Express Constraints Editor is not available to non-

registered users or with Base Express licenses. All the functionality
covered by the Express Constraints Editor can be achieved by
component instantiation (Pullups, Pulldowns, Clock Buffers, I/O Flip
Flops), UCF file (timing constraints, pin location constraints), or MAP
options (merging flip flops into IOBs). If you are a Base Express
customer, skip to the “Functional Simulation” chapter.
The Express Constraints Editor (Foundation

Express Only)
You control optimization options and pass timing specifications to
the Place and Route software through a GUI in the Express Synthesis
software. This editor is only available with the Foundation Express
product not Base Express. All timing specifications are passed in the
netlist directly to the place and route engine and are used in the
synthesis process for timing estimation purposes only.
• Clocks
The Default Frequency set in Synthesis → Options is applied
to all clocks in the design. To change the specification of a clock,
click inside the box to the right of the clock and select Define.
Enter the clock period or give the rise and fall times.
• Paths
All types of paths that can be covered by timing specifications are
listed here, with unique specifications given for each clock in the
design. To modify these specifications, enter a new delay in the
Req. Delay column.
To create a subpath within a path, right click the source or
destination and select New Subpath. Give the subpath a new
name and delay value, then select sources and destinations by
double clicking the instances. You can also use wildcards in the
selection filters to choose a group of elements.

• Ports
With the Ports tab, you set input and out delay requirements,
assign clock buffers, insert pullup or pulldown resistors in the I/
O, set delay properties for input registers, set slew rate, disable
the use of I/O registers, and assign pin locations. For all but the
pin locations, click in the box to use the pulldown menu. For pin
locations, type the pin number in the box.
• Modules
With the Modules tab, you to keep or eliminate hierarchy and
disable resource sharing. You can also override the default
settings for effort and area versus speed at the module level.
• Xilinx Options
The Ignore unlinked cells during GSR mapping option directs
Express to infer a global reset signal (and, therefore, insert the
STARTUP module), even if black boxes have been instantiated.
Express cannot know the reset characteristics of any logic in black
boxes, so it will not insert STARTUP unless you check this
option.
Using the Express Constraints Editor (Foundation

Express Only)
Xilinx recommends that you let the automatic placement and routing
program, PAR, define the pinout of your design. Pre-assigning
locations to the pins can sometimes degrade the performance of the
place-and-route tools. However, it is usually necessary, at some
point, to lock the pinout of a design so that it can be integrated into a
PCB (printed circuit board).
Define the initial pinout by running the place-and-route tools
without pin assignments, then locking down the pin placement so
that it reflects the locations chosen by the tools. Assign locations to
the pins in the Watch design so that the design can function in a
Xilinx demonstration board. Because the design is simple and timing
is not critical, these pin assignments do not adversely affect the
ability of PAR to place-and-route the design.
For HDL-based designs, these pin assignments can be done in a User
Constraints File (.UCF) or with the Express Constraints Editor.

HDL-Based Design
Although UCF files are provided for this tutorial, you will assign the
pin location constraints in the Express Constraints Editor.
1. In the Express Constraint Editor, click the Import Constraints
button. Select WATCHVHD.EXC or WATCHVER.EXC,
depending on the language you are using. These files are located
in the project directory.
This file has been created for you. The only difference you should
see between your initial constraints and the ones saved in the
.EXC file is the set of pin locations under the Ports tab.
You can save Constraint Editor settings for a design by selecting
File → Export Constraints. When this .EXC file is read in
for a later synthesis run, all constraints are re-established in the
GUI, as long as they can be matched to instances in the current
version.
2. Under the Paths tab, click in the box in Row 2 below the Req.
Delay header (from All Input Ports to RC-CLK). Change the
delay to 15. Under the Ports tab, the Input Delays for RESET and
STRTSTOP have changed to 15, as these represent all the Pad to
Setup delays.
You can change the values of individual Input or Output Delays
by clicking the value in the Ports tab and either editing the value
there or using the pulldown tab to select a value or define a new
one. Change the values on one of the output signals using one of
these methods.
3. Under the Paths tab, right click either RC-CLK or All Output
Ports in the third row and select New Subpath. The Create/
Edit Timing Subpath window opens.
Give this new subpath a name, Sub_flops_to_out, and a Delay
value, 18. On the left hand side, double click all four flip flops
that contain the name /ver1/sixty/lsbcount/QOUT*, to
determine the sources of this subpath. On the lower right hand
side, use the filter to select the destinations. Type ONE* in the
field and click the Select button. All the ports beginning with
ONESOUT will be highlighted. Click OK to see your new
subpath.

Note: Base Express users cannot access the Express Constraints

Editor. Pin location constraints must therefore be defined in a UCF
file, which Xilinx has provided. Select Implementation →
Implementation Options. Click the Browse button next to User
Constraints and select BASE.UCF.
Figure 2-14 Editing Subpath in the Express Constraints Editor

4. Under the Ports tab, add the three final pin locations in the Pad
Loc column. Scroll to the right to see this column. CLK must be
assigned to P13. RESET must be assigned to P28, and STRTSTOP
must be assigned to P18. To reassign, click the box and enter the
pin number (including the P).
Note: The remaining I/Os have pin assignments. This information is
contained in the .exc file. which you imported in Step 1.

HDL-Based Design
Figure 2-15 Ports Tab Display

5. Click OK to continue synthesis. Express now optimizes the
design.

Viewing Synthesis Results (Foundation Express

Only)
With the View Estimated Performance after Optimization box
checked, the Express Constraints Editor opens after the optimization
phase of synthesis with preliminary performance results. The delay
values are based on wireload models and, therefore, must be
considered preliminary. Consult the post-route timing reports for the
most accurate delay information.
1. Under the Clocks tab, examine the estimated delay value of the
clock. Delays greater than the specification appear in red.
2. Under the Paths tab, examine the estimated delays for the paths
and subpath. Click the source or destination of a path to see the
members of the path, and click a specific path to see the
individual segments of that path.
Figure 2-16 Estimated Timing Data Under Paths Tab

3. Examine the Ports tab to see that all of the settings and delays
have been assigned and met.

HDL-Based Design
4. Under the Modules tab, you can examine the elements used to
synthesize this design. Click the box in the second row under
Area and select Details. This section summarizes all the design
elements used in the Stopwatch design that Express knows
about.
Since the Tenths module is a LogiBLOX component and has not
been synthesized by Express, it is UNLINKED and no summary
information is available.
Note: Black boxes (modules not read into the Express design
environment) are always noted as UNLINKED in the Express
reports. As long as the underlying netlist (.xnf, .ngo, .ngc or EDIF) for
a black box exists in the project directory, the Implementation tools
merge the netlist in during the Translate phase. Since the Tenths
module was built using LogiBLOX called from the project, the tenths
NGC file will be found.
5. Click OK to complete the Synthesis phase.
At this point, an XNF file exists for the Stopwatch design. See the
“Functional Simulation” chapter to perform a post-synthesis
simulation of this design or refer to the “Design Implementation”
chapter to place and route the design.


Chapter 3
Functional Simulation
You can perform functional simulation before design implementation
to verify that the logic that you have created is correct. Foundation
provides a Logic Simulator, which is a gate-level simulator. You can
perform functional simulation on a schematic-based design
immediately after the design is captured in the Schematic Capture
tool. In the case of an HDL-based design, you can perform functional
simulation immediately following synthesis. In a later section, you
can perform timing simulation, which takes place after the design is
implemented (placed and routed) with the Xilinx Implementation
Tools.
This chapter contains the following sections.
• “Starting the Logic Simulator”
• “Performing Simulation”
• “Adding Signals”
• “Adding Stimulus”
• “Running the Simulation”
• “Saving the Simulation”

Starting the Logic Simulator

Click the Functional Simulation phase button in the Project
Flowchart.
You may be prompted to update the schematic netlist if you modified

the schematic but did not write out a netlist. In this case, click Yes to
update the netlist.
The Logic Simulator is invoked, and the project netlist is
automatically loaded into the simulator.
Performing Simulation
There are three basic steps to simulate your design:
1. Adding signals
2. Adding stimulus
3. Running the simulation
There are several different ways to perform each of these steps. These
methods are discussed briefly in the following sections. In this
tutorial, you use the simulator in various ways, and then you can
decide what is best for you with your own designs.
Adding Signals
In order to view signals during the simulation, you must first add
them to the Waveform Viewer in the Simulator. The signals are then
listed in the Waveform Viewer. You can view and monitor the
waveforms next to the corresponding signal names, as well as
monitor the state of these signals in the schematic during the
simulation.

There are two basic methods for adding signals to the Simulator
Waveform Viewer.
• Using Probes from the Schematic Capture tool
• Using the Component Selection window in the Simulator
Adding Signals Using Probes

Note: This section only applies to schematic-based design flows. If
you are using either the all-VHDL or all-Verilog versions of the watch
design, skip to the “Adding Signals Using the Component Selection
Window” section.
In order to add signals for the Watch design simulation, you can use
Probes from the Schematic Capture tool to identify signals that you
want to view in the Simulator.
1. Bring up the Schematic Capture tool from within the Simulator
by clicking the SC icon in the Simulator toolbar.
2. After the schematic has opened, click the Simulation Toolbox

icon in the Schematic Capture toolbar.
This opens the SC Probes toolbox which has several buttons you
can use to control the simulation from within the Schematic
Capture tool.
Note: You can view the results of the simulation either in the
Simulator Waveform Viewer or by looking at the annotated values
that appear directly on the schematic. These methods are examined
more closely later in the tutorial.

When the SC Probes toolbox is open, the cursor is automatically

put into the Add Probes mode. You can see a probes icon
attached to the cursor as shown in the following figure and the
Add Probes button in the SC Probes toolbox is depressed. When
you are adding probes to the schematic, you must remain in this
Add Probes mode.
Figure 3-1 Cursor in Add Probes Mode

3. With the cursor in Add Probes mode, click once on the CLK
signal name on the schematic. A gray box appears to the left of
the CLK label. This gray box indicates that a probe has been
attached to this signal.
4. Repeat Step 3 to add probes to the RESET and STRTSTOP signals
and to the TENTHSOUT[9:0], ONESOUT[6:0] and
TENSOUT[6:0] buses.
5. Return to the Simulator Waveform Viewer by clicking the SIM
button in the SC Probes toolbox.
You should now see all of the signals you just probed listed in the
Simulator Waveform Viewer.

Figure 3-2 Simulator Signals List
Adding Signals Using the Component Selection

Window
Follow these steps to add more signals using the Component
Selection window within the Simulator.
1. Click the Component Selection icon in the toolbar in the
Simulator or select Signal → Add Signals.
The Component Selection Window opens.

This window is divided into three panes. The left-most pane is
the Signals Selection pane. This pane displays a list of all of the
available signals for a given level of hierarchy. The middle pane,
Chip Selection, displays a list of all of the components for a given
level of hierarchy.
You can select a different level of hierarchy in the right-most
pane entitled Scan Hierarchy. For instance, click the OUTS1
macro in the Scan Hierarchy pane. You are now looking at
signals and components from the OUTS1 macro in the Signals
Selection and Chip Selection panes, respectively.

Note: Because Express flattens the design during synthesis, you will
only see this OUTS1 component with the schematic version of the
design.
Figure 3-3 Scan Hierarchy Signals Selector

Return to the Root level of hierarchy by clicking the Hierarchy
button and then selecting Root in the Scan Hierarchy pane to
again view the signals from the top-level of the Watch design.
2. This step is divided into two parts, a) and b), for schematic-based
design and HDL-based design, respectively.
a) Schematic-based design only
In the Signals Selection pane, several signals have red
checkmarks next to their names. These signals have already
been added to the Simulator, in this case by using probes in
the Schematic Capture tool. Now you add more signals to the
Waveform Viewer.
From the Signals Selection pane, you can either double click
signals to add them to the Waveform Viewer, or you can
single click and then press Add. Use whichever method you
prefer to add the following buses.
ONES3, ONES0
TENS3, TENS0

Note: It is possible to add these signals using probes on the schematic

as you did for the other signals, but this process demonstrates the
various methods for adding signals.
b) HDL-based design only
You add signals from the Signals Selection pane to the
Waveform Viewer to view them during the simulation. From
the Signals Selection pane, you can either double click signals
to add them to the Waveform Viewer, or you may single click
and then press Add. Use whichever method you prefer to
add the following signals.
TENTHSOUT9, TENTHSOUT0
ONESOUT6, ONESOUT0
TENSOUT6, TENSOUT0
CLK
STRTSTOP
RESET
If you mistakenly add any signals you do not want to add, you
double click them again in the Signals Selection pane to remove
them from the Waveform Viewer. The red checkmark should
then disappear.
3. Close the Component Selection window by clicking the Close
button.
All of the signals you added are now shown in the Waveform
Viewer.
Deleting a Signal
To delete any of the signals from the Waveform Viewer, first select
the signal in the signal list in the Waveform Viewer, right-click, and
then select Delete Signals → Selected. This operation removes
the highlighted signal from the Waveform Viewer.

Adding Stimulus
To define the function of the input signals, you must add stimulus to
your simulation. There are many ways to define stimulus with the
Foundation Simulator. Some of these methods are listed below and
are discussed in more detail in the sections to follow.
• Keyboard stimulus
• Custom formulae
• Internal binary counter outputs
• Stimulator state selector
• Script file
• Waveform file
In this tutorial, you use the keyboard stimulus, custom formulae,
internal binary counter, and script file. The script file method is used
later in the tutorial when you are performing a timing simulation. All
of these stimulator methods may be used in both functional and
timing simulations.
Open the Stimulator Selection Window by clicking the Stimulator
icon in the toolbar or by selecting Signal → Add Stimulators...
The various components of this window are discussed in the

following sections.
Figure 3-4 Stimulator Selector

Stimulating with the Internal Binary Counter

The Foundation Simulator includes an internal free-running 16-bit
binary counter. You can use each of the 16 output bits of the counter
as stimulators. These signals provide 50% duty cycle signals, each bit
having half the frequency of the next least significant bit. These are
useful when defining clock stimulus. You may define the frequency
of the LSB of the counter (B0) and can therefore derive the frequen-
cies of the other counter outputs.
These counter outputs are represented by the round yellow LEDs in
the Stimulator Selection window. The row of red round LEDs below
it represents the complement of the counter outputs. The B0 output
(LSB) of the counter is the farthest LED to the right, and B15 (MSB) is
all the way to the left.
To simulate the system clock, you assign stimulus to the CLK signal
in the simulator. You use the B0 stimulator signal to stimulate the
CLK signal in the Watch design.
1. In the Waveform Viewer, select the CLK signal by clicking it.
2. In the Stimulator Selection Window, click the B0 stimulator (the
right-most yellow LED). You should now see a B0 next to the
CLK signal in the Waveform Viewer indicating that the B0
stimulator is assigned to CLK.
3. Select Options → Preferences from the Simulator window.
This opens the Preferences window. In the Simulation tab of this
window, you can set the frequency of the B0 counter output.
4. Set the B0 frequency to 10MHz.

Figure 3-5 Simulator Preferences

5. Press OK to close the Preferences window.
Stimulating with Keyboard Stimulators

You assign keyboard keys as stimulus for signals in your design with
the keyboard in the Stimulator Selection window. After you assign
this stimulus, the signal’s value toggles between 1 and 0 whenever
you press the corresponding key on your PC’s keyboard.
Additionally, you can assign a constant 1 or 0 to a signal using the 1
and 0 keys on the Stimulator Selector’s keyboard.
Now assign the R keyboard stimulus to the RESET signal in the
Watch design.
1. Click and drag the R key on the keyboard in the Stimulator
Selector onto the RESET signal name in the Waveform Viewer.
You should now see an R next to the RESET signal in the Wave-
form Viewer, which indicates that this is the assigned stimulus.
2. Press the R key on your PC keyboard a few times to see the state
of the stimulus changing in the Waveform Viewer.
Stimulating with Custom Formulae

The 16 square LEDs in the Stimulator Selector represent Custom
Formulae. You have the option to define each of these 16 formulae to
any custom stimulus pattern you want.

Now create a custom formula and then assign that formula to the
STRTSTOP signal in the Watch design.
1. Click the Formula... button in the Stimulator Selection
Window to bring up the Set Formulas window.
Note: There are two sections of the Set Formulas window: Clocks and
Formulas. Any pattern that you specify for a Clock repeats forever.
Any pattern that you specify for a Formula executes just once, and
then holds the last specified value for the rest of the simulation.
2. Double click on F0 in the Formulas section. The Edit Formula
field at the bottom of the window should now be active.
3. Type the following formula into the Edit Formula field:
H200L100H2000L100H500L200H1000
This formula means “High for 200ns, then Low for 100ns, then
High for 2000ns, then Low for 100ns, etc...”. This defines the
stimulus pattern which you assign to STRTSTOP.
4. Click Accept. This assigns the formula you just entered to the F0
formula. You should now see it displayed next to the F0.
Figure 3-6 Creating Formulas

5. Click Close.

6. Assign this newly created F0 formula to the STRTSTOP signal.

Click the F0 LED in the Stimulator Selection box (the farthest
square LED to the right) and drag it onto the STRTSTOP signal in
the Waveform Viewer. You should now see an F0 next to the
STRTSTOP signal indicating that the F0 formula has been
assigned as stimulus for that signal. The F0 formula may now
also be used for any other signals you want within this same
project.
Other Sections of the Stimulator Selector

There are a few more sections of the Stimulator Selector that are not
used in this tutorial, but are discussed briefly here. For complete
documentation on these topics, refer to the Foundation Logic
Simulator online help.
The Clocks section contains four custom clock signals. These custom
clocks are defined in the Set Formulas window as mentioned above
in the Custom Formula section. These custom clocks are useful for
clocks with duty cycles other than 50%. You could not use the
internal binary counter outputs for those types of clocks or for other
repeating functions.
The EN, DS, CC, OV, and CS buttons pertain to the “mode” of the
signal and stimulus. These modes control options, such as whether
the stimulus is overridden by internally driven signals and whether
the stimulus is enabled or disabled at a given time.
Finally, the Delete button deletes the stimulus from a selected signal.
This function does not delete the signal from the waveform viewer. It
merely deletes the stimulus associated with that signal.
Close the Stimulator Selection window by clicking Close.
Running the Simulation

Now you should see the three inputs of the Watch design, CLK,
RESET, and STRTSTOP listed in the Waveform Viewer, each having
some type of stimulus associated with it. You should also see the
outputs TENTHSOUT, TENSOUT, ONESOUT, ONES, and TENS
listed (ONES and TENS will only be visible for the schematic-based
designs). You are now ready to run the simulation.

Figure 3-7 Signals with Stimulus

Use the Step button in the Simulator toolbar to advance the
simulation for a set amount of time. You can define the size of the
Step using the pulldown menu next to the Step button, shown below.
Figure 3-8 Simulator Step

1. Set the Step size to 100ns.
2. Press the r key on your PC keyboard until the RESET stimulus
state is low.
3. Click the Step button to advance the simulation.
The CLK signal is clocking based on the B0 frequency you set

earlier.

The STRTSTOP signal follows the formula created earlier.

4. Continue to click the Step button to advance the simulation.
Does the circuit appear to be working properly? Is the stopwatch
counting? Remember that the tenths digit is a one-hot encoded
value. To better see the results, you can change the radix of this
bus to binary by first clicking the TENTHSOUT bus, right-
clicking and selecting Bus → Display → Binary. You may also
change the scale of the Waveform Viewer by clicking on the
Scale buttons.
Recall that the ONESOUT and TENSOUT buses are in 7-segment

display format, so the value of the bus may not be readily clear.
Below is a diagram of the layout of the 7-segment display to help
with verification.
5 1
4 2
Decimal point
X8774
Figure 3-9 7-Segment Display

If the design is schematic-based, you can view a model of the 7-
segment display on the schematic, as described below, for easier
debugging. With a schematic-based design, you are also viewing
the ONES and TENS bus in the Waveform viewer. These buses
are the 4-bit binary values of the ones and tens digits. To better
see these values, you can change the radix of the buses. by
clicking the ONES bus, right-clicking and selecting Bus →
Display → Decimal. Repeat this procedure for the TENS bus.

You can view the results of the simulation in the Waveform

Viewer or on the Schematic (for schematic-based design only). To
view the simulation on the Schematic, click the Schematic
Capture icon in the Simulator toolbar. This opens the Schematic
Capture tool. You can see simulation values annotated onto the
schematic. You can continue stepping the simulation from within
the Schematic Capture tool. Click the Simulation Toolbox icon in
the Schematic Capture tool to open the SC Probes window if it is
not already open. Then, click the Step button in the SC Probes
window to advance the simulation.
On the schematic, verify that the value is being displayed
properly on the model of the 7-segment display. Green LEDs
indicate that the LED is active; red LEDs indicate that it is
inactive.
5. Step the simulation until time = 4.6us. At this point in the
simulation, the stopwatch is stopped. Press the r key on the
keyboard to toggle the RESET signal and reset the stopwatch.
Press r once so that it goes high, then step the simulation once,
then press r again to set RESET back to low. Continue stepping
the simulation.
6. As an alternative to manually clicking the Step button, you may
run an extended simulation. Select Options → Start Long
Simulation and set the Simulation Running Time to be 20 sec.
7. Click Start. The simulation runs for 20 seconds of simulation
time.
Figure 3-10 Start Long Simulation

8. Scroll back in the Waveform Viewer using the scroll bar on the
bottom of the window to inspect the results of the simulation.
Does it still appear to be working?

Saving the Simulation

After you run a simulation, you can save it for future use. You can
save the Waveforms you captured as test vectors, and then load them
into the simulator to use again later.
1. Select File → Save Waveform. In the dialog box that opens,
you can enter a name for the waveform file (.TVE). You can
choose any name and save the waveform file.
You can load this waveform file into the simulator using the
File → Load Waveform command.
2. Close the Simulator.

Chapter 4
Design Implementation is the process of translating, mapping,
placing, routing, and generating a BIT file for your design. The
Design Implementation tools are embedded into the Foundation
Project Manager for easy access and project management.
This chapter contains the following sections.
• “Project Management”
• “Starting Implementation”
• “Implementation Options”
• “Running Implementation — The Flow Engine”
• “Viewing Implementation Results”
• “Other Implementation Tools”
Project Management
Project management controls design versions and revisions. A
version represents an input design netlist. Each time a change is
made to the source design, such as logic being added to or removed
from the schematic or the HDL source being modified, a new version
is created. A revision represents an implementation on a given
version, usually with new implementation options, such as different
placement or router effort level.
Foundation maintains revision control, meaning that the resulting
files from each implementation revision are archived in the project
directory.

Note: In 2.1i, you can archive an entire project, design source files,
synthesis files, and implementation files.
Foundation manages and displays your design versions and
revisions graphically in the Versions tab of the Project Manager. Since
you have not yet implemented the design, the Versions tab is
currently empty.
Starting Implementation
This section describes how to begin implementation depending on
which tutorial you performed: HDL or schematic.
• If you performed the schematic tutorial, proceed to the
“Implementing the Schematic Design” section.
• If you performed the HDL tutorial, proceed to the
“Implementing the HDL Design” section.
Implementing the Schematic Design

To begin implementation of your schematic design, click the
Implementation phase button in the Project Flow diagram.
If you are asked if you wish to update the EDIF netlist because the
schematic is newer, say Yes to update the EDIF netlist. This EDIF
netlist is the actual input file to the Design Implementation tools.
Next you will see the Implement Design dialog box.

Figure 4-1 Implement Design Dialog Box

With this dialog box, you can select the target device and various
implementation options. The target device is already set to
XCS05XLPC84-5 because that was the device selected when the
Foundation project was created. The Version and Revision fields have
been filled in automatically. You can also find these version and
revision names in the Project Manager Versions tab after
implementation.
Proceed to the “Implementation Options” section.
Implementing the HDL Design

In the “HDL-Based Design” chapter, you analyzed, synthesized, and
optimized your design. To implement the design, perform the
following steps.
1. Click the Implementation phase button in the Project Flow
diagram.
2. After the Synthesis/Implementation dialog box displays, click

Options to access the Implementation Options dialog box. To
set up your options, refer to the following “Implementation
Options” section.
The Revision Name field is automatically filled in. If you want to
use a new name, enter it in the box.

Figure 4-2 Synthesis/Implementation Dialog Box

Implementation Options
Click the Options button. The Options dialog box opens. A
summary of the options provided in this box follows.
Figure 4-3 Implementation Options Dialog Box

• Place and Route Effort level slider bar. Use this slider bar to select
the amount of time and effort the tools spend implementing the
design.
• Program Option Templates. You can access various
implementation, simulation, and configuration options. For this
design, make sure that “Foundation EDIF” is selected for
Simulation and “Default” for Implementation and Configuration.
Either of these two templates can be set to Off if you do not wish
these output files to be created. See the next section for a
description of the Implementation template.
See the Design Manager/Flow Engine Guide for more details about
these optional target settings.

Implementation Template
You enter and modify implementation options by using the
Implementation template.
1. Click the Edit Options button for the Implementation Program
Options. This opens the Spartan Implementation Options dialog
box.
There are four tabs to control various aspects of the design
implementation.
2. Click the Timing Reports tab.
3. Click the checkbox next to Produce Logic Level Timing
Report.
Figure 4-4 Implementation Options Templates

The Logic Level Timing Report is generated after the design is
mapped, but before it is placed and routed.

It includes logical block delays and optimal routing delays.

Because no actual routing delay information is known at this
time, the routing delays used are the best possible case delays
based on an optimal placement.
The Post Layout Timing Report is generated after the design has
been placed and routed and includes all of the routing delays for
the design.
These reports are examined later.
4. If you want, examine the options available in the other tabs. For
complete documentation on these options, refer to the online
document, Design Manager Flow Engine Guide.
5. Click OK on the Implementation Options dialog box.
Control Files
By default, Foundation creates a blank UCF file in the project
directory. You can edit this UCF file from the Files view in the Project
Manager.
Because the name of this UCF file is the same as the project name, it is
loaded by default. If you have other UCF files that you want to use
instead, browse to find and select them.
You can also designate guide files or Floorplanner files to control the
current implementation. For details, refer to the “Setting Control
Files” section in the “Design Implementation” of Foundation Series 2.1i
User Guide.

Running Implementation — The Flow Engine

After setting the implementation options that you want, you are
ready to implement the design.
1. Click Run in the Schematic Implement Design or click Run in the
Synthesis/Implementation dialog box.
The Flow Engine displays and implementation begins. The Flow
Engine is the tool which performs the design implementation.
The design flow and its status are represented graphically, and a
log of the processes is shown in the console at the bottom of the
Flow Engine.
Figure 4-5 Flow Engine

2. When the implementation is complete, the Flow Engine closes
automatically, and the Foundation Project Manager is fully
visible.

A dialog box opens indicating if the implementation completed

successfully. You can also view the implementation log.
If you encountered any errors in the implementation, refer to the
Implementation Log file for details on the error.
Viewing Implementation Results

As mentioned earlier, the Foundation Project Manager maintains
control over all of your design implementation versions and
revisions. You can directly view and analyze these implementations
from the Project Manager.
1. Click the Versions tab on the left-hand side of the Project
Manager. You should see a hierarchical display of the
implementation you just ran. The revision that is most current is
displayed in bold.
Figure 4-6 Versions Tab (Schematic Design)
Figure 4-7 Versions Tab (HDL Design)

2. With the current revision selected, click the Reports tab in the
right-hand side of the Project Manager. The Reports tab displays
reports and logs for the selected revision of the design.

3. Double click the report entitled Implementation Report Files.

This displays the Xilinx Report Browser, which contains all of the
implementation reports. You have the option to browse through
any of these reports at this time.
4. From within the Xilinx Report Browser, double click the Logic
Level Timing Report. Inspect this report to find the maximum
system frequency specified. Remember this frequency.
5. Again, from within the Xilinx Report Browser, double click the
Post-Layout Timing Report. Inspect this report to find what the
maximum frequency is. Compare this with the delay you found
in the Logic Level Timing Report.
The difference in the two reports’ delays can be accounted for by
the actual routing delays. The routing delays which are assumed
in the Logic Level Timing Report are best-case, which is why they
are generally smaller than the actual delays after placement and
routing. Logic Level timing is useful because it gives you a
preliminary look at how realistic your timing goals are, given the
design’s current mapped state.
A rough guideline (known as the 50/50 rule) is that the logical
block delays in any particular path will make up about 50% of the
total path delay once the design is routed. This is, of course, just a
guideline, and designs vary from case to case. But, this gives you
some estimate to determine whether the design’s timing is even
close to your goals before the design is completely placed and
routed.
6. After you have perused the timing reports, close the reports and
close the Report Browser.
7. Return to the Flow tab on the right-hand side of the Project
Manager by clicking on it.

Other Implementation Tools

The Foundation Project Manager also gives you access to the other
implementation tools, including the Timing Analyzer, FPGA Editor,
Floorplanner, JTAG Programmer, Prom File Formatter and Hardware
Debugger. These tools can be invoked from the Tools →
Implementation and Tools → Device Programming menus.
The Timing Analyzer and Device Programming tools are also
available from the Flow diagram.
These implementation tools are sensitive to the implementation
revision. In other words, depending on which Revision you have
selected in the Versions tab when you invoke the tool, it will load the
tool with data from that implementation revision.
Now you can invoke any of these tools to see what they look like. For
more information on using these tools, refer to the appropriate online
documentation for each tool.


Chapter 5
Timing Simulation
Timing simulation uses the block and routing delay information from
the routed design to give a more accurate assessment of the behavior
of the circuit under worst-case conditions. For this reason, timing
simulation is performed after the design has been placed and routed.
• “Invoking Timing Simulation”
• “Simulating with Script Files”
Invoking Timing Simulation

To invoke the timing simulator, click the Timing Simulation icon in
the Verification phase button in the Project Manager Flow diagram.
The simulator used for timing simulation is the same one used for
functional simulation. The only difference is that the design which is
loaded into the simulator for timing simulation contains worst-case
routing delays based on the actual placed and routed design.
The simulator is now loaded and ready to simulate. For this
simulation, you use script files.

Simulating with Script Files

In the “Functional Simulation” chapter, you simulated by applying
various types of stimulus including keyboard stimulus, formulae,
and by using the internal binary counter. In this chapter, you use a
script file to simulate the design.
Script files contain commands to stimulate inputs, display signals,
and advance the simulation. You enter your commands in the script
file and then press one button to run the entire simulation. Script files
in Foundation support Viewlogic-style commands, as well as other
Foundation-specific commands. The Simulator Online Help provides
a full list and description of all the supported commands.
Creating Script Files — Script Wizard and Script

Editor
The Script Editor is a text editor that you use to enter, edit, and view
script files, as well as actually run the simulation. You may either
create a script file from scratch, use an existing one, or create one with
the help of the Script Wizard, an interactive tool which helps you
create script files for simulation. In this section, you use the Script
Wizard to create a complete script file to simulate the Watch design
and then view the script file and run the simulation from the Script
Editor.
1. To invoke the Script Editor, select Tools → Script Editor
from the pulldown menus within the Simulator. A dialog box
prompts you to select a script file.
2. Choose Use Script Wizard to invoke the Script Wizard.
3. Follow the instructions in the Wizard to advance to the
Initialization page.
4. On the Initialization page, select the following options.

Timing Simulation
• Delete Existing Signals — clears all the waveforms at the

start of each simulation.
• Restart (Power On) — forces the simulator to perform a
global reset at the start of the simulation to initialize all of the
registers.
• Simulation Mode: Timing
• Step Size: 10 ns — determines the size of the simulation step.
• Generate additional comments — inserts comments into the
script file to aid you in further editing of the script file.
• Script File Description — type “Simulation Script File for
Watch Tutorial.” Whatever you type here will be placed as a
comment at the top of the script file.
Figure 5-1 Script Wizard -- Initialization

Note: For more information on any of the options in the Wizard, refer
to the Help topic for the appropriate page, by clicking the Help
button.

5. Click Next to advance to the Vectors page.

Vectors provide a more convenient way to use buses in the script
file. By defining vectors, you can more easily refer to these buses
in the rest of the script file. You can also create vectors out of any
group of signals, regardless of whether they are a bus in the
original design.
In this step, you define vectors for the three output buses,
ONESOUT[6:0], TENSOUT[6:0], and TENTHSOUT[9:0]. For
simplicity, name these vectors ONES, TENS and TENTHS,
respectively.
6. Click the New button. This adds a new vector to the vector list
entitled Vector_Name_1 by default. Type TENS in the place of
Vector_Name_1 to rename it.
7. Click the Browse... button. This displays a Component
Selection window which contains all of the signals in the design.
On the right-hand side, scroll down to find the TENOUTS6..0 7-
bit bus. Select this bus, and then click OK. By doing this, you have
assigned the seven bits of the TENSOUT bus to the newly created
TENS vector.
Figure 5-2 Script Wizard Component Selection

The seven bits of the TENSOUT bus are listed as components in
the newly created TENS vector.

Timing Simulation
8. With the TENS vector selected, click the Radix pulldown menu
to change the radix of the vector to Binary. This determines how
the vector is displayed in the simulator.
9. Repeat Steps 6 through 8 to create vectors called ONES and
TENTHS for both the ONESOUT[6:0] and TENTHSOUT[9:0]
buses, respectively.
Figure 5-3 Script Wizard Vectors

10. Click the Next button to advance to the Stimulators page.
Stimulators define the action of the inputs in the design. There
are several different commands that can be used to define input
stimulus. You will use three different methods in this tutorial.
For a complete description of all available commands, refer to the
online help.
11. To select the first signal to stimulate, click the Browse...
button.

12. In the Component Selection window, scroll down the signal list
on the right-hand side, and locate the CLK signal. Select it and
click OK.
13. See the CLK signal listed in the Simulators and Watched Signals
list. Click the CLK signal and the Stimulator Type field now
becomes active. Use the pulldown menu in the Stimulator Type
field to select Clock.
14. In the Value field, set the pattern of the clock. By typing 0 1
(delimited by a space) in the value field, you define the clock as
having a pattern of low for one simulation step (previously
defined as 10ns), then high for one simulation step. This pattern
repeats indefinitely to produce the clock signal.
Figure 5-4 Clock Stimulus

15. Repeat Steps 11 and 12 to add the STRTSTOP signal to the
Stimulated signals list.
16. With the STRTSTOP signal selected in the Stimulated Signals list,
set the Stimulator Type to Aldec Waveform.

Timing Simulation
17. In the Value field, type the following:

H200L100H2000L100H500L200H1000
Similar to the Custom Formula you created in the Functional
Simulation section, this waveform means high for 200ns, then
low for 100ns, then high for 200ns, and so on. This waveform will
define a stimulus pattern for the STRTSTOP input signal.
18. Repeat Steps 11 through 12 to add the RESET signal to the
Stimulated Signals list.
19. With the RESET signal selected in the Stimulated Signals list, set
the Stimulator Type to be Waveform.
20. In the value field type the following.
@0=0 6500=1 400=0
This means “at 0ns the signal is 0, 650ns later the signal is high,
40ns later the signal is low.” Note that the units of this
measurement are tenths of nanoseconds. This waveform
provides a reset pulse to reset the stopwatch during the
simulation.
21. The Stimulators page also allows you to select signals which you
wish to “watch” in a printed output file. Since you will be setting
a printed output file in the next section of the Wizard, you will
add more signals to this list so that they may be watched.
Repeat Steps 11 and 12 to add the TENS, ONES, and TENTHS
vectors to the Stimulated and Watched Signals list. Be sure that
you add the vectors and not the buses.

Figure 5-5 Selecting Vectors to Watch

22. Because the TENS, ONES, and TENTHS vectors are outputs, they
should not have stimulus assigned to them. Select each of these
vectors individually and set the Stimulator Type to be None.
You should now see six signals listed in the window.

Timing Simulation
Figure 5-6 Signals’ Stimulus

23. Click Next to advance to the Breakpoints and Simulation page.
24. Breakpoints allow you to monitor the simulation for some output
response. You can specify how the simulator will notify you
when the output response is detected.
On the Breakpoints and Simulation page, click the Browse...
button to choose the first signal to set a breakpoint on.
25. In the Component Selection window, choose the ONES vector
from the signal list and click OK.
26. You should now see the ONES vector listed in the Defined
Breakpoints list. Highlight ONES, and then from the Condition
pulldown menu, select Low State. This defines the condition
which must be present on the ONES vector for the breakpoint to
occur.
27. In the Action field, type the following:
print > tim_out.txt

This tells the simulator to write out an output report called

tim_out.txt whenever the breakpoint condition is met.
28. Set the Simulation Command to Cycle, and the Simulation Value
to 400. This tells the simulator to run for 400 clock cycles.
Figure 5-7 Breakpoints and Simulation

29. Click Finish. You can now view your completed script file in
the Script Editor.
Viewing the Script File with the Script Editor

The Script Editor is very similar to the HDL Editor. Commands are
color-coded, with simulation command keywords highlighted in red
and comments in green for easy reading and debugging.
The Script Editor also provides a Macro Assistant that is very similar
to the Language Assistant which you saw earlier in the HDL Editor.
1. From within the Script Editor, select Tools → Macro
Assistant to invoke the Macro Assistant.

Timing Simulation
The Macro Assistant provides templates and help for the various
script file commands. Browse through the various templates to
see what is available.
Figure 5-8 Macro Assistant

2. Close the Macro Assistant by clicking the X in the upper-right
3. Save the script file that was created by the Script Wizard by
selecting File → Save. Be sure that the file is being saved into
the current Foundation project directory (that is,
C:\FNDTN\ACTIVE\PROJECTS\watch_proj_name). Name the
script file watchtim.cmd.
4. Look through the script file to see what the Script Wizard
created.
Running the Simulation from the Script Editor

1. You can execute the simulation directly from the Script Editor. To
do this, select Execute → Go.
A log of the executed commands appears at the bottom of the
Script Editor, including messages indicating when breakpoints
were encountered.

2. To view the simulation results in the Waveform Viewer, move

the Script Editor window and bring the Waveform Viewer
window to the front of your view. Inspect the simulation results
to make sure they are accurate.
You should now see that this is indeed performing a timing
simulation based on actual delays in the placed and routed design. If
you zoom in to get a closer view of the waveforms, you will see that
there is a delay from the rising edge of the clock to the transitions or
the counter outputs.
Figure 5-9 Timing Simulation Waveforms

Note: For the HDL design, the Tenths output bus will be inverted:
1110111111 instead of 0001000000. You are looking at the signals after
the inverters in the HDL design instead of before the inverters as in
the schematic.
For more detailed information related to actual path delays and
system performance requirements, you can use the Xilinx Timing
Analyzer to do Static Timing Analysis. Refer to the Timing Analyzer
Guide for details.

Timing Simulation
Viewing the Printed Output File

As previously mentioned, you set a breakpoint action to write to a
printed output file called tim_out.txt. This file is a text file that is
viewable in any text editor. You can use the Script Editor or any other
text editor to view this file.
To view this file from the Script Editor, select File → Open from the
Script Editor and set the File Type filter to *.*. Locate the file
tim_out.txt, and click Open.
This file is a printed output file in the form of a state table, showing
the states of all the “watched” signals at the times at which
breakpoints were encountered. The times of the five breakpoints
should match the times listed in the log console area of the Script
Editor when the simulation was originally run. You should still be
able to see the console messages to verify this.
Closing the Simulator

When you are satisfied with the results of the simulation, you may
close the Script Editor and the Simulator.


XS40-010XL Prototyping Board
with 3.3V, 20,000-gate FPGA
XS40-010XL The XS40-010XL Board is perfect for experimenting with FPGA designs,
microcontroller programming, or hardware/software codesign. The 20,000-gate
XC4010XL FPGA operates at 3.3V but is 5V-tolerant so you can connect it to
● XC4010XL FPGA
commonly available TTL chips. Digital logic designs can be loaded into the
● 8031 microcontroller
FPGA. The microcontroller can use the FPGA as a coprocessor. The SRAM
● 32 KByte SRAM
can store microcontroller programs/data or serve as general-purpose storage
● 100 MHz programmable
for FPGA-based designs.
oscillator
● Parallel port
● mouse/keyboard PS/2 port The XC4000XL series of FPGAs is supported by Xilinx's Foundation and
● VGA monitor port Alliance Series software. The XC4000XL series has better routing and
● 7-segment LED compilation of designs for these FPGAs is much faster. If you use Win95 or
● 84-pin breadboard interface NT, then you must use the Foundation or Alliance tools.
● Serial EEPROM socket
● 9V DC power jack
● 5V / 3.3V regulators
● Downloading cable
● XSTOOLs utilities diskette
XS40, XSP, and XS95 Board Manual
XESS Corporation
Copyright ©1997, 1998 by X Engineering Software Systems Corporation.
All XS-prefix product designations are trademarks of XESS Corp.
All XC-prefix product designations are trademarks of Xilinx.
ABEL is a trademark of DATA I/O Corporation.
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or
transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise,
without the prior written permission of the publisher. Printed in the United States of America.
Limited Warranty
X Engineering Software Systems Corp. (XESS) warrants that the Product, in the course of its normal use,
will be free from defects in material and workmanship for a period of one (1) year and will conform to
XESS’s specification therefor. This limited warranty shall commence on the date appearing on your
purchase receipt.
XESS shall have no liability for any Product returned if XESS determines that the asserted defect a) is
not present, b) cannot reasonably be rectified because of damage occurring before XESS receives the
Product, or c) is attributable to misuse, improper installation, alteration, accident or mishandling while in
your possession. Subject to the limitations specified above, your sole and exclusive warranty shall be,
during the period of warranty specified above and at XESS’s option, the repair or replacement of the
product. The foregoing warranty of XESS shall extend to repaired or replaced Products for the balance of
the applicable period of the original warranty or thirty (30) days from the date of shipment of a repaired
or replaced Product, whichever is longer.
THE FOREGOING LIMITED WARRANTY IS XESS’S SOLE WARRANTY AND IS APPLICABLE

ONLY TO PRODUCTS SOLD AS NEW. THE REMEDIES PROVIDED HEREIN ARE IN LIEU OF a)
ANY AND ALL OTHER REMEDIES AND WARRANTIES, WHETHER EXPRESSED OR IMPLIED
OR STATUTORY, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTY OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, AND b) ANY AND ALL
OBLIGATIONS AND LIABILITIES OF XESS FOR DAMAGES INCLUDING, BUT NOT LIMITED
TO ACCIDENTAL, CONSEQUENTIAL, OR SPECIAL DAMAGES, OR ANY FINANCIAL LOSS,
LOST PROFITS OR EXPENSES, OR LOST DATA ARISING OUT OF OR IN CONNECTION WITH
THE PURCHASE, USE OR PERFORMANCE OF THE PRODUCT, EVEN IF XESS HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
In the United States, some statutes do not allow exclusion or limitations of incidental or consequential
damages, so the limitations above may not apply to you. This warranty gives you specific legal rights,
and you may also have other rights which vary from state to state.
Getting Help!
If you follow the instructions in this manual and you encounter problems, here are some
places to get help:
• If you can't get the XS Board hardware to work, send an e-mail message describing
your problem to fpga-bugs@xess.com or check our web site at
http://www.xess.com/FPGA. Our web site also has
§ answers to frequently-asked-questions
(http://www.xess.com/FPGA/ho01000.html),
§ example designs for the XS Boards

§ a place to sign-up for our email forum where you can post questions to other XS
Board users (http://www.xess.com/FPGA/list_reg.html).
• If you can't get your XILINX F1 software tools installed properly, send an e-mail
message describing your problem to hotline@xilinx.com or check their web
site at http://www.xilinx.com.
1 Installing the XS40, XSP and XS95 Boards

1.1 WARNING!
The XS40, XSP and XS95 Boards require a power supply to operate! They do not draw
power through the downloading cable from the PC parallel port.
1.2 Packing List

Here is what you should have received in your package:
• an XS40, XS95 or XSP Board (note that your XSP Board will be labeled as an XS40
but the socket will contain a Xilinx Spartan FPGA with an "XCS" prefix);
• a 6' cable with a male DB-25 connector on each end;
• a floppy diskette with software utilities for using the XS40, XSP or XS95 Board and
documentation (you should be OK on this one).
1.3 Installing the XS Board Software Tools

XILINX currently provides the XACTstep F1 tools for programming their FPGAs and
CPLDs. Any recent version of XILINX software should generate bitstream configuration
files that are compatible with the XS40, XSP and XS95 Boards. Follow the directions
XILINX provides for installing their software.
XESS Corp. provides the additional software utilities for interfacing the PC to the XS
Board. Just activate the SETUP.EXE program on the 3.5" diskette to install these tools.
Once the additional software tools are installed, you will see the following subdirectories:
XSTOOLS\BIN contains the executable programs for downloading to the XS Board and
for applying signals to the XS Board through the printer port. An assembler for the
microcontroller is also included.
XSTOOLS\DOCS contains the documentation and schematics for the XS40, XSP and
XS95 Boards.
1.4 Installing the XS40, XSP and XS95 Boards
1.4.1 Free-Standing Operation

You can use the XS Board all by itself to experiment with XC4000/XC9500 + 8031
designs. Just place the XS Board on a non-conducting surface. Then apply power to jack
J9 of the XS Board from a 9V DC wall transformer with a 2.1 mm female, center-positive
plug. The on-board voltage regulation circuitry will create the voltages required by the
rest of the XS Board circuitry.
1.4.2 Protoboard Installation

The two rows of pins from the XS Board can be plugged into a protoboard with holes
spaced at 0.1" intervals. (One of the A.C.E. protoboards from 3M is a good choice.)
Once plugged in, all the pins of the XC4000/XC9500 and the 8031 microcontroller are
accessible to other circuits on the protoboard. (The numbers printed next to the rows of
pins on the XS Board correspond to the pin numbers of the XC4000 or XC9500.) Power
can still be supplied to the XS Board though jack J9, or power can be applied directly
through several pins of the XS Board. Just connect +5V and +3.3V to the following VCC
pins of the XS40, XSP or XS95 Board, and connect ground to the GND pin. (You need
+3.3V if your XS40 Board contains an XC4000XL type of FPGA.)
XS Board Type GND Pin +5V Pin +3.3V Pin

XS95-072 V1.0 49 78 none
XS95-072 V1.1 49 78 none
XS95-072 V1.2 49 78 none
XS95-108 V1.0 49 78 none
XS95-108 V1.1 49 78 none
XS95-108 V1.2 49 78 none
XS40-005E V1.0 52 2 none
XS40-005E V1.1 52 2, 54 none
XS40-005E V1.2 52 2, 54 none
XS40-005XL V1.0 52 none 54
XS40-005XL V1.1 52 2 54
XS40-005XL V1.2 52 2 54
XS40-010E V1.0 52 2 none
XS40-010E V1.1 52 2, 54 none
XS40-010E V1.2 52 2, 54 none
XS40-010XL V1.0 52 none 54
XS40-010XL V1.1 52 2 54
XS40-010XL V1.2 52 2 54
XSP-010 52 2,54 none
Table 1: Power and ground connections for all types and versions of the XS Boards.
1.5 XS Board-PC Connection

The 6' cable included with your XS Board connects it to the parallel port of your PC. One
end of the cable attaches to the printer port and the other connects to the female DB-25
connector (J1) at the top of the XS Board as shown in Figure 1 (the XSP Board is
identical with the XS40 Board V1.2).
Figure 1: XS40/XSP/XS95-PC parallel port connection.
1.6 Configuring the XS40, XSP and XS95 Boards Jumpers
Jumper Setting Purpose

J4 On A shunt should be installed if you are downloading the XS40 or
(default) XSP Board through the parallel port.
Off The shunt should be removed if the XS40 or XSP Board is being
configured from the on-board serial EEPROM (U7).
J5 On The shunt should be installed if you are using a single XS40

(absent (default) Board or if this is the last board in a cascaded chain of XS40
on V1.2 Boards.
of XS40
or XSP) Off The shunt should be removed on all but the last board in a chain
of cascaded XS40 Boards.
J6 On The shunt should be installed when the on-board serial

EEPROM (U7) is being programmed.
Off The shunt should be removed during normal board use.

(default)
J7 1-2 The shunt should be installed on pins 1 and 2 (ext) if the 8031
(ext) microcontroller program is stored in the external 32 KByte RAM
(default) (U8) of the XS40 Board.
2-3 The shunt should be installed on pins 2 and 3 (int) if the

(int) program is stored internally in the 8031 chip.
J8 On The shunt should be installed in XS40 or XSP Boards which use

the 3.3V XC4000XL type of FPGAs.
Off The shunt should be removed on XS40 or XSP Boards which

use the 5V XC4000E type of FPGAs.
J10 On The shunt should be installed if the XS40 or XSP Board is being
configured from the on-board serial EEPROM.
(default) downloaded from the PC parallel port.
J11 On The shunt should be installed if the XS40 or XSP Board is being
(default) downloaded from the PC parallel port.
configured from the on-board serial EEPROM.
Table 2: Jumper settings for the XS40 and XSP Boards.

J5 On The shunt should be installed if you are using a single XS95
(absent (default) Board or if this is the last board in a cascaded chain of XS95
on V1.2 Boards.
of XS95)
Off The shunt should be removed on all but the last board in a chain
of cascaded XS95 Boards.
J7 1-2 The shunt should be installed on pins 1 and 2 (ext) if the 8031
(ext) microcontroller program is stored in the external 32 KByte RAM
(default) (U8) of the XS95 Board.
2-3 The shunt should be installed on pins 2 and 3 (int) if the

(int) program is stored internally in the 8031 chip.
Table 3: Jumper settings for the XS95 Board.
1.7 Testing the XS40, XSP and XS95 Boards

Once your XS Board is installed and the jumpers are in their default configuration, you
can test the board using one of the following commands (you must be in the
XSTOOLS\BIN directory to run the XSTEST command):
XS Board Type Test Command

XS95-072 XSTEST XS95-072
XS40-005E XSTEST XS40-005E
XS40-005XL XSTEST XS40-005XL
XSP-010 XSTEST XSP-010
Table 4: Commands for testing the various types of XS Boards.

The test procedure programs the FPGA or CPLD, loads the RAM with a test program for
the microcontroller, and then the microcontroller executes this program. The total test
period (including programming the board) is about 20 seconds for an XS40 or XSP
Board, and about a minute for an XS95 Board. If the test completes successfully, then
you will see a O displayed on the LED digit.
However, if the test program detects an error, then the LED digit displays an E or
remains blank. In this case, check the following items:
• Make sure the board is receiving power from a 9V DC power supply through jack J9
or through the VCC and GND pins.
• Check that the board is sitting upon a non-conducting surface and that there are no
connections to any of the pins (except for the VCC and GND pins if this is the way
you are powering the board).
• Verify that the jumpers are in their default configuration.
• Make sure the downloading cable is securely attached to the XS Board and the PC
parallel port.
• Verify that the parallel port is in SPP mode. (The mode is usually set in the BIOS as
either SPP, EPP, or ECP. SPP is the safest and least ambitious mode.)
If all these checks are positive, then test the board using another PC. In our experience,
99.9% of all problems are due to the parallel port.
1.8 Programming the XS40, XSP and XS95 Boards

You can download an XC4000-based design into the XS40 or XSP Board as follows:
C:\> XSLOAD CIRCUIT.BIT
where CIRCUIT.BIT is an XC4000 bitstream file that contains the configuration for the
XC4000 or XCS FPGA. Make sure the file contains a bitstream for the type of FPGA
chip installed on your XS40 or XSP Board. This file is created using the XILINX F1
software tools.
You can download an XC9500-based design into the XS95 Board as follows:
C:\> XSLOAD CIRCUIT.SVF
where CIRCUIT.SVF is an XC9500 bitstream file that contains the configuration for the
XC9500 CPLD. Make sure the file contains a bitstream for the type of XC9500 chip
installed on your XS95 Board. This file is created using the XILINX F1 software tools.
Use one of the following commands if you need to configure the FPGA or CPLD and
also download an Intel-formatted HEX file into the RAM of the XS Board:
C:\> XSLOAD FILE.HEX CIRCUIT.BIT
C:\> XSLOAD FILE.HEX CIRCUIT.SVF
XSLOAD assumes the XS Board is connected to parallel port #1 of your PC. You can
use another port number like so:
XSLOAD -P 2 FILE.HEX CIRCUIT.BIT
1.9 Stand-Alone Configuration of the XS40, XSP and XS95 Boards

During the development and testing phases, you will usually connect the XS Board to the
parallel port of a PC and download your circuit each time you make changes to it. But
once your design is finished, you may want to store the design on the XS Board so that it
is configured for operation as soon as power is applied.
This is easy with the XS95 Board. The XC9500 CPLD always stores its current
configuration in an on-chip Flash memory. This configuration is restored whenever
power is applied to the XS95 Board. So your design is always available even when the
board is not connected to a PC.
But the XC4000 or XCS FPGA on the XS40 or XSP Board stores its configuration in an
on-chip RAM which is erased whenever power is interrupted. However, an external
serial EEPROM (such as the Atmel AT17C65/128/256) can be placed in socket U7 to
store the FPGA configuration and reload it on power-up. You will have to perform
several manual steps to 1) load the FPGA configuration into the EEPROM and 2) enable
the configuration of the FPGA from the EEPROM.
Perform the following steps to load your design into the EEPROM:
1. Turn off power to the XS Board.
2. Place a shunt on jumper J6. This enables the programming circuitry in the Atmel
EEPROM chip.
3. Apply power to the XS Board.
4. Use the following command to load the FPGA bitstream file into the EEPROM:
C:\> XSLOAD –SERIAL_EEPROM CIRCUIT.BIT
5. Turn off power to the XS Board.
6. Remove the shunt on jumper J6. This disables the programming circuitry in the Atmel
EEPROM chip so your design cannot be overwritten.
Once your design is loaded into the EEPROM, you must do the following to make the
XS Board configure itself from the EEPROM instead of the PC parallel port interface:
1. Remove the downloading cable from connector J1 of the XS Board.
2. Place a shunt on jumper J10. This sets the FPGA into the active-serial mode so it will
provide a clock signal to the EEPROM which sequences the loading of the
configuration from the EEPROM into the FPGA.
3. Remove the shunt on jumper J4. This prevents the PC interface circuitry from
interfering with the clock signal from the FPGA.
4. Remove the shunt on jumper J11. This prevents the PC interface circuitry from
interfering with the data coming from the EEPROM.
5. Apply power to the XS Board. The FPGA will be configured from the serial
EEPROM. You may reattach the downloading cable if you need to inject test signals
into your design using the XSPORT program.
2 Designing with the XS40, XSP and XS95 Boards

This section introduces the concepts required to create applications that use both the
microcontroller and the FPLD (field programmable logic device). Building FPLD-based
designs is covered in detail in the Practical Xilinx Designer by Prentice-Hall.
2.1 Microcontroller + FPLD Design Flow

The basic design flow for building microcontroller+FPLD applications is shown in Figure
2. Initially you have to get the specifications for the system you are trying to design.
Then you have to determine what inputs are available to your system and what outputs it
will generate.
At this point, you have to partition the functions of your system between the
microcontroller and the FPLD. Some of the input signals will go to the microcontroller,
some will go to the FPLD, and some will go to both. Likewise, some of the outputs will
be computed by the microcontroller and some by the FPLD. There will also be some new
intra-system inputs and outputs created by the need for the microcontroller and the FPLD
to cooperate.
In general, the FPLD will be used mainly for low-level functions where signal transitions
occur more frequently and the control logic is simpler. A specialized serial
transmitter/receiver would be a good example. Conversely, the microcontroller will be
used for higher-level functions where the responses occur less quickly and the control
logic is more complex. Reacting to commands passed in by the receiver is a good
example.
Figure 2: Microcontroller + FPLD design flow.
Once the design has been partitioned and you have assigned the various inputs, outputs,
and functions to the microcontroller and the FPGA, then you can begin doing detailed
design of the software and hardware. For the software, you can use your favorite editor
to create a .ASM assembly-language file and assemble it with ASM51 to create a .HEX
file for the 8031 microcontroller on the XS Board. For the FPLD hardware portion, you
will enter truth-tables and logic equations into a .ABL file and compile it into a .BIT or
.SVF bitstream file using the XILINX F1 programming software.
With the .HEX 8031-program file and the FPLD bitstream file in hand, you can download
them to the XS Board using the XSLOAD program. XSLOAD stores the contents of the
.HEX file into the 32 KByte RAM on the XS Board and then it reconfigures the FPLD
by loading it with the bitstream file.
When the XS Board is loaded with the hardware and software, you need to test it to see if
it really works. The answer usually starts as "No" so you need a method of injecting test
signals and observing the results. XSPORT is a simple program that lets you send test
signals to the XS Board through the PC parallel port. You can trace the reaction of your
system to signals from the parallel port by programming the microcontroller and the
FPLD to output status information on the LED digit (much like placing "printf"
statements in your C language programs). This is admittedly crude but will serve if you
don't have access to programmable stimulus generators and logic analyzers.
2.2 Microcontroller+FPLD Interconnections

The 8031 microcontroller and the FPLD on the XS Board are already connected
together. These existing connections save you the effort of having to wire them yourself,
but they also impose limitations on how your program and the FPLD hardware will
interact. A high-level view of how the microcontroller, RAM, and FPLD are connected is
shown in
Figure 3. More detailed schematics are presented at the end of this addendum.
The 12 MHz oscillator output goes directly to a synchronous clock input of the FPLD.
The FPLD can control the clock it sends to the XTAL1 input of the microcontroller.
The 8031 multiplexes the lower eight bits of a memory address with eight bits of data and
outputs this on its P0 port. Both the RAM data lines and the FPLD are connected to P0.
The RAM uses this connection to send and receive data to and from the 8031. The
FPLD is programmed to latch the address from P0 under control of the ALE signal and
send the latched address bits to the lower eight address lines of the RAM.
Figure 3: Connections between the 8031 microcontroller, RAM, and FPLD of the XS
Board.
Meanwhile, the upper eight bits of the address are output on port P2 of the 8031. The
RAM uses the lower seven of these address bits. The FPLD also receives the upper eight
address bits and decodes these along with the PSEN and read/write control line (from pin
P3.6 of port P3 ) from the 8031 to generate the CS and OE signals that enable the RAM
and its output drivers, respectively. Either of the CS or OE signals can be pulled high to
disable the RAM and prevent it from having any effect on the rest of the XS Board
circuitry.
One of the outputs of the CPLD controls the reset line of the microcontroller. The 8031
can be prevented from having any effect on the rest of the circuitry by forcing the RST
pin high through the FPLD. (When RST is active, most of the 8031 pins are weakly
pulled high.)
Many of the I/O pins of ports P1 and P3 of the 8031 connect to the FPLD and can be
used for general-purpose I/O between the microcontroller and the FPLD. In addition to
being general-purpose I/O, the P3 pins also have special functions such as serial
transmitters, receivers, interrupt inputs, timer inputs, and external RAM read/write
control signals. If you aren't using a particular special function, then you can use the
associated pin for general-purpose I/O between the microcontroller and the FPLD. In
many cases, however, you will program the FPLD to make use of the special-purpose
8031 pins. (For example, the FPLD could generate 8031 interrupts.) If you want to use
the special-purpose pin with an external circuit, then the FPLD I/O pin connected to it
must be tristated.
An LED digit connects directly to the FPLD. (These same FPLD pins also drive the VGA
monitor connector on versions 1.2 and higher of the XS Board.) The FPLD can be
programmed so the microcontroller can control the LEDs either through P1 or P3 or by
memory-mapping a latch for the LED into the memory space of the 8031.
The PC can transmit signals to the XS Board through the eight data output bits of the
printer port. The FPLD has direct access to these signals. The microcontroller can also
access them by programming the FPLD to pass the data output bits onto the FPLD I/O
pins connected to the 8031. The printer port data bits are also passed through the
cascade header to the next XS Board in the chain (if there is one).
Communication from the XS Board back to the PC also occurs through the parallel port.
Four of the parallel port status pins are connected to three pins of P1 and one pin of P3 .
Either the microcontroller or the FPLD can drive the status pins. The PC can read the
status pins to fetch data from the XS Board.
2608 Sweetgum Drive
Apex NC 27502
Toll-free: 800-549-9377
International: 919-387-0076
FAX: 919-387-1302
XS40, XSP, XS95 Board

User Manual
How to install, test, and use

your new XS Board
Copyright ©1997-1999 by X Engineering Software Systems Corporation.
All rights reserved. No part of this publication may be reproduced, stored in a retrieval
system, or transmitted, in any form or by any means, electronic, mechanical,
photocopying, recording, or otherwise, without the prior written permission of the publisher.
Printed in the United States of America.
Limited Warranty
X Engineering Software Systems Corp. (XESS) warrants that the Product, in the course of
its normal use, will be free from defects in material and workmanship for a period of one
(1) year and will conform to XESS’s specification therefor. This limited warranty shall
commence on the date appearing on your purchase receipt.
XESS shall have no liability for any Product returned if XESS determines that the asserted
defect a) is not present, b) cannot reasonably be rectified because of damage occurring
before XESS receives the Product, or c) is attributable to misuse, improper installation,
alteration, accident or mishandling while in your possession. Subject to the limitations
specified above, your sole and exclusive warranty shall be, during the period of warranty
specified above and at XESS’s option, the repair or replacement of the product. The
foregoing warranty of XESS shall extend to repaired or replaced Products for the balance
of the applicable period of the original warranty or thirty (30) days from the date of
shipment of a repaired or replaced Product, whichever is longer.
THE FOREGOING LIMITED WARRANTY IS XESS’S SOLE WARRANTY AND IS

APPLICABLE ONLY TO PRODUCTS SOLD AS NEW. THE REMEDIES PROVIDED
HEREIN ARE IN LIEU OF a) ANY AND ALL OTHER REMEDIES AND WARRANTIES,
WHETHER EXPRESSED OR IMPLIED OR STATUTORY, INCLUDING BUT NOT
LIMITED TO, ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A
PARTICULAR PURPOSE, AND b) ANY AND ALL OBLIGATIONS AND LIABILITIES OF
XESS FOR DAMAGES INCLUDING, BUT NOT LIMITED TO ACCIDENTAL,
CONSEQUENTIAL, OR SPECIAL DAMAGES, OR ANY FINANCIAL LOSS, LOST
PROFITS OR EXPENSES, OR LOST DATA ARISING OUT OF OR IN CONNECTION
WITH THE PURCHASE, USE OR PERFORMANCE OF THE PRODUCT, EVEN IF
XESS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
In the United States, some statutes do not allow exclusion or limitations of incidental or
consequential damages, so the limitations above may not apply to you. This warranty
gives you specific legal rights, and you may also have other rights which vary from state to
state.
Chapter
1
Preliminaries
Getting Help!
Here are some places to get help if you encounter problems:
n If you can't get the XS Board hardware to work, send an e-mail message describing
your problem to fpga-bugs@xess.com or check our web site at
http://www.xess.com/FPGA. Our web site also has
n answers to frequently-asked-questions
n example designs for the XS Boards (http://www.xess.com/FPGA/ho03000.html),
n a place to sign-up for our email forum where you can post questions to other XS
Board users (http://www.xess.com/FPGA/list_reg.html).
n If you can't get your XILINX Foundation software tools installed properly, send an e-
mail message describing your problem to hotline@xilinx.com or check their web site
at http://www.xilinx.com.
Take notice!!
n The XS Boards require an external power supply to operate! They do not draw power
through the downloading cable from the PC parallel port.
n If you are connecting a 9VDC power supply to your XS Board, please make sure the
center terminal of the plug is positive and the outer sleeve is negative.
n The V1.3 version of the XS40 and XSP Boards now use a programmable oscillator
with a default setting of 50 MHz. You must reprogram the oscillator if you want to use
another frequency. The procedure for doing this is described on page 9. The XS95
Board uses a 12 MHz fixed-frequency oscillator and does not need to be
programmed.
Packing List
n an XS40, XS95 or XSP Board (note that your XSP Board will be labeled as an XS40
but the socket will contain a Xilinx Spartan FPGA with an "XCS" prefix);
n a 6' cable with a male DB-25 connector on each end;
n a 3.5" floppy diskette or CDROM with software utilities for using the XS40, XSP or
XS95 Board and documentation.
3
Chapter
2
Installation
Installing the XSTOOLs Utilities and Documentation
XILINX currently provides the Foundation tools for programming their FPGAs and CPLDs.
Any recent version of XILINX software should generate bitstream configuration files that
are compatible with your XS40, XSP or XS95 Boards. Follow the directions XILINX
provides for installing their software.
XESS Corp. provides the additional XSTOOLs utilities for interfacing a PC to your XS
Board. Run the SETUP.EXE program on the 3.5" diskette or CDROM to install these
utilities.
Once the XSTOOLs are installed you will see the following subdirectories:
XSTOOLS\BIN contains the executable programs for downloading to the XS Board

and for applying signals to the XS Board through the printer port. An assembler for
the microcontroller is also included.
XSTOOLS\DOCS contains the documentation and schematics for the XS40, XSP
and XS95 Boards.
Applying Power to Your XS Board
You can use your XS Board in two ways, distinguished by the method you use to apply
power to the board.
Using a 9VDC wall-mount
You can use your XS Board all by itself to experiment logic and microcontroller designs.
Just place the XS Board on a non-conducting surface as shown in Figure 1. Then apply
power to jack J9 of the XS Board from a 9V DC wall transformer with a 2.1 mm female,
center-positive plug. (See Figure 2 or Figure 3 for the location of jack J9 on your
XS40/XSP or XS95 Board, respectively.) The on-board voltage regulation circuitry will
create the voltages required by the rest of the XS Board circuitry.
Protoboard Installation
The two rows of pins from your XS Board can be plugged into a protoboard with holes
spaced at 0.1" intervals. (One of the A.C.E. protoboards from 3M is a good choice.)
4
Once plugged in, all the pins of the FPLD and microcontroller are accessible to other
circuits on the protoboard. (The numbers printed next to the rows of pins on your XS
Board correspond to the pin numbers of the FPGA or CPLD.) Power can still be supplied
to your XS Board though jack J9, or power can be applied directly through several pins on
the underside of the board. Just connect +5V, +3.3V, and ground to the following pins for
your particular type of XS Board. (You will need +3.3V only if your XS40 Board contains
an XC4000XL type of FPGA.)
• Table 1: Power supply pins for the various XS Boards.
XS95-072 V1.2 49 78 none
XS95-108 V1.2 49 78 none
XS40-005E V1.3 52 2, 54 none
XS40-005XL V1.3 52 2 54
XS40-010E V1.3 52 2, 54 none

XS40-010XL V1.3 52 2 54
XSP-010 V1.3 52 2,54 none
• Figure 1: External connections to the XS Board.
5
• Figure 2: Arrangement of components on the XS40 and XSP Boards.
• Figure 3: Arrangement of components on the XS95 Board.
6
Connecting a PC to Your XS Board
The 6' cable included with your XS Board connects it to the parallel port of a PC. One end
of the cable attaches to the printer port and the other connects to the female DB-25
connector (J1) at the top of the XS Board as shown in Figure 1.
Connecting a VGA Monitor to Your XS Board
You can display images on a VGA monitor by connecting it to the 15-pin J2 connector at
the bottom of your XS Board (see Figure 1). You will have to download a VGA driver
circuit to your XS Board to actually display an image. You can find an example VGA driver
at www.xess.com/FPGA.
Connecting a Mouse or Keyboard to Your XS Board
You can accept inputs from a keyboard or mouse by connecting it to the J5 PS/2
connector at the bottom of your XS40 or XSP Board (see Figure 1). The XS95 Board
does not have a PS/2 connector. You will have to download a mouse or keyboard driver
circuit to your XS Board to actually display an image. You can find an example keyboard
driver at www.xess.com/FPGA..
Setting the Jumpers on Your XS Board
The default jumper settings shown in Table 2 and Table 3 configure your XS Board for use
in a logic design environment. You will need to change the jumper settings only if you are:
n using your XS40 or XSP Board in a stand-alone mode where it is unconnected from
the PC parallel port,
n executing microcontroller code from internal ROM instead of the external RAM on the
XS Board,
n reprogramming the clock frequency on your XS40 or XSP Board.
The procedures for performing the operations are described in the rest of this manual.
• Table 2: Jumper settings for XS95 Board.

J7 1-2 (ext) The shunt should be installed on pins 1 and 2 (ext) if the 8031 microcontroller program is stored in the
(default) external 32 KByte RAM (U8) of the XS95 Board.
2-3 (int) The shunt should be installed on pins 2 and 3 (int) if the program is stored internally in the
microcontroller.
7
• Table 3: Jumper settings for XS40 and XSP Boards.

J4 On A shunt should be installed if you are downloading the XS40 or XSP Board through the parallel port.
(default)
Off The shunt should be removed if the XS40 or XSP Board is being configured from the on-board serial
EEPROM (U7).
J6 On The shunt should be installed when the on-board serial EEPROM (U7) is being programmed.
(default)
(default) external 32 KByte RAM (U8) of the XS40 Board.
microcontroller.
J8 On The shunt should be installed in XS40 or XSP Boards which use the 3.3V XC4000XL type of FPGAs.
Off The shunt should be removed on XS40 or XSP Boards which use the 5V XC4000E type of FPGAs.
J10 On The shunt should be installed if the XS40 or XSP Board is being configured from the on-board serial
EEPROM.
Off The shunt should be removed if the XS40 or XSP Board is being downloaded from the PC parallel
(default) port.
J11 On The shunt should be installed if the XS40 or XSP Board is being downloaded from the PC parallel port.
(default)
EEPROM.
J12 Off The shunt should be removed during normal operations when the programmable oscillator is
(default) generating a clock signal.
On The shunt should be installed when the programmable oscillator frequency is being set.
Testing Your XS Board
Once your XS Board is installed and the jumpers are in their default configuration, you can
test the board using one of the commands listed in Table 4. You must execute the
command in a DOS window and be in the XSTOOLS\BIN directory to run the XSTEST
command.
• Table 4: Commands for testing the various types of XS Boards.
XS Board Type Test Command
8
The test procedure programs the FPGA or CPLD, loads the RAM with a test program for
the microcontroller, and then the microcontroller executes this program. The total test
period (including programming the board) is about 15 seconds for an XS40 or XSP Board,
and about a minute for an XS95 Board. If the test completes successfully, then you will
see a O displayed on the LED digit.
However, if the test program detects an error, then the LED digit displays an E or remains
blank. In this case, check the following items:
n Make sure the board is receiving power from a 9V DC power supply through jack J9
or through the VCC and GND pins.
n Check that the board is sitting upon a non-conducting surface and that there are no
connections to any of the pins (except for the VCC and GND pins if this is the way you
are powering the board).
n Verify that the jumpers are in their default configuration.
n Make sure the downloading cable is securely attached to the XS Board and the PC
parallel port.
n Verify that the parallel port is in ECP mode. (The mode is usually set in the BIOS as
either SPP, EPP, ECP, or bidirectional. ECP mode works most reliably while
bidirectional mode is not recommended.)
99.9% of all problems are due to the parallel port. If you cannot get your XS Board to pass
the test even after taking these steps, then contact XESS Corp. to get a replacement
board.
Programming the XS Board Clock Oscillator
The XS40 and XSP Boards have a 100 MHz programmable oscillator (a Dallas
Semiconductor DS1075Z-100). The 100 MHz master frequency can be divided by factors
of 1, 2, ... up to 2048 to get clock frequencies of 100 MHz, 50 MHz, ... down to 48.8 KHz,
respectively. The divided frequency is sent to the rest of the circuitry as a clock signal.
The divisor is stored in non-volatile memory in the oscillator chip so it will resume
operation at its set frequency whenever power is applied to the board. These steps will
store a particular divisor into the oscillator chip memory:
1) In a DOS window, use the following command with arguments that list the type of XS
Board you are using and the particular clock divisor you want:
C:\> XSSETCLK XS40-005XL 8
9
This example command will set the programmable oscillator on an XS40-005XL
Board to a frequency of 100 MHz / 8 = 12.5 MHz You may use any divisor between 1
and 2048 depending upon the clock frequency you want to use.
2) The XSSETCLK will prompt you to remove the power and download cables from your
XS Board. Then you should place a shunt on jumper J12. Then re-attach the
download cable. Then reattach the power cable only after the download cable is
attached!. When power is restored to the XS Board, the programmable oscillator will
power up in its programming mode instead of generating a clock signal.
3) Press RETURN and the clock divisor will be programmed into the oscillator chip. If
you wish to change the value of the divisor, you may re-issue the XSSETCLK
command at this point with a new divisor value without having to power-down the XS
Board.
Once again, remove the power and download cables from your XS Board. Then remove
the shunt from jumper J12. Then re-attach the download cable and the power cable.
When power is restored to the XS Board, the programmable oscillator will power up in its
active mode and output a clock signal at the set frequency.
10
Chapter
3
Programming
This section will show you how to download a logic design from a PC into your XS Board,
and how to store a design in non-volatile memory on your XS Board that will become
active when power is applied.
Downloading Designs into Your XS Board
During the development and testing phases, you will usually connect the XS Board to the
parallel port of a PC and download your circuit each time you make changes to it. You
can download an FPGA design into your XS40 or XSP Board as follows:
where CIRCUIT.BIT is an XC4000 or Spartan bitstream file that contains the configuration
for the XC4000 or XCS FPGA. Make sure the file contains a bitstream for the type of
FPGA chip installed on your XS40 or XSP Board. This file is created using the XILINX
Foundation software tools.
You can download an XC9500-based design into the XS95 Board as follows:
C:\> XSLOAD CIRCUIT.SVF
where CIRCUIT.SVF is an XC9500 bitstream file that contains the configuration for the
XC9500 CPLD. Make sure the file contains a bitstream for the type of XC9500 chip
installed on your XS95 Board. This file is created using the XILINX Foundation software
tools.
Use one of the following commands if you need to configure the FPGA or CPLD and also
download an Intel-formatted HEX file into the static RAM of the XS Board:
C:\> XSLOAD FILE.HEX CIRCUIT.SVF
where CIRCUIT.BIT is a bitstream file and FILE.HEX is a file containing hexadecimal data.
The HEX file could contain microcontroller object code generated by the ASM51
11
assembler, or it could be arbitrary data from some other source. Whatever its source, the
hexadecimal data is downloaded into the XS Board RAM.
XSLOAD assumes the XS Board is connected to parallel port #1 of your PC. You can
specify another port number using the -P option like so:
C:\> XSLOAD -P 2 FILE.HEX CIRCUIT.BIT
Storing Non-Volatile Designs in Your XS Board
Once your design is finished, you may want to store the design on the XS Board so that it
is configured for operation as soon as power is applied.
This is easy with the XS95 Board. The XC9500 CPLD always stores its current
configuration in an on-chip Flash memory. This configuration is restored whenever power
is applied to the XS95 Board. So your design is always available even when the board is
not connected to a PC.
But the XC4000 or XCS FPGA on the XS40 or XSP Board stores its configuration in an
on-chip RAM which is erased whenever power is interrupted. You can place an external
serial EEPROM in socket U7 which stores the FPGA configuration and reloads it on
power-up. The XILINX XC1700 series of serial EEPROMs is a good choice for this, but
you will need an external programmer to load your bitstream into the XC1700 chip. Also
the XC1700 is one-time programmable (OTP), so you will need a new chip every time you
change your logic design. Table 5 lists the serial EEPROM chips you need for storing the
bitstream files for the various types of XS Boards.
• Table 5: Recommended XILINX serial EEPROMS for various types of XS Boards.
XS Board Type Bitstream Size XILINX EEPROM

XS40-005E 95,008 XC17128E
XS40-005XL 151,960 XC17256E
XS40-010E 178,144 XC17256E
XS40-010XL 283,424 XC1701
XSP-010 95,008 XC17S10
You also have the option of storing your design into an AT17C256 Atmel reprogrammable
serial EEPROM if you have an XS40-005E, XS40-005XL, or XS40-010E Boards. The
XS40 Board can directly program the Atmel chip and the FPGAs on these boards have
bitstream files which are small enough to fit in the AT17C256. The following steps will
enable you to load your design into the Atmel EEPROM:
1) Turn off power to the XS Board.
2) Place a shunt on jumper J6. This enables the programming circuitry in the Atmel
EEPROM chip.
12
3) Apply power to the XS Board.
4) Use the following command to load the FPGA bitstream file into the EEPROM:
It will take less than a minute to program the contents of the bitstream in CIRCUIT.BIT
into the Atmel EEPROM.
5) Turn off power to the XS Board.
6) Remove the shunt on jumper J6. This disables the programming circuitry in the Atmel
Once you have your design loaded into a XILINX or Atmel EEPROM, you can place it in
socket U7 on the XS Board. Then the following steps will make the XS Board configure
itself from the EEPROM instead of the PC parallel port interface:
1) Remove the downloading cable from connector J1 of the XS Board. (As an

alternative, you can use the command ''XSPORT 0'' to make sure the upper two data
bits of the parallel port are at logic 0. These bits are connected to the mode pins of
the FPGA and must be at logic 0 or the FPGA will not power-up in the active-serial
mode.)
2) Place a shunt on jumper J10. This sets the FPGA into the active-serial mode so it will
3) Remove the shunts on jumpers J4 and J11. This prevents the PC interface circuitry
on the XS Board from interfering with the clock and data signals from the FPGA.
4) Apply power to the XS Board. The FPGA will be configured from the serial EEPROM.
You may reattach the downloading cable if you need to inject test signals into your
design using the XSPORT program.
13
Chapter
4
Programmer's
Models
This section discusses the organization of components on the XS Boards and introduces
the concepts required to create applications that use both the microcontroller and the
FPLD (field programmable logic device). Building FPLD-based designs is covered in
detail in the Practical Xilinx Designer by Prentice-Hall.
Microcontroller + FPLD Design Flow
The basic design flow for building microcontroller+FPLD applications is shown in Figure 4.
Initially you have to get the specifications for the system you are trying to design. Then
you have to determine what inputs are available to your system and what outputs it will
generate.
At this point, you have to partition the functions of your system between the microcontroller
and the FPLD. Some of the input signals will go to the microcontroller, some will go to the
FPLD, and some will go to both. Likewise, some of the outputs will be computed by the
microcontroller and some by the FPLD. There will also be some new intra-system inputs
and outputs created by the need for the microcontroller and the FPLD to cooperate.
In general, the FPLD will be used mainly for low-level functions where signal transitions
example.Once the design has been partitioned and you have assigned the various inputs,
outputs, and functions to the microcontroller and the FPLD, then you can begin doing
detailed design of the software and hardware. For the software, you can use your favorite
editor to create a .ASM assembly-language file and assemble it with ASM51 to create a
.HEX file for the 8031 microcontroller on the XS Board. For the FPLD hardware portion,
you will enter truth-tables and logic equations into a .ABL or .VHDL file and compile it into
a .BIT or .SVF bitstream file using the XILINX Foundation software.
With the .HEX 8031-program file and the FPLD bitstream file in hand, you can download
them to the XS Board using the XSLOAD program. XSLOAD stores the contents of the
.HEX file into the static RAM on the XS Board and then it reconfigures the FPLD by
loading it with the bitstream file.
When the XS Board is loaded with the hardware and software, you need to test it to see if
it really works. The answer usually starts as "No" so you need a method of injecting test
14
signals to the XS Board through the PC parallel port. You can trace the reaction of your
system to signals from the parallel port by programming the microcontroller and the FPLD
to output status information on the LED digit (much like placing "printf" statements in your
C language programs). This is admittedly crude but will serve if you don't have access to
programmable stimulus generators and logic analyzers.
• Figure 4: FPLD+microcontroller design flow.
XS Board Component Interconnections
The microcontroller and the FPLD on the XS Board are already connected together.
These existing connections save you the effort of having to wire them yourself, but they
also impose limitations on how your program and the FPLD hardware will interact. High-
level views of how the microcontroller, RAM, and FPLD on the XS40, XSP, and XS95
Boards are connected are shown in Figure 5, Figure 6, and Figure 7, respectively. More
detailed schematics are presented at the end of this manual.
The oscillator output goes directly to a synchronous clock input of the FPLD. The FPLD
can control the clock it sends to the XTAL1 clock input of the microcontroller.
15
The microcontroller multiplexes the lower eight bits of a memory address with eight bits of
data and outputs this on its P0 port. Both the RAM data lines and the FPLD are
connected to P0. The RAM uses this connection to send and receive data to and from the
microcontroller. The FPLD is programmed to latch the address from P0 under control of
the ALE signal and send the latched address bits to the lower eight address lines of the
RAM.
Meanwhile, the upper eight bits of the address are output on port P2 of the microcontroller.
The RAM uses the lower seven of these address bits. The FPLD also receives the upper
eight address bits and decodes these along with the PSEN and read/write control line
(from pin P3.6 of port P3 ) from the microcontroller to generate the CE and OE signals that
enable the RAM and its output drivers, respectively. Either of the CE or OE signals can be
pulled high to disable the RAM and prevent it from having any effect on the rest of the XS
Board circuitry.
One of the outputs of the CPLD controls the reset line of the microcontroller. The
microcontroller can be prevented from having any effect on the rest of the circuitry by
forcing the RST pin high through the FPLD. (When RST is active, the microcontroller pins
are weakly pulled high.)
Many of the I/O pins of ports P1 and P3 of the microcontroller connect to the FPLD and
can be used for general-purpose I/O between the microcontroller and the FPLD. In
addition to being general-purpose I/O, the P3 pins also have special functions such as
serial transmitters, receivers, interrupt inputs, timer inputs, and external RAM read/write
associated pin for general-purpose I/O between the microcontroller and the FPLD. In
many cases, however, you will program the FPLD to make use of the special-purpose
microcontroller pins. (For example, the FPLD could generate microcontroller interrupts.) If
you want to use the special-purpose pin with an external circuit, then the FPLD I/O pin
connected to it must be tristated.
An LED digit connects directly to the FPLD. (These same FPLD pins also drive the VGA
monitor connector. The FPLD can be programmed so the microcontroller can control the
LEDs either through P1 or P3 or by memory-mapping a latch for the LED into the memory
space of the 8031.
The PC can transmit signals to the XS Board through the eight data output bits of the
printer port. The FPLD has direct access to these signals. The microcontroller can also
access them if you program the FPLD to pass the data bits onto the FPLD I/O pins
connected to the microcontroller.
Communication from the XS Board back to the PC also occurs through the parallel port.
The parallel port status pins are connected to pins of microcontroller ports P1 and P3 .
Either the microcontroller or the FPLD can drive the status pins. The PC can read the
status pins to fetch data from the XS Board.
The FPGAs on the XS40 and XSP Boards also have access to the clock and data lines of
a keyboard or mouse attached to the PS/2 port of the board.
16
• Table 6: XS40 Board pin descriptions.
XS40 Pin Connects to… Description

25 S0, BLUE0 These pins drive the individual segments of the LED display (S0-S6 and DP). They
26 S1, BLUE1 also drive the color and horizontal sync signals for a VGA monitor.
24 S2, GREEN0
20 S3, GREEN1
23 S4, RED0
18 S5, RED1
19 S6, HSYNCB
13 CLK An input driven by the 100 MHz programmable oscillator.
44 PC_D0 These pins are driven by the data output pins of the PC parallel port. Clocking signals
45 PC_D1 can only be reliably applied through pins 44 and 45 since these have additional
46 PC_D2 hysterisis circuitry. Pins 32 and 34 are mode signals for the FPGA so you must adjust
47 PC_D3 your design to account for the way that the Foundation tools handle these pins.
48 PC_D4
49 PC_D5
32 PC_D6
34 PC_D7
37 XTAL1 Pin that drives the uC clock input
36 RST Pin that drives the uC reset input
29 ALEB Pin that monitors the uC address latch enable
14 PSENB Pin that monitors the uC program store enable
7 P1.0 These pins connect to the pins of Port 1 of the uC. Some of the pins are also
8 P1.1 connected to the status input pins of the PC parallel port. Pin 67 drives the vertical
9 P1.2 sync signal for a VGA monitor.
6 P1.3
77 P1.4, PC_S4
70 P1.5, PC_S3
66 P1.6, PC_S5
67 P1.7, VSYNCB
69 P3.1(TXD), PC_S6, These pins connect to some of the pins of Port 3 of the uC. The uC has specialized
68 P3.4(T0),PS/2 CLK functions for each of the port pins indicated in parentheses. Pin 62 connects to the
62 P3.6(WRB), WEB data write pin of the uC and the write-enable pin of the RAM. Pin 69 connects to a
27 P3.7(RDB) status input pin of the PC parallel port and the PS/2 data line. Pin 68 connects to the
41 P0.0(AD0), D0 These pins connect to Port 0 of the uC which is also a multiplexed address/data port.
40 P0.1(AD1), D1 These pins also connect to the data pins of the RAM.
39 P0.2(AD2), D2
38 P0.3(AD3), D3
35 P0.4(AD4), D4
81 P0.5(AD5), D5
80 P0.6(AD6), D6
10 P0.7(AD7), D7
59 P2.0(A8), A8 These pins connect to Port 2 of the uC which also outputs the upper address byte.
57 P2.0(A9), A9 These pins also connect to the 7 upper address bits of the RAM.
51 P2.0(A10), A10
56 P2.0(A11), A11
50 P2.0(A12), A12
58 P2.0(A13), A13
60 P2.0(A14), A14
28 P2.0(A15)
3 A0 These pins drive the 8 lower address bits of the RAM.
4 A1
5 A2
78 A3
79 A4
82 A5
83 A6
84 A7
61 OEB Pin that drives the RAM output enable.
65 CEB Pin that drives the RAM chip enable.
75 PC_S7 Pin that drives a status input pin of the PC parallel port.
17
• Figure 5: XS40 Board programmer's model.
18
• Table 7: XSP Board pin descriptions.

25 S0, BLUE0 These pins drive the individual segments of the LED display (S0-S6 and DP). They
26 S1, BLUE1 also drive the color and horizontal sync signals for a VGA monitor.
24 S2, GREEN0
20 S3, GREEN1
23 S4, RED0
18 S5, RED1
19 S6, HSYNCB
44 PC_D0 These pins are driven by the data output pins of the PC parallel port. Clocking signals
46 PC_D2 hysterisis circuitry.
47 PC_D3
48 PC_D4
49 PC_D5
7 P1.0 These pins connect to the pins of Port 1 of the uC. Some of the pins are also
8 P1.1 connected to the status input pins of the PC parallel port. Pin 67 drives the vertical
9 P1.2 sync signal for a VGA monitor.
6 P1.3
77 P1.4, PC_S4
70 P1.5, PC_S3
66 P1.6, PC_S5
67 P1.7, VSYNCB
P3.1(TXD), PC_S6, These pins connect to some of the pins of Port 3 of the uC. The uC has specialized
69
PS/2 DATA functions for each of the port pins indicated in parentheses. Pin 62 connects to the
data write pin of the uC and the write-enable pin of the RAM. Pin 69 connects to a
68 P3.4(T0),PS/2 CLK
status input pin of the PC parallel port and the PS/2 data line. Pin 68 connects to the
62 P3.6(WRB), WEB PS/2 clock line.
27 P3.7(RDB)
40 P0.1(AD1), D1 These pins also connect to the data pins of the RAM.
39 P0.2(AD2), D2
38 P0.3(AD3), D3
35 P0.4(AD4), D4
81 P0.5(AD5), D5
80 P0.6(AD6), D6
10 P0.7(AD7), D7
57 P2.0(A9), A9 These pins also connect to the 7 upper address bits of the RAM.
51 P2.0(A10), A10
56 P2.0(A11), A11
50 P2.0(A12), A12
58 P2.0(A13), A13
60 P2.0(A14), A14
28 P2.0(A15)
4 A1
5 A2
78 A3
79 A4
82 A5
83 A6
84 A7
19
• Figure 6: XSP Board programmer's model.
20

21 S0,BLUE0 These pins drive the individual segments of the LED display (S0-S6 and DP). They also drive
23 S1,BLUE1 the color, horizontal, and vertical sync signals for a VGA monitor.
19 S2,GREEN0
17 S3,GREEN1
18 S4,RED0
14 S5,RED1
15 S6,HSYNCB
24 DP,VSYNCB
9 CLK An input driven by the 12 MHz oscillator.
46 PC_D0 These pins are driven by the data output pins of the PC parallel port. Clocking signals can only
47 PC_D1 be reliably applied through pins 46 and 47 since these have additional hysterisis circuitry.
48 PC_D2
50 PC_D3
51 PC_D4
52 PC_D5
81 PC_D6
80 PC_D7
6 P1.0 These pins connect to the pins of Port 1 of the uC. Some of the pins are also connected to the
7 P1.1 status input pins of the PC parallel port.
11 P1.2
5 P1.3
72 P1.4,PC_S4
71 P1.5,PC_S3
66 P1.6,PC_S5
67 P1.7
31 P3.0(RXD) These pins connect to the pins of Port 3 of the uC. The uC has specialized functions for each of
70 P3.1(TXD), PC_S6 the port pins indicated in parentheses. Pin 63 connects to the data write pin of the uC and the
69 P3.2(INTB0) write-enable pin of the RAM. Pin 70 connects to a status input pin of the PC parallel port.
68 P3.3(INTB1)
26 P3.4(T0)
33 P3.5(T1)
63 P3.6(WRB), WEB
32 P3.7(RDB)
44 P0.0(AD0), D0 These pins connect to Port 0 of the uC which is also a multiplexed address/data port. These
43 P0.1(AD1), D1 pins also connect to the data pins of the RAM.
41 P0.2(AD2), D2
40 P0.3(AD3), D3
39 P0.4(AD4), D4
37 P0.5(AD5), D5
36 P0.6(AD6), D6
35 P0.7(AD7), D7
58 P2.0(A8), A8 These pins connect to Port 2 of the uC which also outputs the upper address byte. These pins
56 P2.0(A9), A9 also connect to the 7 upper address bits of the RAM.
54 P2.0(A10), A10
55 P2.0(A11), A11
53 P2.0(A12), A12
57 P2.0(A13), A13
61 P2.0(A14), A14
34 P2.0(A15)
79 A1
82 A2
84 A3
1 A4
3 A5
83 A6
2 A7
4 FREE0 These pins are not connected to other devices and can be used as general purpose I/O.
12 FREE1
25 FREE2
74 FREE3
21
76 FREE4
77 FREE5
22
• Figure 7: XS95 Board programmer's model.
23
XS40 and XSP Board Schematic
XS95 Board Schematic
2608 Sweetgum Drive
Apex NC 27502
Toll-free: 800-549-9377
FAX: 919-387-1302
XS40, XSP Board V1.4

User Manual

your new XS40 or XSP Board
RELEASE DATE: 9/24/1999

Limited Warranty

state.

1
Preliminaries
Getting Help!
n If you can't get the XS40 Board hardware to work, send an e-mail message describing
your problem to fpga-bugs@xess.com or check our web site at http://www.xess.com.
Our web site also has
n answers to frequently-asked-questions,
n example designs for the XS Boards,
n a place to sign-up for our email forum where you can post questions to other XS
Board users.
n If you can't get your XILINX Foundation software tools installed properly, send an e-
at http://support.xilinx.com.
Take notice!!
n The XS40 Board requires an external power supply to operate! It does not draw
power through the downloading cable from the PC parallel port.
n If you are connecting a 9VDC power supply to your XS40 Board, please make sure
the center terminal of the plug is positive and the outer sleeve is negative.
n The V1.4 version of the XS40 Board now uses a programmable oscillator with a
default frequency of 50 MHz. You must reprogram the oscillator if you want to use
another frequency. The procedure for doing this is described on page 7.
XS40 BOARD V1.4 USER MANUAL 1

Packing List
n an XS40 or XSP Board (note that your XSP Board will be labeled as an XS40 but the
socket will contain a Xilinx Spartan FPGA with an "XCS" prefix);
n a 6' cable with a 25-pin male connector on each end;
n a 3.5" floppy diskette or CDROM with software utilities and documentation for using
the XS40 Board.

2
Installation
Installing the XSTOOLs Utilities and Documentation
XILINX currently provides the Foundation tools for programming their FPGAs and CPLDs.
Any recent version of XILINX software should generate bitstream configuration files that
are compatible with your XS40 Board. Follow the directions XILINX provides for installing
their software.
XESS Corp. provides the additional XSTOOLs utilities for interfacing a PC to your XS40
Board. Run the SETUP.EXE program on the 3.5" diskette or CDROM to install these
utilities.
Once the XSTOOLs are installed you will see the following subdirectories:
XSTOOLS\BIN contains the executable programs for downloading to the XS40 Board
and for applying signals to the XS40 Board through the printer port. An assembler for
the microcontroller on the XS40 Board is also included.
XSTOOLS\DOCS contains the documentation and schematics for the XS40 Board.
Applying Power to Your XS40 Board
You can use your XS40 Board in two ways, distinguished by the method you use to apply
power to the board.
Using a 9VDC wall-mount
You can use your XS40 Board all by itself to experiment with logic and microcontroller
designs. Just place the XS40 Board on a non-conducting surface as shown in Figure 1.
Then apply power to jack J9 of the XS40 Board from a 9V DC wall transformer with a 2.1
mm female, center-positive plug. (See Figure 2 for the location of jack J9 on your XS40
Board.) The on-board voltage regulation circuitry will create the voltages required by the
rest of the XS40 Board circuitry.
Solderless Breadboard Installation
The two rows of pins from your XS40 Board can be plugged into a solderless breadboard
with holes spaced at 0.1" intervals. (One of the A.C.E. protoboards from 3M is a good
choice.) Once plugged in, all the pins of the FPGA and microcontroller, and SRAM are
accessible to other circuits on the breadboard. (The numbers printed next to the rows of
pins on your XS40 Board correspond to the pin numbers of the FPGA.) Power can still be

supplied to your XS40 Board though jack J9, or power can be applied directly through
several pins on the underside of the board. Just connect +5V, +3.3V, and ground to the
following pins for your particular type of XS40 Board. (You will need +3.3V only if your
XS40 Board contains an XC4000XL type of FPGA.)
• Table 1: Power supply pins for the various XS40 Boards.
XS40 Board Type GND Pin +5V Pin +3.3V Pin
XS40-005E V1.4 52 2, 54 none
XS40-005XL V1.4 52 2 54
XS40-010E V1.4 52 2, 54 none
XS40-010XL V1.4 52 2 54
XSP-010 V1.4 52 2,54 none
• Figure 1: External connections to the XS40 Board.

PC Parallel Port
J1
100 MHz Osc. U3 U5 J8 (not installed)

U4 U7 U9
J12
J6 9VDC Power Supply
J4
J11 J9
SRAM
U15
Serial EEPROM
Socket
FPGA
U1
J10 U10
J7
Microcontroller
J2
J5
PS/2 Mouse VGA Monitor

or Keyboard
• Figure 2: Arrangement of components on the XS40 Board.
Connecting a PC to Your XS40 Board
The 6' cable included with your XS40 Board connects it to a PC. One end of the cable
attaches to the parallel port on the PC and the other connects to the female DB-25
connector (J1) at the top of the XS40 Board as shown in Figure 1.
Connecting a VGA Monitor to Your XS40 Board
the bottom of your XS40 Board (see Figure 1). You will have to download a VGA driver
circuit to your XS40 Board to actually display an image. You can find an example VGA
driver at http://www.xess.com.

Connecting a Mouse or Keyboard to Your XS40 Board
connector at the bottom of your XS40 Board (see Figure 1). You can find an example
keyboard driver at http://www.xess.com.
Setting the Jumpers on Your XS40 Board
The default jumper settings shown in Table 2 configure your XS40 Board for use in a logic
design environment. You will need to change the jumper settings only if you are:
n using your XS40 in a stand-alone mode where it is unconnected from the PC parallel
port (see page 10),
n reprogramming the clock frequency on your XS40 Board (see page 7),
n executing microcontroller code from internal ROM instead of the external SRAM on
the XS40 Board. (You will have to replace the ROMless microcontroller on the XS40
Board with a ROM version to use this feature.)
• Table 2: Jumper settings for XS40 and XSP Boards.

J4 On A shunt should be installed if you are downloading the XS40 or XSP Board through the parallel port.
(default)
EEPROM (U7).
J6 On The shunt should be installed when the on-board serial EEPROM (U7) is being programmed.
(default)
(default) external 32 KByte SRAM (U8) of the XS40 Board.
microcontroller.
J8 On The shunt should be installed in XS40 or XSP Boards which use the 3.3V XC4000XL type of FPGAs.
Off The shunt should be removed on XS40 or XSP Boards which use the 5V XC4000E type of FPGAs.
J10 On The shunt should be installed if the XS40 or XSP Board is being configured from the on-board serial
EEPROM.
Off The shunt should be removed if the XS40 or XSP Board is being downloaded from the PC parallel
(default) port.
J11 On The shunt should be installed if the XS40 or XSP Board is being downloaded from the PC parallel port.
(default)
EEPROM.
J12 1-2 (osc) The shunt should be installed on pins 1 and 2 (osc) during normal operations when the programmable
(default) oscillator is generating a clock signal.
2-3 (set) The shunt should be installed on pins 2 and 3 (set) when the programmable oscillator frequency is
being set.

Testing Your XS40 Board
Once your XS40 Board is installed and the jumpers are in their default configuration, you
can test the board by typing one of the commands listed in Table 3 into a DOS window.
• Table 3: Commands for testing the various types of XS40 Boards.
XS40 Board Type Test Command
The test procedure programs the FPGA, loads the SRAM with a test program for the
microcontroller, and then the microcontroller executes this program. The total test period
(including programming the board) is about 15 seconds for an XS40 Board. If the test
completes successfully, then you will see a O displayed on the LED digit.
However, if the test program detects an error, then the LED digit displays an E or remains
blank. In this case, check the following items:
n Make sure the XS40 Board is receiving power from a 9V DC power supply through
jack J9 or through the VCC and GND pins.
n Check that the XS40 Board is sitting upon a non-conducting surface and that there
are no connections to any of the pins (except for the VCC and GND pins if this is the
way you are powering the board).
n Verify that the jumpers are in their default configuration.
n Make sure the downloading cable is securely attached to the XS40 Board and the PC
parallel port.
n Verify that the parallel port is in ECP mode. (The mode is usually set in the BIOS as
either SPP, EPP, ECP, or bidirectional. ECP mode works most reliably while
bidirectional mode is not recommended.)
99.9% of all problems are due to the parallel port. If you cannot get your XS40 Board to
pass the test even after taking these steps, then contact XESS Corp. to get a replacement
board.
Programming the XS40 Board Clock Oscillator
The XS40 Board has a 100 MHz programmable oscillator (a Dallas Semiconductor
DS1075Z-100). The 100 MHz master frequency can be divided by factors of 1, 2, ... up to

2052 to get clock frequencies of 100 MHz, 50 MHz, ... down to 48.7 KHz, respectively.
The divided frequency is sent to the FPGA as a clock signal.
operation at its programmed frequency whenever power is applied to the XS40 Board.
The following steps will store a particular divisor into the oscillator chip memory:
1) In a DOS window, use the following command with the type of XS40 Board and the
clock divisor you want listed as arguments:
C:\> XSSETCLK XS40-005XL 8
The example shown above will set the programmable oscillator on an XS40-005XL
Board to a frequency of 100 MHz / 8 = 12.5 MHz You may use any divisor between 1
and 2052 depending upon the clock frequency you want to use.
2) The XSSETCLK program will prompt you to remove the power and download cables
from your XS40 Board. Then you should place a shunt on jumper J12. Then re-
attach the download cable. Then reattach the power cable only after the download
cable is attached!. When power is restored to the XS40 Board, the programmable
oscillator will power up in its programming mode instead of generating a clock signal.
3) Press RETURN and the clock divisor will be programmed into the oscillator chip. If
you wish to change the value of the divisor, you may re-issue the XSSETCLK
command at this point with a new divisor without having to power-down the XS40
Board.
4) Finally, remove the power and download cables from your XS40 Board. Then
remove the shunt from jumper J12. Then re-attach the download cable and the
power cable. When power is restored to the XS40 Board, the programmable
oscillator will power up in its active mode and output a clock signal at the programmed
frequency.

3
Programming
This section will show you how to download a logic design from a PC into your XS40
Board and how to store a design in its optional serial EEPROM that will become active
when power is applied.
Downloading Designs into Your XS40 Board
During the development and testing phases, you will usually connect the XS40 Board to
the parallel port of a PC and download your circuit each time you make changes to it. You
can download an FPGA design into your XS40 Board as follows:
where CIRCUIT.BIT is an XC4000 or Spartan bitstream file that contains the configuration
for the XC4000 or XCS FPGA. This file is created using the XILINX Foundation software
tools. Make sure the file contains a bitstream for the type of FPGA chip installed on your
XS40 Board.
Use one of the following commands if you need to configure the FPGA and also
download an Intel-formatted HEX file into the SRAM of the XS40 Board:
where CIRCUIT.BIT is a bitstream file and FILE.HEX is a file containing hexadecimal data.
The HEX file could contain microcontroller object code generated by the ASM51
assembler, or it could be arbitrary data from some other source. Whatever its source, the
hexadecimal data is downloaded into the XS40 Board SRAM.
XSLOAD assumes the XS40 Board is connected to parallel port #1 of your PC. You can
specify another port number using the -P option like so:
C:\> XSLOAD -P 2 FILE.HEX CIRCUIT.BIT

Storing Non-Volatile Designs in Your XS40 Board
Once your design is finished, you may want to store the design on the XS40 Board so that
it is configured for operation as soon as power is applied.
The XC4000 or XCS FPGA on the XS40 Board stores its configuration in an on-chip
SRAM which is erased whenever power is removed. You can place an external serial
EEPROM in socket U7 which stores the FPGA configuration and reloads it on power-up.
The XILINX XC1700 series of serial EEPROMs is a good choice for this, but you will need
an external programmer to download your bitstream into the XC1700 chip. Also the
XC1700 is one-time programmable (OTP), so you will need a new chip every time you
change your logic design. Table 4 lists the serial EEPROM chip you need for storing the
bitstream files for each type of XS40 Board.
• Table 4: Recommended XILINX serial EEPROMS for various types of XS40 Boards.
XS40 Board Type Bitstream Size XILINX EEPROM

XS40-005E 95,008 XC17128E
XS40-005XL 151,960 XC17256E
XS40-010E 178,144 XC17256E
XS40-010XL 283,424 XC1701
XSP-010 95,008 XC17S10
You also have the option of storing your design into an AT17C256 Atmel reprogrammable
serial EEPROM if you have an XS40-005E, XS40-005XL, or XS40-010E Boards. The
XS40 Board can directly program the Atmel chip and the FPGAs on these boards have
bitstream files which are small enough to fit in the AT17C256. You can load your design
into the Atmel EEPROM by following these steps:
1) Turn off power to the XS40 Board.
2) Place the Atmel AT17C256 EEPROM chip into the U7 socket.
3) Place a shunt on jumper J6. This enables the programming circuitry in the Atmel
EEPROM chip.
4) Apply power to the XS40 Board.
5) Use the following command to load the FPGA bitstream file into the EEPROM:
It will take less than a minute to program the contents of the bitstream in CIRCUIT.BIT
into the Atmel EEPROM.
6) Turn off power to the XS40 Board.

7) Remove the shunt on jumper J6. This disables the programming circuitry in the Atmel
Once your design is loaded into an EEPROM, the following steps will make the XS40
Board configure itself from the EEPROM in socket U7 instead of the PC parallel port
interface:
1) Remove the downloading cable from connector J1 of the XS40 Board. (As an
alternative, you can use the command XSPORT 0 to make sure the upper two data
bits of the parallel port are at logic 0. These bits are connected to the mode pins of
the FPGA and must be at logic 0 or the FPGA will not power-up in the active-serial
mode.)
2) Place a shunt on jumper J10. This sets the FPGA into the active-serial mode so it will
3) Remove the shunts on jumpers J4 and J11. This prevents the PC interface circuitry
on the XS40 Board from interfering with the clock and data signals from the FPGA.
4) Apply power to the XS40 Board. The FPGA will be configured from the serial
EEPROM. You may reattach the downloading cable if you need to inject test signals
into your design using the XSPORT program.

4
Programmer's
Models
This section discusses the organization of components on the XS40 Board and introduces
the concepts required to create applications that use both the microcontroller and the
FPGA. Building FPGA-based designs is covered in detail in the Practical Xilinx Designer
Lab Book by Prentice-Hall.
Microcontroller + FPGA Design Flow
The basic design flow for building microcontroller+FPGA applications is shown in Figure 3.
Initially you have to get the specifications for the system you are trying to design. Then
you have to determine what inputs are available to your system and what outputs it will
generate.
At this point, you have to partition the functions of your system between the microcontroller
and the FPGA. Some of the input signals will go to the microcontroller, some will go to the
FPGA, and some will go to both. Likewise, some of the outputs will be computed by the
microcontroller and some by the FPGA. There will also be some new intra-system inputs
and outputs created by the need for the microcontroller and the FPGA to cooperate.
In general, the FPGA will be used mainly for low-level functions where signal transitions
example. Once the design has been partitioned and you have assigned the various
inputs, outputs, and functions to the microcontroller and the FPGA, then you can begin
doing detailed design of the software and hardware. For the software, you can use your
favorite editor to create a .ASM assembly-language file and assemble it with ASM51 to
create a .HEX file for the microcontroller on the XS40 Board. For the FPGA hardware
portion, you will enter truth-tables and logic equations into a .ABL or .VHDL file and
compile it into an .BIT bitstream file using the XILINX Foundation software.
You can download the .HEX program file and the .BIT bitstream file to the XS40 Board
using the XSLOAD program. XSLOAD stores the contents of the .HEX file into the
SRAM on the XS40 Board and then it reconfigures the FPGA by loading it with the
bitstream file.
When the XS40 Board is loaded with the hardware and software, you need to test it to see
if it really works. The answer usually starts as "No" so you need a method of injecting test

signals to the XS40 Board through the PC parallel port. You can trace the reaction of your
system to signals from the parallel port by programming the microcontroller and the FPGA
to output status information on the LED digit (much like placing "printf" statements in your
C language programs). This is admittedly crude but will serve if you don't have access to
a programmable stimulus generator or logic analyzer.
• Figure 3: FPLD+microcontroller design flow.
XS40 Board Component Interconnections
The microcontroller and the FPGA on the XS40 Board are already connected together.
These pre-existing connections save you the effort of having to wire them yourself, but
they also impose limitations on how your microcontroller program and the FPGA hardware
will interact. A high-level view of how the microcontroller, SRAM, and FPGA on the XS40
Board are connected is shown on the following pages. A more detailed schematic is also
presented at the end of this manual.
The programmable oscillator output goes directly to a synchronous clock input of the
FPGA. The FPGA uses this clock to generate a clock that it sends to the XTAL1 clock
input of the microcontroller.

The microcontroller multiplexes the lower eight bits of a memory address with eight bits of
data and outputs this on its P0 port. Both the SRAM data lines and the FPGA are
connected to P0. The SRAM uses this connection to send and receive data to and from
the microcontroller. The FPGA is programmed to latch the address output on P0 under
control of the ALE signal and send the latched address bits to the lower eight address
lines of the SRAM.
Meanwhile, the upper eight bits of the address are output on the P2 port of the
microcontroller. The 32 KByte SRAM on the XS40 Board uses the lower seven of these
address bits. The FPGA also receives the upper eight address bits and decodes these
along with the PSENB and read/write control line (from pin P3.6 of port P3 ) from the
microcontroller to generate the CEB and OEB signals that enable the SRAM and its output
drivers, respectively. Either of the CEB or OEB signals can be pulled high to disable the
SRAM and prevent it from having any effect on the rest of the XS40 Board circuitry.
One of the outputs of the FPGA controls the reset line of the microcontroller. The
microcontroller can be prevented from having any effect on the rest of the circuitry by
forcing the RST pin high through the FPGA. (When RST is active, the microcontroller pins
are weakly pulled high.)
Many of the I/O pins of ports P1 and P3 of the microcontroller connect to the FPGA and
can be used for general-purpose I/O between the microcontroller and the FPGA. In
addition to being general-purpose I/O, the P3 pins also have special functions such as
serial transmitters, receivers, interrupt inputs, timer inputs, and external SRAM read/write
associated pin for general-purpose I/O between the microcontroller and the FPGA. In
many cases, however, you will program the FPGA to make use of the special-purpose
microcontroller pins. (For example, the FPGA could generate microcontroller interrupts.)
If you want to drive the special-purpose pin from an external circuit, then the FPGA I/O pin
connected to it must be tristated.
A seven-segment LED digit connects directly to the FPGA. (These same FPGA pins can
also drive a VGA monitor.) The FPGA can be programmed so the microcontroller can
control the LEDs either through P1 or P3 or by memory-mapping a latch for the LED into
the memory space of the microcontroller.
The PC can transmit signals to the XS40 Board through the eight data output bits of the
parallel port. The FPGA has direct access to these signals. The microcontroller can also
access these signals if you program the FPGA to pass them onto the FPGA I/O pins
connected to the microcontroller.
Communication from the XS40 Board back to the PC also occurs through the parallel port.
The parallel port status pins are connected to pins of microcontroller ports P1 and P3 .
Either the microcontroller or the FPGA can drive the status pins. The PC can read the
status pins to fetch data from the XS40 Board.
The FPGA also has access to the clock and data lines of a keyboard or mouse attached to
the PS/2 port of the board.


25 S0, BLUE0
26 S1, BLUE1
24 S2, GREEN0
These pins drive the individual segments of the LED display (S0-S6). They also drive
20 S3, GREEN1 the color and horizontal sync signals for a VGA monitor.
23 S4, RED0
18 S5, RED1
19 S6, HSYNCB
44 PC_D0
45 PC_D1
These pins are driven by the data output pins of the PC parallel port. Clocking signals
47 PC_D3 hysterisis circuitry. Pins 32 and 34 are mode signals for the FPGA so you must adjust
48 PC_D4 your design to account for the way that the Foundation tools handle these pins. pins
32 and 34 are not usable as general-purpose I/O on the Spartan FPGA on the XSP
49 PC_D5
Board.
32 PC_D6
34 PC_D7
7 P1.0
8 P1.1
9 P1.2
These pins connect to the pins of Port 1 of the uC. Some of the pins are also
6 P1.3
connected to the status input pins of the PC parallel port. Pin 67 drives the vertical
77 P1.4, PC_S4 sync signal for a VGA monitor.
70 P1.5, PC_S3
66 P1.6, PC_S5
67 P1.7, VSYNCB
69 P3.1(TXD), PC_S6, These pins connect to some of the pins of Port 3 of the uC. The uC has specialized
68 P3.4(T0),PS/2 CLK functions for each of the port pins indicated in parentheses. Pin 62 connects to the
data write pin of the uC and the write-enable pin of the SRAM. Pin 69 connects to a
62 P3.6(WRB), WEB
status input pin of the PC parallel port and the PS/2 data line. Pin 68 connects to the
27 P3.7(RDB) PS/2 clock line.
41 P0.0(AD0), D0
40 P0.1(AD1), D1
39 P0.2(AD2), D2
35 P0.4(AD4), D4 These pins also connect to the data pins of the SRAM.
81 P0.5(AD5), D5
80 P0.6(AD6), D6
10 P0.7(AD7), D7
59 P2.0(A8), A8
57 P2.0(A9), A9
51 P2.0(A10), A10
These pins also connect to the upper address bits of the SRAM. Pins 28 and 16 are
50 P2.0(A12), A12 connected to the 128 KB SRAM address pins only on the XS40+ Board. Pins 28 and
58 P2.0(A13), A13 16 do not connect to the 32 KB SRAM on the XS40 Board.
60 P2.0(A14), A14
28 P2.0(A15), A15
16 A16
3 A0
4 A1
5 A2
78 A3
These pins drive the 8 lower address bits of the SRAM.
79 A4
82 A5
83 A6
84 A7
61 OEB Pin that drives the SRAM output enable.
65 CEB Pin that drives the SRAM chip enable.

PC Parallel Port
Status Inputs
PS/2 Port
PC_S7
PC_S6
PC_S5 KB_DATA
PC_S4
PC_S3 KB_CLK
VSYNC 21
VGA Inputs
37 XTAL1
HSYNC 36 10 RST
RED1 29 33 ALE
8031 uC
RED0 32
GREEN1 14 PSEN
GREEN0 67 9 P1.7
BLUE1 66 8 P1.6
BLUE0 70 7 P1.5
77 6 P1.4
6 5 P1.3
9 4 P1.2
8 3 P1.1
7 2 P1.0
S6
S6 19 27 19 P3.7 (RD)
S5 S3 S4 S5 18 18 P3.6 (WR)
S4 23 17
S3 20 P3.5 (T1)
S2 S1 S2 68 16 P3.4 (T0)
S0 24
S1 26 15 P3.3 (INT1)
S0 25 75 14 P3.2 (INT0)
69 13 P3.1 (TXD)
11 P3.0 (RXD)
7-Segment LED 10 36 P0.7 (A7/D7)
80 37 P0.6 (A6/D6)
81 38 P0.5 (A5/D5)
35 39 P0.4 (A4/D4)
38 40 P0.3 (A3/D3)
39 41 P0.2 (A2/D2)
40 42 P0.1 (A1/D1)
41 43 P0.0 (A0/D0)
28 31 P2.7 (A15)
FPGA
60 30 P2.6 (A14)
58 29 P2.5 (A13)
28
100 MHz 13
50
56 27
P2.4 (A12)
P2.3 (A11)
Prog. Osc. 51 26
25
P2.2 (A10)
57 P2.1 (A9)
59 24 P2.0 (A8)
13 D7
14
32K/128K** x 8 SRAM
D6
15 D5
21 D4
20 D3
19 D2
18 D1
17
PC Parallel Port
D0
Data Outputs
16 2 A16**
PC_D7* 34* 31
PC_D6* 32* A15**
6 A14
PC_D5 49 27
PC_D4 48 A13
4 A12
PC_D3 47 5
PC_D2 46 A11
3 A10
PC_D1 45 28
PC_D0 44 A9
26 A8
84 9 A7
83 23 A6
82 10 A5
79 11 A4
78 12 A3
5 7 A2
4 25 A1
3 8 A0
62 29 WE
* = not connected on XSP Board 24
61 OE
** = applies to XS40+ Board
65 22 CE

XS40, XSP Board V1.4 Detailed Schematic
GXSTOOLs V3.0 User Manual
XS Board utilities with a graphical user

interface

Limited Warranty

state.

GXSTOOLS Components
The GXSTOOLs package contains these utilities:
GXSTEST: This utility lets the user test an XS Board for proper functioning.
GXSSETCLK: this utility lets the user set the clock frequency of the programmable
oscillator on an XS Board.
GXSLOAD.EXE: This utility lets the user download FPGA and CPLD configuration files
and HEX files to an XS Board.
GXSPORT.EXE: This utility lets the user send logic inputs to an XS Board by toggling the
data pins of the PC parallel port.
Instructions for using these utilities are presented in the following sections.
GXSTEST
You start GXSTEST by clicking on the icon placed on the desktop during the
GXSTOOLs installation. This brings up the screen shown below.
Your next step is to select the parallel port that your XS Board is connected to from the
port pulldown list. GXSTEST starts with parallel port LPT1 as the default, but you can also
select LPT2 or LPT3 depending upon the configuration of your PC.
After selecting the parallel port, you select the type of XS Board you are testing from the
associated pulldown list. Then click on the TEST button to start the testing procedure.
GXSTEST will program the microcontroller and the FPGA or CPLD to perform a test
procedure. Status messages will be printed at the bottom of the GXSTEST window as the
testing proceeds. At the end of the test, you will receive a message informing you whether
your XS Board passed the test or not.
GXSTOOLS 3.0 USER MANUAL 1

GXSSETCLK
You start GXSSETCLK by clicking on the icon placed on the desktop during
the GXSTOOLs installation. This brings up the screen shown below.
port pulldown list. GXSSETCLK starts with parallel port LPT1 as the default, but you can
also select LPT2 or LPT3 depending upon the configuration of your PC. After selecting
the parallel port, you select from the pulldown list the type of XS Board you have
connected to the PC parallel port.
Next you must enter a divisor between 1 and 2052 into the text box. Once programmed,
the oscillator will output a clock signal generated by dividing its 100 MHz master frequency
by the divisor. The divisor is stored in non-volatile storage in the oscillator chip so you only
need to use GXSSETCLK when you want to change the frequency.
An external clock signal can be substituted for the internal master frequency of the
programmable oscillator. Checking the external clock checkbox will enable this feature in
the programmable oscillator chip. Of course, you are then responsible for providing the
external clock to the XS Board.
Clicking on the SET button will start the oscillator programming procedure. Status
messages will be printed at the bottom of the GXSSETCLK window as the programming
proceeds. You will also receive instructions on how to set the shunts on the XS Board
jumpers to place the oscillator into its programming mode. At the end of the programming,
you will receive a message informing you that your XS Board clock has been set.
GXSLOAD
You start GXSLOAD by clicking on the icon placed on the desktop during the
GXSTOOLs installation. This brings up the screen shown below.

Your next step is to select the parallel port that your XS Board is connected to as shown
below. GXSLOAD starts with parallel port LPT1 as the default, but you can also select
LPT2 or LPT3 depending upon the configuration of your PC. If you are programming an
XS40 Board with an Atmel serial EEPROM, you can also check the EEPROM box to
enable the programming of the EEPROM. In most cases, however, you will leave the box
unchecked so that the FPGA or CPLD on the XS Board will be programmed.
After setting the parallel port and EEPROM flag, you can download files to the XS Board
simply by dragging them to the GXSLOAD window as shown below. Once you release
the mouse left-button and drop the files, GXSLOAD will begin sending the files to the XS
Board through the parallel port connection. If you drag & drop a non-downloadable file
(one with a suffix other than .BIT, .SVF, or .HEX), GXSLOAD will ignore it.

During the process, GXSLOAD will display the name of the file currently being
downloaded below the Recent Files window as shown below.
Once the downloading is finished, the file names are added to the Recent Files window
and the Reload button is enabled. Now you can download these files to the XS Board just
by clicking on the Reload button. This is a useful shortcut to have as you make changes
to your design in Foundation and need to test the modifications.

The Recent Files window records the name of each file you download. As shown below,
a scrollbar will appear once you have dropped more than eight files on the GXSLOAD
window. You can click your mouse on multiple file names to toggle their selections on or
off. Then clicking on the Reload button will download the highlighted files to the XS Board.
Note that the Reload button is disabled if you do not select any files to be downloaded.
This situation is shown below.

GXSPORT
Once you have loaded the XS Board with a configuration file using GXSLOAD, you can
then use GXSPORT to exercise the functions of your design. Click on the icon
to bring up the window shown below.
The window contains several controls which perform the following functions:
n The Port list box lets you select the parallel port that your XS Board is connected to
just like you did with the GXSLOAD program.
n There are eight buttons, each of which is associated with one of the eight data bits of
the parallel port. On startup, each button is labeled with the binary value currently
output on the associated data pin. When you click one of these buttons, the displayed
binary value toggles but this new value does not appear on the data pin until
you press the Strobe button (see below).
n The Strobe button transfers the bit values displayed on the data button to the data
pins of the parallel port. The Strobe button is enabled if at least one value on a data
button is different from the actual value output on its data pin. The Strobe button is
disabled if the value on each data pin matches the value on its associated button,
because then there is no need to transfer the values.

n If you check the Count box, the value output on the data pins will increment every time
you click on the Strobe button. In this case, the Strobe button will stay enabled.
n Clicking the Exit button terminates GXSPORT without updating the data pins with any
new values that may have been entered.

MSM80C154S
MSM83C154S
MSM85C154HVS
USER'S MANUAL
 Copyright 1988, OKI ELECTRIC INDUSTRY COMPANY, LTD.
OKI makes no warranty for the use of its products and assumes no
responsibility for any errors which may appear in this document nor
does it make a commitment to update the information contained
herein.
OKI retains the right to make changes to these specifications at
any time, without notice.
CONTENTS
1. INTRODUCTION
1.1 MSM80C154S/MSM83C154S/MSM85C154HVS Outline .................................. 3
1.2 MSM80C154S/MSM83C154S Features ............................................................. 5
1.3 Additional Features in MSM80C154S/MSM83C154S/MSM85C154HVS ........... 7
2. SYSTEM CONFIGURATION
2.1 MSM80C154S/MSM83C154S/MSM85C154HVS Logic Symbols .................... 11
2.2 MSM80C154S/MSM83C154S Pin Layout ........................................................12
2.2.1 MSM80C154S/MSM83C154S external dimensions .................................. 15
2.2.2 MSM85C154HVS pin layout and external dimensions .............................. 17
2.3 MSM80C154S Block Diagram ..........................................................................18
2.4 MSM83C154S Block Diagram ..........................................................................19
2.5 MSM85C154HVS Block Diagram .....................................................................20
2.6 Timing and Control ........................................................................................... 21
2.6.1 Outline of MSM80C154S/MSM83C154S timing ........................................21
2.6.2 Major synchronizing signals ......................................................................23
(1) ALE ......................................................................................................23
(2) PSEN ...................................................................................................23
(3) WR ...................................................................................................... 23
(4) RD ....................................................................................................... 23
2.6.3 MSM80C154S fundamental operation time charts .................................... 24
(1) External program memory read cycle timing chart ...............................24
(2) MOVX A, @Rr ......................................................................................24
(3) MOVX @Rr, A ......................................................................................25
(4) MOVX A, @DPTR ................................................................................25
(5) MOVX @DPTR, A ................................................................................26
(6) MOV direct, PORT[0, 1, 2, 3] execution ...............................................26
2.6.4 MSM83C154S fundamental operation time charts .................................... 27
(1) MOVX A, @Rr ......................................................................................27
(2) MOVX @Rr, A ..................................................................................... 27
(3) MOVX A, @DPTR ................................................................................28
(4) MOVX @DPTR, A ................................................................................28
(5) MOV direct, PORT[0, 1, 2, 3] execution ...............................................29
2.7 Instruction Register (IR) and Instruction Decoder (PLA) .................................. 30
2.8 Arithmetic Operation Section ............................................................................31
(1) Outline ..................................................................................................31
(2) Arithmetic operation instruction decoder .............................................. 31
(3) Arithmetic and logic unit (ALU) ............................................................. 31
2.9 Program Counter ..............................................................................................32
2.10 Program Memory and External Data Memory .................................................. 33
2.10.1 MSM80C154S/MSM83C154S program area and
external ROM connections ........................................................................33
2.10.2 Procedures and circuit connections used when external
data memory (RAM) is accessed by data pointer (DPTR) ........................35
2.10.3 Procedures and circuit connections used when external
data memory (RAM) is accessed by registers R0 and R1 ......................... 38
3. CONTROL
3.1 Oscillators [XTAL1 .2] .......................................................................................43
3.2 CPU Resetting ..................................................................................................45
3.2.1 Outline .......................................................................................................45
3.2.2 Reset Schmitt trigger circuit .......................................................................50
3.2.3 CPU internal status by reset ......................................................................51
3.3 EA(CPU Memory Separate) ..............................................................................52
3.3.1 Outline .......................................................................................................52
(1) Internal ROM mode ..............................................................................52
(2) External ROM mode ............................................................................. 52
4. INTERNAL SPECIFICATIONS
4.1 Internal Data Memory (RAM) and Special Function Registers ......................... 55
4.1.1 Outline ..........................................................................................................55
4.2 Internal Data Memory (RAM) ............................................................................57
4.2.1 Internal data memory (RAM) .....................................................................57
4.2.2 Internal data memory registers R0 thru R7 ...............................................59
4.2.3 Stack ..........................................................................................................60
4.3 Internal Data Memory (RAM) Operating Procedures ........................................61
4.3.1 Internal data memory indirect addressing .................................................61
4.3.2 Internal data memory register R0 thru R7 designation .............................. 62
4.3.3 Internal data memory 1-bit data designation ............................................. 63
4.4 Special Function Registers(TCON, SCON,...ACC, B) ...................................... 65
4.4.1 Outline .......................................................................................................65
4.4.2 Special function registers ..........................................................................67
4.4.2.1 Timer mode register (TMOD) ................................................................ 67
4.4.2.2 Power control register (PCON) ..............................................................68
4.4.2.3 Timer control register (TCON) ...............................................................69
4.4.2.4 Serial port control register (SCON) ........................................................70
4.4.2.5 Interrupt enable register (IE) .................................................................. 71
4.4.2.6 Interrupt priority register (IP) .................................................................. 72
4.4.2.7 Program status word register (PSW) .....................................................73
4.4.2.8 I/O control register (IOCON) .................................................................. 74
4.4.2.9 Timer 2 control register (T2CON) ..........................................................75
4.5 Timer/Counters 0, 1, and 2 ...............................................................................76
4.5.1 Outline .......................................................................................................76
4.5.2 Timer/counters 0 and 1 ..............................................................................76
4.5.2.1 Outline ...................................................................................................76
4.5.2.2 Timer/counter 0 and 1 counting control .................................................76
4.5.2.3 Timer/counter 0 and 1 count clock designation ..................................... 78
4.5.2.3.1 External clock detector circuit for timer/counters 0 and 1 ............... 79
4.5.2.4 Counting control of timer/counters 0 and 1 by INT pin ..........................80
4.5.2.5 Timer/counters 0/1 timer modes ............................................................82
4.5.2.5.1 Outline ............................................................................................82
4.5.2.5.2 Mode 0 ............................................................................................82
4.5.2.5.3 Mode 1 ............................................................................................84
4.5.2.5.4 Mode 2 ............................................................................................86
4.5.2.5.5 Mode 3 ............................................................................................88
4.5.2.5.6 32-bit timer mode ............................................................................89
4.5.2.5.7 Caution about use of timer counters 0 and 1 .................................. 90
4.5.2.5.8 Caution about use of timer counters 0 and 1 when setting software
power down mode........................................................................... 91
4.5.3 Timer/counter 2 .........................................................................................92
4.5.3.1 Outline ...................................................................................................92
4.5.3.2 Timer 2 control register (T2CON) ..........................................................92
4.5.3.3 Timer/counter 2 operation modes ..........................................................93
4.5.3.3.1 16-bit auto reload mode .................................................................. 93
4.5.3.3.2 16-bit capture mode ........................................................................94
4.5.3.3.3 16-bit baud rate generator mode .................................................... 95
4.5.3.4 Timer/counter 2 detector circuit ............................................................. 97
4.5.3.4.1 T2(timer/counter 2 external clock detector) .................................... 97
4.5.3.4.2 T2EX(timer/counter 2 external flag input detector) ......................... 97
4.5.3.5 Timer/counter carry signal detector circuit ............................................. 98
4.6 Serial Port .........................................................................................................99
4.6.1 Outline .......................................................................................................99
4.6.2 Special function registers for serial port .................................................. 101
4.6.2.1 SCON ..................................................................................................101
4.6.2.2 SBUF ...................................................................................................103
4.6.2.3 TCLK ...................................................................................................103
4.6.2.4 RCLK ...................................................................................................103
4.6.2.5 SMOD ..................................................................................................104
4.6.2.6 SERR ..................................................................................................105
4.6.3 Operating modes .....................................................................................106
4.6.3.1 Mode 0 .................................................................................................106
4.6.3.1.1 Outline........................................................................................... 106
4.6.3.1.2 Mode 0 baud rate ..........................................................................106
4.6.3.1.3 Mode 0 transmit operation ............................................................106
4.6.3.1.4 Mode 0 receive operation ............................................................. 106
4.6.3.2 Mode 1 ..................................................................................................110
4.6.3.2.1 Outline........................................................................................... 110
4.6.3.2.2 Mode 1 baud rate ..........................................................................110
4.6.3.2.5 Mode 1 UART error detection ....................................................... 112
4.6.3.3 Mode 2 .................................................................................................115
4.6.3.3.1 Outline........................................................................................... 115
4.6.3.3.2 Mode 2 baud rate ..........................................................................115
4.6.3.4 Mode 3 .................................................................................................119
4.6.3.4.1 Outline........................................................................................... 119
4.6.3.4.2 Mode 3 baud rate ..........................................................................119
4.6.3.4.4 Mode 3 receive operation. ............................................................120
4.6.4 Serial port application examples ..............................................................124
4.6.4.1 I/O extension .......................................................................................124
4.6.4.2 Multi-processor systems ......................................................................128
4.7 Interrupt .............................................................................................................129
4.7.1 Outline .....................................................................................................129
4.7.2 Interrupt enable register (IE) .................................................................... 131
4.7.3 Interrupt priority register (IP) .................................................................... 132
4.7.3.1 Priority interrupt routine flow ................................................................ 133
4.7.3.2 Interrupt routine flow when priority circuit is stopped ........................... 134
4.7.3.3 Interrupt priority when priority register (IP) contents are all “0” ........... 135
4.7.4 Detection of external interrupt signals INT0 and INT1 ............................. 136
4.7.4.1 Outline of INT signal detection............................................................. 136
4.7.4.2 External interrupt signal 0 and 1 level detection .................................. 136
4.7.4.3 External interrupt signal 0 and 1 trigger detection ...............................137
4.7.5 MSM80C154S/MSM83C154S interrupt response time charts ................ 138
4.7.5.1 Interrupt response time chart when interrupt conditions are satisfied
during execution of ordinary instruction in main routine ...................... 138
4.7.5.2 Interrupt response time chart when interrupt conditions are satisfied
during execution of IE or IP register operation instruction in main
routine ..................................................................................................140
4.7.5.3 Interrupt response time chart when an ordinary instruction is
executed after temporarily returning to the main routine from
continuous interrupt processing ........................................................... 142
4.7.5.4 Interrupt response time chart when an IE or IP manipulating
instruction is executed after temporarily returning to the main
routine from continuous interrupt processing ...................................... 144
4.8 CPU “Power Down” ........................................................................................146
4.8.1 Outline .....................................................................................................146
4.8.2 Idle mode (IDLE) setting ..........................................................................146
4.8.3 Soft power down mode (PD) setting ........................................................151
4.8.3.1 Caution about software power down mode setting ............................. 151
4.8.4 Hard power down mode (HPD) setting .................................................... 161
4.9 CPU Power Down Mode (IDLE, PD, and HPD) Cancellation (CPU Activation) 169
4.9.1 Outline .....................................................................................................169
4.9.2 Cancellation by CPU resetting (RESET pin) ........................................... 169
4.9.3 Cancellation of CPU power down mode(IDLE, PD)by interrupt signal .... 176
4.9.3.1 Cancellation of CPU power down mode (IDLE, PD) from interrupt
address ................................................................................................176
4.9.3.2 Cancellation of CPU power down mode (IDLE, PD) by interrupt
request signal and restart from next address of stop address ............. 182
4.10 MSM80C154S/83C154S Battery Backup with Hard Power Down Mode ....... 187
5. INPUT/OUTPUT PORTS
5.1 Outline ............................................................................................................192
5.2 Port 0 ..............................................................................................................192
5.3 Port 1 ..............................................................................................................195
5.4 Port 2 ..............................................................................................................201
5.5 Port 3 ..............................................................................................................203
5.6 Port 0, 1, 2, and 3 Output and Floating Status Settings in CPU Power Down
Mode (PD, HPD) .............................................................................................205
5.7 High Impedance Input Port Setting of Each Quasi-bidirectional
Port 1, 2, and 3 ...............................................................................................207
5.8 100 kW Pull-Up Resistance Setting for Quasi-bidirectional Input
Ports 1, 2, and 3 .............................................................................................207
5.9 Precautions When Driving External Transistors by Quasi-bidirectional
Port Output Signals .........................................................................................208
5.10 Port Output Timing ..........................................................................................210
1) One machine cycle instruction output timing .............................................. 210
2) Two machine cycle instruction output timing .............................................. 211
5.11 Port Data Manipulating Instructions ................................................................ 212
6. ELECTRICAL CHARACTERISTICS
6.1 Absolute Maximum Ratings ............................................................................216
6.2 Operational Ranges. .......................................................................................216
6.3 DC Characteristics ..........................................................................................217
6.4 External Program Memory Access AC Characteristics .................................. 221
6.5 External Data Memory Access AC Characteristics ......................................... 223
6.6 Serial Port (I/O Extension Mode) AC Characteristics ..................................... 225
6.7 AC Characteristics Measuring Conditions ......................................................227
6.8 XTAL1 External Clock Input Waveform Conditions ........................................228
7. DESCRIPTION OF INSTRUCTIONS
7.1 Outline ............................................................................................................231
7.2 Description of Instruction Symbols .................................................................232
7.3 List of Instructions. ..........................................................................................233
7.4 Simplified Description of Instructions ..............................................................234
7.5 Detailed Description of MSM80C154S/MSM83C154S Instructions ............... 246
1. INTRODUCTION
MSM80C154S/83C154S/85C154HVS
2
INTRODUCTION
1. INTRODUCTION
1.1 MSM80C154S/MSM83C154S/MSM85C154HVS Outline
MSM80C154S/MSM83C154S/MSM85C154HVS are single-chip 8-bit fully static microcon-

trollers featuring high performance and low power consumption. All MSM80C31F /MSM80C51F
instructions and functions have been retained.
Apart from being without the internal program memory (ROM), MSM80C154S is identical to
MSM83C154S. And the difference between MSM85C154HVS and MSM83C154S is that the
internal program memory (ROM) in MSM83C154S is replaced by an external ROM
connected to MSM85C154HVS by using a piggy-back package.
While the MSM83C154S microcontroller integrates a 16384-word × 8-bit program memory
(ROM) in a single chip, MSM80C154S/MSM83C154S/MSM85C154HVS all feature comput-
er functions including a 256-word × 8-bit data memory (RAM), 32 input/ output ports, three
16-bit timer/counters, six interrupts, serial I/O, an 8-bit parallel processing circuit, and a clock
generator.
The internal operation in these CPUs is based on an instruction code address method for
greater efficiency. In this method, operations are specified in the instruction code (OP)
section, and the objective registers are specified by part of that instruction code and the
second or third byte following the code. A feature of this method is the ability to achieve
several operations by simply changing the manipulation register designation in a single
instruction code.
Inclusion of 8-bit multiplication and division instructions further increases the processing
capacity of these CPUs.
In addition to expansion of the bit processing area, a comprehensive range of bit processing
instructions has also been included. Processing operations include logical processing of the
carry flag and specified bit within each register, transfer between the carry flag and specified
bit in certain registers, transfer of specified bits between different registers, setting, resetting,
and complement of the specified bit in each register, and execution of various bit tests within
a wide area.
To make a relative jump after the execution of a bit test instruction, jumps can be made within
a wide address range between –128 and +127 relative to the address of the instruction and
there is no page field restriction.
The contents of specified registers can be saved in stack by using the PUSH instruction, and
the saved contents can be returned from stack to a specified register by the POP instruction.
Absolute interrupt priority can be allocated to any interrupt when in priority circuit operation
mode. And by controlling only the interrupt enable register (IE) when in priority circuit stop
mode, multi-level interrupt processing can be executed to make interrupt processing much
easier than in conventional CPUs.
Employing the low-power consumption feature of C-MOS devices, these CPUs are designed
to operate in a number of “CPU power down” modes. In idle mode the IDL bit in the power
control register (PCON) is set to “1” to halt CPU operations while the oscillator continues to
run. In soft power down mode the PD bit in the power control register is set to “1” to halt CPU
operations as well as the oscillator. And in hard power down mode where the HPD bit in the
power control register is set in advance to “1”, CPU operations and the oscillator are stopped
if the HPDI pin (P3.5) power failure detect signal level is changed from “1” to “0”. CPU power
down modes can be cancelled by resetting the CPU via reset pin and restarting execution
from address 0, by restarting execution from the relevant interrupt address, or by resuming
3
MSM80C154S/83C154S/85C154HVS
execution from the next address after the stop address where CPU power down mode was
activated.
Each of the quasi-bidirectional ports 1, 2, and 3 can be set independently as high impedance
input ports. And the 10 kW pull-up resistance for these input ports can be isolated from the
power supply (VCC), leaving only the 100 kW pull-up resistance and thereby enabling the
quasi-bidirectional ports to be driven by devices with low drive capacity. Furthermore, the
outputs of ports, 0, 1, 2, and 3 can be switched to floating status during CPU power down
modes (PD, HPD).
Three built-in 16-bit timer/counters capable of operating in a wide range of modes enable the
CPUs to be used in many different ways. And since timer/counters 0 and 1 can be operated
by external clock during CPU power down modes (PD, HPD) where the oscillator is stopped,
these two counters can also be used in cancelling CPU power down modes.
UART based serial communication can be executed at any baud rate by carry signal from
timer/counter 1 or timer/counter 2.
If an overrun or framing error is generated during data reception, the SERR bit in the I/O
control register is set. And by testing this SERR bit, the accuracy of the data can be checked
quite easily to ensure correct serial communication.
As can be seen, these CPUs are equipped with a very comprehensive range of functions. Also
note that EASE80C51mkII is available for use as the program development support system
for these CPUs.
Equipped with the MSM85C154E dedicated evachip, EASE80C51mkII is capable of pro-
gram area mapping, realtime tracing, generating breaks according to accumulator contents,
and various other functions designed for accurate and efficient support of program develop-
ment of these CPUs.
With this great line-up of functions and with EASE80C51mkII capable of developing
programs in a very short time, MSM80C154S/MSM83C154S/MSM85C154HVS give a highly
integrated high performance solution.
4
INTRODUCTION
1.2 MSM80C154S/MSM83C154S Features
• Full static circuitry

• Internal program memory (ROM)
16384 words × 8 bits (MSM83C154S)
• External program memory (ROM)
Connectable up to 64K bytes
• Internal data memory (RAM)
256 words × 8 bits
• External data memory (RAM)
Connectable up to 64K bytes
• Four sets of working registers (R0 thru R7 × 4)
• Stack
Free use of 256-word × 8-bit internal data memory area
• Four input/output ports (8-bit × 4)
• Serial ports (UART operation)
• Six types of interrupts
(1) Two external interrupts
(2) Three timer interrupts
(3) One serial port interrupt
* Priority allocated interrupt processing
* Multi-level interrupt processing by software management
• CPU power down function
(1) Idle mode: CPU stopped while oscillation continued.
(Software setting)
(2) PD mode: CPU and oscillation all stopped.
(Software setting)
(Setting I/O ports to floating status possible)
(3) HPD mode: CPU and oscillation all stopped.
(Hardware setting)
(Setting I/O ports to floating status possible)
• CPU power down mode cancellation
(1) Execution commenced from address 0 by CPU resetting.
(IDLE, PD, and HPD mode cancellation)
* RESET pin is used
(2) Execution from interrupt address by interrupt request, or execution resumed from next
address after the stop address. (IDLE and PD mode cancellation)
* External, timer, and serial port interrupts
• I/O control registers (0F8H)
b0: Port 0, 1, 2, and 3 floating setting (PD, HPD)
b1: Port 1 high impedance input port setting
b4: Port 1, 2, and 3 pull-up resistance switching (10 kW pull-up resistance switch off to
leave only 100 kW)
b5: Serial port reception error detector bit
b6: 32-bit timer mode setting (TL0+TH0+TL1+TH1)
5
MSM80C154S/83C154S/85C154HVS
• Timer/counters (three 16-bit timer/counters)

(1) 8-bit timer with 5-bit prescalar
(2) 16-bit timer
(3) 8-bit timer with 8-bit auto-reloader
(4) 8-bit separate timer
(5) 16-bit timer with 16-bit auto-reloader
(6) 16-bit capture timer
(7) 16-bit baud rate generator timer
(8) 32-bit timer
• Wide operating temperature range –40 to +85°C
• Wide operating voltage range
(1) When operating: VCC=+2.2 to 6V (varies according to frequency)
(2) When stopped:
VCC=+2 to +6V (PD or HPD mode)
• Instruction execution cycle
(1) 2-byte 1-machine cycle instructions
(2) Multiplication/division instructions
• Direct initialization of ports 0, 1, 2, and 3 by input of reset signal even if oscillator have been
stopped.
(All ports output “1”.)
• High noise margin (with Schmitt trigger input for each I/O)
• 40-pin plastic DIP/44-pin plastic flat package/44-pin plastic PLCC/44/pin plastic TQFP
• Software compatibility with MSM80C31F and MSM80C51F
6
INTRODUCTION
1.3 Additional Features in MSM80C154S/MSM83C154S/MSM85C154HVS
In addition to the basic operations of MSM80C31F/MSM80C51F, the MSM80C154S/

MSM83C154S/MSM85C154HVS devices also include the following functions.
• ROM capacity increased from 4K bytes to 16K bytes
• RAM capacity increased from 128 bytes to 256 bytes
• An additional timer counter 2
• An additional timer interrupt 2
• An additional 8-bit timer 2 control register (T2CON 0C8H)
• An additional 8-bit I/O control register (IOCON 0F8H)
• Addition of two bits (bit 5, PT2 and bit 7, PCT) to the priority register (IP 0B8H)
• Addition of one bit (bit 5, ET2) to the interrupt enable register (IE 0A8H)
• Addition of two bits (bit 5, RPD and bit 6, HPD) to the power control register (PCON 87H)
Addition of these extra functions has further increased the performance and widen the range
of application of these CPU devices.
7
MSM80C154S/83C154S/85C154HVS
8
2. SYSTEM
CONFIGURATION
MSM80C154S/83C154S/85C154HVS
10
SYSTEM CONFIGURATION
2. SYSTEM CONFIGURATION
2.1 MSM80C154S/MSM83C154S/MSM85C154HVS Logic Symbols
XTAL1 P0.0
P0.1
P0.2
P0.3 PORT 0
XTAL2 P0.4 (BUS PORT)
P0.5
P0.6
P0.7
RESET RESET
P1.0 T2
P1.1 T2EX
P1.2
P1.3
PORT 1
P1.4
ADDRESS LATCH ALE P1.5
ENABLE P1.6
PROGRAM STORE PSEN P1.7
ENABLE
P2.0
P2.1
CPU MEMORY EA P2.2
SEPARATE P2.3
PORT 2
P2.4
P2.5
+5(V) VCC P2.6
P2.7
P3.0 RXD
0(V) VSS P3.1 TXD
P3.2 INT0
P3.3 INT1
PORT 3
P3.4 T0
P3.5 T1/HPDI
P3.6 WR
P3.7 RD
Figure 2-1 MSM80C154S/83C154S/85C154HVS logic symbols
11
MSM80C154S/83C154S/85C154HVS
2.2 MSM80C154S/MSM83C154S pin layouts
MSM80C154SRS/MSM83C154SRS
(Top View) 40 Pin Plastic DIP
P1.0/T2 1 40 VCC
P1.1/T2EX 2 39 P0.0
P1.2 3 38 P0.1
P1.3 4 37 P0.2
P1.4 5 36 P0.3
P1.5 6 35 P0.4
P1.6 7 34 P0.5
P1.7 8 33 P0.6
RESET 9 32 P0.7
P3.0/RXD 10 31 EA
P3.1/TXD 11 30 ALE
P3.2/INT0 12 29 PSEN
P3.3/INT1 13 28 P2.7
P3.4/T0 14 27 P2.6
P3.5/T1/HPDI 15 26 P2.5
P3.6/WR 16 25 P2.4
P3.7/RD 17 24 P2.3
XTAL2 18 23 P2.2
XTAL1 19 22 P2.1
VSS 20 21 P2.0
MSM80C154SGS/MSM83C154SGS
(Top View) 44 Pin Plastic Package
P1.1/T2EX
P1.0/T2
O0.1
P1.4
P1.3
P1.2
P0.0
P0.2
P0.3
VCC
NC
44 43 42 41 40 39 38 37 36 35 34
P1.5 1 33 P0.4
P1.6 2 32 P0.5
P1.7 3 31 P0.6
MSM83C154SGS
MSM80C154SGS/
RESET 4 30 P0.7
P3.0/RXD 5 29 EA
NC 6 28 NC
P3.1/TXD 7 27 ALE
P3.2/INT0 8 26 PSEN
P3.3/INT1 9 25 P2.7
P3.4/T0 10 24 P2.6
P3.5/T1/HPDI 11 23 P2.5
12 13 14 15 16 17 18 19 20 21 22
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
VSS
P2.0
P2.1
P2.2
P2.3
P2.4
12
MSM80C154SJS/MSM83C154SJS
(Top View) 44 Pin Plastic QFJ
P1.1/T2EX
P1.0/T2
P1.4
P1.3
P1.2
P0.0
P0.1
P0.2
P0.3
VCC
NC
6 5 4 3 2 1 44 43 42 41 40
P1.5 7 39 P0.4
P1.6 8 38 P0.5
P1.7 9 37 P0.6
RESET 10 36 P0.7
P3.0/RXD 11 35 EA
NC 12 34 NC
P3.1/TXD 13 33 ALE
P3.3/INT1 15 31 P2.7
P3.4/T0 16 30 P2.6
P3.5/T1/HPDI 17 29 P2.5
18 19 20 21 22 23 24 25 26 27 28
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
NC
P2.0
P2.1
P2.2
P2.3
P2.4
MSM80C154STS/MSM83C154STS
(Top View) 44 Pin Plastic Package
P1.1/T2EX
P1.0/T2
O0.1
P1.4
P1.3
P1.2
P0.0
P0.2
P0.3
VCC
NC
44 43 42 41 40 39 38 37 36 35 34
P1.5 1 33 P0.4
P1.6 2 32 P0.5
P1.7 3 31 P0.6
MSM83C154STS
MSM80C154STS/
RESET 4 30 P0.7
P3.0/RXD 5 29 EA
NC 6 28 NC
P3.1/TXD 7 27 ALE
P3.2/INT0 8 26 PSEN
P3.3/INT1 9 25 P2.7
P3.4/T0 10 24 P2.6
P3.5/T1/HPDI 11 23 P2.5
12 13 14 15 16 17 18 19 20 21 22
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
VSS
P2.0
P2.1
P2.2
P2.3
P2.4
Figure 2-2 MSM80C154S/MSM83C154S pin layout (top view)
13
MSM80C154S/83C154S/85C154HVS
Applicable Packages
MSM80C154S RS
40-Pin Plastic DIP (DIP40-P-600-2.54)
MSM83C154S-XXX RS
MSM80C154S JS
44-Pin Plastic QFJ (QFJ44-P-S650-1.27)
MSM83C154S-XXX JS
MSM80C154S GS-2K
44-Pin Plastic QFP (DFP44-P-910-0.80-2K)
MSM83C154S-XXX GS-2K
MSM80C154S TS-K
44-Pin Plastic TQFP (TQFP44-P-1010-0.80-K)
MSM83C154S-XXX TS-K
40-Pin Ceramic Piggy Back (ADIP40-C-600-2.54) MSM85C154HVS
14
2.2.1 MSM80C154S/MSM83C154S external dimensions
40-pin Plastic DIP (DIP40-P-600-2.54)
MSM80C154SGS/MSM83C154SGS
44-Pin Plastic QFP (QFP44-P-910-0.80-2K)
44-Pin Plastic QFJ (QFJ44-P-S650-1.27)
Figure 2-3 MSM80C154S/MSM83C154S external dimensions
15
MSM80C154S/83C154S/85C154HVS
MSM80C154STS/MSM83C154STS
44-Pin Plastic TQFP (TQFP44-P-1010-0.80-K)
16
2.2.2 MSM85C154HVS pin layout and external dimensions
M85C154H
2764/27128 OKI
JAPAN XXXX
Pin 1 for 2764, 27128
* The MSM85C154HVS pin layout of bottom side is the same as the pin layout for
MSM83C154SRS.
* The 27C64/128 device should be used for EPROM.
40-Pin Ceramic Piggy Back (ADIP40-C-600-2.54)
Figure 2-4 MSM85C154HVS pin layout and external dimensions
17
2.3 MSM80C154S Block Diagram
MSM80C154S/83C154S/85C154HVS
P2.0
PORT 2
P2.7 CONTROL SIGNAL R/W SIGNAL
DPH
P0.0 SPECIAL
PORT 0
FUNCTION
DPL PLA REGISTER
Figure 2-5 MSM80C154S block diagram
P0.7 ADDRESS
DECODER
XTAL1
OSC AND TIMING
PCON
PCHL PCLL
XTAL2 SP
ALE IR AIR
PCH PCL
PSEN
IOCON
C-ROM
18
EA
RESET
T2CON TL2 TH2 R/W AMP ACC TR2 TR1
TIMER/
P1.0 COUNTER 2
PORT 1
RCAP RCAP 256WORD RAMDP

2L 2H ×8bit PSW BR
P1.7 ALU
P3.0
PORT 3
TH1 TL1 TH0 TL0 TMOD TCON IE IP SBUF SBUF SCON

(T) (R)
P3.7 TIMER/COUNTER 0&1 INTERRUPT
SERIAL IO
2.4 MSM83C154S Block Diagram
P2.0
PORT 2
DPH
P0.0 SPECIAL
PORT 0
ROM FUNCTION
16KWORD DPL PLA REGISTER
Figure 2-6 MSM83C154S block diagram
P0.7 ×8bit ADDRESS

DECODER
XTAL1
OSC AND TIMING
PCON
PCHL PCLL
XTAL2 SENSE AMP SP
ALE IR AIR
PCH PCL
PSEN
IOCON
C-ROM
19
EA
RESET
TIMER/
P1.0 COUNTER 2
PORT 1

2L 2H ×8bit PSW BR
ALU
P1.7
P3.0
PORT 3

(T) (R)
SERIAL IO
2.5 MSM85C154HVS Block Diagram
MSM80C154S/83C154S/85C154HVS
P2.0
PORT 2
SOCKET
DPH
A0
P0.0 EXTERNAL SPECIAL
PORT 0
ROM FUNCTION
Figure 2-7 MSM85C154HVS block diagram
DPL PLA REGISTER

P0.7 A13
ADDRESS
16KWORD DECODER
XTAL1 ×8bit
OSC AND TIMING
PCON
PCHL PCLL
XTAL2 D0 ... D7 SP
ALE IR AIR
PCH PCL
PSEN
IOCON
C-ROM
20
EA
RESET
TIMER/
P1.0 COUNTER 2
PORT 1

2L 2H ×8bit PSW BR
P1.7 ALU
P3.0
PORT 3

(T) (R)
SERIAL IO
2.6 Timing and Control
2.6.1 Outline of MSM80C154S/MSM83C154S timing
The MSM80C154S/MSM83C154S devices are both equipped with a built-in oscillation

inverter (see Figure 2-8) for use in the generation of clock pulses by external crystal or ceramic
resonator. These clock pulses are passed to the timing counter and control circuits where the
basic timing and control signals required for internal control purposes are generated.
The basic timing consists of state 1 (S1) thru state 6 (S6) (see Figure 2-9) where each state
cycle is based on two XTAL1·2 fundamental clock pulses. The interval from S1 thru S6 forms
a single machine cycle with a total of 12 fundamental clock pulses. 1-byte 1-machine cycle
and 2-byte 1-machine cycle instructions are fetched into the instruction register during
M1·S1, decoded during M1·S2, and executed during M1·S3 thru M1·S6. The second byte is
fetched during M1·S4. 1-byte 2-machine cycle, 2-byte 2-machine cycle, and 3-byte 2-
machine cycle instructions are also fetched during M1·S1, decoded during M1·S2, and
executed during M1·S3 thru M2·S6. The second and third bytes are fetched during M1·S4,
M2·S1, or M2·S4. The number of clocks used is 24. 1-byte 4-machine cycle instructions are
involved in multiplication and division operations where 48 clocks are used.
S1 S2 S3 S4 S5 S6
DQ DQ DQ DQ DQ DQ
S I/O
S I/O & TIMER CONTROL
TIMER & INTERRUPT
XTAL2
XTAL1 CPU
CPU CONTROL
PLA
1/2 POWER DOWN
1/2 IDLE
RESET
INT PLA OUT
Figure 2-8 Oscillator, timing counter, and control stage block diagram
21
CYCLE M1 M1 M2 M1
STEP S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
RD/WR
0
DPL & Rr
1
PORT–0 PCL PCL PCL ACC & RAM PCL PCL PCL
0
MSM80C154S/83C154S/85C154HVS
1
PORT–2 PCH PCH PCH PCH DPH & PORT DATA PCH PCH PCH
0
DATA STABLE DATA STABLE
1
CPU←PORT
22
0
1
PORT←CPU PORT OLD DATA PORT NEW DATA
0
Instruction decoding Instruction decoding Instruction decoding

Instruction excecution Instruction excecution Instruction excecution
PC+1 PC+1 PC+1 PC+1 PC+1
TM+1 TM+1 TM+1 TM+1
Figure 2-9 MSM80C154S/MSM83C154S fundamental timing

2.6.2 Major synchronizing signals
(1) ALE (Address Latch Enable)

The ALE signal is used as a clock signal where the address signals 0 thru 7 output from
CPU port 0 can be latched externally when external program or external data memory
(RAM) is used.
Although two ALE signal outputs are obtained in a single machine cycle during normal
operations, no output is obtained during output of the RD/WR signal when an external
memory instruction (MOVX...... ) is executed.
(2) PSEN (Program Store Enable)

The PSEN output signal is generated during execution of an external program. The
output is obtained when an instruction or data is fetched.
The PSEN signal is valid when at “0” level, and external program data is enabled when
in this valid state.
Although two PSEN signal outputs are obtained in a single machine cycle during
normal operations, no output is obtained during output of the RD/WR signal when an
external data memory instruction (MOVX...... ) is executed.
(3) WR (Write Strobe)

The WR output signal is obtained when an external data memory instruction (MOVX
@Rr, A or MOVX @ DPTR, A) is executed.
CPU port 0 output data is written in the external RAM when the WR signal is at “0” level.
(4) RD (Read Strobe)

The RD output signal is obtained when an external data memory instruction (MOVX
A, @ Rr or MOVX A, @ DPTR) is executed.
The external RAM is enabled and output data is passed to CPU port 0 when the RD
signal is at “0” level.
23
MSM80C154S/83C154S/85C154HVS
2.6.3 MSM80C154S fundamental operation time charts

(1) External program memory read cycle timing chart
M1 M1 or M2
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1
1
XTAL1
0
1
ALE
0
1
PSEN
0
INST IN INST IN INST IN INST IN INST IN
1 PCL PCL PCL PCL
PORT–0
0 OUT OUT OUT OUT
1
PORT–2 PCH OUT PCH OUT PCH OUT PCH OUT PCH OUT
0
Figure 2-10 MSM80C154S external program memory read cycle timing chart
(2) MOVX A, @Rr

M1 M2
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
RD
0
INST IN RAM DATA IN INST IN
1 PCL Rr EXT RAM PCL
PORT–0
0 OUT OUT DATA OUT
1
PORT–2 PCH OUT PCH OUT PORT 2 LATCH DATA OUT PCH OUT
0
Figure 2-11 MSM80C154S MOVX A, @Rr execution
24
(3) MOVX @Rr, A
M1 M2
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
WR
0
INST IN INST IN
1 PCL Rr PCL
PORT–0 ACC DATA OUT
0 OUT OUT OUT
1
PORT–2 PCH OUT PCH OUT PORT 2 LATCH DATA OUT PCH OUT
0
Figure 2-12 MSM80C154S MOVX @Rr, A execution
(4) MOVX A, @DPTR

M1 M2
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
RD
0
INST IN RAM DATA IN INST IN
1 PCL DPL EXT RAM PCL
PORT–0
0 OUT OUT DATA OUT
1
PORT–2 PCH OUT PCH OUT DPH OUT PCH OUT
0
Figure 2-13 MSM80C154S MOVX A, @DPTR execution
25
MSM80C154S/83C154S/85C154HVS
(5) MOVX @DPTR, A
M1 M2
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
WR
0
INST IN INST IN
1 PCL DPL PCL
PORT–0 ACC DATA OUT
0 OUT OUT OUT
1
PORT–2 PCH OUT PCH OUT DPH OUT PCH OUT
0
Figure 2-14 MSM80C154S MOVX @DPTR, A execution
(6) MOV direct, PORT [0, 1, 2, 3] execution

M1 M2
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1
1
XTAL1
0
1
ALE
0
1
PSEN
0
PORT 0,1,2,3 1
PIN DATA 0
PIN DATA STABLE
CPU DATA 1
SAMPLED 0
Figure 2-15 MSM80C154S MOV direct, PORT[0, 1, 2, 3] execution
26
2.6.4 MSM83C154S fundamental operation time charts

(1) MOVX A, @Rr
M1 M2
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
RD
0
RAM DATA IN
1 Rr EXT RAM FLOATING
PORT–0 PORT 0 LATCH DATA
0 OUT DATA
1
PORT–2 PORT 2 LATCH DATA OUT
0
Figure 2-16 MSM83C154S MOVX A, @Rr execution
(2) MOVX @Rr, A

M1 M2
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
WR
0
1 Rr FLOATING
PORT–0 PORT 0 LATCH DATA ACC DATA OUT
0 OUT
1
PORT–2 PORT 2 LATCH DATA OUT
0
Figure 2-17 MSM83C154S MOVX @Rr, A execution
27
MSM80C154S/83C154S/85C154HVS
(3) MOVX A, @DPTR
M1 M2
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
RD
0
RAM DATA IN
1 DPL EXT RAM FLOATING
PORT–0 PORT 0 LATCH DATA
0 OUT DATA
1 PORT 2 LATCH
PORT–2 PORT 2 LATCH DATA OUT DPH OUT
0 DATA OUT
Figure 2-18 MSM83C154S MOVX A, @DPTR execution
(4) MOVX @DPTR, A

M1 M2
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
WR
0
1 DPL FLOATING
PORT–0 PORT 0 LATCH DATA ACC DATA OUT
0 OUT
1 PORT 2 LATCH
PORT–2 PORT 2 LATCH DATA OUT DPH OUT
0 DATA OUT
Figure 2-19 MSM83C154S MOVX @DPTR, A execution
28
(5) MOV direct, PORT [0, 1, 2, 3] execution
M1 M2
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1
1
XTAL1
0
1
ALE
0

1
PSEN
0
PORT 0,1,2,3 1
PIN DATA 0
PIN DATA STABLE
CPU DATA 1
SAMPLED 0
Figure 2-20 MSM83C154S MOV direct, PORT[0, 1, 2, 3] execution
29
MSM80C154S/83C154S/85C154HVS
2.7 Instruction Register (IR) and Instruction Decoder (PLA)
MSM80C154S/MSM83C154S operations are based on an instruction code address method.

Hence, in addition to the instruction code instruction register (IR) and instruction decoder
(PLA), these devices also include an instruction register (AIR) and register manipulation
decoder (PLA) for data addresses and bit addresses.
Operation codes are passed to the IR, and data and bit addresses are passed to the AIR. CPU
control signals are formed at the respective PLA for each instruction register, thereby
activating the CPU. The block diagram is outlined in Figure 2-21.
Timing
AND
Matrix Control signals
AIR
Data bus Decoder
PLA
WAIR
Timing
AND
Matrix Control signals

IR
Data bus Decoder
PLA
WIR
Figure 2-21 lR and PLA block diagram
30
2.8 Arithmetic Operation Section
(1) Outline
The MSM80C154S/MSM83C154S arithmetic operation section consists of
(1) an arithmetic operation instruction decoder, and
(2) an arithmetic and logic unit [ALU].
(2) Arithmetic operation instruction decoder:

Arithmetic operation instructions are passed to the instruction register (IR) and then to
the PLA where they are converted into control signals.
The control signals from the PLA are used to control ALU peripheral circuits and ALU
arithmetic operations (ADD, AND, OR, EOR).
(3) Arithmetic and logic unit [ALU]:

Upon reception of 8-bit data from one or two data sources the ALU processes that data
in accordance with control signals from the PLA. The ALU is capable of executing the
following processes:
• Additions and subtractions with and without carry
• Increments (+1) and decrements (–1)
• Bit complements
• Rotations (either direction with and without carry)
• BCD (decimal adjust)
• Carry, auxiliary carry, and overflow signal output
• Multiplications and divisions
• Bit detection
• Exchange of low and high order nibbles
• Logical AND, logical OR, and exclusive OR
If a bit-3 auxiliary carry (AC), a bit-7 carry (CY), or an overflow (OV) is generated as a
result of the arithmetic operation executed by the ALU, that result is set in the program
status word (PSW 0D0H).
PSW(0D0H)
CY AC F0 RS1 RS0 OV F1 P
7 6 5 4 3 2 1 0
Figure 2-22 Program status word
31
MSM80C154S/83C154S/85C154HVS
2.9 Program Counter
The MSM80C154S/MSM83C154S program counter has a 16-bit configuration PC0 thru

PC15, as shown in Figure 2-23.
ENABLE ROM
CPU INTERNAL
DATA BUS
MSM83C154S INTERNAL ROM

16KWORD × 8BIT
EXTERNAL
ROM MODE
Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
PC+1
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CPU INTERNAL DATA BUS
Figure 2-23 MSM80C154S/MSM83C154S program ounter
This program counter is a binary up-counter which is incremented by 1 each time one byte
of instruction code is fetched. When the program counter is counted by 1 after counter
contents have reached 0FFFFH, the counter is returned to 0000H. MSM83C154S is
automatically switched to external ROM mode when the counter contents exceed 3FFFH.
32
2.10 Program Memory and External Data Memory
2.10.1 MSM80C154S/MSM83C154S program area and external ROM connections
Since MSM80C154S/MSM83C154S are equipped with a 16-bit program counter, these

devices can execute programs of up to 64K bytes (including both internal and external
programs).
Since the MSM80C154S is not equipped with an internal program ROM, however, only
external instructions are executed. MSM83C154S, on the other hand, is equipped with a 16K
byte program ROM which enables it to execute internal instructions from address 0 thru
address 16383. External instructions are executed when the address is greater than 16383.
The program area is outlined in Figure 2-24, and a diagram of ROM connections made when
external instructions are executed is shown in Figure 2-25.
65535 0FFFFH
Timer interrupt 2 start address 43 002BH
MSM83C154S external ROM area
Serial I/O interrupt start address 35 0023H

MSM80C154S external ROM area
External interrupt 1 start address 19 0013H

16384 4000H
16383 3FFFH
MSM83C154S internal ROM area
44 002CH
43 002BH
External interrupt 0 start address 3 0003H
2 0002H
1 0001H
0 7 6 5 4 3 2 1 0 CPU reset start address 0 0000H
Figure 2-24 MSM80C154S/MSM83C154S program area
33
MSM80C154S/83C154S/85C154HVS
Figure 2-25 MSM80C154S/MSM83C154S external ROM connection diagram
P0.0 D0 Q0 A0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
P0.1 D1 Q1 A1
MSM74HC373
P0.2 D2 Q2 A2
P0.3 D3 Q3 A3
P0.4 D4 Q4 A4
P0.5 D5 Q5 A5
MSM80C154S/MSM83C154S
P0.6 D6 Q6 A6
P0.7 D7 Q7 A7
34
ALE LATCH
ROM
P2.0 A8 64kW × 8BIT
P2.1 A9
P2.2 A10
P2.3 A11
P2.4 A12
P2.5 A13
P2.6 A14
P2.7 A15
CS
PSEN OUTPUT ENABLE
2.10.2 Procedures and circuit connections used when external data memory (RAM)
is accessed by data pointer (DPTR)
The MSM80C154S/MSM83C154S can be connected to an external 64K word × 8-bit data

memory (RAM) when accessing the memory by data pointer (DPTR).
The data pointer (DPTR) consists of DPL and DPH registers. The DPL register contents serve
as addresses 0 thru 7 of the external data memory, and the DPH register contents serve as
addresses 8 thru 15.
The MOVX @DPTR, A instruction is used when accumulator contents are transferred to an
external data memory, and the MOVX A, @DPTR instruction is used when external data
memory contents are transferred to the accumulator. The external data memory connection
diagram is shown in Figure 2-26 and the external data memory access time chart is shown
in Figure 2-27.
When the data pointer indirect external memory instruction is executed, the CPU passes the
DPL register contents to port 0, and the port 0 contents are latched externally by ALE signal.
Data stored in the latch serves as the lower order addresses 0 thru 7 of the external data
memory (RAM), and the DPH register contents passed to port 2 serve as the higher order
addresses 8 thru 15 for addressing of the external data memory.
The WR or RD external data memory control signal is subsequently generated by the CPU
to enable transfer of data between port 0 and the external data memory.
35
MSM80C154S/83C154S/85C154HVS
Figure 2-26 Connection circuit for external data memory addressed by DPTR
I/O 0 1 2 3 4 5 6 7
P0.0 D0 Q0 A0
P0.1 D1 Q1 A1
MSM74HC373
P0.2 D2 Q2 A2
P0.3 D3 Q3 A3
P0.4 D4 Q4 A4
P0.5 D5 Q5 A5
P0.6 D6 Q6 A6
P0.7 D7 Q7 A7
36
ALE LATCH
ROM
P2.0 A8 64kW × 8BIT
P2.1 A9
P2.2 A10
P2.3 A11
P2.4 A12
P2.5 A13
P2.6 A14
P2.7 A15
WR R/W
RD CS
M1 M1 M2 M1
S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
1
XTAL1
0
1
ALE
0
1
PSEN
0
INSTRUCTION IN
1
PORT–0 PCL PCL PCL PCL DPL ACC DATA PCL PCL PCL
0
1
PORT–2 PCH PCH PCH PCH DPH PCH PCH PCH
0
1
WR
0
MOVX @DPTR, A
37
M1 M1 M2 M1
1
XTAL1
0
1
ALE
0
1
PSEN
0
INSTRUCTION IN RAM DATA IN
1
PORT–0 PCL PCL PCL PCL DPL PCL PCL PCL
0
Figure 2-27 DPTR external data memory access timing

1
PORT–2 PCH PCH PCH PCH DPH PCH PCH PCH
0
1
RD
0
MOVX A, @DPTR
MSM80C154S/83C154S/85C154HVS
2.10.3 Procedures and circuit connections used when external data memory (RAM)
is accessed by registers R0 and R1
The MSM80C154S/MSM83C154S can be connected to an external 256 word ¥ 8-bit data

memory (RAM) when addressing the memory according to the contents of registers R0 and
R1 in the internal data memory (RAM).
The MOVX @Rr, A instruction is used when accumulator contents are transferred to an
external data memory, and the MOVX A, @Rr instruction is used when external data memory
contents are transferred to the accumulator. The external data memory connection diagram
is shown in Figure 2-28 and the external data memory access time chart is shown in Figure
2-29.
When the indirect register external memory instruction is executed, the CPU passes the R0
or R1 register contents to port 0, and the port 0 contents are latched externally by the ALE
signal. Data stored in the latch serves as the addresses 0 thru 7 of the external data memory.
The WR or RD external data memory control signal is subsequently generated by the CPU
to enable transfer of data between port 0 and the external data memory.
However, if the port 2 latched data is used in addresses 8 thru 15 of the external data memory,
the circuit connections are the same as when the data pointer (DPTR) is used, thereby
enabling a 64K byte ¥ 8-bit data memory to be accessed.
38
7
6
5
256W × 8BIT
4
ROM
3
2
1 I/O 0
R/W
CS
A0
A1
A2
A3
A4
A5
A6
A7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LATCH
MSM74HC373
D0
D1
D2
D3
D4
D5
D6
D7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
ALE
WR
RD
Figure 2-28 Connection circuit for external data memory addressed by register R0 or R1
39
M1 M1 M2 M1
1
XTAL1
0
1
ALE
0
1
PSEN
0
INSTRUCTION IN
1
PORT–0 PCL PCL PCL PCL Rr ACC DATA PCL PCL PCL
0
1
PORT–2 PCH PCH PCH PCH PORT 2 LATCH DATA PCH PCH PCH
0
MSM80C154S/83C154S/85C154HVS
1
WR
0
MOVX @Rr, A
40
M1 M1 M2 M1
1
XTAL1
0
1
ALE
0
1
PSEN
0
INSTRUCTION IN RAM DATA IN
1
PORT–0 PCL PCL PCL PCL Rr PCL PCL PCL
0
1
PORT–2 PCH PCH PCH PCH PORT 2 LATCH DATA PCH PCH PCH
0
Figure 2-29 Register R0/R1 external data memory access timing

1
RD
0
MOVX A, @Rr
3. CONTROL
MSM80C154S/83C154S/85C154HVS
42
CONTROL
3. CONTROL
3.1 Oscillators: XTAL1

XTAL2
An oscillator is formed by connecting a crystal or ceramic resonator between the XTAL1 and
XTAL2 pins of the MSM80C154S/MSM83C154S devices.
If an external clock is applied to XTAL1, the input should be at 50% duty and C-MOS level.
IDLE MODE
CPU CONTROL CLOCK
PD & HPD MODE TIMER, S I/O & INTERRUPT
C XTAL1
*
XTAL 1MΩ
C XTAL2
*
* The capacity of the compensating capacitor depends on the crystal resonator.

* The XTAL1·2 frequency depends on VCC.
Figure 3-1 Crystal resonator connection diagram
43
MSM80C154S/83C154S/85C154HVS
IDLE MODE
CPU CONTROL CLOCK
C XTAL1
*
C 1MΩ
XTAL2
*
* The capacity of the compensating capacitor depends on the ceramic resonator.

* The XTAL1·2 frequency depends on VCC.
Figure 3-2 Ceramic resonator connection diagram
IDLE MODE
CPU CONTROL CLOCK
XTAL1
74HC04 1MΩ
XTAL2
*CLOCK
* Supply of 50% duty clock
Figure 3-3 External clock supply circuit
44
CONTROL
3.2 CPU Resetting
3.2.1 Outline
If a reset signal (kept at “1” level for at least 1µsec) is applied to the RESET pin when the
correct voltage (in respect to the various specifications) is applied to the MSM80C154S/
MSM83C154S VCC pin, a reset signal is stored in the CPU even if the XTAL1·2 oscillators
have been stopped.
The internally stored reset signal is used in direct initialization (setting to “1”) of ports 0, 1, 2,
and 3. All of the special function registers are then initialized (set to “0”) two machine cycles
after the XTAL1·2 oscillator commences regular operation.
When the reset is released, instruction execution is started in the third machine cycle if the
reset signal is changed from “1” level to “0” level before the M1·S1 signal leading edge, and
in the fifth machine cycle if the reset signal is changed from “1” to “0” after the leading edge.
The reset circuit block diagram is shown in Figure 3-4, the reset start time charts in Figures
3-5 and 3-6, and the reset release time charts in Figures 3-7 and 3-8.
VCC
+
– RESET
IN CPU RESET CONTROL
•
R=40KΩ
•
Figure 3-4 MSM80C154S/MSM83C154S reset circuit block diagram
45
M1 or M2 M1 M2 M1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1 PORT DATA FLOATING
PORT 0
0
1
PORT 1 PORT DATA PORT DATA = 1
0
MSM80C154S/83C154S/85C154HVS
1
0
1
46
0
1
RESET
0
CPU RESET 1
CONTROL 0
RESET 1
CPU RESET EXCECUTE CYCLE
EXCECUTE 0
Figure 3-5 Reset execution time chart (internal ROM mode)

M1 or M2 M1 M2 M1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1 FLOATING
PORT 0 PCL
0
1
PORT 2 PCH PCH PORT DATA = 1
0
1
RESET
0
CPU RESET 1
47
CONTROL 0
RESET 1
EXCECUTE 0
1
0
1
0
Figure 3-6 Reset execution time chart (external ROM mode)

CONTROL
M1 M1 M2 M1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1 FLOATING
PORT 0
0
1
PORT 1 PORT DATA = 1
0
MSM80C154S/83C154S/85C154HVS
1
0
1
48
0
1
RESET
0
CPU RESET 1
CONTROL 0
RESET 1
EXCECUTE 0
EXCECUTE CYCLE
Figure 3-7 Reset release time chart (internal ROM mode)

M1 M1 M2 M1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1 FLOATING
PORT 0 PCL PCL PCL
0
1
PORT 2 PORT DATA = 1 PCH PCH PCH
0
1
RESET
0
CPU RESET 1
49
CONTROL 0
RESET 1
EXCECUTE 0
1
0
1
0
EXCECUTE CYCLE
Figure 3-8 Reset release time chart (external ROM mode)

CONTROL
MSM80C154S/83C154S/85C154HVS
3.2.2 Reset Schmitt trigger circuit
The Schmitt trigger circuit connected to the RESET pin shown in the MSM80C154S/ MSM-
83C154S reset circuit block diagram in Figure 3-4 operates in the following way when the VCC
power supply voltage is +5V.
If the voltage of the reset signal applied to the RESET pin exceeds 3V when the level of that
signal is changed from “0” to “1”, the Schmitt trigger output level is changed from “0” to “1”,
and the reset signal is set in the CPU reset control circuit, resulting in the reset operation being
started by the CPU.
The CPU reset state is released when the “1” level on the RESET pin is changed to “0”. An
input signal level below 1.5V is regarded as “0” level, and the Schmitt trigger output level is
changed from “1” to “0”. When the reset signal is changed to “0” level, the CPU reset control
circuit is ready for reset release. The Schmitt trigger circuit operation time chart for changes
in the reset input voltage is outlined in Figure 3-9.
5 [V]
VCC
0 [V]
VIH =•• 3.0[V] VIL =•• 1.5[V]

5 [V]
RESET
0 [V] VTH =•• 1.5[V]
5 [V]
Schmitt trigger gate output
0 [V]
CPU reset
control input
Figure 3-9 Reset Schmitt trigger gate detector time chart
50
CONTROL
3.2.3 CPU internal status by reset
When a reset signal is applied to the CPU with normal voltage applied to the MSM80C154S/
MSM83C154S VCC power supply pin, ports 0, 1, 2, and 3 are set to “1” (input mode) even if
XTAL1·2 oscillation has been stopped. The output status of the ALE and PSEN pins also
becomes “1”. The CPU is then reset after normal XTAL1·2 oscillation has resumed. The
internal CPU status when the CPU is reset is shown in Table 3-1.
Table 3-1 MSM80C154S/MSM83C154S reset internal status
Register Name Register Reset Status

PC 0000H
SP 07H
IP 40H(0 × 000000)
IE 40H(0 × 000000)
PCON 10H(000 × 0000)
PSW, DPH, DPL, A, B
SCON, TCON, TMOD
T2CON, IOCON, TL0 00H
TL1, TL2, TH0, TH1
TH2, RCAP2L, RCAP2H
P1, P2, P3 *0FFH(input port)
P0 *0FFH(floating)
SBUF
Undefined
INTERNAL RAM
ALE, PSEN *“1” OUT
* Denotes direct resetting even if XTAL1·2 has stopped.
51
MSM80C154S/83C154S/85C154HVS
3.3 EA (CPU Memory Separate)
3.3.1 Outline
The function of the EA pin is to determine whether a CPU internal program memory (ROM)
instruction or an external program instruction is to be executed.
(1) Internal ROM mode
If the EA pin is connected to VCC and a “1” reset signal is applied to the RESET pin to
reset the CPU, an internal program memory (ROM) is executed from address 0.
(MSM83C154S, MSM85C154HVS)
(2) External ROM mode
If the EA pin is connected to VSS and a “1” reset signal is applied to the RESET pin to
reset the CPU, an external program memory is executed from address 0.
52
4. INTERNAL
SPECIFICATIONS
MSM80C154S/83C154S/85C154HVS
54
INTERNAL SPECIFICATIONS
4. INTERNAL SPECIFICATIONS
4.1 Internal Data Memory (RAM) and Special Function Registers
4.1.1 Outline
MSM80C154S/MSM83C154S operation is based on an instruction code address method

where operations are specified in an instruction code (OP) section, and the data memory
(RAM) and special function registers (ACC, B, TCON, P0........ ) are specified directly by part
of the instruction code and the second or third byte of data following that instruction code.
According to this instruction code address method, all eight bits of data in the data memory
and special function register may be specified, or one bit of data memory and one bit of data
in the special function register may be specified. Direct designation of all eight bits of data is
called data addressing, and direct designation of one bit of data is called bit addressing.
Since these CPU devices specify data memory (RAM) and special function register contents
by the above method, specific addresses are assigned to the respective CPU data memory
(RAM) and special function registers (ACC, B, TCON, P0, .... ). Data addresses consist of
eight bits, and range from 00 to 0FFH in binary (which correspond to 0 thru 255 in decimal).
All data memory (RAM) and special function registers (ACC, B, TCON, P0, .... ) exist in these
256 locations.
The data memory contains 256 bytes. The data memory between addresses 00 thru 7FH can
be specified directly by data address, and the data memory from address 80H to 0FFH can
be specified by indirect register instruction where R0 or R1 contents are set to 80H thru 0FFH.
Note that the entire data memory (RAM) from 00 thru 0FFH can be specified by indirect
register instruction.
Special function registers are located between addresses 80H thru 0FFH, and can also be
specified directly by data address. Bit addresses consist of eight bits, the manipulation bits
being specified by the three lower order bits and the data memory (RAM) or special function
register (ACC, B, TCON, P0, .... ) by the five higher order bits. Data memory between
addresses 20 thru 2FH can be specified by bit addressing. Other areas cannot be specified
by bit designation.
The special function registers which can be specified by bit address are P0, P1, P2, P3,
TCON, SCON, IE, IP, T2CON, PSW, ACC, B, and IOCON, a total of 13 registers. The data
memory (RAM) and special function register address space layout is shown in Figure 4-1.
55
MSM80C154S/83C154S/85C154HVS
HEX
OFF IOCON 0FFH~0F8H 248 (0F8H)
B 0F7H~0F0H 240 (0F0H)
ACC 0E7H~0E0H 224 (0E0H)
PSW 0D7H~0D0H 208 (0D0H)
TH2 205 (0CDH)
TL2 204 (0CCH)
RCAP2H 203 (0CBH)
RCAP2L 202 (0CAH)
T2CON 0CFH~0C8H 200 (0C8H)
SPECIAL FUNCTION REGISTERS IP 0BFH~0B8H 184 (0B8H)
P3 0B7H~0B0H 176 (0B0H)
IE 0AFH~0A8H 168 (0A8H)
P2 0A7H~0A0H 160 (0A0H)
USER DATA RAM SBUF 153 (99H)
SCON 9FH~98H 152 (98H)
P1 97H~90H 144 (90H)
REGISTER INDIRECT ADDRESSING
TH1 141 (8DH)

TH0 140 (8CH)
TL1 139 (8BH)
TL0 138 (8AH)
TMOD 137 (89H)
TCON 8FH~88H 136 (88H)
PCON 135 (87H)
DPH 131 (83H)
DPL 130 (82H)
SP 129 (81H)
80 P0 87H~80H 128 (80H)

7F
USER DATA RAM
30
2F 7F 78
BIT RAM
20 7 0
BIT ADDRESSING
1F R7
BANK 3
18 R0
17 R7
BANK 2
10 R0
0F R7 DATA ADDRESSING
BANK 1
08 R0
07 R7
BANK 0
00 R0
Figure 4-1 Data memory and special function register layout
56
4.2 Internal Data Memory (RAM)
4.2.1 Internal data memory (RAM)
The storage capacity of the MSM80C154S/MSM83C154S data memory is 256 words ¥ 8 bits.
The layout diagram is shown in Figure 4-2.
The data memory can be accessed (R/W) in four different ways - direct register designation,
indirect register designation, data addressing, and bit addressing.
Four banks of registers group (R0 thru R7 ¥ 4) exist within the data memory address range
from 00 to 1FH. Banks are specified by RS0 and RS1 data combinations within the PSW.
The data memory address range from 20 to 2FH is an area where bit addressing is possible.
One bit of data can be manipulated directly by bit manipulation instructions.
The data memory address range from 00 to 7FH is an area where data addressing is possible.
8-bit data manipulations can be handled directly by data address manipulation instructions.
The data memory address range from 80H to 0FFH is an area where data addressing is not
possible. To manipulate data in this data memory area, the contents of register R0 or R1 are
set in 80H thru 0FFH, then an indirect register instruction is used. (Indirect register
instructions can be used to specify the entire data memory from address 00 to 0FFH.)
In addition to data storage in the CPU, the data memory is used as the place for saving stack
data. This stack data storage area is addressed by a stack pointer (SP 81H).
Since the stack pointer can be set any desired value by software, the data memory can be
used as stack from any data memory address. Note that 07H data is set automatically in the
stack pointer when the CPU is reset.
57
MSM80C154S/83C154S/85C154HVS
0FFH 255
USER DATA RAM
80H 128
7FH 127
USER DATA RAM
30H 48
2FH 7F 7E 7D 7C 7B 7A 79 78 47
2EH 77 76 75 74 73 72 71 70 46
2DH 6F 6E 6D 6C 6B 6A 69 68 45
REGISTER 0, 1 INDIRECT ADDRESSING

2CH 67 66 65 64 63 62 61 60 44
2BH 5F 5E 5D 5C 5B 5A 59 58 43
DATA ADDRESSING
2AH 57 56 55 54 53 52 51 50 42
BIT ADDRESSING
29H 4F 4E 4D 4C 4B 4A 49 48 41
28H 47 46 45 44 43 42 41 40 40
27H 3F 3E 3D 3C 3B 3A 39 38 39
26H 37 36 35 34 33 32 31 30 38
25H 2F 2E 2D 2C 2B 2A 29 28 37
24H 27 26 25 24 23 22 21 20 36
REGISTER 0~7 DIRECT ADDRESSING

23H 1F 1E 1D 1C 1B 1A 19 18 35
22H 17 16 15 14 13 12 11 10 34
21H 0F 0E 0D 0C 0B 0A 09 08 33
20H 07 06 05 04 03 02 01 00 32
1FH 31
BANK 3
18H 24
17H 23
BANK 2
10H 16
0FH 15
BANK 1
08H 8
07H 7
BANK 0
00H 0
Figure 4-2 RAM layout diagram
58
4.2.2 Internal data memory registers R0 thru R7
Four banks of registers group exist in the data memory (RAM) between memory addresses
00 thru 1FH. Banks are specified by RS0 and RS1 bit combinations within the program status
word (PSW). Note that the register area R0 thru R7 can also be used as normal data memory.
The PSW table is shown in Table 4-1, and the data memory register bank layout in Figure 4-
3.
Table 4-1 Program status word (PSW)
Bit 7 6 5 4 3 2 1 0
Flag CY AC F0 RS1 RS0 OV F1 P
Set • •
OFF 255 D7 D6 D5 D4 D3 D2 D1 D0
STACK & DATA RAM
USER DATA RAM
30 48 D7 D6 D5 D4 D3 D2 D1 D0
2F 47 D7 D6 D5 D4 D3 D2 D1 D0
BIT ADDRESSING RS1 RS0
20 32 D7 D6 D5 D4 D3 D2 D1 D0
1F 31 D7 D6 D5 D4 D3 D2 D1 D0 R7
BANK 3 1 1
18 24 D7 D6 D5 D4 D3 D2 D1 D0 R0
17 23 D7 D6 D5 D4 D3 D2 D1 D0 R7
BANK 2 1 0
10 16 D7 D6 D5 D4 D3 D2 D1 D0 R0
0F 15 D7 D6 D5 D4 D3 D2 D1 D0 R7
BANK 1 0 1
08 8 D7 D6 D5 D4 D3 D2 D1 D0 R0
07 7 D7 D6 D5 D4 D3 D2 D1 D0 R7
06 6 D7 D6 D5 D4 D3 D2 D1 D0 R6
05 5 D7 D6 D5 D4 D3 D2 D1 D0 R5
04 4 D7 D6 D5 D4 D3 D2 D1 D0 R4 BANK 0 0 0
03 3 D7 D6 D5 D4 D3 D2 D1 D0 R3
02 2 D7 D6 D5 D4 D3 D2 D1 D0 R2
01 1 D7 D6 D5 D4 D3 D2 D1 D0 R1
00 0 D7 D6 D5 D4 D3 D2 D1 D0 R0
Figure 4-3 Internal data memory register bank layout
59
MSM80C154S/83C154S/85C154HVS
4.2.3 Stack
The stack data save (storage) area is in the internal data memory (RAM), and is specified by
stack pointer (SP 81H).
Although 07H data is automatically set in the stack pointer when the CPU is reset, any desired
data can be set by software to enable the data memory to be used as stack from any address.
Two bytes of data memory are used when the stack is used by interrupt or CALL instruction,
and a single byte of data memory is used when the PUSH instruction is used. The status
where an interrupt is generated and the program counter contents are saved in the stack
when the stack pointer contents are 7FH, and the status where accumulator contents are
pushed during interrupt routine and are subsequently saved in the stack are shown in Table
4-2. The stack status up to completion of interrupt processing upon execution of POP and
RETI instructions is also included.
Table 4-2 Stack storage layout
Stack RAM data bit

Stack processing
pointer 7 6 5 4 3 2 1 0
Before execution 7FH D7 D6 D5 D4 D3 D2 D1 D0
Interrupt process 80H PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
(push PC) 81H PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8
PUSH process (ACC) 82H A7 A6 A5 A4 A3 A2 A1 A0
POP process (ACC) 82H A7 A6 A5 A4 A3 A2 A1 A0
81H PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8
RETI process (pop PC)
80H PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
After execution 7FH D7 D6 D5 D4 D3 D2 D1 D0
60
4.3 lnternal Data Memory (RAM) Operating Procedures
4.3.1 Internal data memory indirect addressing
Operation of the internal data memory indirect increment instruction is described here as an
example. This instruction (INC @Rr) is a 1-byte 1-machine cycle instruction (see Figure 4-
4). The indirect address register is specified by instruction code bit 0 data r where r denotes
either register 0 or 1 in the register group specified by PSW RS0 and RS1 bank data. Register
0 is specified when the r data is 0, and register 1 is specified when the data is 1.
When this instruction is executed, register data is read from the specified register 0 or 1, and
the read out register data is written into the data pointer for the data memory.
The data memory contents specified by the data pointer are read by the CPU into a temporary
register. Then a subsequent increment (+1) by the ALU is followed by a return to the data
memory at the address where the data were read out. In this way, the contents of the data
memory at the address specified by the contents of R0 or R1 are incremented.
Instruction (OP) Register

code portion designation portion
INC @Rr: 0 0 0 0 0 1 1 r Byte 1

7 6 5 4 3 2 1 0
Figure 4-4 INC @Rr bit arrangement
61
MSM80C154S/83C154S/85C154HVS
4.3.2 Internal data memory register R0 thru R7 designation
Operation of the internal data memory register decrement instruction is described here as an
example. This instruction (DEC Rr) is a 1-byte 1-machine cycle instruction (see Figure 4-5).
Register R0 thru R7 is specified by r0, r1, and r2 data of instruction code bit 0, 1, and 2. The
r0, r1, and r2 data is represented in binary code, r0 being the LSB, and r2 the MSB. The code
is weighted 1, 2, and 4 from the LSB. Any one of the eight registers can be specified by
combinations of this code. See Table 4-3 for the register designation combinations.
When this instruction is executed, one of the registers R0 thru R7 from the register group
specified by the PSW RS0 and RS1 bank data is specified. The contents of the specified
register is read by the CPU into a temporary register. Then a subsequent decrement (–1) by
the ALU is followed by a return to the register where the data were read out. In this way, the
register contents specified by r0, r1, and r2 are decremented.
Instruction (OP) Register

code portion designation portion
DEC Rr: 0 0 0 1 1 r2 r1 r0 Byte 1

7 6 5 4 3 2 1 0
Figure 4-5 DEC Rr bit arrangement
Table 4-3 Register designation table
Register name r2 r1 r0
Register 0 0 0 0
Register 1 0 0 1
Register 2 0 1 0
Register 3 0 1 1
Register 4 1 0 0
Register 5 1 0 1
Register 6 1 1 0
Register 7 1 1 1
62
4.3.3 Internal data memory 1-bit data designation
In the MSM80C154S/MSM83C154S, 1-bit data manipulations (test, reset, set, complement,

transfer) can be executed directly between internal data memory addresses 20 thru 2FH by
bit manipulation instructions. The operation of a bit reset instruction is described below as an
example.
This instruction (CLR bit address) is a 2-byte 2-machine cycle instruction (see Figure 4-6).
The instruction code is indicated in byte 1, and the data memory address and bit designation
are indicated in byte 2. The manipulation bit is specified by the b0, b1, and b2 data in bits 0,
1, and 2 of byte 2. The b0, b1, and b2 portion is expressed in binary code which is weighted
1, 2, and 4. Combinations of this code enable any one of eight bits to be specified. The bit
designation combinations are listed in able 4-4.
The data memory is addressed by bits b3, b4, b5, b6 and b7 of byte 2 with b7 being “0”. These
bits can be expressed in binary by 0 thru 0FH, and a total of 16 designations of the data
memory are possible.
When data memory addresses are specified, the data memory bit manipulation start address
20H is added to the b3, b4, b5, and b6 binary data to obtain the data memory address.
The data memory contents specified by the above method are read by the CPU into a
temporary register, the specified bit data is reset to “0” by the ALU, and the CPU returns the
result to the data memory where the data were read. One bit of specified data memory is thus
reset to “0”.
Instruction (OP) code
CLR bit address: 1 1 0 0 0 0 1 0 Byte 1

7 6 5 4 3 2 1 0
Address Bit designation

designation portion portion
b7 b6 b5 b4 b3 b2 b1 b0 Byte 2
7 6 5 4 3 2 1 0
Figure 4-6 CLR bit address bit arrangement
63
MSM80C154S/83C154S/85C154HVS
Table 4-4 Bit designation table
Bit name b2 b1 b0
Bit 0 0 0 0
Bit 1 0 0 1
Bit 2 0 1 0
Bit 3 0 1 1
Bit 4 1 0 0
Bit 5 1 0 1
Bit 6 1 1 0
Bit 7 1 1 1
Table 4-5 Addressing combination table
b7 b6 b5 b4 b3 RAM address
0 0 0 0 0 0 20H 32
1 0 0 0 0 1 21H 33
2 0 0 0 1 0 22H 34
3 0 0 0 1 1 23H 35
4 0 0 1 0 0 24H 36
5 0 0 1 0 1 25H 37
6 0 0 1 1 0 26H 38
7 0 0 1 1 1 27H 39
8 0 1 0 0 0 28H 40
9 0 1 0 0 1 29H 41
A 0 1 0 1 0 2AH 42
B 0 1 0 1 1 2BH 43
C 0 1 1 0 0 2CH 44
D 0 1 1 0 1 2DH 45
E 0 1 1 1 0 2EH 46
F 0 1 1 1 1 2FH 47
64
4.4 Special Function Registers (TCON, SCON,.... ACC, B)
4.4.1 Outline
As can be seen from the configuration shown in Table 4-6, the MSM80C154S/ MSM83C154S
special function registers consist of 27 8-bit registers.
Special function registers can be accessed (R/W) by either data addressing or bit addressing.
All 27 registers can be specified by data addressing. 13 registers (P0, P1, P2, P3, TCON,
T2CON, SCON, IE, IP, PSW, ACC, B, and IOCON) can be specified by bit addressing.
If a register which does not exist at the data address is accessed when a special function
register is used, the read data becomes 0FFH. And when data is written, none of the registers
in the CPU are effected at all. Note, however, that since a jump is always executed when a
bit test instruction which results in a relative jump at data condition “1” is executed, make sure
that no instruction is executed for a register which does not exist.
65
MSM80C154S/83C154S/85C154HVS
Table 4-6 List of special function registers
Register Bit address

Data address
name b7 b6 b5 b4 b3 b2 b1 b0
IOCON FF FE FD FC FB FA F9 F8 0F8H(248)
B F7 F6 F5 F4 F3 F2 F1 F0 0F0H(240)
ACC E7 E6 E5 E4 E3 E2 E1 E0 0E0H(224)
PSW D7 D6 D5 D4 D3 D2 D1 D0 0D0H(208)
TH2 0CDH(205)
TL2 0CCH(204)
RCAP2H 0CBH(203)
RCAP2L 0CAH(202)
T2CON CF CE CD CC CB CA C9 C8 0C8H(200)
IP BF BE BD BC BB BA B9 B8 0B8H(184)
P3 B7 B6 B5 B4 B3 B2 B1 B0 0B0H(176)
IE AF AE AD AC AB AA A9 A8 0A8H(168)
P2 A7 A6 A5 A4 A3 A2 A1 A0 0A0H(160)
SBUF 99H(153)
SCON 9F 9E 9D 9C 9B 9A 99 98 98H(152)
P1 97 96 95 94 93 92 91 90 90H(144)
TH1 8DH(141)
TH0 8CH(140)
TL1 8BH(139)
TL0 8AH(138)
TMOD 89H(137)
TCON 8F 8E 8D 8C 8B 8A 89 88 88H(136)
PCON 87H(135)
DPH 83H(131)
DPL 82H(130)
SP 81H(129)
P0 87 86 85 84 83 82 81 80 80H(128)
66
4.4.2 Special function registers
4.4.2.1 Timer mode register (TMOD)
MSB LSB
Name Address
7 6 5 4 3 2 1 0
TMOD 89H GATE C/T M1 M0 GATE C/T M1 M0
Bit location Flag Function
TMOD.0 M0 M1 M0 Timer/counter 0 mode setting
0 0 8-bit timer/counter with 5-bit prescalar
0 1 16-bit timer/counter
TMOD.1 M1 1 0 8-bit timer/counter with 8-bit auto reloading
1 1 Timer/counter 0 separated into TL0 (8-bit) timer/counter
and TH0 (8-bit) timer/counter. TF0 is set by TL0 carry,
and TF1 is set by TH0 carry.
TMOD.2 C/T Timer/counter 0 count clock designation control bit.
XTAL1·2 divided by 12 clock is the input applied to timer/counter 0
when C/T="0".
The external clock applied to the T0 pin is the input applied to
timer/counter 0 when C/T="1".
TMOD.3 GATE When this bit is "0", the TR0 bit of TCON (timer control register) is
used to control the start and stop of timer/counter 0 counting. If
this bit is "1", timer/counter 0 starts counting when both the TR0 bit
of TCON and INT0 pin input signal are "1", and stops counting
when either is changed to "0".
0 0 8-bit timer/counter with 5-bit prescalar
TMOD.5 M1 1 0 8-bit timer/counter with 8-bit auto reloading
1 1 Timer/counter 1 operation stopped
XTAL1·2 divided by 12 clock is the input applied to timer/counter 1
when C/T="0".
The external clock applied to the T1 pin is the input applied to
timer/counter 1 when C/T="1".
TMOD.7 GATE When this bit is "0", the TR1 bit of TCON is used to control the
start and stop of timer/counter 1 counting.
If this bit is "1", timer/counter 1 starts counting when both the TR1
bit of TCON and INT1 pin input signal are "1", and stops counting
when either is changed to "0".
67
MSM80C154S/83C154S/85C154HVS
4.4.2.2 Power control register (PCON)
MSB LSB
Name Address
7 6 5 4 3 2 1 0
PCON 87H SMOD HPD RPD — GF1 GF0 PD IDL
PCON.0 IDL IDLE mode set when this bit is set to "1". CPU operations are
stopped when IDLE mode is set, but XTAL1·2, timer/counters 0, 1,
and 2, the interrupt circuits, and serial port remain active. IDLE
mode is cancelled when the CPU is reset or when an interrupt is
generated.
PCON.1 PD PD mode set when this bit is set to "1". CPU operations and
XTAL1·2 are stopped when PD mode is set. PD mode is cancelled
when the CPU is reset or when an interrupt is generated.
PCON.2 GF0 User flag. Testing this flag when IDLE mode is cancelled by an
interrupt shows whether the interrupt is a normal interrupt or an
IDLE mode release interrupt.
PCON.3 GF1 User flag. Testing this flag when PD mode is cancelled by an
interrupt shows whether the interrupt is a normal interrupt or a PD
mode release interrupt.
PCON.4 — Reserved bit. The output data is "1" if the bit is read.
PCON.5 RPD Bit used to specify cancellation of CPU power down mode (IDLE
or PD) by interrupt signal.
Power down mode cannot be cancelled by interrupt signal if
interrupt is not enabled by IE (interrupt enable register) when this
bit is "0".
If the interrupt flag is set to "1" by an interrupt request signal when
this bit is "1" (even if interrupt is disabled), the program is executed
from the next address of the power down mode setting instruction.
The flag is reset to "0" by software.
PCON.6 HPD The hard power down setting mode is enabled when this bit is set
to "1".
If the level of the power failure detect signal applied to the HPDI
pin (pin 3.5) is changed from "1" to "0" when this bit is "1",
XTAL1·2 oscillation is stopped and the system is put into hard
power down mode.
PCON.7 SMOD When the serial port is used in mode 1, 2 or 3, this bit has the
following functions. The serial port operation clock is reduced by
1/2 when the bit is "0" for delayed processing. And when the bit is
"1", the serial port operation clock is normal for faster processing.
68
4.4.2.3 Timer control register (TCON)
MSB LSB
Name Address
7 6 5 4 3 2 1 0
TCON 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
TCON.0 IT0 External interrupt 0 signal used in level detect mode when this bit
is "0", and in trigger detect mode when "1".
TCON.1 IE0 Interrupt request flag for external interrupt 0.
Bit is reset automatically when interrupt is serviced.
Bit can be set and reset by software when IT0="1".
TCON.2 IT1 External interrupt 1 signal used in level detect mode when this bit
is "0",and in trigger detect mode when "1".
TCON.3 IE1 Interrupt request flag for external interrupt 1 .
Bit is reset automatically when interrupt is serviced.
Bit can be set and reset by software when IT1="1".
TCON.4 TR0 Counting start and stop control bit for timer/counter 0.
Timer/counter 0 starts counting when this bit is "1", and stops
counting when "0".
TCON.5 TF0 Interrupt request flag for timer interrupt 0.
Bit is reset automatically when interrupt is serviced. Bit is set to "1"
when carry signal is generated from timer/counter 0.
Timer/counter 1 starts counting when this bit is "1", and stops
counting when "0".
TCON.7 TF1 Interrupt request flag for timer interrupt 1 .
Bit is reset automatically when interrupt is serviced. Bit is set to "1"
when carry signal is generated from timer/counter 1.
69
MSM80C154S/83C154S/85C154HVS
4.4.2.4 Serial port control register (SCON)
MSB LSB
Name Address
7 6 5 4 3 2 1 0
SCON 98H SM0 SM1 SM2 REN TB8 RB8 TI RI
SCON.0 RI "End of serial port reception" interrupt request flag. This flag must
be reset by software during interrupt service routine.
This flag is set after the eighth bit of data has been received when
in mode 0, or by the STOP bit when in any other mode. In mode 2
or 3, however, RI is not set if the RB8 data is "0" with SM2="1". RI
is set if STOP bit is received when SM2="1" in mode 1.
SCON.1 TI "End of serial port transmission" interrupt request flag. This flag
must be reset by software during interrupt service routine. This flag
is set after the eighth bit of data has been sent when in mode 0, or
after the last bit of data has been sent when in any other mode.
SCON.2 RB8 The ninth bit of data received in mode 2 or 3 is passed to RB8.
The STOP bit is applied to R88 if SM2="0" when in mode 1. RB8
cannot be used in mode 0.
SCON.3 TB8 The TB8 data is sent as the ninth data bit when in mode 2 or 3.
Any desired data can be set in TB8 by software.
SCON.4 REN Reception enable control bit.
No reception when REN="0".
Reception enabled when REN="1".
SCON.5 SM2 If the ninth bit of received data is "0" with SM2="1" in mode 2 or 3,
the "end of reception" signal is not set in the RI flag.
Nor is the "end of reception" signal set in the RI flag if the STOP bit
is not "1" when SM2="1" in mode 1.
SCON.6 SM1 SM0 SM1 MODE
0 0 0 8-bit shift register I/O
0 1 1 8-bit UART variable baud rate
SCON.7 SM0 9-bit UART 1/32 XTAL1, 1/64 XTAL1
1 0 2
baud rate
70
4.4.2.5 Interrupt enable register (IE)
MSB LSB
Name Address
7 6 5 4 3 2 1 0
IE 0A8H EA — ET2 ES ET1 EX1 ET0 EX0
IE.0 EX0 Interrupt control bit for external interrupt 0.
Interrupt disabled when bit is "0".
Interrupt enabled when bit is "1".
IE.1 ET0 Interrupt control bit for timer interrupt 0.
IE.2 EX1 Interrupt control bit for external interrupt 1 .
IE.3 ET1 Interrupt control bit for timer interrupt 1 .
IE.4 ES Interrupt control bit for serial port.
IE.6 — Reserved bit. The output data is "1" if the bit is read.
IE.7 EA Overall interrupt control bit.
All interrupts are disabled when bit is "0".
All interrupts are enabled/disabled by IE.0 thru IE.5 when bit is "1".
71
MSM80C154S/83C154S/85C154HVS
4.4.2.6 Interrupt priority register (IP)
MSB LSB
Name Address
7 6 5 4 3 2 1 0
IP 0B8H PCT — PT2 PS PT1 PX1 PT0 PX0
IP.0 PX0 Interrupt priority bit for external interrupt 0.
Priority is assigned when bit is "1".
IP.1 PT0 Interrupt priority bit for timer interrupt 0.
IP.2 PX1 Interrupt priority bit for external interrupt 1 .
Priority is assigned when bit is " 1 ".
IP.3 PT1 Interrupt priority bit for timer interrupt 1 .
IP.4 PS Interrupt priority bit for serial port.
IP.6 — Reserved bit. The output data is "1" if the bit is read.
IP.7 PCT Priority interrupt circuit control bit.
The priority register contents are valid and priority assigned
interrupts can be processed when this bit is "0". When the bit is
"1", the priority interrupt circuit is stopped, and interrupts can only
be controlled by the interrupt enable register (IE).
72
4.4.2.7 Program status word register (PSW)
MSB LSB
Name Address
7 6 5 4 3 2 1 0
PSW 0D0H CY AC F0 RS1 RS0 OV F1 P
PSW.0 P Accumulator (ACC) parity indicator.
"1" when the "1" bit number in the accumulator is an odd number,
and "0" when an even number.
PSW.1 F1 User flag which may be set to "0" or "1" as desired by the user.
PSW.2 OV Overflow flag which is set if the carry C6 from bit 6 of the ALU or
CY is "1" as a result of an arithmetic operation. The flag is also set
to "1" if the resultant product of a multiplication instruction (MUL
AB) is greater than 0FFH, but is reset to "0" if the product is less
than or equal to 0FFH.
PSW.3 RS0 RAM register bank switch
RS1 RS0 BANK RAM ADDRESS
0 0 0 00H – 07H
PSW.4 RS1 0 1 1 08H – 0FH
1 0 2 10H – 17H
1 1 3 18H – 1FH
PSW.5 F0 User flag which ma be set to "0" or "1" as desired by the user.
PSW.6 AC Auxiliary carry flag.
This flag is set to "1" if a carry C3 is generated from bit 3 of the
ALU as a result of executing an arithmetic operation instruction. In
all other cases, the flag is reset to "0".
PSW.7 CY Main carry flag.
This flag is set to "1" if a carry C7 is generated from bit 7 of the
ALU as a result of executing an arithmetic operation instruction. In
all other cases, the flag is reset to "0".
73
MSM80C154S/83C154S/85C154HVS
4.4.2.8 I/O control register (IOCON)
MSB LSB
Name Address
7 6 5 4 3 2 1 0
IOCON 0F8H — T32 SERR IZC P3HZ P2HZ P1HZ ALF
IOCON.0 ALF If CPU power down mode (PD, HPD) is activated with this bit set
to "1", the outputs from ports 0, 1, 2, and 3 are switched to floating
status.
When this bit is "0", ports 0, 1, 2, and 3 are in output mode.
IOCON.1 P1HZ Port 1 becomes a high impedance input port when this bit is "1".
IOCON.4 IZC The 10 kohm pull-up resistance for ports 1, 2, and 3 is switched off
when this bit is "1", leaving only the 100 kohm pull-up resistance.
IOCON.5 SERR Serial port reception error flag.
This flag is set to "1" if an overrun or framing error is generated
when data is received at a serial port. The flag is reset by software.
IOCON.6 T32 Timer/counters 0 and 1 are connected serially to form a 32-bit
timer/counter when this bit is set to "1". TF1 of TCON is set if a
carry is generated in the 32-bit timer/counter.
IOCON.7 — The output data is "0" if the bit is read.
This bit should not be set to "1".
74
4.4.2.9 Timer 2 control register (T2CON)
MSB LSB
Name Address
7 6 5 4 3 2 1 0
TMOD 0C8H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
T2CON.0 CP/RL2 Capture mode is set when TCLK+RCLK="0" and CP/RL2 16-bit
auto reload mode is set when TCLK+RCLK="0" and CP/RL2="0".
CP/RL2 is ignored when TCLK+RCLK="1".
T2CON.1 C/T2 Timer/counter 2 count clock designation control bit.
The internal clocks (XTAL1·2÷12, XTAL1·2÷2) are used when this
bit is "0", and the external clock applied to the T2 pin is passed to
timer/counter 2 when the bit is "1".
T2CON.2 TR2 Timer/counter 2 counting start and stop control bit.
Timer/counter 2 commences counting when this bit is "1" and
stops counting when "0".
T2CON.3 EXEN2 T2EX timer/counter 2 external control signal control bit. Input of the
T2EX signal is disabled when this bit is "0", and enabled when "1".
T2CON.4 TCLK Serial port transmit circuit drive clock control bit.
Timer/counter 2 is switched to baud rate generator mode when this
bit is "1", and the timer/counter 2 carry signal becomes the serial
Port transmit clock. Note, however, that the serial ports can only
use the timer/counter 2 carry signal in serial port modes 1 and 3.
T2CON.5 RCLK Serial port receive circuit drive clock control bit.
Timer/counter 2 is switched to baud rate generator mode when this
bit is "1", and the timer/counter 2 carry signal becomes the serial
Port receive clock. Note, however, that the serial ports can only
use the timer/counter 2 carry signal in serial port modes 1 and 3.
T2CON.6 EXF2 Timer/counter 2 external flag.
This bit is set to "1" when the T2EX timer/counter 2 external
control signal level is changed from "1" to "0" while EXEN2="1".
This flag serves as the timer interrupt 2 request signal. if an
interrupt is generated, it must be reset to "0" by software.
T2CON.7 TF2 Timer/counter 2 carry flag.
This bit is set to "1" by a carry signal when timer/counter 2 is in 16-
bit auto reload mode or in capture mode.
This flag serves as the timer interrupt 2 request signal. if an
interrupt is generated, it must be reset to "0" by software.
75
MSM80C154S/83C154S/85C154HVS
4.5 Timer/Counters 0, 1 and 2
4.5.1 Outline
Timer/counters 0, 1 and 2 are all equipped with 16-bit binary up-counting and Read/Write
functions, and can be operated independently.
All control of timer/counters 0 and 1 is handled by the timer control register (TCON 88H) and
the timer mode register (TMOD 89H). And both timer/counters can be set independently to
modes 0 thru 3 for a diversity of applications.
Timer/counters 0 and 1 can be operated by an external clock applied to the T0 and T1 pins
(if external clock mode has been set) during soft power down mode (PD) and hard power
down mode (HPD) where XTAL1·2 are stopped. Therefore, CPU power down mode can be
cancelled by generating a timer/counter carry signal.
Timer/counter 2 can be fully controlled by timer 2 control register (T2CON 0C8H). There are
three operational modes for a wide range of applications. Note that counting is stopped when
XTAL1·2 are stopped.
4.5.2 Timer/counters 0 and 1
4.5.2.1 Outline
Timer/counters 0 and 1 are both equipped with a 16-bit binary counting function which can
be operated independently.
All control of timer/counters 0 and 1 is handled by the timer control register (TCON) and the
timer mode register (TMOD). And both timer/counters can be set independently to modes 0
thru 3 for a diversity of applications. The overall control circuit for timer/counters 0 and 1 is
outlined in Figure 4-7 (excluding timer mode 3).
4.5.2.2 Timer/counter 0 and 1 counting control
Counting start and stop in timer/counters 0 and 1 is controlled by bit 4, TR0, and bit 6, TR1,
in the timer control register (TCON 88H) as indicated in Table 4-7.
TR0 controls timer/counter 0, and TR1 controls timer/counter 1. Timer/counter operation is
stopped when the bit data is “0”, and enabled when “1”.
Table 4-7 Timer control register (TCON 88H)
Timer 1 Timer 0
Bit 7 6 5 4 3 2 1 0
Flag TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Set • •
76
XTAL 1 ÷12 S3
TIMER 1
T1 PIN
DETECTOR
(PORT 3.5)
INT1 PIN
(PORT 3.3) DATA
Q
S5 LATCH
77
TIMER 0
T0 PIN
DETECTOR
(PORT 3.4)
INT0 PIN
(PORT 3.2) DATA
Q
S5 LATCH
Figure 4-7 Overall clock input control circuit for timer/counters 0 and 1
GATE C/T M1 M0 GATE C/T M1 M0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
TIMER MODE REGISTER (TMOD) TIMER CONTROL REGISTER (TCON)

MSM80C154S/83C154S/85C154HVS
4.5.2.3 Timer/counter 0 and 1 count clock designation
Designation of count clock inputs to timer/counters 0 and 1 is controlled by bit 2 and 6, C/T,
in the timer mode register (TMOD 89H).
Timer/counter 0 is controlled by bit 2, C/T, and timer/counter 1 is controlled by bit 6, C/T.
The internal clock is passed to the timer/counter when the C/T bit is “0”. This internal clock
is the result of dividing XTAL1·2 by 12. The S3 timing signal (see Figure 2-9) becomes the
clock.
The external clock is applied to the timer/counter when the C/T bit is “1”. The external clock
applied to the T0 pin serves as the timer/counter 0 input, while the external clock applied to
the T1 pin serves as the timer/counter 1 input.
Table 4-8 Timer mode register (TMOD 89H)
Timer 1 Timer 0
Bit 7 6 5 4 3 2 1 0
Flag GATE C/T M1 M0 GATE C/T M1 M0
Set • •
78
4.5.2.3.1 External clock detector circuit for timer/counters 0 and 1
The detector circuit shown in Figure 4-8 is inserted between the timer/counters and the
external clock pin.
This detector circuit operates in the following way. When the external clock applied to the T0
and T1 pins is changed from “1” to “0” level, that clock is fetched by F/Fl, and is then passed
to F/F2 when the S5 timing signal appears. This F/F2 output is subsequently ANDed (logical
product) with the S3 timing signal to form the timer/counter clock signal which then serves as
the F/Fl reset signal. The reset F/Fl then waits for the next external clock. The “0” and “1” signal
cycle widths of the respective external clocks applied to the T0 and T1 pins must have a
minimum of period 12 times (12T) the XTAL1·2 oscillator clock cycle T. However, when the
CPU is in PD mode or HPD mode the external clock applied to the T0 and T1 pins is input
to timer/counters 0 and 1 directly. The operational time chart for this detector circuit is outlined
in Figure 4-9.
TIMER 0
F/F1 F/F2
or
VCC D Q D Q TIMER 1
L
T0 or T1 R
S5 S3
1
RESET
12T 12T PD & HPD
Figure 4- 8 T0 and T1 external clock detector circuit
79
MSM80C154S/83C154S/85C154HVS
M1 M1 or M2
S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2
1
XTAL1
0
1
ALE
0
T0 or T1 1
COUNT IN 0
1
F/F1Q
0
1
F/F2Q
0
1
TIMER COUNT
0
Figure 4-9 Detector circuit operational time chart
4.5.2.4 Counting control of timer/counters 0 and 1 by INT pin
In addition to control by TR0 and TR1 bits of timer control register (TCON), timer/counter 0
and 1 counting start and stop can also be controlled by the signal level applied to the external
interrupt pin in accordance with the GATE data values of bits 3 and 7 in the timer mode register
(TMOD 89H) indicated in Table 4-9.
Timer/counter 0 is controlled by the bit 3, GATE bit. When the GATE bit is “0”, counting is
started and stopped only by TR0.
When the GATE bit is “1”, counting in timer/counter 0 is enabled if the TR0 bit and INT0 pin
input signal are both “1”. Counting is subsequently stopped if either is changed to “0” level.
Timer/counter 1 is controlled by the bit 7, GATE bit, the functional operation being the same
as timer/counter 0. The GATE - INT timer/counter counting control circuit is outlined in Figure
4-10, and the control table is given in Table 4-10.
Timer 1 Timer 0
Bit 7 6 5 4 3 2 1 0
Set • •
80
XTAL 1 ÷12 S3
TIMER 0
or
T0 or T1 DETECTOR TIMER 1
CLOCK
C/ T
INT0 or INT1 D Q
S5 L
✽ GATE
TR0 or TR1
Figure 4-10 INT0 and INT1 timer/counter start/stop control circuit
Table 4-10 GATE·INT·TR timer/counter control tables
TIMER 0 TIMER 1
GATE 0 0 1 1 1 GATE 0 0 1 1 1
TR0 0 1 0 1 1 TR1 0 1 0 1 1
INT0 × × 0 0 1 INT1 × × 0 0 1
RUN • • RUN • •
STOP • • • STOP • • •
81
MSM80C154S/83C154S/85C154HVS
4.5.2.5 Timer/counters 0/1 timer modes
4.5.2.5.1 Outline
The timer/counter 0 and 1 timer modes are set by combinations of M0 and M1 bit data in the
timer mode register (TMOD 89H) shown in Table 4-11. The timer modes which can be set
are 0, 1, 2, and 3.
Timer/counter 0 modes are specified by M0 and M1 of bits 0 and 1, and timer/counter 1 modes
are specified by M0 and M1 of bits 4 and 5.
TIMER COUNTER 1 TIMER COUNTER 0

Bit 7 6 5 4 3 2 1 0
Set • • • •
4.5.2.5.2 Mode 0
M1 M0
0 0
In mode 0, timer/counters 0 and 1 both become 13-bit timer/counters by the circuit connection
shown in Figures 4-11 and 4-12. TL0 and TL1 in timer/counters 0 and 1 serve as the counter
for the five lower bits, and TH0 and TH1 serve as the counter for the eight upper bits.
TF0 of TCON is set by the timer/counter 0 carry signal, and TF1 of TCON is set by the timer/
counter 1 carry signal. Note that the timer/counter 1 carry signal can also be used as the serial
port transmission/reception clock.
Although the three upper bits of TL0 and TL1 are operative, they are invalid as signals.
82
XTAL 1 ÷12 S3 DETECTOR TF0
Q0------Q4 Q0------Q7
TL0 TH0 C
T0 PIN DETECTOR (5BITS) (8BITS)
(PORT 3.4)
C/ T
TR0
GATE
INT0 PIN DATA

Q
(PORT 3.2) S5 LATCH
Figure 4-11 Timer/counter 0 mode 0
Q0------Q4 Q0------Q7
TL1 TH1 C
(PORT 3.5)
C/ T
TR1 S I/O CLOCK
GATE
INT1 PIN DATA

Q
(PORT 3.3) S5 LATCH
83
MSM80C154S/83C154S/85C154HVS
4.5.2.5.3 Mode 1
M1 M0
0 1
In mode 1, timer/counters 0 and 1 both become 16-bit timer/counters by the circuit connection
shown in Figures 4-13 and 4-14.
TL0 and TL1 in timer/counters 0 and 1 serve as the counter for the eight lower bits, and TH0
and TH1 serve as the counter for the eight upper bits.
TL0 is set by the timer/counter 0 carry signal, and TF1 is set by the timer/counter 1 carry
signal. Again note that the timer/counter 1 carry signal can also be used as the serial port
transmission/reception clock.
84
Q0------Q7 Q0------Q7
TL0 TH0 C
(PORT 3.4)
C/ T
TR0
GATE
INT0 PIN DATA

Q
(PORT 3.2) S5 LATCH
Figure 4-13 Timer/counter 0 model
Q0------Q7 Q0------Q7
TL1 TH1 C
(PORT 3.5)
C/ T
TR1 S I/O CLOCK
GATE
INT1 PIN DATA

Q
(PORT 3.3) S5 LATCH
Figure 4-14 Timer/counter 1 model
85
MSM80C154S/83C154S/85C154HVS
4.5.2.5.4 Mode 2
M1 M0
1 0
In mode 2, timer/counters 0 and 1 both become 8-bit timer/counters with 8-bit auto reloader
registers by the circuit connection shown in Figures 4-15 and 4-16. TH0 and TH1 in timer/
counters 0 and 1 serve as the 8-bit auto reloader section, and TL0 and TL1 serve as the timer/
counter section.
If a carry signal is generated by the 8-bit timer/counter TL0 and TL1, the respective auto
reloader register data is preset into the timer/counter, and counting proceeds from the preset
value.
TF0 is set by the timer/counter 0 carry signal, and TF1 is set by the timer/counter 1 carry
signal. Note that the timer/counter 1 carry signal can also be used as the serial port
transmission/reception clock.
86
Q0------Q7
TL0 C
T0 PIN DETECTOR (8BITS)
(PORT 3.4)
C/ T
TR0
GATE Q0------Q7
RELOAD
TH0
DATA
(8BITS)
INT0 PIN DATA
Q
(PORT 3.2) S5 LATCH
S I/O CLOCK
Q0------Q7
TL1 C
(PORT 3.5)
C/ T
TR1
GATE Q0------Q7
RELOAD
TH1
DATA
(8BITS)
INT1 PIN DATA
Q
(PORT 3.3) S5 LATCH
87
MSM80C154S/83C154S/85C154HVS
4.5.2.5.5 Mode 3
M1 M0
1 1
In mode 3, timer/counter 0 TL0 and TH0 become independent 8-bit timer/counters by the
circuit connection shown in Figure 4-17. Timer/counter 1 does not operate when mode 3 is
set. The TL0 8-bit timer/counter is controlled in the same way as the regular timer/counter 0,
TF0 being set if a carry signal is generated by TL0.
The TH0 8-bit timer/counter is controlled only by TR1, and the control only covers count
starting and stopping. TF1 is set by a carry signal generated by TH0.
When timer/counter 0 is set to mode 3, timer/counter 1 can operate in modes 0, 1, or 2, and
be used by the serial port clock. Control of timer/counter 1 count starting and stopping in this
case is handled between operating mode and mode 3. If mode 3 is set, the timer/counter 1
counting operation is stopped.
Q0------Q7
TL0
(PORT 3.4)
C/ T
TR0
GATE
INT0 PIN DATA

Q
(PORT 3.2) S5 LATCH
DETECTOR TF1
XTAL 1 ÷12
Q0------Q7
TR1 TH0 C
(8BITS)
88
4.5.2.5.6 32-bit timer mode
When “1” is set in bit 6 (T32) of the I/O control register (IOCON 0F8H), timer/counters 0 and
1 are connected serially as indicated in Figure 4-18 to become a 32-bit timer/counter.
This 32-bit timer/counter is started by the following procedure. First, “0” is set in TR0, TR1,
TF0, and TF1 of the timer control register (TCON 88H) to stop the timer/counter and reset the
timer flag.
Next timer/counter preset data values are set in timer/counters 0 and 1, and a counter clock
designation is set in bit 2 (C/T) of the timer mode register (TMOD 89H).
If “1” is then set in bit 6 (T32) of the 1/0 control register (IOCON 0F8H) after completing the
above procedure, the 32-bit timer/counter is established and counting is commenced. This
32-bit timer/counter is especially useful in cancelling CPU power down mode. (See power
down mode cancellation.)
T0 PIN DETECTOR
(PORT 3.4) IOCON [0F8H]
7 6 5 4 3 2 1 0
XTAL 1 ÷12 — T32 SERR IZC P3HZ P2HZ P1HZ ALF
•
Q0-----Q7 Q0-----Q7 Q0-----Q7 Q0-----Q7

TL0 TH0 TL1 TH1 TF1
(8BITS) (8BITS) (8BITS) (8BITS)
C/ T
(TMOD bit2)
Figure 4-18 32-bit timer/counter
89
MSM80C154S/83C154S/85C154HVS
4.5.2.5.7 Caution about use of timer counters 0 and 1
Since the internal clock stops operation during soft power down mode (PD), the auto-reload
operation is not executed if timer/counters 0 and 1 are set to mode 2 or mode 3.
If the power down mode is to be cancelled by the timer, timer/counters 0 and 1 must be set
to mode 0 or mode 1.
When timers 0 and 1 are set to external clock mode, the external clock is taken in as shown
in Figure 4-19 and the power down mode can be cancelled through the overflow of the timer.
If the external interrupt occurs when the T0 or T1 pin goes to “1” level and the soft power down
mode (PD) is cancelled, the gate output (A) changes from “1” level to “0” level and the counter
is incremented by 1.
In addition, “Q” of F/F1 is set on the trailing edge of T0 or T1.
Thus, the counter is incremented by additional 1.
The same event occurs not only by the external interrupt but also by the overflow of the timer.
This is because the overflow signal of the timer is made up of the timer count value “FF” and
the clock input signal “AND”. Therefore, the timer interrupt occurs when the T0 or T1 pin goes
to “1” level, and the power down mode is cancelled and the counter is incremented by
additional 1.
In cancelling the soft power down mode with the external interrupt, if the timer is set to external
clock mode, the T0 or T1 pin must be set to “0” level. If the T0 or T1 pin is at “1” level or if the
power down mode is cancelled by the overflow of the timer, the timer must be reset or the
counter must be decremented by 1.
"1" A
TIMER 0
F/F1 F/F2
or
VCC D Q D Q TIMER 1
F/F1 F/F2
"1"
L
T0 or T1 R
S5 S3
RESET
PD
Figure 4-19 T0, T1 external clock detector circuit
90
4.5.2.5.8 Caution about use of timer counters 0 and 1 when setting software power
down mode
When setting sofware power down mode, if the value of a timer counter by which a timer
interrupt is set is immediately before overflow, the software power down mode can not be set.
(Example)
Timer 0 is in mode 1 of external clock.

Content of timer 0 is "FF".
Interrupt by timer 0 is enabled.
TO pin is "1".
If the above conditions all are established, the sofware power down mode cannot be set. This
is because the AND output, shown as (A) of Fig. 4-19, becomes "1" when the software power
down mode is set and timer interrupt is generated.
In this case, set the software power down mode after setting the TO pin to "0".
91
MSM80C154S/83C154S/85C154HVS
4.5.3 Timer/counter 2
4.5.3.1 Outline
Timer/counter 2 is equipped with 16-bit binary counting and Read/Write functions. This timer/
counter is controlled entirely by timer 2 control register (T2CON 0C8H).
The operating modes are 16-bit auto reload mode, capture mode, and baud rate generator
mode. Modes are specified by T2CON RCLK, TCLK, and CP/RL2 bits combinations.
The internal or external clock applied to the timer/counter 2 is specified by the C/T2 bit. And
starting and stopping of timer/counter 2 counting is controlled by the TR2 bit. Note that timer/
counter 2 counting is stopped in CPU power down mode where XTAL1·2 are stopped.
4.5.3.2 Timer 2 control register (T2CON)
The timer 2 control register (T2CON 0C8H) consists of the timer/counter 2 control bits, timer
2 internal flag (TF2), and timer 2 external flag (EXF2). The T2CON contents are outlined in
Table 4-12.
Table 4-12 Timer 2 control register (T2CON 0C8H)
Bit 7 6 5 4 3 2 1 0
Flag TF2 EXF2 RCLK TCLK EXEN2 TR2 C/ T2 CP/ RL2
CP/RL2 : Capture mode is set when TCLK+RCLK=0 and CP/RL2=1. The timer/counter
2 contents are passed to the capture register (RCAP2L/RCAP2H) when the
level o the signal applied to the T2EX pin (bit 1 of port 1) is changed from “1” to
“0” with EXEN2-1.
16-bit auto reload mode is set when TCLK+RCLK=0 and CP/RL2=0. The CP/
RL2 data is ignored when TCLK+RCLK=1.
C/T2 : Timer/counter 2 clock input designation bit.
The internal clock is specified when this bit is “0” and the external clock is
specified
when “1”.
TR2 : Timer/counter 2 counting start and stop control bit.
Timer/counter 2 operation is stopped when this bit is “0”, and enabled when “1”
EXEN2 : The T2EX pin control bit. The signal applied to the T2EX pin is invalid when this
bit is “0”, and valid when “1”.
TCLK : Serial port transmit clock control bit. When this bit is set to “1”, timer/counter 2
is set to 16-bit auto reload operation mode, and the timer/counter 2 carry signal
activates the serial port transmit circuit. This clock is only valid when serial port
mode 1 or 3 has been set.
RCLK : Serial port receive clock control bit. When this bit is set to “1”, timer/counter 2
is set to 16-bit auto reload operation mode, and the timer/counter 2 carry signal
activates the serial port receive circuit.
This clock is only valid when serial port mode 1 or 3 has been set.
92
EXF2 : Timer/counter 2 external flag bit which is set when the T2EX pin level (bit 1 of
port 1) is changed from “1” to “0” at EXEN2=1. This flag serves as the timer
interrupt 2 request signal. When an interrupt is generated, this flag must be reset
to “0” by software.
TF2 : Timer/counter 2 internal flag bit which is set when a carry signal is generated by
timer/counter 2 in 16-bit auto reload mode or capture mode. This flag serves as
the timer interrupt 2 request signal. When an interrupt is generated, this flag
must be reset to “0” by software.
4.5.3.3 Timer/counter 2 operation modes
Timer/counter 2 operation modes are set by combinations of the CP/RL2, TCLK, and RCLK
bits in timer 2 control register (T2CON 0C8H) shown in Table 4-13. The timer modes are listed
in Table 4-14.
Table 4-13 Timer 2 control register (T2CON 0C8H)
Bit 7 6 5 4 3 2 1 0
Flag TF2 EXF2 RCLK TCLK EXEN2 TR2 C/ T2 CP/ RL2
Set • • •
Table 4-14 Timer/counter 2 modes
RCLK TCLK CP/ RL2 TR2 Mode

0 0 0 1 16-bit auto reload
0 0 1 1 16-bit capture
RCLK + TCLK = 1 × 1 Baud rate generator
× × × 0 All operations stopped
4.5.3.3.1 16-bit auto reload mode
16-bit auto reload mode is set by making the circuit connection shown in Figure 4-20 by setting
RCLK=0, TCLK=0, and CP/RL2=0 as the bit conditions in timer 2 control register (T2CON).
Timer/counter 2 operates in the following way when 16-bit auto reload mode is set. When a
timer/counter 2 carry signal is generated, or when the signal applied to the T2EX pin (bit 1
of port 1) is changed from level “1” to “0”, the reload data in the RCAP2L and RCAP2H
registers is preset in L2 and TH2 of timer/counter 2. The timer/counter thus starts counting
from this preset value.
The timer/counter 2 carry signal is set in internal timer flag 2 (TF2), and the T2EX change is
set in external timer flag 2 (EXF2). The TF2 and EXF2 serve as the timer interrupt 2 request
signals with an interrupt call being made to address 43 (2BH) if the timer interrupt 2 has been
enabled. If an interrupt routine is commenced, the TF2 and EXF2 flags must be reset to “0”
by software.
93
MSM80C154S/83C154S/85C154HVS
S3
XTAL 1 ÷12
RCLK=0
TCLK=0
CP/ RL2=0
Q0------Q7 Q0------Q7
TL2 C TH2 C
C/ T2 8 BIT 8 BIT
TR2
T2
DETECTOR
[PORT 1.0] RCAP2L RCAP2H
DETECTOR TF2
T2EX
DETECTOR TIMER 2
[PORT 1.1] DETECTOR EXF2 INTERRUPT
EXEN2
Figure 4-20 Timer/counter 2 16-bit auto reload mode circuit
4.5.3.3.2 16-bit capture mode
The 16-bit capture mode is set by making the connections shown in Figure 4-21 with the
following timer 2 control register (T2CON) bit conditions, viz. RCLK=0, TCLK=0, and CP/
RL2=1.
Timer/counter 2 operates in the following way when 16-bit capture mode is set. When the
signal applied to the T2EX pin (bit 1 of port 1) is changed from level “1” to “0”, the TL2 and
TH2 count contents of timer/counter 2 are stored into capture registers RCAP2L and
RCAP2H. The T2EX signal change is set in external timer flag 2 (EXF2) at this time, and a
carry signal from timer/counter 2 is set in internal timer flag 2 (TF2). The EXF2 and TF2 serve
as the timer interrupt 2 request signals with an interrupt call being made to address 43 (2BH)
if timer interrupt 2 has been enabled. If an interrupt routine is commenced, the EXF2 and TF2
flags must be reset to “0” by software.
94
S3
XTAL 1 ÷12
RCLK=0
TCLK=0
CP/ RL2=1
Q0------Q7 Q0------Q7
TL2 C TH2 C
C/ T2 8 BIT 8 BIT
TR2
T2
DETECTOR
DETECTOR TF2
T2EX TIMER 2
DETECTOR DETECTOR EXF2 INTERRUPT
[PORT 1.1]
EXEN2
Figure 4-21 Timer/counter 2 16-bit capture mode circuit
4.5.3.3.3 16-bit baud rate generator mode
The 16-bit baud rate generator mode is set by making the connections shown in Figure 4-22
with the following timer 2 control register (T2CON) bit conditions, viz.
RCLK+TCLK=1.
Timer/counter 2 commences to operate in the following way when 16-bit baud rate generator
mode is set.
Timer/counter 2 is put into 16-bit auto reload mode. When timer/counter 2 generates a carry
signal, the reload data in the RCAP2L and RCAP2H registers is preset in the timer/counter
2 TL2 and TH2 and the timer/counter commences to count from that preset value. The carry
signal is passed to a serial port.
The timer/counter 2 carry signal activates the serial port receive circuit when RCLK 1, and
activates the transmit circuit when TCLK=1. Note, however, that the serial port can use these
clocks only when the serial port is in mode 1 and 3.
When in this mode, the timer/counter 2 carry signal is not set in internal timer flag 2 (TF2).
But since the change in level (from “1” to “0”) of the signal applied to the T2EX pin (bit 1 of
port 1) is set in external timer flag 2, the T2EX pin can be used for ordinary external interrupt
input pin. If an interrupt routine is commenced, the EXF2 flag must be reset to “0” by software.
Since timer/counter 2 is operated at 1/2 of the XTAL1·2 clock if the internal clock is used in
this mode, only undefined data will be read from the timer/counter 2 TL2 and TH2 by software.
Correct data, however, is read from the RCAP2L and RCAP2H registers.
95
MSM80C154S/83C154S/85C154HVS
SMOD[PCON bit 7] *RCLK+TCLK=1
CP/ RL2=×
TIMER 1 OVERFLOW
Figure 4-22 Timer/counter 2 baud rate generator mode circuit
÷16 RX CLOCK
[MODE1, 3]
÷2
S3
XTAL 1 ÷2
RCLK
Q0------Q7 Q0------Q7
TL2 C TH2 C
C/ T2 8 BIT 8 BIT
96
TR2
÷16 TX CLOCK
[MODE1, 3]
T2 DETECTOR
TCLK
T2EX DETECTOR DETECTOR EXF2 TIMER 2 INTERRUPT

[PORT 1.1]
EXEN2
4.5.3.4 Timer/counter 2 detector circuit
4.5.3.4.1 T2 (timer/counter 2 external clock detector)
The T2 detector circuit block diagram is shown in Figure 4-23. Operation of this circuit is
outlined below. When the level of the signal applied to T2 (bit 0 of port 1) is changed from “1”
to “0”, output of F/Fl becomes “1”. This output signal is then passed to F/F2 at S5 timing and
F/F2 output also becomes “1”. The T2 signal change passed to F/F2 is synchronized with the
S3 timing signal to become the external clock for timer/counter 2. At the same time, F/F1 is
reset and waits for the next external clock input. Note that the “0” and “1” level cycle times of
the external clock signal applied to the T2 pin must be at least 12 times (12T) the XTAL1·2
oscillator clock cycle time T.
1 F/F1 F/F2
VCC D Q D Q TIMER COUNTER 2
0
12T 12T CLOCK
S5 L
T2 R
[PORT 1.0] S3
RESET
Figure 4-23 Timer/counter 2 external clock detector circuit
4.5.3.4.2 T2EX (timer/counter 2 external flag input detector)
T2EX detector circuit block diagram is shown in Figure 4-24. Operation of this circuit is
outlined below. When the level of the signal applied to T2EX (bit 1 of port 1) is changed from
“1” to “0”, output of F/F1 becomes “1”. This output signal is then passed to F/F2 at S2 timing
and F/F2 output also becomes “1”. The T2EX signal change passed to F/F2 Q is synchronized
with the S4 timing signal to become the T2EX signal for timer/counter 2. At the same time,
F/Fl is reset and waits for the next T2EX input. Note that the “0” and “1” level cycle times of
the external clock signal applied to the T2EX pin must be at least 12 times (12T) the XTAL1·2
oscillator clock cycle time T.
1 F/F1 F/F2
VCC D Q D Q TIMER COUNTER 2
0
12T 12T T2EX
S2 L
T2EX R
[PORT 1.0] S4
RESET
Figure 4-24 Timer/counter 2 T2EX detector circuit
97
MSM80C154S/83C154S/85C154HVS
4.5.3.5 Timer/counter carry signal detector circuit
The detector circuit shown in Figure 4-25 is inserted between the MSM80C154S/ MSM83C154S
timer/counter carry output and the timer flag. The purpose of this detector is to prevent timer
flags being set by the timer carry signal during execution of OR, AND, EOR, RESET bit, SET
bit, or MOV bit instruction on the contents of the timer control register (TCON), and thereby
prevent loss of timer flags by manipulated data by the time execution of instruction has been
completed. Hence, even if a timer carry signal is generated during execution of an instruction,
that flag will not be set while the instruction is still being executed. The flag is set at M2·S1
during execution of the next instruction. If a timer carry is generated during M1 thru M3 when
executing a 4-machine cycle instruction, the timer flag is set during M3 or M4. See Figure 4-
26 for the time chart.
In case of driving the timer/counters 0 and 1 with the external clock in the power down mode
(PD, HPD), timer/counters 0 and 1 contents are incremented by falling edge of the external
clock. However, after counting the maximum value of timer/counters 0 and 1, carry signals
are generated and timer flags are set when the external clock level changes from “0” to “1“.
S I/O CLOCK
Timer/counter carry
S2
Timer flag
M2
S1
DETECTOR
PD & HPD
Figure 4-25 Timer/counter detector circuit
MACHINE CYCLE END M1
1
XTAL1
0
1
ALE
0
1
TIMER COUNT
0
1
TIMER CARRY
0
1
DETECTOR OUT
0
1
TIMER FLAG
0
Figure 4- 26 Timer flag setting time chart
98
4.6 Serial Port
4.6.1 Outline
MSM80C154S/MSM83C154S is equipped with a serial port which can be used in I/O

extension and UART (Universal Asynchronous Receiver/Transmitter) applications.
I/O extension mode

• Input and output of 8-bit serial data synchronized with the MSM80C154S/MSM83C154S
output clock.
UART mode
• Independent transmitter and receiver circuits for full duplex communication.
• Double buffer in receiver circuit to provide a 1-frame time margin in processing received
data.
• Selection of 10-bit and 11-bit frame lengths.
• Easier baud rate selection than in MSM80C31F/MSM80C51F
• Setting of different baud rates for transmitting and receiving possible Multi-processor
system applications possible in 11-bit frame mode Framing and overrun error detect
function
See Figure 4-27 for serial port block diagram.
99
MSM80C154S/83C154S/85C154HVS
INTERNAL BUS
MULTIPLEXER
SBUF (T)
TXD (P3.1)
TIMER/COUNTER1 SHIFT CLOCK
OVERFLOW
TIMER/COUNTER2 TX CONTROL
OVERFLOW
1/2OSC.
(PCON.7) (T2CON.4) (T2CON.5) (IOCON.5)
Figure 4-27 Serial port
SCON SMOD TCLK RCLK SERR

100
RX CONTROL
INPUT SHIFT
RXD (P3.0)
Note: REGISTER
: Internal bus connection MULTIPLEXER
: Serial data flow and

shift clock SBUF (R)
: Control coupling
4.6.2 Special function registers for serial port
4.6.2.1 SCON (Serial Port Control Register)
SCON is an 8-bit special function register consisting of control bits for specifying serial port
operation modes and enabling/disabling data reception, storage bits for the ninth data bit
transmitted and received during 11-bit frame UART mode, and the serial port status flag.
In addition to specifying SCON by data address 98H, each bit can be specified by bit
addresses.
The functions of each SCON bit are listed in Table 4-15, and the functions of each operational
mode specified by SCON are indicated in Table 4-16.
101
MSM80C154S/83C154S/85C154HVS
Table 4-15 SCON
Bit Symbol Function

0 RI "End of reception" flag. This is the interrupt request flag set by
hardware when reception of one frame has been completed. The
interrupt is generated by ORing with the T1 flag. Since the flag
cannot be cleared by hardware, it must be cleared by software.
1 TI "End of transmission" flag. This is the interrupt request flag set by
hardware when transmission of one frame has been completed.
The interrupt is generated by ORing with the RI flag.
Since the flag cannot be cleared by hardware, it must be cleared
by software.
2 RB8 Storage of the 9th bit of the data received during 11-bit frame
UART mode (mode 2 or 3). When in 10-bit frame UART mode
(mode 1), the stop bit is stored.
3 TB8 Storage of the 9th bit of the data to be sent during 11-bit frame
UART mode (mode 2 or 3).
4 REN Receive enable bit. Reception is not activated if REN is not set..
5 SM2 If SM2 is set when in 11-bit frame UART mode (mode 2 or 3) and
the 9th bit of the received data is "1", the received data is accepted
and loaded into SBUF and RB8, and the RI flag is set. If the 9th bit
of the received data is "0", on the other hand, the received data is
disregarded and the SBUF, RB8, and RI flags remain unchanged.
This function is used to enable communication between
processors in multi-processor systems.
If SM2 is set when in 10-bit frame UART mode (mode 1) and the
normal stop bit cannot be received (stop bit "0"), the received data
is disregarded, and the SBUF, RB8, and RI flags remain
unchanged. When SM2="0", however, the sent data is received
irrespective of the "0"/"1" status of the stop bit.
SM2 must be cleared when in I/O extension mode (mode 0).
6 SM1 Used in setting serial port operation mode. See Table 4-16.
7 SM0 Used in setting serial port operation mode. See Table 4-16.
102
Table 4-16 Serial port operation modes
SM0 SM1 Mode Function Baud rate

0 0 0 I/O extension 1/12 FOSC
0 1 1 10-bit frame UART Vareable
1 0 2 11-bit frame UART 1/32 FOSC or 1/64 FOSC
1 1 3 11-bit frame UART Vareable
Note: FOSC denotes frequency of fundamental oscillator (XTAL1·2).
4.6.2.2 SBUF (serial port buffer register)
SBUF is an 8-bit special function register used to store transmitting and receiving data.
Although the SBUF is specified by the same data address 99H for both writing and reading,
physically separate registers are specified. That is, the sending circuit SBUF is specified by
instructions where SBUF is used as a destination operand, and the receiving circuit SBUF
is specified by instructions where SBUF is used as a source operand.
4.6.2.3 TCLK
TCLK controls selection of the baud rate clock source for the transmitting circuit when in mode
1 or 3.
The timer/counter 2 overflow becomes the transmitting circuit baud rate clock source when
TCLK is set in mode 1 or 3. And the timer/counter 1 overflow becomes the transmitting circuit
baud rate clock source if TCLK is cleared.
TCLK has no effect on the baud rate clock source when in mode 0 or 2. TCLK is located at
bit 4 of T2CON (timer/counter 2 control register) specified by data address 0C8H. This bit can
also be specified by bit address 0CCH.
4.6.2.4 RCLK
RCLK controls selection of the baud rate clock source for the receiving circuit when in mode
1 or 3.
The timer/counter 2 overflow becomes the receiving circuit baud rate clock source when
RCLK is set in mode 1 or 3. And the timer/counter 1 overflow becomes the receiving circuit
baud rate clock source if RCLK is cleared.
RCLK has no effect on the baud rate clock source when in mode 0 or 2. RCLK is located at
bit 5 of T2CON (timer/counter 2 control register) specified by data address 0C8H. This bit can
also be specified by bit address 0CDH.
103
MSM80C154S/83C154S/85C154HVS
4.6.2.5 SMOD
SMOD controls the division of the baud rate clock source when the serial port is in UART mode
(mode 1, 2, or 3).
If SMOD is cleared when in mode 1 or 3, the timer/counter 1 overflow frequency divided by
2 becomes the baud rate clock source. And if SMOD is set, the timer/counter 1 overflow
becomes the baud rate clock source.
When TCLK is set in mode 1 or 3, however, and timer/counter 2 is the baud rate clock source
for the transmitting circuit, SMOD has no effect on the transmitting baud rate. And if RCLK
has been set, timer/counter 2 becomes the baud rate source for the receiving circuit, and
SMOD has no effect on the receiving baud rate.
If SMOD is cleared in mode 2, 1/2 OSC (oscillator frequency divided by 2) divided by 2
becomes the baud rate clock source. And if SMOD is set, 1/2 OSC becomes the baud rate
clock source.
SMOD is located at bit 7 of PCON (power control register) specified by data address 87H.
Designation by bit address is not possible.
See Table 4-17 for the corresponding baud rate clock sources for TCLK, RCLK, and SMOD.
Table 4-17 Corresponding baud rate clock sources for TCLK, RCLK, and SMOD
Mode TCLK or RCLK SMOD Baud rate colck source

0 X X MSM83C154S fundamental timing
0 0 T/C1 overflow divided by 2
1 0 1 T/C1 overflow
1 X T/C2 overflow
X 0 1/2 OSC divided by 2
2
X 1 1/2 OSC
0 0 T/C1 overflow divided by 2
3 0 1 T/C1 overflow
1 X T/C2 overflow
Note: X : Don't care
T/C1 : Timer/counter1
T/C2 : Timer/counter2
1/2 OSC : Oscillator frequency (XTAL1•2) divided by 2
104
4.6.2.6 SERR
SERR is the status flag set when a framing error or overrun error is generated during UART
mode (mode 1, 2, or 3).
Framing error:
The SERR flag is set when no stop bit is detected in UART mode. Framing error is
detected irrespective of the data reception conditions set by SM2.
Overrun error:
The SERR flag is also set when the next data is ready to be transferred from the input
shift register to the SBUF which is already full in UART mode. Note that an overrun error
is only detected when the data reception conditions set by SM2 have been satisfied.
Although the SERR flag is set by hardware when a framing or overrun error is
generated, it is not an interrupt request flag. The flag must be checked by software to
determine whether it has been set or not. The flag must also be cleared by software.
Since the SERR flag is set by the logical OR of framing and overrun errors, it is not
possible to determine whether the error is a framing or overrun error simply by checking
the flag.
SERR is located at bit 5 of IOCON (I/O control register) specified by data address
0F8H. This bit can also be specified by bit address 0FDH.
105
MSM80C154S/83C154S/85C154HVS
4.6.3 Operating modes
4.6.3.1 Mode 0
4.6.3.1.1 Outline
Mode 0 is the I/O extension mode where input and output of 8-bit data via RXD (P3.0) is
synchronized with the output clock from TXD (P3.1).
The baud rate in mode 0 is fixed to 1/12th of the fundamental oscillator (XTAL1·2) frequency
to enable the serial port to operate synchronized with the basic MSM80C154S/MSM83C154S
timing.
A block diagram of the mode 0 serial port is shown in Figure 4-28, the operational timing chart
is shown in Figure 4-29, and the serial port operation timing in relation to the basic
MSM80C154S/MSM83C154S timing is shown in Figure 4-30.
4.6.3.1.2 Mode 0 baud rate
In mode 0, the baud rate is determined by the following equation to synchronize operations
with the basic MSM80C154S/MSM83C154S timing.
1
B = FOSC ×
12
where B is baud rate, and FOSC is the fundamental (XTAL1·2) frequency.
4.6.3.1.3 Mode 0 transmit operation
Data output is commenced by writing data in SBUF.

The SBUF data is obtained sequentially from RXD about one machine cycle after completion
of the SBUF data writing instruction, the LSB appearing first.
Two states after commencing the LSB output, output of the TXD synchronized clock is
commenced. This synchronized clock is at level “0” from the latter half of S3 thru to the first
half of S6, and at “1” level from the latter half of S6 thru to the first half of S3. The transmit circuit
is initialized immediately following completion of output of the MSB, and the TI flag is set at
the first M1·S3 after that.
4.6.3.1.4 Mode 0 receive operation
Data input is commenced when REN=“1” and R1=“0” is achieved by an instruction used to
set REN or by an instruction used to clear the RI flag (or by an instruction which does both
simultaneously).
Output of the TXD synchronizing clock is commenced following nine states after REN=“1” and
R1=“0” is attained. The synchronized clock is at level “0” from the latter half of S3 thru to the
first half of S6, and at level “1” from the latter half of S6 thru to the first half of S3.
The RXD data is read sequentially into an input shift register in the serial port just before the
synchronized clock is changed from “0” to “1”.
When input of the 8-bit data is completed, loading of the input shift register data into SBUF
(with the LSB at the beginning of the input data) occurs at the same time that receiving circuit
is initialized. The RI flag is then set at the first M1·S3 after completion of input of the 8-bit data.
106
INTERNAL BUS
SHIFT
WRITE CLOCK
START SBUF (T) TXD
TO SBUF
ENABLE
Figure 4-28 Serial port (mode 0)
TI
SERIAL PORT
INTERRUPT
107
REN START RI
RXD
INPUT SHIFT REG.
SBUF (R)
INTERNAL BUS
S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4
ALE
WRITE TO SBUF
RXD D0 D1 D2 D3 D4 D5 D6 D7
TXD
TERMINATE TRANSMISSION
TI
MSM80C154S/83C154S/85C154HVS
108
S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4
ALE
WRITE TO SCON
REN·RI
READ RXD
TXD
SHIFT-IN CLOCK
LOAD SBUF
Figure 4-29 Serial port (mode 0) timing chart

RI
S6
S5
S4
S3
S2
S1
S6
S5
S4
S3
S2
S1
(DATA OUTPUT)
(SHIFT CLOCK)
(SHIFT CLOCK)
OUTPUT:
INPUT:
READ RXD
XTAL1
RXD
TXD
TXD
ALE
Figure 4-30 Serial port (mode 0) timing and corresponding basic MSM80C154S/
MSM83C154S timing
109
MSM80C154S/83C154S/85C154HVS
4.6.3.2 Mode 1
4.6.3.2.1 Outline
Mode 1 is the 10-bit frame UART mode (with one start bit, eight data bits, and one stop bit)
where the baud rate may be set to any value depending on the timer/counter 1 or timer/
counter 2 setting.
A block diagram of the serial port in mode 1 is shown in Figure 4-31, and the operational timing
chart is given in Figure 4-32.
The timer/counter 1 or timer/counter 2 overflow can be set as the baud rate clock source in
mode 1 by independent TCLK and RCLK setting for the transmit and receive circuits.
Where the baud rate is determined by the timer/counter 1 overflow, baud rate is determined
by the overflow frequency and SMOD value according to the following equations.
1 1
B = fTC1 × × (SMOD=0)
2 16
1
B = fTC1 × (SMOD=1)
16
where B is the baud rate and fTC1 is the timer/counter 1 overflow frequency.
When timer/counter 1 is used as a timer (internal clock) in auto reload mode (mode 2), the
baud rate is determined by the following equations.
1 1 1 1
B = fOSC × × × × (SMOD=0)
12 256-DTH1 2 16
1 1 1
B = fOSC × × × (SMOD=1)
12 256-DTH1 16
where B is the baud rate, fOSC the fundamental (XTAL1·2) frequency, and DTH1 the TH1
contents (expressed in decimal).
Where the timer/counter 2 overflow serves as the baud rate clock source, the baud rate is
determined by the overflow frequency irrespective of the SMOD value.
When timer/counter 2 is used as a counter (external clock), the baud rate is determined by
the following equation.
1 1
B = fT2 × ×
65536-DRCAP2 16
where B is the baud rate, fT2 the frequency of the clock applied to the T2 pin, and DRCAP2 the
contents of RCAP2L and RCAP2H (expressed in decimal).
Or if timer/counter 2 is used as a timer, the baud rate is determined in the following way.
110
1 1 1
B = fOSC × × ×
2 65536-DRCAP2 16
where B is the baud rate, fOSC the fundamental frequency (XTAL1·2), and DRCAP2 the
The transmit basic clock (TXCLOCK in Figure 4-31) is obtained from the overflow of a
hexadecimal free-run counter where the timer/counter 1 or timer/counter 2 overflow is used
as the clock.
Transmission is commenced when transmit data is written in SBUF.
The start bit, the eight SBUF data bits (with the LSB first), and the stop bit are transmitted
sequentially from TXD synchronized with the basic clock.
As soon as output of the eight data bits has been completed, the transmit circuit is initialized,
and the T1 flag is set at the first M1·S3 after the completion of that output.
The receive circuit timing is generated by a hexadecimal counter which uses the timer/
counter 1 or timer/counter 2 overflow as the clock, and the input data received from RXD is
bit synchronized. That is, at the same time that reception is started following input of the start
bit, the hexadecimal counter commences to count up, and with one complete round of the
hexadecimal counter corresponding to one bit of received data, reception is continued by the
receive circuit.
The RXD change from “1” to “0” is regarded as the beginning of the start bit for commence-
ment of reception.
When this “1” to “0” RXD change is detected, the hexadecimal counter which had been
stopped in reset status commences to count up. When the hexadecimal counter is in state
7, 8, and 9, the start bit is sampled, and is accepted as valid if at least two of the three sampled
values are “0”, thereby enabling data reception to continue. If two or three of the sampled
values are “1”, the start bit becomes invalid, and the receive circuit is initialized when the
hexadecimal counter reaches state 10.
The reception data is sampled when the hexadecimal counter is in state 7, 8, and 9, and the
more common value of the three sampled values is read sequentially as data into the input
shift register.
If the hexadecimal counter is in state 10 during the period of the next bit (that is, the stop bit)
after the eight bits of data have been received, and if the conditions stated below are satisfied,
the input shift register data (the LSB being read first) is loaded into SBUF, and the sampled
stop bit is read into RB8, thereby initializing the receive circuit. The RI flag is set at the first
M1·S3 after that.
Conditions: (1) RI=“0”
(2) SM2=“0”, or SM2=“1” and sampled stop bit=“0”
If the above conditions are not satisfied, the received data is disregarded, and the receive
circuit is initialized without change to the SBUF, RB8, and RI flags.
Since the receive circuit is double buffered (input shift register and SBUF), processing of the
previous receive data may be completed within the interval up to the stop bit period of the next
frame.
111
MSM80C154S/83C154S/85C154HVS
4.6.3.2.5 Mode 1 UART error detection
If the following two conditions are satisfied when the hexadecimal counter is in state 10 during
reception of the stop bit, it is assumed that new data is received before processing of the
previously received data has been completed. Hence, an overrun error is generated, and the
new data is lost. The SERR flag is set at the first M1·S3 after the hexadecimal counter has
reached state 10. Note that the previous SBUF (R) data is preserved.
(2) SM2=“0”, or SM2=“1” and sampled stop bit=“1”
And if the sampled stop bit is “0” when the hexadecimal counter is in state 10, it is assumed
that correct frame synchronization has not been achieved. Hence, a framing error is detected,
and the SERR flag is set at the first M1·S3 after that. Serial port reception is not effected by
the UART error detector circuit detecting an overrun or framing error and only the status flag
being set.
112
INTERNAL BUS
WRITE TXD
START SBUF (T)
TO SBUF
TCLK
BAUD RATE
TCLK=1 CLOCK
1/16
COUTER TI
TCLK=0
SERIAL PORT
INTERRUPT
113
START RI SERR
RXD
SAMPLE RXD
INPUT SHIFT REG. LOGIC
RCLK
BAUD RATE
SM2
RCLK=1 CLOCK
1/16 RECEIVE DATA
COUTER SBUF (R) REN
NEGLECT LOGIC
TIMER/COUNTER2 RCLK=0
OVERFLOW
SMOD
INTERNAL BUS
TIMER/COUNTER1 SMOD=1
OVERFLOW
1/2
SMOD=0
TX CLOCK
WRITE TO SBUF
TXD START BIT D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT

TI
M1·S3
MSM80C154S/83C154S/85C154HVS
114
RXD START BIT D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT
RX COUNTER RUN
RXD SAMPLE CLOCK
SHIFT-IN CLOCK
LOAD SBUF
TERMINATE RECEPTION
RI or SERR SET

M1·S3
4.6.3.3 Mode 2
4.6.3.3.1 Outline
Mode 2 is an 11-bit frame UART mode (with one start bit, eight data bits, one multipurpose
data bit, and one stop bit) where the baud rate is 1/64th or 1/32nd of the fundamental oscillator
(XTAL1·2) frequency.
Since the fundamental oscillator frequency divided by two serves as the baud rate clock
source in mode 2, the baud rate is determined by the SMOD value according to the following
equations.
1 1 1
B = fOSC × × × (SMOD=0)
2 2 16
1 1
B = fOSC × × (SMOD=1)
2 16
where B is the baud rate and fOSC the fundamental oscillator (XTAL1·2) frequency.
The transmit basic clock (TXCLOCK in Figure 4-34) is obtained from a hexadecimal free-run
counter overflow where the frequency of 1/2XTAL1·2 (fundamental oscillator frequency
divided by 2) divided by 2 (when SMOD=0) or the 1/2XTAL1·2 frequency (when SMOD=1)
is used as the clock.
Transmission is commenced when transmit data is written in SBUF. The start bit, the eight
SBUF data bits (with the LSB first), TB8, and the stop bit are transmitted sequentially from
the TXD synchronized with the basic clock.
As soon as the TB8 output has been completed, the transmit circuit is initialized, and the T1
flag is set at the first M1·S3 after the completion of that output.
The receive circuit timing is generated by a hexadecimal counter overflow where the
frequency of 1/2XTAL1·2 (fundamental oscillator frequency divided by 2) divided by 2 (when
SMOD=0) or the 1/2XTAL1·2 frequency (when SMOD=1) is used as the clock, and the input
data received from the RXD is bit synchronized. That is, at the same time that reception is
started following input of the start bit, the hexadecimal counter commences to count up, and
with one complete round of the hexadecimal counter corresponding to one bit of received
data, reception is continued by the receive circuit. Therefore, the reception data baud rate
must be equal to the period of a single round of the hexadecimal counter.
The RXD change from “1” to “0” is regarded as the beginning of the start bit where reception
is commenced.
115
MSM80C154S/83C154S/85C154HVS
The receive data is sampled when the hexadecimal counter is in state 7, 8, and 9, and the
shift register.
If the hexadecimal counter is in state 10 during the period of the next bit (that is, the multi-
purpose data bit) after the eight bits of data have been received, and if the conditions stated
below are satisfied, the input shift register data (the LSB being read first) is loaded into SBUF,
and the sampled multi-purpose data bit is read into RB8. And when the hexadecimal counter
is in state 10 during the period of the next after that (that is, the stop bit) the receive circuit
is initialized.
The RI flag is set at the first M1·S3 after that.
Conditions: (1) R1=“0”
(2) SM2=“0”, or SM2=“1” and sampled multi-purpose data bit=“1”
If the above conditions are not satisfied when the hexadecimal counter is in state 10 during
the multi-purpose data bit interval, the received data is disregarded, the SBUF, RB8, and RI
flags remain unchanged, and the receive circuit is initialized when the hexadecimal counter
is in state 10 during the stop bit interval.
previous receive data may by completed within the interval up to the multipurpose data bit
period of the next frame.
If the following two conditions are satisfied when the hexadecimal counter is in state 1 0 during
reception of a multi-purpose data bit, it is assumed that new data is received before
processing of the previously received data has been completed. Hence, an overrun error is
generated, and the new data is lost. The SERR flag is set at the first M1·S3 after the
hexadecimal counter has reached state 10 during the stop bit interval. Note that the previous
SBUF (R) data is preserved.
Conditions: (1) R1 =“1”
and the SERR flag is set at the first M1·S3 after that. Serial port reception is not effected by
the UART error detector circuit detecting an overrun or framing error and only the status flag
being set.
116
INTERNAL BUS
WRITE
START TBB SBUF (T) TXD
TO SBUF
SMOD
BAUD RATE
SMOD=1 CLOCK
1/2
1/16
XTAL1·2 COUTER TI
1/2
SMOD=0
SERIAL PORT
INTERRUPT
117
START RI SERR
RXD
SAMPLE
INPUT SHIFT REG. RXD
LOGIC
BAUD RATE
SM2
CLOCK
1/16 RECEIVE DATA
COUTER SBUF (R) REN
NEGLECT LOGIC
INTERNAL BUS
TX CLOCK
WRITE TO SBUF
TXD START BIT D0 D1 D2 D3 D4 D5 D6 D7 TBB STOP BIT

TI
MSM80C154S/83C154S/85C154HVS
M1·S3
118
RXD START BIT D0 D1 D2 D3 D4 D5 D6 D7 RBB STOP BIT
RX COUNTER RUN
RXD SAMPLE CLOCK
SHIFT-IN CLOCK
LOAD SBUF
TERMINATE RECEPTION
RI or SERR SET

M1·S3
4.6.3.4 Mode 3
4.6.3.4.1 Outline
Mode 3 is another 11-bit frame UART mode (with one start bit, eight data bits, one multi-
purpose data bit, and one stop bit). Whereas the baud rate is 1/64th or 1/32nd of the
fundamental oscillator frequency in mode 2, the mode 3 baud rate can be freely selected
according to the timer/counter 1 or timer/counter 2 setting. Apart from the ability to vary the
baud rate, mode 3 is identical to mode 2.
As in mode 1, the timer/counter 1 or timer/counter 2 overflow can be set as the baud rate clock
source in mode 3 by independent TCLK and RCLK setting for the transmit and receive
circuits.
Where the baud rate is determined by the timer/counter 1 overflow, baud rate is determined
by the overflow frequency and SMOD value according to the following equations.
1 1
B = fTC1 × × (SMOD=0)
2 16
1
B = fTC1 × (SMOD=1)
16
Where B is the baud rate and fTC1 is the timer/counter 1 overflow frequency.
When timer/counter 1 is used as a timer in auto reload mode (mode 2), the baud rate is
determined by the following equations.
1 1 1 1
B = fOSC × × × × (SMOD=0)
12 256-DTH1 2 16
1 1 1
B = fOSC × × × (SMOD=1)
12 256-DTH1 16
where B is the baud rate, fOSC the fundamental oscillator (XTAL1·2) frequency, and DTH1 the
TH1 contents (expressed in decimal).
Where the timer/counter 2 overflow serves as the baud rate clock source, the baud rate is
determined by the overflow frequency irrespective of the SMOD value.
When timer/counter 2 is used as a counter, the baud rate is determined by the following
equation.
1 1
B = fT2 × ×
65536-DRCAP2 16
where B is the baud rate, fT2 the frequency of the clock applied to the T2 pin, and DRCAP2 the
Or if timer/counter 2 is used as a timer, the baud rate is determined by the following way.
119
MSM80C154S/83C154S/85C154HVS
1 1 1
B = fOSC × × ×
2 65536-DRCAP2 16
where B is the baud rate, fOSC the fundamental oscillator (XTAL1·2) frequency, and DRCAP2
the contents of RCAP2L and RCAP2H (expressed in decimal).
The transmit basic clock (TXCLOCK in Figure 4-36) is obtained from a hexadecimal free-run
counter overflow where timer/counter 1 or timer/counter 2 overflow is used as the clock.
Transmission is commenced when transmit data is written in SBUF.
The start bit, the eight SBUF data bits (with the LSB first), TB8, and the stop bit are transmitted
sequentially from the TXD synchronized with the basic clock.
As soon as the TB8 output has been completed, the transmit circuit is initialized, and the T1
flag is set at the first M1·S3 after the completion of that output.
The receive circuit timing is generated by a hexadecimal counter overflow where timer/
counter 1 or timer/counter 2 overflow is used as the clock, and the input data received from
the RXD is bit synchronized. That is, at the same time that reception is started following input
of the start bit, the hexadecimal counter commences to count up, and with one complete
round of the hexadecimal counter corresponding to one bit of received data, reception is
continued by the receive circuit. Therefore, timer/counter 1 must be set so that the period of
a single round of the hexadecimal counter is equal to the reception data baud rate.
The RXD change from “1” to “0” is regarded as the beginning of the start bit where reception
is commenced.
The reception data is sampled when the hexadecimal counter is in state 7, 8, and 9, and the
shift register.
If the hexadecimal counter is in state 10 during the period of the next bit (that is, the multi-
purpose data bit) after the eight bits of data have been received, and if the conditions stated
below are satisfied, the input shift register data (the LSB being read first) is loaded into SBUF,
and the sampled multi-purpose data bit is read into RB8. And when the hexadecimal counter
is in state 10 during the period of the next after that (that is, the stop bit) the receive circuit
is initialized.
The RI flag is set at the first M1·S3 after that.
120
If the above conditions are not satisfied when the hexadecimal counter is in state 10 during
the multi-purpose data bit interval, the received data is disregarded, the SBUF, RB8, and RI
flags remain unchanged, and the receive circuit is initialized when the hexadecimal counter
is in state 10 during the stop bit interval.
previous receive data may be completed within the interval up to the multipurpose data bit
period of the next frame.
Mode 3 UART error detection is identical to mode 2 UART error detection.

If the following two conditions are satisfied when the hexadecimal counter is in state 10 during
reception of a multi-purpose data bit, it is assumed that new data is received before
processing of the previously received data has been completed. Hence, an overrun error is
generated, and the new data is lost. The SERR flag is set at the first M1·S3 after the
hexadecimal counter has reached state 10 during the stop bit interval. Note that the previous
SBUF (R) data is preserved.
Conditions: (1) RI =“1”
and the SERR flag is set at the first M1·S3 after that.
Serial port reception is not effected by the UART error detector circuit detecting an overrun
or framing error and only the status flag being set.
121
MSM80C154S/83C154S/85C154HVS
INTERNAL BUS
WRITE TXD
START SBUF (T)
TO SBUF
TCLK
BAUD RATE
TCLK=1 CLOCK
1/16
COUTER TI
TCLK=0
SERIAL PORT
INTERRUPT
122
START RI SERR
RXD
SAMPLE RXD
INPUT SHIFT REG. LOGIC
RCLK
BAUD RATE
SM2
RCLK=1 CLOCK
1/16 RECEIVE DATA
COUTER SBUF (R) REN
NEGLECT LOGIC
TIMER/COUNTER2 RCLK=0
OVERFLOW
SMOD
INTERNAL BUS
TIMER/COUNTER1 SMOD=1
OVERFLOW
1/2
SMOD=0
TX CLOCK
WRITE TO SBUF
TXD START BIT D0 D1 D2 D3 D4 D5 D6 D7 TBB STOP BIT

TI
M1·S3
123
RXD START BIT D0 D1 D2 D3 D4 D5 D6 D7 RBB STOP BIT
RX COUNTER RUN
RXD SAMPLE CLOCK
SHIFT-IN CLOCK
LOAD SBUF
TERMINATE RECEPTION
RI or SERR SET

M1·S3
MSM80C154S/83C154S/85C154HVS
4.6.4 Serial port application examples
4.6.4.1 I/O extension
I/O extension can be achieved by using the serial port in mode 0. An input extension example
is shown in Figure 4-37 and the corresponding timing chart is shown in Figure 4-38.
Following output of the latch pulse from PX.X, REN=“1” and R1=“0” are set for shift in of 74LS1
65 data.
MSM80C154S
MSM83C154S
RXD
VCC
QH SHIFT/ LOAD
SERIAL IN PX.X
CLOCK 74LS165
INHIBIT CK TXD
H G F E D C B A
INPUT
Figure 4-37 Input extension example
RX.X
TXD
74LS165-QH
Figure 4-38 Input extension example timing chart
124
An output extension example is shown in Figure 4-39 and the corresponding timing chart is
shown in Figure 4-40. After output data has been written into SBUF and the output sequence
completed, the latch pulse output from PX.X is obtained and the 74LS164 data is shifted to
74LS373.
OUTPUT
MSM80C154S
VCC MSM83C154S
8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q
74LS373
OC G PX.X
8D 7D 6D 5D 4D 3D 2D 1D
QHQG QF QE QDQC QB QA
B A RXD
74LS164
CLK CK TXD
Figure 4-39 Output extension example
RXD
TXD
PX.X
Figure 4-40 Output extension example timing chart
An input/output extension example is shown in Figure 4-41 and the corresponding timing
chart is shown in Figure 4-42. When input data is applied, INPUT CONTROL is changed from
“0” to “1”, and the parallel input is latched. This is then followed by REN=1 and RI=0 settings,
and shift in of 74LS165 data. INPUT CONTROL is returned to “0” after the input has been
completed. Since INPUT CONTROL is connected to the 74LS126 control pin, the
MSM80C154S/MSM83C154S switches the 74LS126 output to high impedance when
74LS165 input data is not being applied, thereby preventing collision between the 74LS126
and MSM80C154S/MSM83C154S outputs.
When output data is generated, and the output is completed after writing output data into
SBUF, an output latch pulse is generated from OUTPUT CONTROL, and the 74LS164 data
is transferred to 74LS373. Although the 74LS164 data is changed to parallel input data when
74LS165 data is passed to MSM80C154S/MSM83C154S, an output latch pulse is generated
only when output data is obtained from MSM80C154S/MSM83C154S, thereby preserving
the correct data in 74LS373.
125
MSM80C154S/83C154S/85C154HVS
OUTPUT
VCC
8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q
74LS373 OUTPUT
OC G PX.X CONTROL
8D 7D 6D 5D 4D 3D 2D 1D
MSM80C154S
MSM83C154S
QHQG QF QE QDQC QB QA
B A
74LS164
CLK CK
74LS126
RXD
VCC
QH SHIFT/ LOAD INPUT

SERIAL IN PX.X CONTROL
CLOCK 74LS165
INHIBIT CK TXD
H G F E D C B A
INPUT
Figure 4-41 Input/output extension example
126
MSM80C154S/MSM83C154S OUTPUT
OUTPUT
74LS165 OUTPUT
INPUT
CONTROL
CONTROL
OUTPUT
INPUT
RXD
TXD
In all examples, additional multiple bit I/O extension is made possible by multiple cascade
connections of 74LS164 or 74LS165.
Figure 4-42 lnput/output extension example timing chart
127
MSM80C154S/83C154S/85C154HVS
4.6.4.2 Multi-processor systems
Multi-processor systems can be formed with MSM80C154S/MSM83C154S by using the

serial port in mode 2 or mode 3 for inter-processor communications.
If reception data bit 9 (multi-purpose data bit) is “1” when SM2 is set in mode 2 or 3, reception
data is received and an interrupt is generated. If the data bit is “0”, however, the reception data
is disregarded and no interrupt is generated. This function is used in forming a multi-processor
system when more than one MSM80C154S/MSM83C154S device is coupled by serial bus.
An example of a multi-processor system with one master processor and a number of slave
processors is shown in Figure 4-43. In this example, data is transmitted only from master to
slave processors. Operation proceeds in accordance with the following protocol.
(1) Set SM2=“1”. All slave processors wait in standby for address data from the master
processor specifying which slave is to be selected.
(2) With TB8 set to “1” to distinguish address data from other data, the master processor
generates address data which ensures that data bit 9 (the multi-purpose data bit) is “1”.
(3) At this stage, all slave processors generate interrupts and check whether the received
address data has specified itself or not.
(4) The specified slave processor sets SM2 “0” to prepare for reception of the subsequent
data to be sent by the master processor.
Slave processors which are not specified remain at SM2=“1”
(5) With TB8=“0”, the master processor next sends data which ensures that data bit 9 (the
multi-purpose data bit) is “0” following the address data.
(6) Since the specified slave processor is changed to SM2=“0”, all data following the
address data is received and processed.
(7) The slave processors which are not specified (that is, where SM2=“1”) disregard all
data after the address data and wait in standby for the next address data.
(8) After transmitting all of the intended data the master processor transmits a final special
code (predetermined in advance).
(9) When this special code is received by the specified slave processor, SM2 is set to “1”
and that slave processor is again put into standby waiting for address data.
TXD RXD TXD RXD TXD RXD TXD RXD
MSM83C154S MSM83C154S MSM83C154S MSM83C154S
(MASTER) (SLAVE) (SLAVE) (SLAVE)
Figure 4-43 Multi-processor system example
128
4.7 Interrupt
4.7.1 Outline
MSM80C154S/MSM83C154S is equipped with six interrupts.

1. INT0 External interrupt 0
2. TM0 Timer interrupt 0
3. INT1 External interrupt 1
5. SI/O Serial port interrupt
These six interrupts are controlled by interrupt enable register (IE) and interrupt priority
register (IP). When the relevant interrupt conditions are met, the respective interrupt address
is called and the interrupt routine is commenced.
The interrupt addresses are listed in Table 4-18, and the interrupt control equivalent circuit
is shown in Figure 4-44.
Table 4-18 lnterrupt addresses
Interrupt source Interruput address

1 External interruput 0 3[0003hH]
2 Timer interruput 0 11[000BhH]
3 External interruput 1 19[0013hH]
5 Serial port interruput 35[0023hH]
MSM80C154S/83C154S/85C154HVS
INTERRUPT REQUEST INTERRUPT ENABLE INTERRUPT PRIORITY
FLAG REGISTER REGISTER REGISTER
SOURCE ENABLE
EX0 PX0
TCON.1 IE0 PI
EXTERNAL INTERRUPT 0
IE.0 NI
IP.0
INTERRUPT ADDRESS DATA
Figure 4-44 Interrupt control equivalent circuit
EX0 PT0
TCON.5 TF0 PI
INTERRPUT PRIORITY COMPARATOR

TIMER INTERRUPT 0
IE.0 NI
IP.1
EX0 PX1 NORMAL
TCON.3 IE1 PI I
EXTERNAL INTERRUPT 1 INTERRUPT
IE.0 NI
IP.2
EX0 PT1 HIGH PRIORITY
130
TCON.7 TF1 PI H D Q
INTERRUPT
TIMER INTERRUPT 1
IE.0 NI R
IP.3
SCON.0 RI EX0 PS CLOCK
PI
SCON.0 TI LOW PRIORITY
SERIAL PORT INTERRUPT IE.0 NI L D Q
IP.4 INTERRUPT
T2CON.7 TF2 EX0 PT2 R
PI
T2CON.6 EXF2 CLOCK
TIMER INTERRUPT 2 IE.0 NI
IP.5
VCC VCC
EA PCT
IE.7 IP.7
RETI
GLOBAL ENABLE
4.7.2 Interrupt enable register (IE)
The function of the interrupt enable register (IE, 0A8H) is to enable or disable interrupt
processes when an interrupt is requested.
To execute the intended interrupt routine, the interrupt is first enabled by setting “1” in the
corresponding interrupt bit in the interrupt enable register, and the routine then is executed
when the interrupt is requested.
Requested interrupts are disabled if the corresponding interrupt bit is “0”, and no interrupt
routines are executed.
The contents of the interrupt enable register (IE) are shown in Table 4-19.
Table 4-19 lnterrupt enable register (IE, 0A8H)
Bit 7 6 5 4 3 2 1 0
Flag EA — ET2 ES ET1 EX1 ET0 EX0
EX0 : External interrupt 0 control bit

Interrupt enabled when “1”, disabled when “0”.
ET0 : Timer interrupt 0 control bit
EX1 : External interrupt 1 control bit
ES : Serial port interrupt control bit
— : Reserve bit for output of “1” when read.
EA : Interrupt control bit for all six interrupts (EX0, ET0, EX1, ET1, ES, and ET2) When
EA is “1”, an interrupt routine is commenced if interrupt conditions are met for any
one of the six interrupts.
When EA is “0”, no interrupt routine is commenced even if interrupt conditions are
met for one of the six interrupts.
131
MSM80C154S/83C154S/85C154HVS
4.7.3 Interrupt priority register (IP)
The function of the interrupt priority register (IP, 0B8H) is to allocate rights to commence
interrupt routines on a priority basis when an interrupt is requested.
Interrupt priority can be programmed by setting the bit corresponding to the interrupt request
in the interrupt priority register (IP) to “1”. If the interrupt conditions have been satisfied for an
interrupt where “1” data has been set, processing of that interrupt is commenced. If another
interrupt (with “0” priority bit) is already being processed, that routine is suspended, and
processing of the higher priority interrupt is commenced. Note that once a priority interrupt
routine has been commenced, processing of the next interrupt cannot start until processing
of the current interrupt has been completed.
This priority circuit function can be stopped by setting “1” in bit 7 (PCT) of the priority register.
The functions of the priority interrupt control circuit are suspended, and interrupt control is
handled only by the interrupt enable register (IE 0A8H). After this mode has been set, the
interrupt disable instruction (CLR EA) must be placed at the beginning of interrupt routines
to disable the generation of other interrupts.
If another interrupt routine have to be generated during the processing of an interrupt routine,
set the desired interrupt enable bit in the interrupt enable register (IE 0A8H). The desired
interrupt routine is processed when the conditions for that routine are met. Multi-level interrupt
processing can thus be achieved by software control of the interrupt enable register.
The contents of the interrupt priority register are given in Table 4-20, and a priority interrupt
routine flow chart is shown in Figure 4-45. The flow chart for an interrupt routine when the
priority circuit is stopped (PCT=“1”) is shown in Figure 4-46.
Table 4-20 nterrupt priority register (IP, 0B8H)
Bit 7 6 5 4 3 2 1 0
Flag PCT — PT2 PS PT1 PX1 PT0 PX0
PX0 : External interrupt 0 priority bit.

Priority is allocated when this bit is “1”.
PT0 : Timer interrupt 0 priority bit.
PX1 : External interrupt 1 priority bit. Priority is allocated when this bit is “1”.
PT1 Timer interrupt 1 priority bit.
PS : Serial port interrupt priority bit
PT2 : Timer interrupt 2 priority bit.
— : Reserve bit for output of “1” when read.
PCT : Priority interrupt circuit control bit.
The priority interrupt control circuit is activated when this bit is “0”, and an interrupt
is processed on the priority basis (2 level interrupt processing).
The priority interrupt control circuit is stopped when this bit is “1”. In this case, all
interrupts are controlled by the interrupt enable register (IE) where multi-level
interrupt processing is possible by software management.
132
4.7.3.1 Priority interrupt routine flow
The flow of interrupt processing when a priority interrupt is generated and processed after a
routine has been commenced by a non-priority interrupt generated during execution of a main
routine program is outlined in Figure 4-45 below. This diagram shows the flow chart up to the
point of return to the main routine.
Start of non-priority interrput
M Start of non-priority interrput
Main routine
NI
PI
priority interrput routine

Generation
of interrput
Generation
of interrput
NI
M
RETI
Non-priority interrput routine
Main routine
RETI
Figure 4-45 Interrupt processing flow chart when priority circuit is activated
133
MSM80C154S/83C154S/85C154HVS
4.7.3.2 Interrupt routine flow when priority circuit is stopped
When bit 7 (PCT) of the priority register (IP 0B8H) is set to “1”, all interrupt control is transferred
to the interrupt enable register (IE 0A8H). When this mode is set, the interrupt disable
instruction (CLR EA) must always be placed at the beginning of the interrupt routine to prevent
any other interrupt from being generated. If another interrupt routine have to be generated
during the processing of an interrupt routine, set the desired interrupt enable bit in the interrupt
enable register (IE 0A8H) to commence the new interrupt routine. Multi-level interrupt
processing can thus be achieved by control of the interrupt enable register. The flow of this
interrupt routine is shown in Figure 4-46.
Main routine
CLREA CLREA CLREA CLREA

M
EA EA EA EA
Generation Generation Generation Generation

of interrput of interrput of interrput of interrput
EA
RETI RETI RETI RETI
M
Interrput routine
Main routine
Figure 4-46 lnterrupt routine flow chart when priority circuit is stopped
134
4.7.3.3 Interrupt priority when priority register (IP) contents are all “0”
The interrupt priority when the priority register (IP, 0B8H) contents are all “0” indicates the
priority in which a certain interrupt is processed in preference to other interrupts when
interrupt requests are generated simultaneously.
As can be seen from Table 4-21, the interrupt to be processed in preference to all other
interrupts is external interrupt 0, and the interrupt routine with lowest priority is timer interrupt
2.
The interrupt level when all priority bits are “0” is 1 level, and even if the interrupt conditions
for an external interrupt 0 (highest priority) are satisfied while timer interrupt 2 (lowest priority)
is being processed, the external interrupt cannot be processed.
The same operational preferences as described above also exist when all priority bits are “
1”.
Table 4-21 Non-priority interrupt order of preference
Order of preference Interrupt source

1 External interruput 0
2 Timer interruput 0
3 External interruput 1
5 Serial port interruput
135
MSM80C154S/83C154S/85C154HVS
4.7.4 Detection of external interrupt signals INT0 and INT1
4.7.4.1 Outline of INT signal detection
Detect modes of the external interrupt signals 0 and 1 can be set to level-detect or trigger-
detect mode by the IT0 and IT1 data values in the timer control register (TCON 88H) as
indicated in Table 4-22.
Table 4-22 TCON[88H] register
Timer INT1 INT0

Bit 7 6 5 4 3 2 1 0
Flag TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Set • •
4.7.4.2 External interrupt signal 0 and 1 level detection
When bit 0 (IT0) in the timer control register (TCON 88H) is “0”, external interrupt 0 is level-
activated. And when bit 2 (IT1) is “0”, external interrupt 1 is also level-activated. With the
external interrupt signals in level-detect mode, external interrupts 0 and 1 are level-detected
by the equivalent circuit shown in Figure 4-47.
When the level of the external interrupt pin is “0” at S5 timing, the level is latched and the Q
output becomes “1”. The latched external interrupt signal is set as the external interrupt flag
in the timer control register (TCON) at S3 timing. The interrupt flag set by external interrupt
signal is always reset at S6 timing of the end of the machine cycle, thereby executing the
equivalent of a “level sense” operation. The cycle width of the respective “0” and “1” levels
of the external interrupt signal applied to the external interrupt pin in this case must be at least
12 times (12T) the XTAL1·2 oscillator clock cycle time T.
And the external interrupt signal should be held at “0” level until the corresponding interrupt
is actually generated.
S3
IE0 or 1
INT0 or INT1 D Q S Q
S5 L RESET R
1
0
S6
12T 12T 12T
MEND
Figure 4-47 Interrupt level detect equivalent circuit for IT bit “0”
136
4.7.4.3 External interrupt signal 0 and 1 trigger detection
When bit 0 (IT0) in the timer Control register (TCON 88H) is “1”, external interrupt 0 is edge-
activated. And when bit 2 (IT1) is “1”, external interrupt 1 is also edge-activated. With the
external interrupt signals in trigger-detect mode, external interrupts 0 and 1 are trigger-
detected by the equivalent circuit shown in Figure 4-48. When the level of the external
interrupt pin is “0” at S5 timing, the level is latched at the first stage and the latched Q output
becomes “1”. The external interrupt signal stored in the first stage latch is transferred to the
second stage latch and is subject to digital differentiation until the S3 timing signal. The RS-
F/F in the next stage is set by the differentiated output signal.
The external interrupt signal applied to the RS-F/F is synchronized with the M2·S3 timing
signal to be applied as a trigger for the external interrupt flag in the timer control register
(TCON). The RS-F/F is subsequently reset at M2·S4 and waits for the next interrupt. Note that
the next interrupt signal is invalid until the first stage latch detects level “1” after detecting level
“0”.
The cycle width of the respective “0” and “1” levels of the external interrupt signal applied to
the external interrupt pin in this case must be at least 12 times (12T) the XTAL1·2 oscillator
clock cycle time T.
INT0 or INT1 D Q D
S5 L L Q
1
S3
0
12T 12T 12T
S4
IE0 or 1
S3 S Q
M2 BUS D
W TCON L
R
RESET
Figure 4-48 lnterrupt edge detect equivalent circuit for IT bit “1”
137
MSM80C154S/83C154S/85C154HVS
4.7.5 MSM80C154S/MSM83C154S interrupt response time charts
4.7.5.1 Interrupt response time chart when interrupt conditions are satisfied during
execution of ordinary instructions in main routine
If interrupt conditions are satisfied during execution of an ordinary instruction (which does not
manipulate IE or IP) in the main routine, the MSM80C154S/MSM83C154S calls the interrupt
address in the next cycle following completion of the ordinary instruction. The time chart is
given in Figure 4-49.
138
M1~M4 M1~M4
M1 M2
M1 or M2 M1 or M2
1-
XTAL1
0
1
ALE
0-
139
Instruction
execution Execution of one instruction Execution of one instruction Timer 1 interrput address call
execution of ordinary instruction in main routine

1-
Timer flag 1
0
Figure 4-49 lnterrupt response time chart when interrupt conditions are satisfied during
MSM80C154S/83C154S/85C154HVS
4.7.5.2 Interrupt response time chart when interrupt conditions are satisfied during
execution of IE or IP register operation instruction in main routine
If interrupt conditions are satisfied during execution of an instruction used to manipulate the
interrupt enable register (IE) or the interrupt priority register (IP) in the main routine, the
MSM80C154S/MSM83C154S reactivates the interrupt mask circuit in the next cycle follow-
ing completion of the register manipulation instruction. If interrupt conditions were met as a
result of the re-interrupt mask, the interrupt address is called in the next cycle. That is, if the
interrupt conditions are satisfied during execution of the IE or the IP manipulating instruction,
the interrupt address is called after the next instruction is executed following execution of the
register manipulating instruction. The time chart is given in Figure 4-50.
* In the MOV data address 1, data address 2 instructions, transfer of data to another register
from IE or IP is an exception. (example: MOV ACC, IE)
140
M1~M4
M1 or M2 M1 M2
M1 or M2
1-
XTAL1
0
1
ALE
0-
141
Instruction Execution of IE or IP
execution manipulation instruction Execution of one instruction Timer 1 interrput address call
1-
Timer flag 1
0
execution of IE or IP register manipulating instruction in main routine

Figure 4-50 Interrupt response time chart when interrupt conditions are satisfied during
MSM80C154S/83C154S/85C154HVS
4.7.5.3 Interrupt response time chart when an ordinary instruction is executed after
temporarily returning to the main routine from continuous interrupt
processing
If an ordinary instruction (which does not manipulate IE or IP) is executed after returning to
the main routine following execution of the interrupt routine end instruction RETI, and if the
next interrupt conditions have been met during execution of a previous interrupt routine, the
MSM80C154S/MSM83C154S calls the interrupt address in the next cycle following execu-
tion of one main routine instruction. The same occurs when interrupt conditions are satisfied
during execution of the first main routine instruction after returning to the main routine from
the interrupt routine. The time chart is shown in Figure 4-51.
142
M1~M4
M2 M1 M2
M1 or M2
1-
XTAL1
0
1
ALE
0-
143
Instruction Execution of one ordinary
execution RETI execution main routine instruction Timer 1 interrput address call
1
Timer flag 1
0
returning to main routine during continuous interrupt processing

Figure 4-51 Interrupt response time chart when ordinary instruction is executed after
MSM80C154S/83C154S/85C154HVS
4.7.5.4 Interrupt response time chart when an IE or IP manipulating instruction is

executed after temporarily returning to the main routine from continuous
interrupt processing
If the next interrupt conditions are satisfied during execution of an interrupt processing routine
and the interrupt terminating instruction RETI is then executed and followed by a return to the
main routine where an instruction which manipulates the interrupt enable register (IE) or
interrupt priority register (IP) is executed, the MSM80C154S/MSM83C154S activates the
interrupt mask circuit in the next cycle following execution of the register manipulating
instruction. And if interrupt conditions are met as a result of the re-interrupt mask, the interrupt
address is called in the next cycle. That is, if the instruction executed in the main routine
manipulates either IE or IP, the interrupt address is called after two instructions are executed.
The time chart is shown in Figure 4-52.
144
processing
M1~M4
M2 M1 or M2 M1
M1 or M2
1-
XTAL1
0
1
ALE
0-
145
Instruction Execution of IE or IP
execution RETI execution manipulation instruction Execution of one instruction Timer 1 interrput address call
1
Timer flag 1
0
executed after returning to main routine during continuous interrupt

Figure 4-52 Interrupt response time chart when IE or IP manipulating instruction is
MSM80C154S/83C154S/85C154HVS
4.8 CPU “Power Down”
4.8.1 Outline
Since the internal MSM80C154S/MSM83C154S circuits have been designed as completely

static circuits, all internal information (register data) is preserved if XTAL1·2 oscillation is
stopped.
This feature is utilized to incorporate a fuller range of power down modes.
In idle mode (IDLE) where “1” is set in bit 0 (IDL) of the power control register (PCON),
XTAL1·2 operation is continued but CPU operations are stopped. In soft power down mode
where “1” is set in bit 1 (PD) of the power control register (PCON), XTAL1·2 operation and
CPU operations are both stopped.
And in hard power down mode where “1” is set in advance in bit 6 (HPD) of the power control
register (PCON), XTAL1·2 and CPU operations are stopped when the level of the power
failure detect signal applied to the HPDI pin (P3.5) is changed from “1” to “0”.
If “1” is set in bit 0 (ALF) of the I/O control register (IOCON 0F8H) prior to activation of soft
and hard power down modes where CPU and XTAL1·2 operations are stopped, the port 0,
1, 2, and 3 outputs can be floated.
CPU power down modes can be released (CPU start-up) by CPU resetting, interrupt
generation, and interrupt source signal generation.
Execution can be recommenced from address 0, resumed from the interrupt address or from
the next address after the power down setting instruction.
4.8.2 Idle mode (IDLE) setting
Idle mode is set when “1” is set in bit 0 (IDL) of the power control register (PCON 87H). The
circuit connections involved in this setting are shown in Figure 4-53.
The idle mode cancellation conditions can be set through manipulation of bit 5 (RPD) of the
power control register. When “0” is set in RPD, idle mode cannot be cancelled by the interrupt
signal if the corresponding interrupt enable bit has not been set. And if “1” is set in RPD, idle
mode is cancelled by setting the interrupt flag and the program is executed from the next
address of the idle mode setting instruction, even when the corresponding interrupt enable
bit is not set.
In idle mode, the supply of clocks to the CPU control section is stopped and CPU operations
are halted. But since XTAL1·2 operations are maintained, the serial port, interrupt circuits,
and timer/counters 0, 1, and 2 remain operative.
The CPU pin status during idle mode is outlined in Table 4-23, and the corresponding time
charts for starting idle mode are shown in Figures 4-54 and 4-55.
146
XTAL 2 TIMER, S-I/O &

INTERRUPT
CPU CONTROL
CLOCK
XTAL 1
CONTROL
PCON, 87H
SMOD HPD RPD — GF1 GF0 PD IDL
Bit 7 6 5 4 3 2 1 0
Set * •
Figure 4-53 ldle mode equivalent circuit
147
MSM80C154S/83C154S/85C154HVS
Table 4-23 CPU pin details in idle mode

Name Internal ROM External ROM
P1.0/T2 Port data output Port data output
P1.1/T2EX Port data output Port data output
P1.2 Port data output Port data output
RESET “0” level input “0” level input
P3.0/RXD Port data output Port data output
P3.1/TXD Port data output Port data output
P3.2/ INT0 Port data output Port data output
P3.4/ T0 Port data output Port data output
P3.5/ T1/HPDI Port data output Port data output
P3.6/ WR Port data output Port data output
P3.7/RD Port data output Port data output
XTAL 2 Oscillator operative Oscillator operative
VSS 0 [V] 0 [V]
P2.0 Port data output Address 8 output
PSEN “1” level output “1” level output
ALE “1” level output “1” level output
EA “1” level input “0” level input
P0.7 Port data output Floating
VCC +2.2~+6 [V] +2.2~+6 [V]
148
M1 or M2 M1 M1 M1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
W-PCON
0
1
*PCON-bit 0
0
1
PORT 0 PORT DATA
0
1
PORT 1 PORT DATA
149
0
1
PORT 2 PORT DATA
0
1
PORT 3 PORT DATA
0
IDLE SET CYCLE IDLE MODE
Figure 4-54 Idle mode setting time chart (internal ROM mode)
M1 or M2 M1 M1 M1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
W-PCON
0
1
*PCON-bit 0
0
MSM80C154S/83C154S/85C154HVS
1 FLOATING
PORT 0 PCL PCL PCL
0
1
PORT 1 PORT DATA
150
0
1
PORT 2 PCH PCH PCH
0
1
PORT 3 PORT DATA
0
IDLE SET CYCLE IDLE MODE
Figure 4-55 Idle mode setting time chart (external ROM mode)
4.8.3 Soft power down mode (PD) setting
Soft power down mode (PD) is set when “1” is set in bit 1 (PD) of the power control register
(PCON 87H). The circuit connection involved in this setting is shown in Figure 4-56.
Soft power down mode cancellation conditions can be set through manipulation of bit 5 (RPD)
of the power control register.
When “0” is set in RPD, soft power down mode cannot be cancelled by the interrupt signal
if the corresponding interrupt enable bit has not been set. And if “1” is set in RPD, the power
down mode is cancelled by setting the interrupt flag and the program is executed from the next
address of the soft power down mode setting instruction, even when the corresponding
interrupt enable bit is not set. In soft power down mode, XTAL1·2 operations are halted. Then
with all internal data preserved, all CPU operations are stopped apart from timer/counters 0
and 1.
(Timer/counters 0 and 1 operate in external clock mode.)
Note, however, that the soft power down mode can not be set under the following conditions.
4.8.3.1 Caution about software power down mode setting
If the software power down mode can be cancelled by interruption and the following
conditions are established, the software power down mode cannot be set.
(1) If trying to set the software power down mode under the conditions that the mode can
be cancelled by external interrupt 0 or 1 and the INT0 or INT1 pin is set to "0" (either
level input or edge input).
(2) If trying to set the software power down mode under the conditions that the mode can
be cancelled by timer 0 or 1 (external clock mode is set) and the T0 or T1 pin is set to
"1" when the value of the counter is "FF".
Figures 4-57, 4-58, and 4-59 show power down cancellation circuits by external interrupt or
timer interrupt.Note, however, that the soft power down mode can not be set under the
following conditions.
The pin output status of ports 0 thru 3 in soft power down mode can be left in port data output
status, or set to port output floating status.
The ports are set to data output status by setting bit 0 (ALF) of the I/O control register (IOCON)
to “0” when soft power down mode is activated, and to floating status by setting ALF to “1”
before activating power down mode. In floating status, the port pins are disconnected
electrically from the external circuitry. Apart from pins 2,3, 4, and 5 of port 3, all floating status
input port pins may be open, or undefined within the –0.5 to VCC+0.5V range.
The CPU pin status during soft power down mode (PD) with “0” on the ALF bit is /outlined in
Table 424, and the corresponding time charts for starting soft power down mode are shown
in Figures 4-60 and 4-61.
The CPU pin status during soft power down mode with “1” on the ALF bit is outlined in Table
4-25, and the corresponding time charts for starting soft power down mode are shown in
Figures 4-62 and 4-63.
151
MSM80C154S/83C154S/85C154HVS
XTAL 2
CPU CLOCK
Figure 4-56 Soft power down mode equivalent circuit
XTAL 1
CONTROL I/O FLOATING

152
PCON 87H
Bit 7 6 5 4 3 2 1 0
Set * •
IOCON 0F8H
— T32 SERR IZC P3HZ P2HZ P1HZ ALF
Bit 7 6 5 4 3 2 1 0
Set •
PD
PCON5(RPD)
S3
IE0 or 1
PDRESET
INT0 or INT1 D Q S Q
S5 L RESET R
S6
M END
Figure 4-57 Power down cancellation circuit at INTERRUPT level input
INT0 or INT1 D Q D
S5 L L Q
S3
PCON5(RPD)
PD
S4 IE0 or 1
PDRESET
S3 S Q
BUS D
S2
W TCON LR
RESET
Figure 4-58 Power down cancellation circuit at INTERRUPT edge input
153
MSM80C154S/83C154S/85C154HVS
F/F1 F/F2 TIMER0, 1

VCC D Q D Q C
F/F1 F/F2
L SQ PDRESET
T0 or T1 R
S5 S3 RESET R
RESET TF0 or 1
PD
PCON5(RPD)
Figure 4-59 TIMER0, 1 power down cancellation circuit
154
Table 4-24 CPU pin details (ALF=0) in soft power down mode (PD)

P3.5/ T1/HPDI Port data output Port data output
P3.7/RD Port data output Port data output
VSS 0 [V] 0 [V]
VCC *+2.0~+6 [V] *+2.0~+6 [V]
* VCC=+2.0~+6V when internal CPU data is held.
155
M1 or M2 M1
S6 S1 S2 S3 S4 S5 S6 S1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
IOCON-bit 0
0
1
W-PCON
0
MSM80C154S/83C154S/85C154HVS
1
*PCON-bit 1
0
PORT 0 PORT DATA PORT DATA
156
1
0
1
0
1
0
PD SET CYCLE SOFT POWER DOWN MODE
*ALF=“0”
Figure 4-60 Soft power down mode setting time chart (internal ROM mode)
M1 or M2 M1
S6 S1 S2 S3 S4 S5 S6
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
IOCON-bit 0
0
1
W-PCON
0
1
*PCON-bit 1
0
1 FLOATING
PORT 0 PCL PCL PCL
157
0
1
0
1
PORT 2 PCH PCH PCH PORT DATA PORT DATA
0
1
0
*ALF=“0”
Figure 4-61 Soft power down mode setting time chart (external ROM mode)
MSM80C154S/83C154S/85C154HVS
Table 4-25 CPU pin details (ALF=1) in soft power down mode (PD)

P1.0/T2 Floating Floating
P1.1/T2EX Floating Floating
P1.2 Floating Floating
P3.0/RXD Floating Floating
P3.1/TXD Floating Floating
P3.2/ INT0 External data input External data input
P3.4/ T0 External data input External data input
P3.5/ T1/HPDI External data input External data input
P3.6/ WR Floating Floating
P3.7/ RD Floating Floating
VSS 0 [V] 0 [V]
VCC *+2.0~+6 [V] *+2.0~+6 [V]
158
M1 or M2 M1
S6 S1 S2 S3 S4 S5 S6 S1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
IOCON-bit 0
0
1
W-PCON
0
1
PCON-bit 1
0
1 FLOATING
*PORT 0 PORT DATA
159
0
1 FLOATING
PORT 1 PORT DATA
0
1 FLOATING
PORT 2 PORT DATA
0
1 FLOATING
PORT 3 PORT DATA
0
*ALF=“1”
Figure 4-62 Soft power down mode setting and I/O floating time chart (internal ROM mode)
M1 or M2 M1
S6 S1 S2 S3 S4 S5 S6 S1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
IOCON-bit 0
0
1
W-PCON
0
MSM80C154S/83C154S/85C154HVS
1
*PCON-bit 1
0
1 FLOATING
PORT 0 PCL PCL PCL
160
0
1 FLOATING
PORT 1 PORT DATA
0
1 FLOATING
PORT 2 PCH PCH PCH
0 PORT DATA
1 FLOATING
PORT 3 PORT DATA
0
*ALF=“1”
Figure 4-63 Soft power down mode setting and I/O floating time chart (external ROM mode)
4.8.4 Hard power down mode (HPD) setting
To set hard power down mode (HPD), “1” is set in bit 6 (HPD) of the power control register
(PCON 87H) in advance to attain the circuit connections shown in Figure 4-61. Hard power
down mode is set when the level of the power failure detect signal applied to the HPDI pin
(bit 5 of port 3) is changed from level “1” to level “0”. XTAL1·2 operations are stopped in this
mode. And while all internal data is retained, the CPU operations also are stopped apart from
timer/counter 0 and 1. (Timer/counters 0 and 1 operate in external clock mode.)
The pin output status of ports 0 thru 3 in hard power down mode can be left in port data output
status, or set to port output floating status.
The ports are set to data output status by setting bit 0 (ALF) of the I/O control register (IOCON
0F8H) to “0” when hard power down mode is activated, and to floating status by setting ALF
to “1” before activating power down mode. In floating status, the port pins are disconnected
electrically from the external circuitry.
Apart from pins 2, 3, 4, and 5 of port 3, all floating status input port pins may be open, or
undefined within the –0.5 to VCC+0.5 V range.
The CPU pin status during hard power down mode (HPD) with “0” on the ALF bit is outlined
in Table 4-26, and the corresponding time charts for starting hard power down mode are
And the CPU pin status during hard power down mode (HPD) with “1” on the ALF bit is outlined
in Table 4-27, and the corresponding time charts for starting hard power down mode are
161
MSM80C154S/83C154S/85C154HVS
XTAL 2
CPU CLOCK
Figure 4-64 Hard power down mode equivalent circuit
XTAL 1
HPDI
CONTROL I/O FLOATING
162
PCON 87H
Bit 7 6 5 4 3 2 1 0
Set • •
IOCON 0F8H
— T32 SERR IZC P3HZ P2HZ P1HZ ALF
Bit 7 6 5 4 3 2 1 0
Set •
Table 4-26 CPU pin details (ALF=0) in hard power down mode (HPD)

P3.5/ T1/HPDI “0” level input “0” level input
P3.7/ RD Port data output Port data output
VSS 0 [V] 0 [V]
VCC *+2.0~+6 [V] *+2.0~+6 [V]
163
M1 or M2 M1
S6 S1 S2 S3 S4 S5 S6 S1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
IOCON-bit 0
0
1
*HPDI [P3.5]
0
MSM80C154S/83C154S/85C154HVS
1
PCON-bit 6
0
1
164
0
1
0
1
0
1
0
HPD SET CYCLE HARD POWER DOWN MODE
*ALF=“0”
Figure 4-65 Hard power down mode setting time chart (internal ROM mode)
M1 or M2 M1
S6 S1 S2 S3 S4 S5 S6 S1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
IOCON-bit 0
0
1
*HPDI [P3.5]
0
1
PCON-bit 6
0
1 FLOATING
PORT 0 PCL PCL PCL
165
0
1
0
1
PORT 2 PCH PCH PCH PORT DATA PORT DATA
0
1
0
*ALF=“0”
Figure 4-66 Hard power down mode setting time chart (external ROM mode)
MSM80C154S/83C154S/85C154HVS
Table 4-27 CPU pin details (ALF=1) in hard power down mode (HPD)

P1.0/T2 Floating Floating
P1.1/T2EX Floating Floating
P3.0/RXD Floating Floating
P3.1/TXD Floating Floating
P3.4/ T0 External data input External data input
P3.5/ T1/HPDI “0” level input “0” level input
P3.6/ WR Floating Floating
P3.7/ RD Floating Floating
VSS 0 [V] 0 [V]
VCC *+2.0~+6 [V] *+2.0~+6 [V]
166
M1 or M2 M1
S6 S1 S2 S3 S4 S5 S6 S1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
IOCON-bit 0
0
1
*HPDI [P3.5]
0
1
PCON-bit 6
0
1 FLOATING
PORT 0 PORT DATA
167
0
1 FLOATING
PORT 1 PORT DATA
0
1 FLOATING
PORT 2 PORT DATA
0
1 FLOATING
PORT 3 PORT DATA
0
*ALF=“1”
Figure 4-67 Hard power down mode setting and I/O floating time chart (internal ROM mode)
M1 or M2 M1
S6 S1 S2 S3 S4 S5 S6 S1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
IOCON-bit 0
0
1
*HPDI [P3.5]
0
MSM80C154S/83C154S/85C154HVS
1
PCON-bit 6
0
1 FLOATING
PORT 0 PCL PCL PCL
168
0
1 FLOATING
PORT 1 PORT DATA
0
1 FLOATING
PORT 2 PCH PCH PCH
0 PORT DATA
1 FLOATING
PORT 3 PORT DATA
0
*ALF=“1”
Figure 4-68 Hard power down mode setting andl/Of loating time chart (external ROM mode)
4.9 CPU Power Down Mode (IDLE, PD, and HPD) Cancellation (CPU Activation)
4.9.1 Outline
CPU power down mode (IDLE, PD, and HPD) can be cancelled (CPU activation) in the
following two ways.
The CPU is reset when a “1” reset signal is applied to the CPU RESET pin, and the program
is executed from address 0. This method can be used in IDLE, PD, and HPD modes.
By generating the respective interrupt source signals, the program can be executed from the
interrupt address, and can also be continued from the next address after the stop address.
This method can be used in IDLE and PD modes.
4.9.2 Cancellation by CPU resetting (RESET pin)
The CPU is reset when a “1” level signal is applied (for at least 1µAsec.) to the CPU RESET
pin, and the CPU power down mode (IDLE, PD, or HPD) is cancelled. Programs are
subsequently executed by the CPU from address 0. The reset cancellation time charts are
outlined in Figures 4-69 thru 4-74.
169
M1 → M2 M1 → M2 M1 M1
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
PCON-bit 0
0
1
*RESET
0
MSM80C154S/83C154S/85C154HVS
CPU RESET 1
CONTROL 0
PORT 0
170
0
1
PORT 1 PORT DATA PORT DATA=1
0
1
0
1
0
RESET CYCLE EXECUTE CYCLE
IDLE MODE
Figure 4-69 Restart from idle mode by reset (internal ROM mode)
M1 M1 → M2 M1 M1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
*RESET
0
CPU RESET 1
CONTROL 0
1
PCON-bit 0
0
1 FLOATING
PORT 0 PCL PCL PCL
171
0
1
0
1
PORT 2 PCH PORT DATA=1 PCH PCH PCH
0
1
0
IDLE MODE RESET CYCLE EXECUTE CYCLE
Figure 4-70 Restart from idle mode by reset (external ROM mode)
M1 → M2 M1 → M2 M1 M1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
PCON-bit 1
0
1
*RESET
0
MSM80C154S/83C154S/85C154HVS
CPU RESET 1
CONTROL 0
PORT 0
172
0
1
0
1
0
1
0
SOFT POWER DOWN MODE
Figure 4-71 Restart from soft power mode by reset (internal ROM mode)
M1 → M2 M1 → M2 M1 M1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
PCON-bit 1
0
1
*RESET
0
CPU RESET 1
CONTROL 0
1 FLOATING
PORT 0 PCL PCL PCL
173
0
1
0
1
PORT 2 PORT DATA PORT DATA=1 PCH PCH PCH
0
1
0
Figure 4-72 Restart from soft power mode by reset (external ROM mode)
M1 → M2 M1 → M2 M1 M1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
IOCON-bit 0
0
1
HPDI[P3.5]
0
MSM80C154S/83C154S/85C154HVS
1
*RESET
0
CPU RESET 1
174
CONTROL 0
1
PCON-bit 6
0
1 PORT FLOATING FLOATING
PORT 0
0
1
PORT 1 PORT FLOATING PORT DATA=1
0
1
0
1
0
HARD POWER DOWN MODE
Figure 4-73 Restart from hard power down mode by reset (internal ROM mode)
M1 → M2 M1 → M2 M1 M1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
IOCON-bit 0
0
1
HPDI[P3.5]
0
1
*RESET
0
CPU RESET 1
175
CONTROL 0
1
PCON-bit 6
0
1 PORT FLOATING FLOATING
PORT 0 PCL PCL PCL
0
1
0
1
PORT 2 PORT FLOATING PORT DATA=1 PCH PCH PCH
0
1
0
HARD POWER DOWN MODE
Figure 4-74 Restart from hard power down mode by reset (external ROM mode)
MSM80C154S/83C154S/85C154HVS
4.9.3 Cancellation of CPU power down mode (IDLE, PD) by interrupt signal
When idle mode (IDLE) and soft power down mode (PD) are cancelled by interrupt signal,
power down mode cancellation condition is determined by bit 5 (RPD) of the power control
register (PCON 87H) shown in Table 4-29.
When RPD is “0”, power down mode can be cancelled by interrupt signal and CPU executes
program from the interrupt address only when the CPU has been set to interrupt enable
status.
And when RPD is “1”, power down mode can be cancelled and resumes execution from the
next address after the stop address if “1” is set in the interrupt flag by interrupt signal even
when the CPU is in interrupt disable mode.
The conditions for cancellation of power down mode by interrupt signal can thus be specified
by the RPD content.
Table 4-29 Power control register (PCON 87H)

Bit 7 6 5 4 3 2 1 0
Set •
4.9.3.1 Cancellation of CPU power down mode (IDLE, PD) from interrupt address
To cancel idle mode (IDLE) or soft power down mode (PD) and resume execution from the
interrupt address, an interrupt is specified in the interrupt enable register (IE 0A8H) prior to
setting CPU power down mode and “0” is set in bit 5 (RPD) of the power control register
(PCON 87H).
All six interrupts can be used to cancel idle mode. The interrupt conditions are satisfied when
“1” is set in the specified interrupt flag in TCON, T2CON, or SCON. Clock signals are then
passed to the CPU, and execution is commenced from the interrupt address.
Soft power down mode (PD) can be cancelled by four different interrupts - external interrupts
0 and 1, and timer interrupts 0 and 1. (Timer/counters 0 and 1 are operated in external clock
mode.)
The external interrupts are generated by “0” level being applied to either the INT0 or INT1 pin.
When the specified interrupt flag in TCON is set to “1” to satisfy the interrupt conditions,
XTAL1·2 operation is commenced, and the program is executed from the interrupt address.
When the interrupt routine is completed, the program returns to the next address after the stop
address.
If all interrupts have been disabled, however, CPU power down mode cannot be cancelled
from the interrupt address by this method. A “1” reset signal must be applied to the RESET
pin and execution commenced from address 0 in this case. The equivalent circuit involved
in CPU power down mode cancellation by interrupt is shown in Figure 4-75, and the CPU
power down mode (PD, HPD) cancellation time charts are shown in Figures 4-76 thru 4-79.
176
IE0 [TCON.1]
IE.0
TF0 [TCON.5]
IE.1
IE1 [TCON.3]
IE.2
IDLE, PD MODE
TF1 [TCON.7]
INTERRUPT &
IE.3 RESTART
RI/TI [SCON.0, 1]
IE.4
EXF2/TF2[T2CON.6, 7]
IE.5
IE.7
Figure 4-75 Equivalent circuit for, DLE and PD mode rancellation by interrupt signal
177
M1 M1 M1 M2
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
*INT0 or INT1
0
IE0 or IE1 1
OUT 0
MSM80C154S/83C154S/85C154HVS
1
PCON-bit 0
0
1 PORT DATA
PORT 0
178
0
1
PORT 1 PORT DATA
0
1
PORT 2 PORT DATA
0
1
PORT 3 PORT DATA
0
IDLE MODE WASTE CYCLE INTERRUPT EXECUTE CYCLE
Figure 4-76 Restart from idle mode by interrupt INT0 or 1 (internal ROM mode)
M1 M1 M1 M2
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
*INT0 or INT1
0
IE0 or IE1 1
OUT 0
1
PCON-bit 0
0
1 FLOATING
PORT 0 PCL PCL PCL PCL PCL
179
0
1
PORT 1 PORT DATA
0
1
PORT 2 PCH PCH PCH PCH PCH
0
1
PORT 3 PORT DATA
0
Figure 4-77 Restart from idle mode by interrupt INT0 or 1 (external ROM mode)
M1 M1 M2 M1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
*INT0 or INT1
0
IE0 or IE1 1
OUT 0
MSM80C154S/83C154S/85C154HVS
1
PCON-bit 1
0
1
PORT 0 PORT DATA
180
0
1
PORT 1 PORT DATA
0
1
PORT 2 PORT DATA
0
1
PORT 3 PORT DATA
0
WASTE CYCLE INTERRUPT EXECUTE CYCLE EXECUTE CYCLE
Figure 4-78 Restart from soft power down mode by Interrupt INT0 or 1 (internal ROM mode)
M1 M1 M2 M1
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
*INT0 or INT1
0
IE0 or IE1 1
OUT 0
1
PCON-bit 1
0
1
PORT 0 PCL PCL PCL PCL PCL PCL PCL
181
0
1
PORT 1 PORT DATA
0
1
PORT 2 PCH PCH PCH PCH PCH PCH PCH PCH
0
1
PORT 3 PORT DATA
0
WASTE CYCLE INTERRUPT EXECUTE CYCLE EXECUTE CYCLE
Figure 4-79 Restart from soft power down mode by interrupt INT0 or 1 (external ROM mode)
MSM80C154S/83C154S/85C154HVS
4.9.3.2 Cancellation of CPU power down mode (IDLE, PD) by interrupt request signal
and restart from next address of stop address
To cancel idle mode (IDLE) or soft power down mode (PD) by interrupt request signal and
then resume execution from the next address after the stop address, “1” is set in bit 5 (RPD)
of the power control register. When “1” is set in this bit, the circuit connections shown in Figure
4-80 are made, and the CPU power down mode is cancelled when the interrupt flag has been
set to “1”, even if the entire contents of the interrupt enable register (IE 0A8H) have been put
into interrupt disable status.
All six interrupt sources can be used to cancel idle mode (IDLE). If an interrupt source is
generated and “1” is set in one of the interrupt flags in TCON, T2CON, or SCON, clock signals
are passed to the CPU control stage, and execution is resumed from the next address after
the stop address.
Soft power down mode (PD) can be cancelled by four different interrupt sources - external
interrupts 0 and 1 , and timer interrupts 0 and 1. The external interrupt flag is set by “0” level
being applied to either the INT0 or INT1 pin. And timer/counters 0 and 1 are used in external
clock mode. When one of the interrupt flags in TCON is set to “1”, XTAL1·2 operation is
commenced, and the program is executed from the next address after the stop address.
Note, however, that the interrupt flags are reset by software. The cancellation time charts are
shown in Figures 4-81 thru 4-84.
IE0 [TCON.1]
TF0 [TCON.5]
IE1 [TCON.3]
IDLE, PD MODE
TF1 [TCON.7] RESTART
RI/TI [SCON.0, 1]
EXF2/TF2 [T2CON.6, 7]
*MODE SET
Bit 7 6 5 4 3 2 1 0
Set • * *
Figure 4-80 Equivalent circuit for power down mode cancellation and restart by interrupt
source signal
182
M1 M1 M1 M2
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
*INT0 or INT1
0
EDGE SENSE
IE0 or IE1 1
OUT 0 LEVEL SENSE
1
PCON-bit 0
0
1 PORT DATA
PORT 0
183
0
1
PORT 1 PORT DATA
0
1
PORT 2 PORT DATA
0
1
PORT 3 PORT DATA
0
Figure 4-81 Restart from idle mode by INT0 or 1 (internal ROM mode)
M1 M1 M1 M2
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
INT0 or INT1
0
EDGE SENSE
*IE0 or IE1 1
OUT 0 LEVEL SENSE
MSM80C154S/83C154S/85C154HVS
1
PCON-bit 0
0
1 FLOATING
184
0
1
PORT 1 PORT DATA
0
1
PORT 2 PCH PCH PCH PCH PCH
0
1
PORT 3 PORT DATA
0
Figure 4-82 Restart from idle mode by INT0 or 1 (external ROM mode)
M1 M1 M1
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
INT0 or INT1
0
EDGE SENSE
IE0 or IE1 1
OUT 0 LEVEL SENSE
1
PCON-bit 1
0
1 FLOATING
PORT 0 PORT DATA
185
0
1 FLOATING
PORT 1 PORT DATA
0
1 FLOATING
PORT 2 PORT DATA
0
1 FLOATING
PORT 3 PORT DATA
0
SOFT POWER DOWN MODE WASTE CYCLE EXECUTE CYCLE EXECUTE CYCLE
Figure 4-83 Restart from soft power down mode by INT0 or 1 (internal ROM mode)
M1 M1 M1
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
1
XTAL1
0
1
ALE
0
1
PSEN
0
1
*INT0 or INT1
0
EDGE SENSE
IE0 or IE1 1
OUT 0 LEVEL SENSE
MSM80C154S/83C154S/85C154HVS
1
PCON-bit 1
0
1 FLOATING
186
0
1 FLOATING
PORT 1 PORT DATA
0
1 FLOATING
PORT 2 PORT DATA PCH PCH PCH PCH PCH
0
1 FLOATING
PORT 3 PORT DATA
0
SOFT POWER DOWN MODE WASTE CYCLE EXECUTE CYCLE EXECUTE CYCLE
Figure 4-84 Restart from soft power down mode by INT0 or 1 (external ROM mode)
4.10 MSM80C154S/83C154S Battery Backup with Hard Power Down Mode
Figures 4-85-1/2 and 2/2 show the examples of the MSM80C154S/83C154S battery backup
circuits with hard power down mode. The hard power down mode serves to retain data stored
in the CPU and external RAM if the AC 100V power failure occurs. Figure 4-85-1/2 shows the
CPU, power failure detector, and external RAM control unit. Figure 4-85-2/2 shows the
external RAM. The power failure detection voltage is set up by VR of the circuit A of Figure
4-85-1/2.
If the AC 100V power failure occurs when the power failure detection voltage is 4.5V, the
circuit works as described below.
When the power failure occurs, the internal power supply voltage VCA goes down from 5V
to 0V. When the VCA goes down less than 4.5V, a power failure detection signal is output from
the A circuit to the B circuit.
If data is being transferred between the CPU and external RAM during the detection of power
failure, information on power failure is stored in RS-F/F of the B circuit, when data transfer
ends. When information on on power failure is stored in RS-F/F, the I/O control signal goes
from “1” level to “0” level, which separates the external RAM and the peripheral circuit
electrically to retain data in the external RAM. At the same time, a hard power down signal
is output, the T1 pin of the CPU goes from “1” level to “0” level, and the CPU enters the hard
power down mode.
If the I/O port is ready to output data during hard power down mode, electric current flows to
the external via a 100KW pull-up resistance of the T1 pin.
The current flow to the external can be prevented by setting “1” into bit 0 (ALF) of IOCON
(0F8H) when setting the hard power down mode. If the hard power down mode is set when
ALF is at “1” level, electric current does not flow from the T1 pin to the external because I/O
becomes a floating state.
When AC 100V power supply is restored and the internal VCA goes from 0V to 5V, the hard
power down mode is cancelled.
When VCA exceeds 4.5V, the A circuit stops outputting a power failure signal for the B circuit.
When a power failure signal is not output, the power failure memory RS-F/F of the B circuit
is reset after a time constant of the internal 200W and 10mF, and the external RAM I/O control
signal and hard power down signal turn from “0” level to “1” level.
When RS-F/F is reset, a CPU reset signal is output and the CPU’s power down mode is
cancelled. The CPU starts the operation of XTAL1, 2 and executes a command starting from
address 0.
187
PSEN RD OE
1K 1K
WR
10K
P0.0 P0.0
P1
P0.1 P0.1 SN7408 WR
AC100V 1K 1K
P0.2 P0.2 10K
P0.3 P0.3
SN7408
P0.4 P0.4
5V
+ P0.5 P0.5
P3
MSM80C154S/83C154S
– P0.6 P0.6 CS0
1K 1K
1000µF
P0.7 P0.7
XTAL1 10K
10PF ALE ALE G2A Y0
XTAL2 P2.0 P2.0 G2B Y1
VCC P2.1 P2.1 Y2
P2.2 P2.2 Y3
MSM80C154S/83C154S/85C154HVS
P2.3 A Y4
0.1µF
P2.3
VSS P2.4 B Y5 CS7
P2.4 1K 1K
SN74NS138
P2.5 C Y6
P2.5 10K
188
RESET P2.6 P2.6 G1 Y7
P2.7 P2.7 ACC
T1(P3.5) EA I/O control signal GND
74HC08
74HC02 VCA
A
VCB
74HC02 1K 330
43K
8 +
5.1K
100µF
5.1K
VR
–
2.2V
20K
1K
3 4
ICL3211
5.1K
3N-100AAL S
200K
18K
5.1K
0.1µF
+
RRB51A05W
5 – 10µF 5.1K
Figure 4-85-1/2 MSM80C154S/83C154S battery back up with hard power down mode
B 74HC08
VCB
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1 D0 D1 D2 D3 D4 D5 D6 D7 VCC
P0.0
CS MSM5128RS
0.1µF
CS WE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9A10 VSS
CS7
CS0
P2.0
P2.1
P2.2
189
VCA
VCC
P0.7 D7 Q7
P0.6 D6 Q6
P0.5 D5 Q5 D0 D1 D2 D3 D4 D5 D6 D7 VCC
P0.4 D4 Q4
CS MSM5128RS
P0.3 D3 Q3
0.1µF
P0.2 D2 Q2 CS WE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9A10 VSS

P0.1 D1 Q1
SN74LS373
P0.0 D0 Q0
51K
ALE L
GND 51K
51K
OE
Figure 4-85-2/2 MSM80C154S/83C154S battery back up with hard power down mode
WR
1k ×8
MSM80C154S/83C154S/85C154HVS
5. INPUT/OUTPUT
PORTS
190
INPUT/OUTPUT PORTS
191
MSM80C154S/83C154S/85C154HVS
5. INPUT/OUTPUT PORTS
5.1 Outline
MSM80C154S/MSM83C154S is equipped with four 8-bit input/output ports. The functions of

these four ports (port 0, 1, 2, and 3) are listed below.
1) Port 0: Input/output bus port, address output port, and data input/output port.
2) Port 1: Quasi-bidirectional input/output port and control input pin.
3) Port 2: Quasi-bidirectional input/output port and address output port.
4) Port 3: Quasi-bidirectional input/output port and control input/output pin.
5.2 Port 0
Port 0 is an 8-bit input/output port. The circuit configuration is shown in Figure 5-1. When port
0 is used as an input/output port in internal ROM mode (MSM83C154S), the equivalent circuit
is indicated in Figure 5-2. When operated as an output port, port 0 becomes an open drain
output port, and when operated as an input port, “1” should be set in the port 0 latch to put
the port 0 pin into floating status prior to using the port for input purposes.
When port 0 is used in external ROM mode (MSM80C154S) and external RAM mode, the
equivalent circuit is shown in Figure 5-3 where addresses and data outputs are obtained as
“1” and “0” by totem pole output driver. When data from external ROM or external RAM is
applied as input data, port 0 automatically becomes a tri-state input port. When the CPU is
reset or when an external ROM or external RAM is accessed, “1” data is set automatically in
the port 0 latch. The port 0 pin table is shown in Table 5-1.
PD/DATA
PC0~7
RA0~7
INTERNAL
ACC0~7
BUS VCC
D Q
P
WPO
PORT 0
MODIFY
READ
FLOATING
Figure 5-1 Port 0 internal equivalent circuit
192
INPUT/OUTPUT PORTS
INTERNAL BUS
PORT 0
READ
D Q N
WPO
MODIFY
Figure 5-2 Port 0 input/Output port equivalent circuit in internal ROM mode
INTERNAL BUS VCC
PC0~7 P
RA0~7
ACC0~7
PORT 0
N
READ
Figure 5-3 Port 0 equivalent circuit during address and data input/output in external
ROM/RAM mode
193
MSM80C154S/83C154S/85C154HVS
Table 5-1 Port 0 pin table
PORT0 Accumulator bit Address
1 P0.0 ACC.0 PC –0
RA
2 P0.1 ACC.1 PC –1
RA
3 P0.2 ACC.2 PC –2
RA
4 P0.3 ACC.3 PC –3
RA
5 P0.4 ACC.4 PC –4
RA
6 P0.5 ACC.5 PC –5
RA
7 P0.6 ACC.6 PC –6
RA
8 P0.7 ACC.7 PC –7
RA
194
INPUT/OUTPUT PORTS
5.3 Port 1
Port 1 is a quasi-bidirectional port capable of handling input and output of 8-bit data in the
circuit configuration outlined in Figure 5-4.
A “quasi-bidirectional port” refers to a port which has internal pull-up resistance when used
as an input port. The internal equivalent circuit is shown in Figure 5-5.
If a quasi-bidirectional port is used exclusively as an output port, the port output driver
becomes a totem-pole type for driving “1” and “0” data. The output impedance during output
of “1” data is approximately 9 kohm, while a sink current is 1.6mA during output of “0” data.
When used as an output port, the “1” data accelerator circuit is activated for a period
equivalent to two XTAL1·2 oscillator clocks only when the output data is shifted from “0” to
“1”. During this data acceleration operation, the “1” output impedance is changed to about 500
ohms, the IOH current is increased, and the output signal leading edge is speeded up. The
accelerator circuit operation time chart is given in Figure 5-6. Once port output data has been
written in port latch it is preserved until output of the next item of data.
If a quasi-bidirectional port is used exclusively as an input port, “1” data is first set in the port
latch in advance. When the input signal applied to the input port is changed from level “1” to
level “0”, the port 10 kohm pull-up resistance is disconnected from the VCC, leaving only the
100 kohm pull-up resistance for reducing external IIL current. And when the input signal is
changed from level “0” to level “1”, the 10 kohm resistance is reconnected, thereby connecting
the 10 and 100 kohm resistances to the VCC supply in parallel. The quasi-bidirectional port
input equivalent circuit is outlined in Figure 5-7.
To change port 1 from a quasi-bidirectional input port to a high impedance input port, “1” is
set in bit 1 (P1HZ) of the I/O control register (IOCON 0F8H). The output driver circuit is thus
disconnected from the port pin and the port becomes a high impedance input port. The signal
levels applied to high impedance input ports are normal “0” and “1” level signals. The pins
cannot be used in open status.
The bit 0 and bit 1 of port 1 have alternate functions apart from serving as port pins. Bit 0 can
function as the external clock input pin for timer/counter 2, and bit 1 can function as the capture
signal input pin for timer/counter 2, or as the auto reload signal input pin, or as the external
timer flag 2 setting pin, depending on the timer/counter 2 operation mode.
When the bit 0 and 1 pins are to be used as timer/counter 2 control pins, “1” must be set in
the port in advance.
And if port output is to be put into floating status during CPU power down mode (PD, HPD),
“1” is to be set in bit 1 (ALF) of the I/O control register (IOCON 0F8H) before CPU power down
mode is activated. Floated port 1 pins may be either open, or undefined within the –0.5 to VCC
+0.5V range.
And when port 1, 2, and 3 quasi-bidirectional ports are used as input ports, the port pull-up
resistance may be set only to 100 kohms. If “1” is set in bit 4 (IZC) of the I/O control register
(IOCON 0F8H), the 10 kohm pull-up resistance for ports 1, 2, and 3 is all disconnected from
VCC, leaving only the 100 kohm resistance. This mode is useful when input data is applied
to the quasi-bidirectional port by external devices having low output driving capacity (high
output impedance). The port 1 CPU control pin functions are listed in Table 5-2, and the port
pin list is given in Table 5-3.
195
MSM80C154S/83C154S/85C154HVS
INTERNAL
BUS
VCC
CONTROL
C
D Q P1 P2 P3
MODIFY
PORT 1
READ
WP1 Q N
196
INPUT/OUTPUT PORTS
. .
.
R=500Ω ON .
R=500Ω OFF
VCC VCC
P1 P1
. .
.
R=10kΩ ON IOH .
R=10kΩ ON IOH
P2 P2
. .
.
R=100kΩ ON .
R=100kΩ ON
P3 P3
INTERNAL INTERNAL
BUS BUS
READ OFF READ OFF
N N
(A) When accelerator circuit is activated (B) When "1" data is held
.
.
R=500Ω OFF
VCC
P1
.
.
R=10kΩ OFF
P2
.
.
R=100kΩ OFF
P3
INTERNAL
BUS
READ IOL
ON
N
(C) When "0" data is held
Figure 5-5 Quasi-bidirectional port equivalent circuit
197
MSM80C154S/83C154S/85C154HVS
M1 M1
1-
XTAL1
0-
1-
ALE
0-
1
PSEN
0
1-
W-PORT
0
1
CPU-BUS
0
1-
PORT-OUT PORT DATA="0" PORT DATA="1"
0
1-
*P1·2·3TR-ON
0 *
Figure 5-6 Quasi-bidirectional port accelerator circuit operation time chart
198
INPUT/OUTPUT PORTS
VCC
. .
.
R=100kΩ .
R=10kΩ
ON P3 ON P2
INTERNAL
BUS
READ OFF
N
(A) "1" data writing equivalent circuit
VCC VCC
. .
.
R=100kΩ .
R=10kΩ
ON
ON P3 ON P2
10kΩ
IIH
INTERNAL
BUS
READ OFF OFF
N
(B) "1" data input equivalent circuit
VCC VCC
. .
.
R=100kΩ .
R=10kΩ
OFF
ON P3 OFF P2
10kΩ
IOH
INTERNAL
BUS
READ OFF ON
N
(C) "0" data input equivalent circuit
Figure 5-7 Quasi-bidirectional port input equivalent circuit
199
MSM80C154S/83C154S/85C154HVS
Table 5-2 Port 1 CPU control pin table
PORT1 Function
P1.0 T2 [TIMER COUNTER 2 EXTERNAL CLOCK]
P1.1 T2EX [TIMER COUNTER 2 EXTERNAL CONTROL]
PORT1 Accumulator bit

1 P1.0 ACC.0
2 P1.1 ACC.1
3 P1.2 ACC.2
4 P1.3 ACC.3
5 P1.4 ACC.4
6 P1.5 ACC.5
7 P1.6 ACC.6
8 P1.7 ACC.7
200
INPUT/OUTPUT PORTS
5.4 Port 2
Port 2 can function as a quasi-bidirectional port capable of handling input and output of 8-bit
data in the circuit configuration outlined in Figure 5-8. It can also be used for output of
addresses 8 thru 15 in external ROM and external RAM (using DPTR) modes. When port 2
is used as a quasi-bidirectional port, it functions in much the same way as port 1. Note,
however, that the port 2 “1” data accelerator circuit operates for a period equivalent to four
XTAL1·2 oscillator clocks.
Output of addresses 8 thru 15 obtained from port 2 is activated by the circuit outlined in Figure
5-9. When the address output data is “1”, the “1” data accelerator circuit is activated during
output of the data, resulting in a higher driving capacity.
disconnected from the port pin and the port becomes a high impedance input port. The signal
levels applied to high impedance input ports are normal “0” and “1” level signals. The pins
When port outputs are floated in CPU power down mode (PD, HPD), the port 2 pins may be
either open, or undefined within the –0.5 to VCC+0.5V range. The port 2 pin table is given in
Table 5-4.
INTERNAL
BUS
VCC
PC/DATA
PC8~15 P1 P2 P3
RA8~15
(DPH)
PORT 2
READ
MODIFY Q
D Q C
D
WP2 Q N
CONTROL
201
MSM80C154S/83C154S/85C154HVS
VCC
PC/DATA P1 P2 P3
PC8~15
RA8~15
(DPH)
PORT 2
Figure 5-9 Port 2 address output equivalent circuit for external memory
PORT2 Accumulator bit Address
1 P2.0 ACC.0 PC –8
RA
2 P2.1 ACC.1 PC –9
RA
3 P2.2 ACC.2 PC –10

RA
4 P2.3 ACC.3 PC –11

RA
5 P2.4 ACC.4 PC –12

RA
6 P2.5 ACC.5 PC –13

RA
7 P2.6 ACC.6 PC –14

RA
8 P2.7 ACC.7 PC –15

RA
202
INPUT/OUTPUT PORTS
5.5 Port 3
Port 3 can function as a quasi-bidirectional port capable of handling input and output of 8-bit
data in the circuit configuration outlined in Figure 5-10, and can also be used as a CPU control
pin.
When port 3 is used as a quasi-bidirectional port, all functions are identical to those described
for port 1. And when used as a CPU control pin, the port is used after first setting “1” data in
the port latch. Note that if the port is used with “0” port latch data, the CPU control signal is
ANDed (logical product) with the port “0” data, resulting in the CPU control signal remaining
at “0” level.
disconnected from the port pin (floating pin status) and the port becomes a high impedance
input port. The signal levels applied to high impedance input ports are normal “0” and “1” level
signals. The pins cannot be used in open status.
When port outputs are floated in CPU power down mode (PD, HPD), normal “0” and “1” level
signals are applied to pins 2 thru 5 of port 3, and pins 0, 1, 6, and 7 may be either open, or
undefined within the –0.5 to VCC+0.5V range. The CPU control function pins are listed in
Table 5-5, and the port 3 pin table is given in Table 5-6.
INTERNAL
BUS
VCC
CONTROL
C
D Q P1 P2 P3
MODIFY
PORT 3
READ
DATA IN
N
D Q
WP3
DATA OUT
203
MSM80C154S/83C154S/85C154HVS
Table 5-5 Port 3 CPU control pin function table
PORT3 PORT 3 PIN ALTERNATE FUNCTION

P3.0 RXD [SERIAL INPUT PORT]
P3.1 TXD [SERIAL OUTPUT PORT]
P3.2 INT0 [EXTERNAL INTERRUPT 0]
P3.3 INT1 [EXTERNAL INTERRUPT 1]
P3.4 T0 [TIMER/COUNTER 0 CLOCK]
T1 [TIMER/COUNTER 1 CLOCK]
P3.5
HPDI [HARD POWER DOWN INPUT]
P3.6 WR [EXTERNAL DATA MEMORY WRITE STROBE]
P3.7 RD [EXTERNAL DATA MEMORY READ STROBE]
PORT3 Control Accumulator bit

1 P3.0 RXD ACC.0
2 P3.1 TXD ACC.1
3 P3.2 INT0 ACC.2
4 P3.3 INT1 ACC.3
5 P3.4 T0 ACC.4
6 P3.5 T1/HDPI ACC.5
7 P3.6 WR ACC.6
8 P3.7 RD ACC.7
204
INPUT/OUTPUT PORTS
5.6 Port 0, 1, 2, and 3 Output and Floating Status Settings in CPU Power Down
Mode (PD, HPD)
The port 0, 1, 2, and 3 output status can be set to either data output or floating when
MSM80C154S/MSM83C154S is in power down mode (PD, HPD).
To set these ports to output status in power down mode, bit 0 (ALF) of the I/O control register
(IOCON 0F8H) is reset to “0” before PD or HPD mode is activated (see Figure 5-11). The CPU
is then stopped with the ports in data output status when power down mode is started.
And to set the ports to floating status in power down mode, “1” is set in bit 0 (ALF) of the I/
O control register (IOCON 0F8H) before PD or HPD mode is activated (see Figure 5-11). The
port output driver is disconnected from the port pins when power down mode is started.
If “1” output from port becomes a power supply factor in respect to the external circuits when
PD or HPD mode is activated in port data output mode, the PD or HPD mode should be
activated after the port data is reset to “0” by software. And in the reverse case, PD or HPD
mode is activated after the port data is set to “1”.
When port pins are in floating status during PD or HPD mode, the port pin status of all pins
except pins 2 thru 5 of port 3 may be either open or undefined in the –0.5 to VCC+0.5V range.
This mode is used only in battery back-up of CPU data.
205
MSM80C154S/83C154S/85C154HVS
MODIFY
PORT1, 2, 3
VCC
D
P2-10kΩ P3-100kΩ
W PORT Q
I/O
READ
N
INTERNAL BUS
POWER DOWN
[IOCON 0F8H]
Bit 7 6 5 4 3 2 1 0
Flag — T32 SERR IZC P3HZ P2HZ P1HZ ALF
Set • • • • •
Figure 5-11 Control circuit for ports 0, 1, 2, 3 by lOCON
206
INPUT/OUTPUT PORTS
5.7 High Impedance Input Port Setting of Each Ouasi-bidirectional Port 1, 2,

and 3
Each of the quasi-bidirectional input ports 1, 2, and 3 can be set as high impedance input
ports.
This high impedance condition is achieved by setting “1” in bits 1 (P1HZ), 2 (P2HZ), and 3
(P3HZ) of the I/O control register (IOCON 0F8H) shown in Figure 5-11. Port 1 is set by P1HZ,
port 2 by P2HZ, and port 3 by P3HZ. When the each bit is set to “1”, the port output driver is
disconnected from the port pins, and the quasibidirectional input ports become high
impedance input ports.
After being changed to high impedance input ports, the port latch data modify instructions and
the input instructions for external input signals can still be used.
Normal “0” and “1” level signals must be applied to high impedance input ports. The pins
5.8 100 kohm Pull-Up Resistance Setting for Quasi-bidirectional Input Ports 1,
2, and 3
Another of the MSM80C154S/MSM83C154S functions disconnects the 10 kW pull-up

resistance from the power supply VCC in the parallel connection of 10/100 kW pull-up
resistances to the quasi-bidirectional input ports.
In normal operations, the 10 kW pull-up resistance is disconnected from the VCC power supply
when the level of the signal applied to the quasi-bidirectional input port is changed from “1”
to “0”, thereby reducing the external IIL current because of the remaining only the 100 kW pull-
up resistance.
When the level of the signal applied to the port is then changed from “0” to “1”, the 10 kW
resistance is reconnected to VCC, and the port is pulled up by the 10 and 100 kW resistances
connected in parallel. The resultant pull-up resistance is about 9 kW and the effect of random
“0” noise is suppressed. But where an external device with low driving capacity is used to
apply a “0” level signal to a quasi-bidirectional input port, the driving current may not be
enough to change the port level to “0”. To overcome this problem, the CPU has been designed
to disconnect the 10 kW pull-up resistance from the power supply leaving only the 100 kW
resistance. This enables devices with low driving capacity to drive the quasi-bidirectional
input ports.
The pull-up resistance for all quasi-bidirectional input ports 1, 2, and 3 can be set to 100 kW
by setting “1” in bit 4 (IZC) of the I/O control register (IOCON 0F8H) shown in Figure 5-11 to
disconnect the 10 kW resistance from VCC.
207
MSM80C154S/83C154S/85C154HVS
5.9 Precautions When Driving External Transistors by Ouasi-bidirectional

Port Output Signals
The following points must be carefully considered when quasi-bidirectional ports are used to
drive a transistor by the circuit shown in Figure 5-12.
Even though the CPU output in this circuit is at “1” level, the port output pin level may be
clamped by the base-emitter voltage VBE (0.7V) of an external NPN transistor, resulting in a
pin level of “0”.
VCC VCC
10kΩ 100kΩ
OUT
P
IB
.
CPU "1" OUT .
VBE=0.7V
Figure 5-12 NPN transistor direct connection circuit
When the pin level is dropped to “0”, the CPU disconnects the 10 kW pull-up resistance from
the power supply, leaving only the 100 kW pull-up resistance connected. Since the base
current IB of an external NPN transistor is supplied via the 100 kW resistance, the transistor
collector current IC may be reduced to a level insufficient for driving purposes.
To resolve this problem, diode can be inserted between the transistor base and CPU pin as
indicated in Figure 5-13 to achieve a pin level of “1” by level shift. or by using a PNP transistor
as indicated in Figure 5-14 where the external transistor is driven by a “0” level port output,
this problem is solved.
208
INPUT/OUTPUT PORTS
VCC VCC
10kΩ 100kΩ
OUT
P
IB
CPU "1" OUT
Figure 5-13 Drive circuit for NPN transistor by level shifter
VCC
CPU "0" OUT
OUT
IB
Figure 5-14 PNP transistor direct connection drive circuit
209
MSM80C154S/83C154S/85C154HVS
5.10 Port Output Timing
1) One machine cycle instruction output timing
M1 M1
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1
1
XTAL1
0
1
ALE
0
1M CYCLE OP
1
W-PORT
0
1
PORT-OUT PORT OLD DATA PORT NEW DATA
0
INC data address XCH A, data address
DEC data address CPL bit address
MOV data address, A CLR bit address
ORL data address, A SETB bit address
ANL data address, A
XRL data address, A
Figure 5-15 One machine cycle instruction port output time chart
210
INPUT/OUTPUT PORTS
2) Two machine cycle instruction output timing
M2 M1
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1
1
XTAL1
0
1
ALE
0
2M CYCLE OP
1
W-PORT
0
1
PORT-OUT PORT OLD DATA PORT NEW DATA
0
MOV data address, # data MOV data address 1, data address 2
ORL data address, # data MOV bit address, C
ANL data address, # data
XRL data address, # data
JBC bit address, code address
POP data address
MOV data address, @Rr
MOV data address, Rr
Figure 5-16 Two machine cycle instruction port output time chart
211
MSM80C154S/83C154S/85C154HVS
5.11 Port Data Manipulating Instructions
The MSM80C154S/MSM83C154S port operation instructions for ports 0, 1, 2, and 3 are

divided into two groups-one where external signals applied to the port pin are used according
to the instruction to be used, and the other where port latch data uneffected by the external
signals is used. Instructions which use port latch data are listed below.
INC data address

DEC data address
ORL data address, # data
ANL data address, # data
XRL data address, # data
ORL data address, A
ANL data address, A
XRL data address, A
CPL bit address
JBC bit address, code address
DJNZ data address, code address
PUSH data address
212
INPUT/OUTPUT PORTS
213
MSM80C154/83C154/85C154
6. ELECTRICAL
CHARACTERISTICS
214
ELECTRICAL CHARACTERISTICS
215
MSM80C154/83C154/85C154
6. ELECTRICAL CHARACTERISTICS
6.1 Absolute Maximum Ratings
Parameter Symbol Conditions Rating Unit

Supply voltage VCC Ta=25°C –0.5~7 V
Input voltage VI Ta=25°C –0.5~VCC+0.5 V
Storage
Tstg — –55~+150 °C
temperature
6.2 Operational Ranges
Parameter Symbol Conditions Rating Unit

Supply voltage VCC See below 2.0~6 V
Memory hold fOSC = 0 Hz
VCC 2~6 V
voltage (Oscillation stop)
Oscillation
fOSC See below 1~24*1 MHz
frequency
External clock
fEXTCLK See below 0~24 MHz
operating frequency
Ambient
Ta — –40~+85*2 °C
temperature
*1 Dpends on the specifications for the oscillator or ceramic resonator.

The MSM85C154HVS is guaranteed for operation at frequencies of up to 22 MHz.
*2 The MSM85C154HVS is guaranteed for operation at ordinary temperatures.
12 1
5
4 3
3
tcy fOSC
(ms) fEXTCLK
2 6 (MHz)
1 12
0.6 20
0.5 24
2 2.2 3 4 5 6
Supply Voltage VCC (V)
216
6.3 DC Characteristics 1
(VCC=4.0 to 6.0V,VSS=0V, Ta=–40°C to +85°C)
Measuring
Parameter Symbol Conditions Min Typ Max Unit
Circuit
Input Low Voltage VIL — –0.5 — 0.2VCC V
–0.1
Input High Voltage VIH Except XTAL1, EA 0.2VCC — VCC+0.5 V
and RESET +0.9
Input High Voltage VIH1 XTAL1 and EA 0.7VCC — VCC+0.5 V
RESET
Output Low Voltage VOL IOL=1.6mA — — 0.45 V
[PORT 1, 2,3]
Output Low Voltage VOL1 IOL=3.2mA — — 0.45 V 1
[PORT 0, ALE, PSEN]
IOH=–60µA 2.4 — — V
Output High Voltage VOH
[PORT 1, 2,3] IOH=–30µA 0.75VCC — — V
IOH=–10µA 0.9VCC — — V
IOH=–400µA 2.4 — — V
Output High Voltage VOH1 VCC=5V±10%
[PORT 0, ALE, PSEN] IOH=–150µA 0.75VCC — — V
IOH=–40µA 0.9VCC — — V
Logical 0 Input Current/ IIL/IOH VI=0.45V/VO=0.45V –5 — –80 µA
logical 1 Output Current
[PORT 1, 2,3]
Logical 1 to 0 2
Transition Current ITL VI=2.0V — — –500 µA
[PORT 1, 2,3]
lnput Leakage Current ILI VSS<VI<VCC — — ±10 µA 3
[PORT 0 loating, EA]
RESET Pull-down RRST — 20 40 125 kΩ 2
Resistor
Pin Capacitance CIO Ta=25°C, f=1MHz — — 10 pF —
[except XTAL1]
Power Down Current IPD — — 1 50 µA 4
217
MSM80C154/83C154/85C154
Maximum Power Supply Current

Normal Operation ICC (mA)
VCC 4V 5V 6V
Freq.
1MHz 2.2 3.1 4.1
3MHz 3.7 5.2 7.0
12MHz 12.0 16.0 20.0
16MHz 16.0 20.0 25.0
20MHz 19.0 25.0 30.0
VCC 4.5V 5V 6V
Freq.
24MHz 25.0 29.0 35.0
Maximum Power Supply Current

Idle Mode ICC (mA)
VCC 4V 5V 6V
Freq.
1MHz 0.8 1.2 1.6
3MHz 1.2 1.7 2.3
12MHz 3.1 4.4 5.9
16MHz 3.8 5.5 7.3
20MHz 4.5 6.4 8.6
VCC 4.5V 5V 6V
Freq.
24MHz 6.4 7.4 9.8
218
DC Characteristics 2
(VCC=2.2 to 4.0 V, VSS=0 V, Ta=-40 to +85°C)
Meas-
Parameter Symbol Condition Min. Typ. Max. Unit uring
circuit
Input Low Voltage VIL — –0.5 — 0.25 VCC–0.1 V
Except XTAL1, EA,
Input High Voltage VIH 0.25 VCC+0.9 — VCC+0.5 V
and RESET
Input High Voltage VIH1 XTAL1, RESET, and EA 0.6 VCC+0.6 — VCC+0.5 V
Output Low Voltage
VOL IOL=10 mA — — 0.1 V
(PORT 1, 2, 3)
Output Low Voltage
VOL1 IOL=20 mA — — 0.1 V
(PORT 0, ALE, PSEN)
1
Output High Voltage
VOH IOH=–5 mA 0.75 VCC — — V
Output High Voltage
(PORT 1, 2, 3)
VOH1 IOH=–20 mA 0.75 VCC — — V
(PORT 0, ALE, PSEN)
Logical 0 Input Current/ VI=0.1 V
Logical 1 Output Current/ IIL / IOH –5 — –40 mA
(PORT 1, 2, 3) VO=0.1 V
2
Logical 1 to 0 Transition
ITL VI=1.9 V — — –300 mA
Output Current (PORT 1, 2, 3)
Input Leakage Current
ILI VSS < VI < VCC — — ±10 mA 3
(PORT 0 floating, EA)
RESET Pull-down Resistance RRST — 20 40 125 kW 2
Ta=25°C, f=1 MHz
Pin Capacitance CIO — — 10 pF —
(except XTAL1)
Power Down Current IPD — — 1 10 mA 4
Maximum power supply current normal operation ICC (mA)
VCC 2.2 V 3.0 V 4.0 V

Freq
1 MHz 0.9 1.4 2.2
3 MHz 1.8 2.4 4.3
12 MHz — 8.0 12.0
16 MHz — — 16.0
Maximum power supply current idle mode ICC (mA)

VCC 2.2 V 3.0 V 4.0 V
Freq
1 MHz 0.3 0.5 0.8
3 MHz 0.5 0.8 1.2
12 MHz — 2.0 3.1
16 MHz — — 3.8
219
MSM80C154/83C154/85C154
Measuring circuits
1 2
VCC Note 2 Note 1 VCC

OUTPUT
OUTPUT
INPUT
INPUT
VIH Note
VIL 3
V A IO V A
VSS VSS
3 4
VCC Note 2 VCC

OUTPUT
OUTPUT
INPUT
INPUT
VIH Note VIH Note
VIL 3 VIL 3
V A
VSS VSS
Note 1 : Repeated for specified input pins.

2 : Repeated for specified output pins.
3 : Input logic for specified status.
220
6.4 External Program Memory Access AC Characteristics
VCC=2.2 to 6.0V, VSS=0V, Ta=–40°C to +85°C

PORT 0, ALE, and PSEN connected with 100pF load, other connected with 80pF load
Variable clock from*1

Parameter Symble 1 to 24 MHz Unit
Min. Max.
XTAL1, XTAL 2 Oscillation Cycle tCLCL 41.7 1000 ns
ALE Signal Width tLHLL 2tCLCL-40 — ns
Address Setup Time
tAVLL 1tCLCL-15 — ns
(to ALE Falling Edge)
Address Hold Time
tLLAX 1tCLCL-35 — ns
(from ALE Falling Edge)
Instruction Data Read Time
tLLPL — 4tCLCL-100 ns
From ALE Falling Edge to PSEN
tLLPL 1tCLCL-30 — ns
Falling Edge
PSEN Signal Width tPLPH 3tCLCL-35 — ns
tPLIV — 3tCLCL-45 ns
(from PSEN Falling Edge)
Instruction Data Hold Time
tPXIX 0 — ns
(from PSEN Rising Edge)
Bus Floating Time after Instruction
tPXIZ — 1tCLCL-20 ns
Data Read (from PSEN Rising Edge)
tAVIV — 5tCLCL-105 ns
(from Address Output)
Bus Floating Time(PSEN Rising
tAZPL 0 — ns
Edge from Address float)
Address Output Time from PSEN
tPXAV 1tCLCL-20 — ns
Rising Edge
*1 The variable check is from 0 to 24 MHz when the external check is used.
221
MSM80C154/83C154/85C154
External program memory read cycle
tLHLL
ALE
tAVLL tLLPL tPLPH
tLLIV
tPLIV
PSEN
tPXAV
tPXIZ
tLLAX tAZPL tPXIX
PORT 0 A0~A7 INSTR IN A0~A7
tAVIV
PORT 2 A8~A15 A8~A15 A0~A7
222
6.5 External Data Memory Access AC Characteristics

Parameter Symbol 1 to 24 MHz Unit
Min. Max.
XTAL1, XTAL2 Oscillator Cycle tCLCL 45.5 1000 ns
Address Setup Time
Address Hold Time
RD Signal Width tRLRL 6tCLCL-100 — ns
WR Signal Width tWLWH 6tCLCL-100 — ns
RAM Data Read Time
tRLDV — 5tCLCL-105 ns
(from RD Signal Falling Edge)
RAM Data Read Hold Time
tRHDX 0 — ns
(from RD Signal Rising Edge)
Data Bus Floating Time
tRHDZ — 2tCLCL-70 ns
RAM Data Read Time
tLLDV — 8tCLCL-100 ns
(from ALE Signal Falling Edge)
RAM Data Read Time
tAVDV — 9tCLCL-105 ns
RD/WR Output Time from ALE 3tCLCL-40
tLLWL 3tCLCL+40 ns
Falling Edge *2 3tCLCL-100
RD/WR Output Time from Address
tAVWL 4tCLCL-70 — ns
Output
WR Output Time from Data Output tQVWX 1tCLCL-40 — ns
Time from Data to WR Rising Edge tQVWH 7tCLCL-105 — ns
Data Hold Time
tWHQX 2tCLCL-50 — ns
(from WR Rising Edge)
Time from to Address Float RD
tRLAZ 0 — ns
Output
Time from RD/WR Rising Edge to 1tCLCL+40
tWHLH 1tCLCL-30 ns
ALE Rising Edge *2 1tCLCL+100
*2 For 2.2£VCC<4 V
223
MSM80C154/83C154/85C154
External data memory read cycle
tLHLL tWHLH
ALE
PSEN
tLLDV
tLLWL tRLRH
RD
tRHDZ
tAVLL tLLAX tRLDV tRHDX
tAZRL
PORT 0 INSTR A0~A7 A0~A7 DATA IN A0~A7
IN PCL RrorDPL PCL
tAVWL
tAVDV
PORT 2 PCH A8~A15 PCH P2.0~P2.7 DATA or A8~A15 PCH A8~A15 PCH
External data memory write cycle
tLHLL tWHLH
ALE
PSEN
tLLWL tWLWH
WR
tLLAX tQVWH
tAVLL tWHQX
tQVWX
PORT 0 INSTR A0~A7 A0~A7 DATA IN A0~A7
IN PCL RrorDPL PCL
tAVWL
PORT 2 A8~A15 A8~A15 PCH P2.0~P2.7 DATA or A8~A15 PCH A8~A15 PCH
PCH
224
6.6 Serial Port (I/O Extension Mode) AC Characteristics
VCC=2.2 to.0V, VSS=0V, Ta=–40°C to 85°C
Parameter Symbol Min Max Unit

Serial Port Clock Cycle Time tXLXL 12tCLCL — ns
Output Data Setup to Clock Rising Edge tQVXH 10tCLCL–133 — ns
Output Data Hold After Clock Rising Edge tXHQX 2tCLCL–75 — ns
Input Data Hold After Clock Rising Edge tXHDX 0 — ns
Clock Rising Edge to Input Data Valid tXHDV — 10tCLCL–133 ns
225
MSM80C154/83C154/85C154
MACHINE CYCLE
ALE
tXLXL
SHIFT CLOCK
226
tQVXH tXHQX
OUTPUT DATA
tXHDV tXHDX
INPUT DATA VALID VALID VALID VALID VALID VALID VALID VALID
6.7 AC Characteristics Measuring Conditions
1. Input/output signal
VOH VOH
VIH VIH
TEST POINT
VIL VIL
VOL VOL
* The input signals in AC test mode are either VOH (logic “1”) orVOL (logic “0”).
Timing measurements are made atVIH (logic “1”) and VIL (10gic “0”).
2. Floating
Floating
VOH VOH
VIH VIH
VIL VIL
VOL VOL
* The port 0 floating interval is measured from the time the port 0 pin Voltage drops below
VIH after sinking to GND at 2.4mA when switching to floating status from a “1” output, and
from the time the port 0 pin Voltage exceeds VIL after connecting to a 400µA source when
switching to floating status from a “0” output.
227
MSM80C154/83C154/85C154
6.8 XTAL1 External Clock Input Waveform Conditions

Oscillator Freq. 1/tCLCL 0 24 MHz
High Time tCHCX 15 — ns
Low Time tCLCX 15 — ns
Rise Time tCLCH — 5 ns
Fall Time tCHCL — 5 ns
VCC–0.5
EXTERMINAL 0.7VCC
OSCILLATOR 0.2VCC–0.1
0.45V
SIGNAL tCHCX tCHCX tCLCH
tCHCL
tCLCL
EXTERMINAL NC XTAL2
OSCILLATOR XTAL1
SIGNAL VSS
228
7. DESCRIPTION OF
INSTRUCTIONS
MSM80C154S/83C154S/85C154HVS
230
DESCRIPTION OF INSTRUCTIONS
7. DESCRIPTION OF INSTRUCTIONS
7.1 Outline
MSM80C154S/MSM83C154S is a microcontroller designed for parallel processing in an

8-bit ALU. The instructions consist of 8-bit units of data, and are available as 1-word 1 -
machine, 2-machine, and 4-machine cycle instructions as well as 2-word 1-machine
and 2-machine cycle instructions and 3-word 2-machine cycle instructions. There is a
total of 112 instructions classified into the following groups.
(1) Arithmetic and logic instructions (15)

(2) Accumulator operation instructions (7)
(3) Increment & decrement instructions (9)
(4) Logical operation instructions (18)
(5) Immediate data setting instructions (5)
(6) Carry flag operation instructions (7)
(7) Bit transfer instructions (3)
(8) Bit manipulaton instructions (3)
(9) Data transfer instructions (11)
(10) Constant value instructions (2)
(11) Data exchange instructions (4)
(12) Subroutine instructions (6)
(13) Jump instructions (4)
(14) Branching instructions (13)
(15) External data memory instructions (4)
(16) Other instruction (1)
231
MSM80C154S/83C154S/85C154HVS
7.2 Description of Instruction Symbols
The instruction symbols have the following meanings.
A Accumulator
AB Register pair
AC Auxiliary carry
B Arithmetic operation register
C Carry (the bit 7 carry represented by CY is changed to C in Chapter 7.)
DPTR Data pointer
PC Program counter
Rr Register representation (r=0/1, or r=0 thru 7)
SP Stack pointer
AND Logical AND
OR Logical OR
XOR Exclusive OR
+ Addition
– Subtraction
× Multiplication
/ Division
(X) Representation of the contents of X
((X)) Representation of the contents addressed by contents of X
# Symbol denoting immediate data
@ Symbol denoting indirect address
= Equal sign
≠ Not equal
← Substitution
→ Substitution
— Negation (upper bar)
< Smaller than
> Larger than
bit address RAM or special function register bit designated address
code address Absolute address (A0 thru A15, A0 thru A11)
data Immediate data (I0 thru I7)
relative offset Corrected relative jump address value
direct address RAM or special function register data designated address (“direct
address” representation changed to “data address” during
detailed description of instructions)
232
L 0 1 2 3 4 5 6 7 8 9 A B C D E F
H 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1
0 AJMP LJMP
NOP address 11 RR A INC A INC direct INC @R0 INC @R1 INC R0 INC R1 INC R2 INC R3 INC R4 INC R5 INC R6 INC R7
0000 (Page 0) address 16
1 JBC bit, ACALL LCALL

address 11 RRC A DEC A DEC direct DEC @R0 DEC @R1 DEC R0 DEC R1 DEC R2 DEC R3 DEC R4 DEC R5 DEC R6 DEC R7
0001 rel (Page 0) address 16
2 JB bit, AJMP ADD A, ADD A, ADD A, ADD A,

address 11 RET RL A ADD A, R0 ADD A, R1 ADD A, R2 ADD A, R3 ADD A, R4 ADD A, R5 ADD A, R6 ADD A, R7
0010 rel (Page 1) #data direct @R0 @R1
3 JNB bit, ACALL ADDC A, ADDC A, ADDC A, ADDC A, ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC
address 11 RETI RLC A
0011 rel (Page 1) #data direct @R0 @R1 A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7
7.3 List of Instructions
4 JC bit, AJMP ORL ORL ORL A, ORL A, ORL A, ORL A,

address 11 direct ORLA, R0 ORLA, R1 ORLA, R2 ORLA, R3 ORLA, R4 ORLA, R5 ORLA, R6 ORLA, R7
0100 rel (Page 2) direct, A , #data #data direct @R0 @R1
5 ACALL ANL ANL ANL A, ANL A, ANL A, ANL A,

JNC rel address 11 direct ANLA, R0 ANLA, R1 ANLA, R2 ANLA, R3 ANLA, R4 ANLA, R5 ANLA, R6 ANLA, R7
0101 (Page 2) direct, A , #data #data direct @R0 @R1
6 AJMP XRL XRL XRL A, XRL A, XRL A, XRL A,

JZ rel address 11 direct XRLA, R0 XRLA, R1 XRLA, R2 XRLA, R3 XRLA, R4 XRLA, R5 XRLA, R6 XRLA, R7
0110 (Page 3) direct, A , #data #data direct @R0 @R1
7 ACALL ORL C, JMP MOV A, MOV MOV @R0, MOV @R1, MOV R0, MOV R1, MOV R2, MOV R3, MOV R4, MOV R5, MOV R6, MOV R7,
JNZ rel address 11 direct
233
0111 (Page 3) bit @A+DPTR #data , #data #data #data #data #data #data #data #data #data #data #data
MSM80C154S/MSM83C154S instruction table
8 SJMP AJMP ANL C, MOVC A, MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV
address 11 DIV AB direct 1, direct, direct, direct, direct, direct, direct, direct, direct, direct, direct,
1000 rel (Page 4) bit @A+PC direct 2 @R0 @R1 R0 R1 R2 R3 R4 R5 R6 R7
9 MOV ACALL MOV bit, MOVC A, SUBB A, SUBB A, SUBB A, SUBB A, SUBB A, SUBB A, SUBB A, SUBB A, SUBB A, SUBB A, SUBB A, SUBB A,
DPTR, address 11
1001 #data 16 (Page 4) C @A+DPTR #data direct @R0 @R1 R0 R1 R2 R3 R4 R5 R6 R7
A ORL AJMP MOV C, INC MOV @R0, MOV @R1, MOV R0, MOV R1, MOV R2, MOV R3, MOV R4, MOV R5, MOV R6, MOV R7,
address 11 MUL AB —
1010 C,/bit (Page 5) bit DPTR direct direct direct direct direct direct direct direct direct direct
B ANL ACALL CJNE A, CJNE A, CJNE@R0, CJNE@R1, CJNE R0, CJNE R1, CJNE R2, CJNE R3, CJNE R4, CJNE R5, CJNE R6, CJNE R7,
address 11 CPL bit CPL C
1011 C,/bit (Page 5) #data, rel direct, rel #data, rel #data, rel #data, rel #data, rel #data, rel #data, rel #data, rel #data, rel #data, rel #data, rel
C PUSH AJMP XCH A, XCH A, XCH A,

address 11 CLR bit CLR C SWAP A XCHA, R0 XCHA, R1 XCHA, R2 XCHA, R3 XCHA, R4 XCHA, R5 XCHA, R6 XCHA, R7
1100 direct (Page 6) direct @R0 @R1
D POP ACALL DJNZ XCHD A, XCHD A, DJNZ R0, DJNZ R1, DJNZ R2, DJNZ R3, DJNZ R4, DJNZ R5, DJNZ R6, DJNZ R7,
address 11 STEB bit STEB C DA A
1101 direct (Page 6) direct, rel @R0 @R1 rel rel rel rel rel rel rel rel
E MOVX A, AJMP MOVX A, MOVX A, MOV A, MOV A, MOV A,

address 11 CLR A MOVA, R0 MOVA, R1 MOVA, R2 MOVA, R3 MOVA, R4 MOVA, R5 MOVA, R6 MOVA, R7
1110 @DPTR (Page 7) @R0 @R1 direct @R0 @R1
F MOVX ACALL MOVX MOVX MOV MOV MOV

address 11 CPL A MOVR0, A MOVR1, A MOVR2, A MOVR3, A MOVR4, A MOVR5, A MOVR6, A MOVR7, A
1111 @DPTR, A (Page 7) @R0, A @R1, A direct A @R0 A @R1 A
Note that “data address” is represented as “direct address” in this description.
7.4 Simplified Description of Instructions
MSM80C154S/83C154S/85C154HVS
Classifi- Instruction code
cation
Mnemonic Byte Cycle Description Page
D7 D6 D5 D4 D3 D2 D1 D0
ADD A, Rr 0 0 1 0 1 r2 r1 r0 1 1 (AC),(OV),(C),(A)←(A)+(Rr) r=0~7 249
0 0 1 0 0 1 0 1
ADD A, direct 2 1 (AC),(OV),(C),(A)←(A)+(direct address) 250
a7 a6 a5 a4 a3 a2 a1 a0
ADD A, @Rr 0 0 1 0 0 1 1 r 1 1 (AC),(OV),(C),(A)←(A)+((Rr)) r=0 or 1 248
0 0 1 0 0 1 0 0
ADD A, #data 2 1 (AC),(OV),(C),(A)←(A)+#data 247
I7 I6 I5 I4 I3 I2 I1 I0
ADDC A, Rr 0 0 1 1 1 r2 r1 r0 1 1 (AC),(OV),(C),(A)←(A)+(C)+(Rr) r=0~7 253
0 0 1 1 0 1 0 1
ADDC A, direct 2 1 (AC),(OV),(C),(A)←(A)+(C)+(direct address) 254
a7 a6 a5 a4 a3 a2 a1 a0
Arithmetic operation instructions
ADDC A, @Rr 0 0 1 1 0 1 1 r 1 1 (AC),(OV),(C),(A)←(A)+(C)+((Rr)) r=0 or 1 252

0 0 1 1 0 1 0 0
ADDC A, #data 2 1 (AC),(OV),(C),(A)←(A)+(C)+#data 251
I7 I6 I5 I4 I3 I2 I1 I0
234
SUBB A, Rr 1 0 0 1 1 r2 r1 r0 1 1 (AC),(OV),(C),(A)←(A)–((C)+(Rr)) r=0~7 359

1 0 0 1 0 1 0 1
SUBB A, direct 2 1 (AC),(OV),(C),(A)←(A)–((C)+(direct address)) 360
a7 a6 a5 a4 a3 a2 a1 a0
SUBB A, @Rr 1 0 0 1 0 1 1 r 1 1 (AC),(OV),(C),(A)←(A)–((C)+((Rr))) r=0 or 1 358
1 0 0 1 0 1 0 0
SUBB A, #data 2 1 (AC),(OV),(C),(A)←(A)–((C)+#data) 357
I7 I6 I5 I4 I3 I2 I1 I0
MUL AB 1 0 1 0 0 1 0 0 1 4 (AB)←(A)×(B) 335
DIV AB 1 0 0 0 0 1 0 0 1 4 (A) quotient, (B) remainder ←(A)/(B) 284
DA A 1 1 0 1 0 1 0 0 1 1 When the contents of accumulator bit 0 thru 3 exceed 278
9, and when the auxiliary carry (AC) is 1, 6 is added to
bits 0 thru 3. And if examination od bits 4 thru 7 shows
that the result of adding the carry following correction of
the lower order bits 0 thru 3 by 6 is in excess of 9, or
carry (C) is 1, 6 is added to bits 4 thru 7. If a carry is
generated as a result, 1 is set in the carry flag.
cation
D7 D6 D5 D4 D3 D2 D1 D0
CLR A 1 1 1 0 0 1 0 0 1 1 (A)←0 272
CPL A 1 1 1 1 0 1 0 0 1 1 (A)←(A) 275
RL A 0 0 1 0 0 0 1 1 1 1 349
Accumulator
C ← ← ← ← ← ← ← ←
7 0
Accumulator operation instructions
RLC A 0 0 1 1 0 0 1 1 1 1 350
Accumulator
C ← ← ← ← ← ← ← ←
235
7 0
RR A 0 0 0 0 0 0 1 1 1 1 351
Accumulator
C ← ← ← ← ← ← ← ←
7 0
RRC A 0 0 0 1 0 0 1 1 1 1 352
Accumulator
C ← ← ← ← ← ← ← ←
7 0
SWAP A 1 1 0 0 0 1 0 0 1 1 →(A0~3)
(A4~7)← 361
MSM80C154S/83C154S/85C154HVS
cation
D7 D6 D5 D4 D3 D2 D1 D0
INC A 0 0 0 0 0 1 0 0 1 1 (A)←(A)+1 290
Increment & decrement instructions
INC Rr 0 0 0 0 1 r2 r1 r0 1 1 (Rr)←(Rr)+1 r=0~7 292

0 0 0 0 0 1 0 1
INC direct 2 1 (direct address)←(direct address)+1 293
a 7 a6 a5 a 4 a3 a 2 a1 a0
INC @Rr 0 0 0 0 0 1 1 r 1 1 ((Rr))←((Rr))+1 r=0 or 1 289
INC DPTR 1 0 1 0 0 0 1 1 1 2 (DPTR)←(DPTR)+1 291
DEC A 0 0 0 1 0 1 0 0 1 1 (A)←(A)–1 281
DEC Rr 0 0 0 1 1 r2 r1 r0 1 1 (Rr)←(Rr)–1 r=0~7 282
0 0 0 1 0 1 0 1
DEC direct 2 1 (direct address)←(direct address)–1 283
a 7 a6 a5 a 4 a3 a 2 a1 a0
DEC @Rr 0 0 0 1 0 1 1 r 1 1 ((Rr))←((Rr))–1 r=0 or 1 280
ANL A, Rr 0 1 0 1 1 r2 r1 r0 1 1 (A)←(A)AND(Rr) r=0~7 258
236
0 1 0 1 0 1 0 1
ANL A, direct 2 1 (A)←(A)AND(direct address) 259
a 7 a6 a5 a 4 a3 a 2 a1 a0
ANL A, @Rr 0 1 0 1 0 1 1 r 1 1 (A)←(A)AND((Rr)) r=0 or 1 257
Logical operation instructions
0 1 0 1 0 1 0 0
ANL A, #data 2 1 (A)←(A)AND#data 256
I7 I6 I5 I4 I3 I2 I1 I0
0 1 0 1 0 0 1 0
ANL direct, A 2 1 (direct address)←(direct address)AND(A) 263
a 7 a6 a5 a 4 a3 a 2 a1 a0
0 1 0 1 0 0 1 1
ANL direct,#data a7 a6 a5 a4 a3 a2 a1 a0 3 2 (direct address)←(direct address)AND#data 262
I7 I6 I5 I4 I3 I2 I1 I0
ORL A, Rr 0 1 0 0 1 r2 r1 r0 1 1 (A)←(A)OR(Rr) r=0~7 339
0 1 0 0 0 1 0 1
ORL A, direct 2 1 (A)←(A)OR(direct address) 340
a 7 a6 a5 a 4 a3 a 2 a1 a0
ORL A, @Rr 0 1 0 0 0 1 1 r 1 1 (A)←(A)OR((Rr)) r=0 or 1 338
cation
D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 0 0 1 0 0
ORL A, #data 2 1 (A)←(A)OR#data 337
I7 I6 I5 I4 I3 I2 I1 I0
0 1 0 0 0 0 1 0
ORL direct, A 2 1 (direct address)←(direct address)OR(A) 344
a7 a6 a5 a4 a3 a2 a1 a0
0 1 0 0 0 0 1 1
Logical operation instructions
ORL direct,#data a7 a6 a5 a4 a3 a2 a1 a0 3 2 (direct address)←(direct address)OR#data 343

I7 I6 I5 I4 I3 I2 I1 I0
XRL A, Rr 0 1 1 0 1 r2 r1 r0 1 1 (A)←(A)XOR(Rr) r=0~7 368
0 1 1 0 0 1 0 1
XRL A, direct 2 1 (A)←(A)XOR(direct address) 369
a7 a6 a5 a4 a3 a2 a1 a0
XRL A, @Rr 0 1 1 0 0 1 1 r 1 1 (A)←(A)XOR((Rr)) r=0 or 1 367
0 1 1 0 0 1 0 0
237
XRL A, #data 2 1 (A)←(A)XOR#data 366

I7 I6 I5 I4 I3 I2 I1 I0
0 1 1 0 0 0 1 0
XRL direct, A 2 1 (direct address)←(direct address)XOR(A) 371
a7 a6 a5 a4 a3 a2 a1 a0
0 1 1 0 0 0 1 1
XRL direct,#data a7 a6 a5 a4 a3 a2 a1 a0 3 2 (direct address)←(direct address)XOR#data 370
I7 I6 I5 I4 I3 I2 I1 I0
0 1 1 1 0 1 0 0
MOV A, #data 2 1 (A)←#data 314
setting instructions
I7 I6 I5 I4 I3 I2 I1 I0
Immediate data
0 1 1 1 1 r2 r1 r0
MOV Rr, #data 2 1 (Rr)←#data r=0~7 320
I7 I6 I5 I4 I3 I2 I1 I0
0 1 1 1 0 1 0 1
MOV direct, #data a7 a6 a5 a4 a3 a2 a1 a0 3 2 (direct address)←#data 324
I7 I6 I5 I4 I3 I2 I1 I0
MSM80C154S/83C154S/85C154HVS
cation
D7 D6 D5 D4 D3 D2 D1 D0
0 1 1 1 0 1 1 r
MOV @Rr, #data 2 1 ((Rr))←#data r=0 or 1 311
data setting
instructions
Immediate
I7 I6 I5 I4 I3 I2 I1 I0
1 0 0 1 0 0 0 0
MOV DPTR,
I15 I14 I13 I12 I11 I10 I9 I8 3 2 (DPTR)←#data 319
#data
I7 I6 I5 I4 I3 I2 I1 I0
CLR C 1 1 0 0 0 0 1 1 1 1 (C)←0 273
Carry flag operation instructions
SETB C 1 1 0 1 0 0 1 1 1 1 (C)←1 353

CPL C 1 0 1 1 0 0 1 1 1 1 (C)←(C) 276
1 0 0 0 0 0 1 0
ANL C, bit 2 2 (C)←(C)AND(bit address) 260
b7 b6 b5 b4 b3 b2 b1 b0
1 0 1 1 0 0 0 0
ANL C,/bit 2 2 (C)←(C)AND(bit address) 261
b7 b6 b5 b4 b3 b2 b1 b0
238
0 1 1 1 0 0 1 0
ORL C, bit 2 2 (C)←(C)OR(bit address) 341
b7 b6 b5 b4 b3 b2 b1 b0
1 0 1 0 0 0 0 0
ORL C,/bit 2 2 (C)←(C)OR(bit address) 342
b7 b6 b5 b4 b3 b2 b1 b0
1 0 1 0 0 0 1 0
instructions
Bit transfer
MOV C, bit 2 1 (C)←(bit address) 318

b7 b6 b5 b4 b3 b2 b1 b0
1 0 0 1 0 0 1 0
MOV bit, C 2 2 (bit address)←(C) 323
b7 b6 b5 b4 b3 b2 b1 b0
1 1 0 1 0 0 1 0
instructions
Bit manipu-
SETB bit 2 1 (bit address)←1 354

lation
b7 b6 b5 b4 b3 b2 b1 b0
1 1 0 0 0 0 1 0
CLR bit 2 1 (bit address)←0 274
b7 b6 b5 b4 b3 b2 b1 b0
cation
D7 D6 D5 D4 D3 D2 D1 D0
instructions
Bit manipu- 1 0 1 1 0 0 1 0
lation
CPL bit 2 1 (bit address)←(bit address) 277

b7 b6 b5 b4 b3 b2 b1 b0
MOV A, Rr 1 1 1 0 1 r2 r1 r0 1 1 (A)←(Rr) r=0~7 316
1 1 1 0 0 1 0 1
MOV A, direct 2 1 (A)←(direct address) 317
a 7 a6 a5 a 4 a3 a2 a 1 a0
MOV A, @Rr 1 1 1 0 0 1 1 r 1 1 (A)←((Rr)) r=0 or 1 315
MOV Rr, A 1 1 1 1 1 r2 r1 r0 1 1 (Rr)←(A) r=0~7 321
1 0 1 0 1 r2 r1 r0
MOV Rr, direct 2 2 (Rr)←(direct address) r=0~7 322
Data transfer instructions
a7 a6 a5 a 4 a3 a2 a 1 a0
1 1 1 1 0 1 0 1
MOV direct, A 2 1 (direct address)←(A) 326
a 7 a6 a5 a 4 a3 a2 a 1 a0
239
1 0 0 0 1 r2 r1 r0
MOV direct, Rr 2 2 (direct address)←(Rr) r=0~7 327
a7 a6 a5 a 4 a3 a2 a 1 a0
1 0 0 0 0 1 0 1
MOV direct1,
a72 a62 a52 a2 a32 a22 a12 a02 3 2 (direct address 1)←(direct address 2) 328
direct 2
a71 a61 a51 a41 a31 a21 a11 a01
1 0 0 0 0 1 1 r
MOV direct, @Rr 2 2 (direct address)←((Rr)) r=0 or 1 325
a 7 a6 a5 a 4 a3 a2 a 1 a0
MOV @Rr, A 1 1 1 1 0 1 1 r 1 1 ((Rr))←(A) r=0 or 1 312
1 0 1 0 0 1 1 r
MOV @Rr, direct 2 2 ((Rr))←(direct address) r=0 or 1 313
a 7 a6 a5 a 4 a3 a2 a 1 a0
instructions
MOVC A,@A+DPTR 1 0 0 1 0 0 1 1 1 2 (A)←((A)+(DPTR)) 329

Constant
value
(PC)←(PC)+1
MOVC A, @A+PC 1 0 0 0 0 0 1 1 1 2 330
(A)←((A)+(PC))
MSM80C154S/83C154S/85C154HVS
cation
D7 D6 D5 D4 D3 D2 D1 D0
XCH A, Rr 0 0 0 1 1 r2 r1 r0 1 1 (A)→
←(Rr) r=0~7 363
Data exchange
instructions
1 1 0 0 0 1 0 1
XCH A, direct 2 1 (A)→
←(direct address) 364
a7 a6 a5 a4 a3 a2 a1 a0
XCH A, @Rr 1 1 0 0 0 1 1 r 1 1 (A)→
←((Rr)) r=0 or 1 362
XCHD A, @Rr 1 1 0 1 0 1 1 r 1 1 (A0~3)→
←((Rr0~3)) r=0 or 1 365
1 1 0 0 0 0 0 0 (SP)←(SP)+1
PUSH direct 2 2 346
a7 a6 a5 a4 a3 a2 a1 a0 ((SP))←(direct address)
1 1 0 1 0 0 0 0 (direct address)←((SP))
POP direct 2 2 345
a7 a6 a5 a4 a3 a2 a1 a0 (SP)←(SP)–1
ACALL addr 11 A10 A9 A8 1 0 0 0 1 2 2 (PC)←(PC)+2 246
A7 A6 A5 A4 A3 A2 A1 A0 (SP)←(SP)+1
((SP))←(PC0~7)
240
Subroutine instructions
(SP)←(SP)+1
((SP))←(PC8~15)
(PC0~10)←A0~10
LCALL addr 16 0 0 0 1 0 0 1 0 3 2 (PC)←(PC)+3 309
A15 A14 A13 A12 A11 A10 A9 A8 (SP)←(SP)+1
A7 A6 A5 A4 A3 A2 A1 A0 ((SP))←(PC0~7)
(SP)←(SP)+1
((SP))←(PC8~15)
(PC0~15)←A0~15
RET 0 0 1 0 0 0 1 0 1 2 (PC8~15)←((SP)) 347
(SP)←(SP)–1
(PC0~7)←((SP))
(SP)←(SP)–1
cation
D7 D6 D5 D4 D3 D2 D1 D0
RETI 0 0 1 1 0 0 1 0 1 2 (PC8~15)←((SP)) 348
instructions
Subroutine
(SP)←(SP)–1
(PC0~7)←((SP))
(SP)←(SP)–1
*INTERRUPT ENABLE
A10 A9 A8 0 0 0 0 1 (PC)←(PC)+2
AJMP addr 11 2 2 255
A7 A6 A5 A4 A3 A2 A1 A0 (PC0~10)←A0~10
Jump instructions
0 0 0 0 0 0 1 0
LJMP addr 16 A15 A14 A13 A12 A11 A10 A9 A8 3 2 (PC0~15)←A0~15 310
A7 A6 A5 A4 A3 A2 A1 A0
1 0 0 0 0 0 0 0 (PC)←(PC)+2
SJMP rel 2 2 355
R7 R6 R5 R4 R3 R2 R1 R0 (PC)←(PC)+relative offset
241
JMP @A+DPTR 0 1 1 1 0 0 1 1 1 2 (PC)←(A)+(DPTR) 300

CJNE A, direct, rel 1 0 1 1 0 1 0 1 3 2 (PC)←(PC)+3 268
a7 a6 a5 a4 a3 a2 a1 a0 IF (A)≠(direct address)
Branching instructions
R7 R6 R5 R4 R3 R2 R1 R0 THEN
(PC)←(PC)+relative offset
IF (A)<(direct address)
THEN
(C)←1
ELSE
(C)←0
MSM80C154S/83C154S/85C154HVS
cation
D7 D6 D5 D4 D3 D2 D1 D0
CJNE A, #data, rel 1 0 1 1 0 1 0 0 3 2 (PC)←(PC)+3 266
I7 I6 I5 I4 I3 I2 I1 I0 IF (A)≠#data
IF (A)<#data
THEN
(C)←1
ELSE
(C)←0
CJNE Rr,#data,rel 1 0 1 1 1 r2 r1 r0 3 2 (PC)←(PC)+3 270
I7 I6 I5 I4 I3 I2 I1 I0 IF (Rr)≠#data r=0~7
242
IF (A)<#data r=0~7
THEN
(C)←1
ELSE
(C)←0
cation
D7 D6 D5 D4 D3 D2 D1 D0
CJNE @Rr, #data, 1 0 1 1 0 1 1 r 3 2 (PC)←(PC)+3 264
rel I7 I6 I5 I4 I3 I2 I1 I0 IF ((Rr))≠#data r=0 or 1
IF ((Rr))<#data r=0 or 1
THEN
(C)←1
ELSE
(C)←0
DJNZ Rr, rel 1 1 0 1 1 r2 r1 r0 2 2 (PC)←(PC)+2 285

R7 R6 R5 R4 R3 R2 R1 R0 (Rr)←(Rr)–1 r=0~7
IF (Rr)≠0 r=0~7
243
THEN
DJNZ direct, rel 1 1 0 1 0 1 0 1 3 2 (PC)←(PC)+3 287
a7 a6 a5 a4 a3 a2 a1 a0 (direct address)←(direct address)–1
R7 R6 R5 R4 R3 R2 R1 R0 IF (direct address)≠0
THEN
JZ rel 0 1 1 0 0 0 0 0 2 2 (PC)←(PC)+2 307
R7 R6 R5 R4 R3 R2 R1 R0 IF (A)=0
THEN
MSM80C154S/83C154S/85C154HVS
cation
D7 D6 D5 D4 D3 D2 D1 D0
JNZ rel 0 1 1 1 0 0 0 0 2 2 (PC)←(PC)+2 305
R7 R6 R5 R4 R3 R2 R1 R0 IF (A)≠0
THEN
JC rel 0 1 0 0 0 0 0 0 2 2 (PC)←(PC)+2 298
R7 R6 R5 R4 R3 R2 R1 R0 IF (C)=1
THEN
JNC rel 0 1 0 1 0 0 0 0 2 2 (PC)←(PC)+2 303
R7 R6 R5 R4 R3 R2 R1 R0 IF (C)=0
THEN
244
JB bit, rel 0 0 1 0 0 0 0 0 3 2 (PC)←(PC)+3 294

b7 b6 b5 b4 b3 b2 b1 b0 IF (bit address)=1
JNB bit, rel 0 0 1 1 0 0 0 0 3 2 (PC)←(PC)+3 301
JBC bit, rel 0 0 0 1 0 0 0 0 3 2 (PC)←(PC)+3 296
(bit address)←0
cation
D7 D6 D5 D4 D3 D2 D1 D0
External memory instructions
MOVX A, @Rr 1 1 1 0 0 0 1 r 1 2 (A)←((Rr)) EXTERNAL RAM r=0 or 1 334
MOVX A, @DPTR 1 1 1 0 0 0 0 0 1 2 (A)←((DPTR)) EXTERNAL RAM 333
MOVX @Rr, A 1 1 1 1 0 0 1 r 1 2 ((Rr))←(A) EXTERNAL RAM r=0 or 1 332
MOVX @DPTR, A 1 1 1 1 0 0 0 0 1 2 ((DPTR))←(A) EXTERNAL RAM 331
NOP 0 0 0 0 0 0 0 0 1 1 (PC)←(PC)+1 336

245
Other instruction
MSM80C154S/83C154S/85C154HVS
7.5 Detailed Description of MSM80C154S/MSM83C154S Instructions
Note: “direct address” is represented as “data address” in this detailed description.
1. ACALL code address (Absolute call within 2K bytes page)

7 0
Instruction code : A10 A9 A8 1 0 0 0 0 Byte 1
7 0
Call address A7 A6 A5 A4 A3 A2 A1 A0 Byte 2
Operations : (PC)←(PC)+2
(SP)←(SP)+1
((SP))←(PC0~7)
(SP)←(SP)+1
((SP))←(PC8~15)
(PC0~10)←A0~10
Number of bytes :2
Number of cycles :2
Flags : C AC F0 RS1 RS0 OV F1 P
(PSW)
Description : This instruction stores the program counter value (return
address) in the stack following an increment operation.
The program counter data PC0~10 following PC+2 is replaced
by 11-bit page address data A0~10. The destination address for
this instruction must always be within the 2K byte page, but if
the instruction is placed at address X7FEH or X7FFH, execution
proceeds from the call address on the next page.
246
2. ADD A, #data (Add immediate data)
7 0
Instruction code : 0 0 1 0 0 1 0 0 Byte 1
7 0
#data I7 I6 I5 I4 I3 I2 I1 I0 Byte 2
Operation : (A)←(A)+#data
Number of bytes :2
Number of cycles :1
(PSW) • • • •
Description : An 8-bit immediate data value is added to the accumulator. The
result is placed in the accumulator, and the flags are updated.
Example ADD A, #07H
7 0
7 0
0 0 0 0 0 1 1 1 Byte 2
Before execution After execution

Accumulator Accumulator
0 1 1 0 0 0 1 0 0 1 1 0 1 0 0 1
7 0 7 0
247
MSM80C154S/83C154S/85C154HVS
3. ADD A, @Rr (Add indirect address)
7 0
Instruction code : 0 0 1 0 0 1 1 r Byte 1
Operation : (A)←(A)+((Rr)) r=0 or 1
Number of bytes :1
Number of cycles :1
(PSW) • • • •
Description : The data memory location contents addressed by the register r
contents are added to the accumulator. The result is placed in
the accumulator, and the flags are updated.
Example ADD A, @R0
7 0

0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0
7 0 7 0
Register 0 Register 0
0 1 0 1 1 1 0 0 0 1 0 1 1 1 0 0
7 0 7 0
5CH 5CH
0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1
7 0 7 0
248
4. ADD A, Rr (Add register)
7 0
Instruction code : 0 0 1 0 1 r2 r1 r0 Byte 1
Operation : (A)←(A)+(Rr) r=0 thru 7
Number of bytes :1
Number of cycles :1
(PSW) • • • •
Description : The register r contents are added to the accumulator. The result
is placed in the accumulator, and the flags are updated.
Example ADD A, R6
7 0

0 1 0 1 0 1 0 0 1 0 1 1 0 0 0 1
7 0 7 0
0 1 0 1 1 1 0 1 0 1 0 1 1 1 0 1
7 0 7 0
249
MSM80C154S/83C154S/85C154HVS
5. ADD A, data address (Add memory)
7 0
7 0
Data address a7 a6 a5 a4 a3 a2 a1 a0 Byte 2
Operation : (A)←(A)+(data address)
Number of bytes :2
Number of cycles :1
(PSW) • • • •
Description : The specified data address contents are added to the
accumulator. The result is placed in the accumulator, and the
flags are updated.
Example ADD A, P1
7 0
7 0
1 0 0 1 0 0 0 0 Byte 2

0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 0
7 0 7 0
Port 1(90H) Port 1(90H)
1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0
7 0 7 0
250
6. ADDC A, #data (Add carry plus immediate data to accumulator)
7 0
7 0
Operation : (A)←(A)+(C)+#data
Number of bytes :2
Number of cycles :1
(PSW) • • • •
Description : The carry flag is added to the accumulator, and an 8-bit
immediate data is added to that result. The result is placed in
the accumulator, and the flags are updated.
Example ADDC A, #76H
7 0
7 0
0 1 1 1 0 1 1 0 Byte 2

0 1 0 1 1 0 0 1 1 1 0 1 0 0 0 0
7 0 7 0
Carry flag Carry flag
1 0
251
MSM80C154S/83C154S/85C154HVS
7. ADDC A, @Rr (Add carry plus indirect address to accumulator)
7 0
Operation : (A)←(A)+(C)+((Rr)) r=0 or 1
Number of bytes :1
Number of cycles :1
(PSW) • • • •
Description : The carry flag is added to the accumulator, and the contents of
data memory location addressed by the register r contents are
added to the accumulator. The result is placed in the
accumulator, and the flags are updated.
Example ADDC A, @R0
7 0

1 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0
7 0 7 0
0 1 1 0 1 0 1 1 0 1 1 0 1 0 1 1
7 0 7 0
6BH 6BH
0 1 1 1 1 0 1 1 0 1 1 1 1 0 1 1
7 0 7 0
0 1
252
8. ADD A, Rr (Add carry plus register to accumulator)
7 0
Operation : (A)←(A)+(C)+(Rr) r=0 thru 7
Number of bytes :1
Number of cycles :1
(PSW) • • • •
Description : The carry flag is added to the accumulator,and the register r
contents are added to the result. The result is placed in the
accumulator, and the flags are updated.
Example ADDC A, R2
7 0

0 1 1 0 1 0 0 0 1 1 0 1 0 1 1 1
7 0 7 0
0 1 1 0 1 1 1 0 0 1 1 0 1 1 1 0
7 0 7 0
1 0
253
MSM80C154S/83C154S/85C154HVS
9. ADDC A, data address (Add carry plus memory to accumulator)
7 0
7 0
Operation : (A)←(A)+(C)+(data address)
Number of bytes :2
Number of cycles :1
(PSW) • • • •
Description : The carry flag is added to the accumulator,and the specified
data address contents are added to that result. The result is
placed in the accumulator, and the flags are updated.
Example ADDC A, 45H
7 0
7 0
0 1 0 0 0 1 0 1 Byte 2

0 0 1 1 0 0 1 1 1 0 0 1 0 0 1 0
7 0 7 0
45H 45H
0 1 0 1 1 1 1 0 0 1 0 1 1 1 1 0
7 0 7 0
1 0
254
10. AJMP code address (Absolute jump within 2K byte page)
7 0
Instruction code : A10 A9 A8 0 0 0 0 1 Byte 1
7 0
(PC0~10)←A0~10
Number of bytes :2
Number of cycles :2
(PSW)
Description : After an increment ,the program counter PC0~10 is replaced by
11-bit page address data A0~10. The destination address for
this instruction must always be within the 2K byte page, but if
the instruction is placed at address X7FEH or X7FFH, execution
proceeds from the jump address on the next page.
255
MSM80C154S/83C154S/85C154HVS
11. ANL A, #data (Logical AND immediate data to accumulator)
7 0
7 0
Operation : (A)←(A) AND #data
Number of bytes :2
Number of cycles :1
(PSW) •
Description : The logical AND between an 8-bit immediate data value and the
accumulator contents is determined. The result is placed in the
accumulator and the flag is updated.
Example ANL A, #0AH
7 0
7 0
0 0 0 0 1 0 1 0 Byte 2

1 0 1 1 1 1 0 1 0 0 0 0 1 0 0 0
7 0 7 0
256
12. ANL A, @Rr (Logical AND indirect address to accumulator)
7 0
Operation : (A)←(A) AND ((Rr)) r=0 or 1
Number of bytes :1
Number of cycles :1
(PSW) •
Description : The logical AND between the accumulator contents and the
data memory location contents addressed by the register r
contents is determined. The result is placed in the accumulator
and the flag is updated.
Example ANL A, @R0
7 0

1 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0
7 0 7 0
0 1 0 1 1 0 0 0 0 1 0 1 1 0 0 0
7 0 7 0
RAM 58H RAM 58H
1 1 1 1 1 0 1 0 1 1 1 1 1 0 1 0
7 0 7 0
257
MSM80C154S/83C154S/85C154HVS
13. ANL A, Rr (Logical AND register to accumulator)
7 0
Operation : (A)←(A) AND (Rr) r=0 thru 7
Number of bytes :1
Number of cycles :1
(PSW) •
register r contents is determined. The result is placed in the
Example ANL A, R5
7 0

1 1 0 1 1 0 1 1 0 1 0 1 0 0 0 1
7 0 7 0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
7 0 7 0
258
14. ANL A, data address (Logical AND memory to accumulator)
7 0
7 0
Operation : (A)←(A) AND (data address)
Number of bytes :2
Number of cycles :1
(PSW) •
specified data address contents is determined. The result is
placed in the accumulator and the flag is updated.
Example ANL A, P1
7 0
7 0
1 0 0 1 0 0 0 0 Byte 2

1 1 1 0 0 1 0 1 1 0 1 0 0 1 0 1
7 0 7 0
Port 1 Port 1
1 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1
7 0 7 0
259
MSM80C154S/83C154S/85C154HVS
15. ANL C, bit address (Logical AND bit to carry flag)
7 0
7 0
Bit address b7 b6 b5 b4 b3 b2 b1 b0 Byte 2
Operation : (C)←(C) AND (bit address)
Number of bytes :2
Number of cycles :2
(PSW) •
Description : The logical AND between the carry flag and the specified bit
address contents is determined. The result is placed in the carry
flag.
Example ANL C, ACC.5
7 0
7 0
1 1 1 0 0 1 0 1 Byte 2

1 0
1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0
7 5 0 7 5 0
260
16. ANL C,/bit address (Logical AND complement bit to carry flag)
7 0
7 0
Operation : (C)←(C) AND (bit address)
Number of bytes :2
Number of cycles :2
(PSW) •
Description : The logical AND between the carry flag and the complement of
specified bit address contents is determined. The result is
placed in the carry flag.
Example ANL C,/P1.3
7 0
7 0
1 0 0 1 0 0 1 1 Byte 2

1 0
Port 1 Port 1
0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0
7 3 0 7 3 0
261
MSM80C154S/83C154S/85C154HVS
17. ANL data address, #data (Logical AND immediate data to memory)
7 0
7 0
7 0
Operation : (data address)←(data address) AND #data
Number of bytes :3
Number of cycles :2
(PSW)
Description : The logical AND between an 8-bit immediate data value and the
placed in the specified data address.
Example ANL DPH, #0AAH
7 0
7 0
1 0 0 0 0 0 1 1 Byte 2
7 0
1 0 1 0 1 0 1 0 Byte 3

DPH DPH
1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0
7 0 7 0
262
18. ANL data address, A (Logical AND accumulator to memory)
7 0
7 0
Operation : (data address)←(data address) AND (A)
Number of bytes :2
Number of cycles :1
(PSW)
Description : The logical AND between the accumulator and the specified
data address contents is determined. The result is placed in the
specified data address.
Example ANL TCON, A
7 0
7 0
1 0 0 0 1 0 0 0 Byte 2

0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0
7 0 7 0
TCON TCON
1 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0
7 0 7 0
263
MSM80C154S/83C154S/85C154HVS
19. CJNE @Rr, #data, code address

(Compare indirect address to immediate data, jump if not equal)
7 0
7 0
7 0
Relative offset R7 R6 R5 R4 R3 R2 R1 R0 Byte 3
IF ((Rr))≠#data r=0 or 1
THEN
IF ((Rr))<#data r=0 or 1
THEN
(C)←1
ELSE
(C)←0
Number of bytes :3
Number of cycles :2
(PSW) •
contents are compared with an immediate data value. Control is
shifted to a relative jump address if the compared data is not
equal. If the compared data is equal, control is shifted to the
next address following this instruction. The carry flag is set to 1
if the immediate data value is greater than the specified address
contents, but is set to 0 if otherwise.
264
Example CJNE @R1, #05H, TEST

LOC OBJ SOURCE
00B4 2155 TEST:AJMP TEST1
0118 B70599 COMP:CJNE @R1, #05H, TEST

011B 020500 OUT:LJMP OUT1
7 0
7 0
0 0 0 0 0 1 0 1 Byte 2
7 0
1 0 0 1 1 0 0 1 Byte 3

0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1
7 0 7 0
35H 35H
0 0 1 0 1 0 1 1 0 0 1 0 1 0 1 1
7 0 7 0
1 0
Program counter Program counter

0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0
15 8 7 0 15 8 7 0
265
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20. CJNE A, #data, code address

(Compare immediate data to accumulator, jump if not equal)
7 0
7 0
7 0
IF (A)≠#data
THEN
IF (A)<#data
THEN
(C)←1
ELSE
(C)←0
Number of bytes :3
Number of cycles :2
(PSW) •
Description : The accumulator contents are compared with an immediate
data value, and control is shifted to a relative jump address if
the compared data is not equal. If the compared data is equal,
control is shifted to the next address following this instruction.
The carry flag is set to 1 if the immediate data value is greater
than the accumulator contents, but is set to 0 if otherwise.
266
Example CJNE A, #0AH, SS1

LOC OBJ SOURCE
0064 FF SS1:MOV R7, A
00C8 B40599 COMP:CJNE A, #0AH, SS1

00CB 0D INCR:INC R5
7 0
7 0
0 0 0 0 1 0 1 0 Byte 2
7 0
1 0 0 1 1 0 0 1 Byte 3

0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0
7 0 7 0
1 0

0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0
15 8 7 0 15 8 7 0
267
MSM80C154S/83C154S/85C154HVS
21. CJNE A, data address, code address

(Compare memory to accumulator, jump if not equal)
7 0
7 0
7 0
IF (A)≠(data address)
THEN
IF (A)<(data address)
THEN
(C)←1
ELSE
(C)←0
Number of bytes :3
Number of cycles :2
(PSW) •
Description : The accumulator contents are compared with the specified data
address contents, and control is shifted to a relative jump
address if the compared data is not equal. If the compared data
is equal, control is shifted to the next address following this
instruction. The carry flag is set to 1 if the specified data
address contents are greater than the accumulator contents,
but is set to 0 if otherwise.
268
Example CJNE A, 50H, NEXT

LOC OBJ SOURCE
10DC B55044 COMP:CJNE A, 50H, NEXT
10DF 120100 CAL:LCALL TEST
1123 14 NEXT:DEC A
7 0
7 0
0 1 0 1 0 0 0 0 Byte 2
7 0
0 1 0 0 0 1 0 0 Byte 3

50H 50H
0 1 0 1 1 1 1 0 0 1 0 1 1 1 1 0
7 0 7 0
0 0 1 0 0 1 1 0 0 0 1 0 0 1 1 0
7 0 7 0
0 1

0 0 0 1 0 0 0 0 1 1 0 1 1 1 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 1
15 8 7 0 15 8 7 0
269
MSM80C154S/83C154S/85C154HVS
22. CJNE Rr, #data, code address

(Compare immediate data to register, jump if not equal)
7 0
7 0
7 0
IF ((Rr))≠#data r=0 thru 7
THEN
IF ((Rr))<#data r=0 thru 7
THEN
(C)←1
ELSE
(C)←0
Number of bytes :3
Number of cycles :2
(PSW) •
Description : The register r contents are compared with an immediate data
value, and control is shifted to a relative jump address if the
compared data is not equal. If the compared data is equal,
control is shifted to the next address following this instruction.
The carry flag is set to 1 if the immediate data value is greater
than the register r contents, but is set to 0 if otherwise.
270
Example CJNE R4, #32H, COUNT

LOC OBJ SOURCE
0473 0C COUNT:INC R4
0482 BC32EE COMP:CJNE R4, #32H, COUNT
7 0
7 0
0 0 1 1 0 0 1 0 Byte 2
7 0
1 1 1 0 1 1 1 0 Byte 3

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
7 0 7 0
1 1

0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 1 0 0 1 1
15 8 7 0 15 8 7 0
271
MSM80C154S/83C154S/85C154HVS
23. CLR A (Clear accumulator)
7 0
Operation : (A)←0
Number of bytes :1
Number of cycles :1
(PSW) •
Description : The accumulator is cleared to 0 and flag is updated.
Example CLR A
7 0

1 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0
7 0 7 0
272
24. CLR C (Clear carry flag)
7 0
Operation : (C)←0
Number of bytes :1
Number of cycles :1
(PSW) •
Description : The carry flag is cleared to 0.
Example CLR C
7 0

1 0
273
MSM80C154S/83C154S/85C154HVS
25. CLR bit address (Clear bit)
7 0
7 0
Operation : (bit address)←0
Number of bytes :2
Number of cycles :1
(PSW)
Description : The specified bit address content is cleared to 0.
Example CLR P1.5
7 0
7 0
1 1 1 0 0 1 0 1 Byte 2

Port 1 Port 1
1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1
7 5 0 7 5 0
274
26. CPL A (Complement accumulator)
7 0
Operation : (A)←(A)
Number of bytes :1
Number of cycles :1
(PSW)
Description : Accumulator data 0 is set to 1 and 1 is set to 0.
Example CPL A
7 0

1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0
7 0 7 0
275
MSM80C154S/83C154S/85C154HVS
27. CPL C (Complement carry flag)
7 0
Operation : (C)←(C)
Number of bytes :1
Number of cycles :1
(PSW) •
Description : The carry flag is set to 1 if 0, set to 0 if 1.
Example CPL C
7 0

1 0

0 1
276
28. CPL bit address (Complement bit)
7 0
7 0
Operation : (bit address)←(bit address)
Number of bytes :2
Number of cycles :1
(PSW)
Description : The specified bit address content is set to 1 if 0, and set to 0 if 1.
Example CLR B.7
7 0
7 0
1 1 1 1 0 1 1 1 Byte 2

B register B register
0 1 0 1 0 1 1 1 1 1 0 1 0 1 1 1
7 0 7 0
277
MSM80C154S/83C154S/85C154HVS
29. DA A (Decimal adjust accumulator)
7 0
Operations : 100+6←(AC)=1 or 100>10
101+6
(C)←1 }
←(C)=1 or 101>10
Number of bytes :1
Number of cycles :1
(PSW) • •
Description : The arithmetic operation result located in the accumulator
following an addition between two 2-digit decimal number is
converted to a normal decimal number. When the contents of
accumulator bits 0 thru 3 (100 digit) are greater than 9, or when
the auxiliary carry (AC) is 1, 6 is added to accumulator bits 0
thru 3. And if the contents of accumulator bits 4 thru 7 (101 digit)
exceed 9, or if the result obtained by adding a carry from the
lower order digits after compensation is greater than 9, or if the
carry flag is 1, 6 is added to the data in accumulator bits 4 thru
7. The flags are also updated.
278
Example DA A
7 0

1 0 1 1 0 1 0 1 0 0 0 1 0 1 0 1
7 0 7 0
C AC C AC
0 0 1 0

0 0 1 1 0 0 0 1 1 0 0 1 0 1 1 1
7 0 7 0
C AC C AC
1 1 1 1

1 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0
7 0 7 0
C AC C AC
0 0 1 0
279
MSM80C154S/83C154S/85C154HVS
30. DEC @Rr (Decrement indirect address)
7 0
Operation : ((Rr))←((Rr))–1 r=0 or 1
Number of bytes :1
Number of cycles :1
(PSW)
Description : The contents of the data memory location addressed by the
register r contents are decremented by 1.
Example DEC @R0
7 0

0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 0
7 0 7 0
6AH 6AH
1 0 0 1 0 0 0 0 1 0 0 0 1 1 1 1
7 0 7 0
280
31. DEC A (Decrement accumulator)
7 0
Operation : (A)←(A)–1
Number of bytes :1
Number of cycles :1
(PSW) •
Description : The accumulator contents are decremented by 1, and the flag is
updated.
Example DEC A
7 0

1 0 1 0 1 0 0 0 1 0 1 0 0 1 1 1
7 0 7 0
281
MSM80C154S/83C154S/85C154HVS
32. DEC Rr (Decrement register)
7 0
Operation : (Rr)←(Rr)–1 r=0 thru 7
Number of bytes :1
Number of cycles :1
(PSW)
Description : The register r contents are decremented by 1.
Example DEC R7
7 0

1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
7 0 7 0
282
33. DEC data address (Decrement memory)
7 0
7 0
Operation : (data address)←(data address)–1
Number of bytes :2
Number of cycles :1
(PSW)
Description : The specified data address contents are decremented by 1.
Example DEC 5AH
7 0
7 0
0 1 0 1 1 0 1 0 Byte 2

5AH 5AH
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
7 0 7 0
283
MSM80C154S/83C154S/85C154HVS
34. DIV AB (Divide accumulator by B)
7 0
Operation : (A) quotient←(A)/(B)
(B) remainder
Number of bytes :1
Number of cycles :4
(PSW) • • •
Description : The accumulator contents are devided by the contents of
arithmetic operation register (B). The two data values are
handled as integers without sign. The quotient is placed in the
accumulator, and the remainder in the arithmetic operation
register (B). The carry flag is always cleared, and the overflow
flag (OV) is set to 1 if division by 0 is executed. This flag is
cleared in all other cases. If division by 0 is executed, the
accumulator and arithmetic operation register (B) contents
remain unchanged.
Example DIV AB(0AEH÷7H=18…………remainder 6H)
7 0

1 0 1 0 1 1 1 0 0 0 0 1 1 0 0 0
7 0 7 0
B register B register
0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 0
7 0 7 0
284
35. DJNZ Rr, code address (Decrement register, and jump if not zero)
7 0
7 0
(Rr)←(Rr)–1 r=0 thru 7
IF (Rr)≠0
THEN
Number of bytes :2
Number of cycles :2
(PSW)
Description : The register r contents are decremented by 1. Control is shifted
to a relative jump address if the register r contents are not 0 as
a result of the decrement. Control is shifted to the next address
following this instruction if the result is 0.
285
MSM80C154S/83C154S/85C154HVS
Example DJNZ R1, LOOP

LOC OBJ SOURCE
00FE 2F LOOP:ADD A, R7
010B D9F1 COUNT:DJNZ R1, LOOP
7 0
7 0
1 1 1 1 0 0 0 1 Byte 2

0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1
7 0 7 0
0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0
15 8 7 0 15 8 7 0
286
36. DJNZ data address, code address (Decrement memory, and jump if not zero)
7 0
7 0
7 0
(data address)←(data address)–1
IF (data address)≠0
THEN
Number of bytes :3
Number of cycles :2
(PSW)
Description : The specified data address contents are decremented by 1.
Control is shifted to a relative jump address if data address
contents are not 0 as a result of the decrement. Control is
shifted to the next address following this instruction if the result
is 0.
287
MSM80C154S/83C154S/85C154HVS
Example DJNZ 57H, LOOP 1

LOC OBJ SOURCE
1033 A957 LOOP 1:MOV R1, 57H
1095 D5579B COUNT:DJNZ 57H, LOOP 1
7 0
7 0
0 1 0 1 0 1 1 1 Byte 2
7 0
1 0 0 1 1 0 1 1 Byte 3

57H 57H
0 1 1 0 1 0 1 1 0 1 1 0 1 0 1 0
7 0 7 0
0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 1 1
15 8 7 0 15 8 7 0
288
37. INC @Rr (Increment indirect address)
7 0
Operation : ((Rr))←((Rr))+1 r=0 or 1
Number of bytes :1
Number of cycles :1
(PSW)
Description : The contents of the data memory location addressed by the
register r contents are incremented by 1.
Example INC @R1
7 0

0 1 1 0 0 1 0 1 0 1 1 0 0 1 0 1
7 0 7 0
65H 65H
0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0
7 0 7 0
289
MSM80C154S/83C154S/85C154HVS
38. INC A (Increment accumulator)
7 0
Operation : (A)←(A)+1
Number of bytes :1
Number of cycles :1
(PSW) •
Description : The accumulator contents are incremented by 1, and the flag is
updated.
Example INC A
7 0

1 0 1 1 0 1 1 1 1 0 1 1 1 0 0 0
7 0 7 0
290
39. INC DPTR (Increment data pointer)
7 0
Operation : (DPTR)←(DPTR)+1
Number of bytes :1
Number of cycles :2
(PSW)
Description : 16-bit contents od the data pointer (DPH·DPL) are incremented
by 1.
Example INC DPTR
7 0
Before execution
DPH DPL
0 1 1 0 1 0 0 0 1 1 1 1 1 1 1 1
15 8 7 0
After execution
DPH DPL
0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0
15 8 7 0
291
MSM80C154S/83C154S/85C154HVS
40. INC Rr (Increment register)
7 0
Operation : (Rr)←(Rr)+1 r=0 thru 7
Number of bytes :1
Number of cycles :1
(PSW)
Description : The register r contents are incremented by 1.
Example INC R5
7 0

1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0
7 0 7 0
292
41. INC data address (Increment memory)
7 0
7 0
Operation : (data address)←(data address)+1
Number of bytes :2
Number of cycles :1
(PSW)
Description : The specified data address contents are incremented by 1.
Example INC P1
7 0
7 0
Data address : 1 0 0 1 0 0 0 0 Byte 2

Port 1 Port 1
0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0
7 0 7 0
293
MSM80C154S/83C154S/85C154HVS
42. JB bit address, code address (Jump if bit is set)
7 0
7 0
7 0
IF (bit address)=1
THEN
Number of bytes :3
Number of cycles :2
(PSW)
Description : Control is shifted to a relative jump address if the specified bit
address content is 1.
Control is shifted to the next address following this instruction if
the content is 0.
294
Example JB 34.3, ENTER

LOC OBJ SOURCE
0903 20134A BITTS:JB 34.3, ENTER
0950 ACA0 ENTER:MOV R4, 0A0H
7 0
7 0
0 0 0 1 0 0 1 1 Byte 2
7 0
0 1 0 0 1 0 1 0 Byte 3

34 34
0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0
7 3 0 7 3 0
0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 0
15 8 7 0 15 8 7 0
295
MSM80C154S/83C154S/85C154HVS
43. JBC bit address, code address (Jump and clear if bit is set)
7 0
7 0
7 0
IF (bit address)=1
THEN
(bit address)←0
Number of bytes :3
Number of cycles :2
(PSW)
address content is 1, and that bit is cleared to 0.
the content is 0.
296
Example JBC 46.1, COUNT 4

LOC OBJ SOURCE
00DC C281 COUNT 4:CLR 128.1
0136 1071A3 BTEST:JBC46.1, COUNT 4
7 0
7 0
0 1 1 1 0 0 0 1 Byte 2
7 0
1 0 1 0 0 0 1 1 Byte 3

46 46
1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0
7 1 0 7 1 0
0 0 0 0 0 0 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0
15 8 7 0 15 8 7 0
297
MSM80C154S/83C154S/85C154HVS
44. JC code address (Jump if carry is set)
7 0
7 0
IF (C)=1
THEN
Number of bytes :2
Number of cycles :2
(PSW)
Description : Control is shifted to a relative jump address if the carry flag is 1.
the content is 0.
298
Example JC CARRY
LOC OBJ SOURCE
16DC 7110 CHECK:ACALL ADDR

16DE 4015 JMPC:JC CARRY
16F5 07 CARRY:INC @R1
7 0
7 0
0 0 0 1 0 1 0 1 Byte 2

1 1

0 0 0 1 0 1 1 0 1 1 0 1 1 1 1 0 0 0 0 1 0 1 1 0 1 1 1 1 0 1 0 1
15 8 7 0 15 8 7 0
299
MSM80C154S/83C154S/85C154HVS
45. JMP @A + DPTR (Jump to sum of accumulator and data pointer)
7 0
Operation : (PC)←(A)+(DPTR)
Number of bytes :1
Number of cycles :2
(PSW)
Description : The accumulator contents are added to the data pointer con-
tents, and the resulting sum is placed in the program counter.
Example JMP @A+DPTR
7 0

1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0
7 0 7 0
DPH DPL DPH DPL
0 0 1 0 1 0 0 0 1 1 0 0 1 1 1 0 0 0 1 0 1 0 0 0 1 1 0 0 1 1 1 0
15 8 7 0 15 8 7 0
0 0 0 1 0 0 1 0 0 0 1 0 1 0 1 1 0 0 1 0 1 0 0 1 1 0 0 0 0 1 0 0
15 8 7 0 15 8 7 0
300
46. JNB bit address, code address (Jump if bit is not set)
7 0
7 0
7 0
IF (bit address)=0
THEN
Number of bytes :3
Number of cycles :2
(PSW)
address content is 0, but shifted to the next address following
this instruction if the content is 1.
301
MSM80C154S/83C154S/85C154HVS
Example JNB 37.3, EXIT

LOC OBJ SOURCE
0835 302B22 TEST:JNB 37.3, EXIT
085A E6 EXIT:MOV A, @R0
7 0
7 0
0 0 1 0 1 0 1 1 Byte 2
7 0
0 0 1 0 0 0 1 0 Byte 3

37 37
0 0 1 1 0 1 1 1 0 0 1 1 0 1 1 1
7 3 0 7 3 0
0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 1 0 0 0 0 1 0 1 1 0 1 0
15 8 7 0 15 8 7 0
302
47. JNC code address (Jump if carry is not set)
7 0
7 0
IF (C)=0
THEN
Number of bytes :2
Number of cycles :2
(PSW)
Description : Control is shifted to a relative jump address if the carry flag is 0.
the content is 1.
303
MSM80C154S/83C154S/85C154HVS
Example JNC EXIT

LOC OBJ SOURCE
0835 5022 TEST:JNC EXIT
0859 85E0F0 EXIT:MOV B, ACC
7 0
7 0
0 0 1 0 0 0 1 0 Byte 2

0 0

0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 1
15 8 7 0 15 8 7 0
304
48. JNZ code address (Jump if accumulator is not 0)
7 0
7 0
IF (A)≠0
THEN
Number of bytes :2
Number of cycles :2
(PSW)
Description : Control is shifted to a relative jump address if the accumulator
contents are not 0. Control is shifted to the next address
following this instruction if the contents are 0.
305
MSM80C154S/83C154S/85C154HVS
Example JNZ TEST

LOC OBJ SOURCE
00FC 7030 CHECK:JNZ TEST
012E FB TEST:MOV R3, A
7 0
7 0
0 0 1 1 0 0 0 0 Byte 2

0 1 0 1 1 1 0 1 0 1 0 1 1 1 0 1
7 0 7 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 1 0
15 8 7 0 15 8 7 0
306
49. JZ code address (Jump if accumulator is not 0)
7 0
7 0
IF (A)=0
THEN
Number of bytes :2
Number of cycles :2
(PSW)
Description : Control is shifted to a relative jump address if the accumulator
contents are 0. Control is shifted to the next address following
this instruction if the contents are not 0.
307
MSM80C154S/83C154S/85C154HVS
Example JZ EMPTY
LOC OBJ SOURCE
0099 04 EMPTY:INC A
00CA 60CD CHECK:JZ EMPTY
7 0
7 0
1 1 0 0 1 1 0 1 Byte 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 0 7 0
0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1
15 8 7 0 15 8 7 0
308
50. LCALL code address (Long call)
7 0
7 0
7 0
(SP)←(SP)+1
((SP))←(PC0~7)
(SP)←(SP)+1
((SP))←(PC8~15)
(PC0~15)←A0~15
Number of bytes :3
Number of cycles :2
(PSW)
Description : The contents of the program counter (return address) are
pushed in the stack following an increment.
Call address A0~15 specified by operand are placed in the
program counter PC0~15.
This instruction is capable of call to anywhere within the entire
range of 64K words.
309
MSM80C154S/83C154S/85C154HVS
51. LJMP code address (Long jump)
7 0
7 0
Jump address A15 A14 A13 A12 A11 A10 A9 A8 Byte 2
7 0
Jump address A7 A6 A5 A4 A3 A2 A1 A0 Byte 3
Operation : (PC0~15)←A0~15
Number of bytes :3
Number of cycles :2
(PSW)
Description : Jump address A0~15 specified by operand are placed in the
program counter PC0~15.
This instruction is capable of jump to anywhere within the entire
range of 64K words.
310
52. MOV @Rr, #data (Move immediate data to indirect address)
7 0
7 0
Data address I7 I6 I5 I4 I3 I2 I1 I0 Byte 2
Operation : ((Rr))←#data r=0 or 1
Number of bytes :2
Number of cycles :1
(PSW)
Description : An 8-bit immediate data value is copied to the data memory
location addressed by the register r contents.
Example MOV @R1, #0AAH
7 0
7 0
1 0 1 0 1 0 1 0 Byte 2

0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 0
7 0 7 0
6AH 6AH
0 1 1 1 0 1 1 1 1 0 1 0 1 0 1 0
7 0 7 0
311
MSM80C154S/83C154S/85C154HVS
53. MOV @Rr, A (Move accumulator to indirect address)
7 0
Operation : ((Rr))←(A) r=0 or 1
Number of bytes :1
Number of cycles :1
(PSW)
Description : The accumulator contents are copied to the data memory
location addressed by the register r contents.
Example MOV @R0, A
7 0

0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0
7 0 7 0
6CH 6CH
1 0 1 1 1 0 1 1 0 1 0 1 0 1 0 1
7 0 7 0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
7 0 7 0
312
54. MOV @Rr, data address (Move memory to indirect address)
7 0
7 0
Operation : ((Rr))←(data address) r=0 or 1
Number of bytes :2
Number of cycles :2
(PSW)
Description : The specified data address contents are copied to the data
memory location addressed by the register r contents.
Example MOV @R0, 0E0H
7 0
7 0
1 1 1 0 0 0 0 0 Byte 2

0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 1
7 0 7 0
0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0
7 0 7 0
72H 72H
0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 1
7 0 7 0
313
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55. MOV A, #data (Move immediate data to accumulator)
7 0
7 0
Operation : (A)←#data
Number of bytes :2
Number of cycles :1
(PSW) •
Description : An 8-bit immediate data is copied to the accumulator, and the
flag is updated.
Example MOV A, #05H
7 0
7 0
0 0 0 0 0 1 0 1 Byte 2

0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1
7 0 7 0
314
56. MOV A, @Rr (Move indirect address to accumulator)
7 0
Operation : (A)←((Rr)) r=0 or 1
Number of bytes :1
Number of cycles :1
(PSW) •
contents are copied to the accumulator, and the flag is updated.
Example MOV A, @R0
7 0

0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0
7 0 7 0
72H 72H
1 0 1 1 0 1 1 1 1 0 1 1 0 1 1 1
7 0 7 0
0 1 0 0 1 1 0 0 1 0 1 1 0 1 1 1
7 0 7 0
315
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57. MOV A, Rr (Move register to accumulator)
7 0
Operation : (A)←(Rr) r=0 thru 7
Number of bytes :1
Number of cycles :1
(PSW) •
Description : The register r contents are copied to the accumulator, and the
flag is updated.
Example MOV A, R6
7 0

1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1
7 0 7 0
0 0 0 0 1 0 1 1 1 0 1 0 0 1 0 1
7 0 7 0
316
58. MOV A, data address (Move memory to accumulator)
7 0
7 0
Operation : (A)←(data address)
Number of bytes :2
Number of cycles :1
(PSW) •
Description : The specified data address contents are copied to the accumu-
lator, and the flag is updated.
Example MOV A, P1
7 0
7 0
1 0 0 1 0 0 0 0 Byte 2

Port 1 Port 1
0 1 1 0 0 1 1 1 0 1 1 0 0 1 1 1
7 0 7 0
0 1 0 0 0 0 1 0 0 1 1 0 0 1 1 1
7 0 7 0
317
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59. MOV C, bit address (Move bit to carry flag)
7 0
7 0
Operation : (C)←(bit address)
Number of bytes :2
Number of cycles :1
(PSW) •
Description : The specified bit address content is copied to the carry flag.
Example MOV C, P3.4
7 0
7 0
1 0 1 1 0 1 0 0 Byte 2

Port 3 Port 3
0 0 0 1 0 1 1 0 0 0 0 1 0 1 1 0
7 4 0 7 4 0
0 1
318
60. MOV DPTR, #data (Move immediate data to data pointer)
7 0
7 0
7 0
Operation : (DPTR)←#data
(DPH)←I8~15
(DPL)←I0~7
Number of bytes :3
Number of cycles :2
(PSW)
Description : A 16-bit immediate data value is copied to the data pointer
(DPH·DPL).
Example MOV DPTR, #0AF5H
7 0
7 0
0 0 0 0 1 0 1 0 Byte 2
7 0
1 1 1 1 0 1 0 1 Byte 3

DPH DPL DPH DPL
1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 1 0 1 1 1 1 0 1 0 1
15 8 7 0 15 8 7 0
319
MSM80C154S/83C154S/85C154HVS
61. MOV Rr, #data (Move immediate data to register)
7 0
7 0
Operation : (Rr)←#data r=0 thru 7
Number of bytes :2
Number of cycles :1
(PSW)
Description : An 8-bit immediate data value is copied to the register r.
Example MOV R5, #0AH
7 0
7 0
0 0 0 0 1 0 1 0 Byte 2

1 0 1 0 1 0 1 1 0 0 0 0 1 0 1 0
7 0 7 0
320
62. MOV Rr, A (Move accumulator to register)
7 0
Operation : (Rr)←(A) r=0 thru 7
Number of bytes :1
Number of cycles :1
(PSW)
Description : The accumulator contents are copied to the register r.
Example MOV R1, A
7 0

0 1 1 1 1 1 1 0 1 0 0 1 1 0 0 1
7 0 7 0
1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
7 0 7 0
321
MSM80C154S/83C154S/85C154HVS
63. MOV Rr, data address (Move memory to register)
7 0
7 0
Operation : (Rr)←(data address) r=0 thru 7
Number of bytes :2
Number of cycles :2
(PSW)
Description : The specified data address contents are copied to the register r.
Example MOV R0, 5AH
7 0
7 0
0 1 0 1 1 0 1 0 Byte 2

0 1 1 1 1 0 1 1 1 0 1 0 1 0 1 0
7 0 7 0
5AH 5AH
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
7 0 7 0
322
64. MOV bit address, C (Move carry flag to bit)
7 0
7 0
Operation : (bit address)←(C)
Number of bytes :2
Number of cycles :2
(PSW)
Description : The carry flag content is copied to the specified bit address.
Example MOV P1.4, C
7 0
7 0
1 0 0 1 0 1 0 0 Byte 2

Port 1 Port 1
1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1
7 4 0 7 4 0
0 0
323
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65. MOV data address, #data (Move immediate data to memory)
7 0
7 0
7 0
Operation : (data address)←#data
Number of bytes :3
Number of cycles :2
(PSW)
Description : An 8-bit immediate data value is copied to the specified data
address.
Example MOV TCON, #50H
7 0
7 0
1 0 0 0 1 0 0 0 Byte 2
7 0
0 1 0 1 0 0 0 0 Byte 3

TCON(88H) TCON(88H)
0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0
7 0 7 0
324
66. MOV data address, @Rr (Move indirect address to memory)
7 0
7 0
Operation : (data address)←((Rr)) r=0 or 1
Number of bytes :2
Number of cycles :2
(PSW)
contents are copied to the specified data address.
Example MOV ACC, @R1
7 0
7 0
1 1 1 0 0 0 0 0 Byte 2

0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1
7 0 7 0
0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 1
7 0 7 0
25H 25H
0 1 1 0 1 1 1 1 0 1 1 0 1 1 1 1
7 0 7 0
325
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67. MOV data address, A (Move accumulator to memory)
7 0
7 0
Operation : (data address)←(A)
Number of bytes :2
Number of cycles :1
(PSW)
Description : The accumulator contents are copied to the specified data
address.
Example MOV P3, A
7 0
7 0
1 0 1 1 0 0 0 0 Byte 2

Port 3 Port 3
1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0
7 0 7 0
1 1 1 0 1 1 0 0 1 1 1 0 1 1 0 0
7 0 7 0
326
68. MOV data address, Rr (Move register to memory)
7 0
7 0
Operation : (data address)←(Rr) r=0 thru 7
Number of bytes :2
Number of cycles :2
(PSW)
Description : The register r contents are copied to the specified data address.
Example MOV 6BH, R2
7 0
7 0
0 1 1 0 1 0 1 1 Byte 2

6BH 6BH
1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1
7 0 7 0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
7 0 7 0
327
MSM80C154S/83C154S/85C154HVS
69. MOV data address 1, data address 2 (Move memory to memory)
7 0
7 0
Data address 2 a72 a62 a52 a42 a32 a22 a12 a02 Byte 2
7 0
Data address 1 a71 a61 a51 a41 a31 a21 a11 a01 Byte 3
Operation : (data address 1)←(data address 2)
Number of bytes :3
Number of cycles :2
(PSW)
Description : The source data address (data address 2) contents are copied
to the destination data address (data address 1).
Example MOV ACC, P1
7 0
7 0
1 0 0 1 0 0 0 0 Byte 2
7 0
1 1 1 0 0 0 0 0 Byte 3

Port 1 Port 1
1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0
7 0 7 0
0 1 1 1 1 0 1 1 1 0 1 1 0 1 0 0
7 0 7 0
328
70. MOVC A, @A + DPTR

(Move code memory offset from data pointer to accumulator)
7 0
Operation : (A)←((A)+(DPTR))
Number of bytes :1
Number of cycles :2
(PSW) •
Description : The data pointer contents are added to the accumulator con-
tents, and after temporary storage of the sum in the program
counter, the ROM data contents specified by the program
counter are stored in the accumulator. The program counter
contents are then restored to former contents, and the flag is
updated.
Example MOVC A, @A+DPTR
7 0

1 1 1 1 0 1 1 1 0 1 0 1 0 1 0 1
7 0 7 0
DPH DPL DPH DPL
0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1
15 8 7 0 15 8 7 0
0200H 0200H
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
7 0 7 0
329
MSM80C154S/83C154S/85C154HVS
71. MOVC A, @A + PC
(Move code memory offset from program counter to accumulator)
7 0
(A)←((A)+(PC))
Number of bytes :1
Number of cycles :2
(PSW) •
Description : The program counter contents following an increment are
added to the accumulator contents, and after temporary storage
of the sum in the program counter, the ROM data contents
specified by the program counter are stored in the accumulator.
The program counter contents are then restored to former
contents, and the flag is also updated.
Example MOVC A, @A+PC
7 0

1 1 1 0 0 0 0 0 1 1 1 0 1 1 1 0
7 0 7 0
0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1
15 8 7 0 15 8 7 0
0301H 0301H
1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0
7 0 7 0
330
72. MOVX @DPTR, A

(Move accumulator to external memory addressed by data pointer)
7 0
Operation : ((DPTR))←(A)
Number of bytes :1
Number of cycles :2
(PSW)
Description : The accumulator contents are stored in external data memory
(RAM) addressed by the data pointer contents.
Example MOVX @DPTR, A
7 0

DPH DPL DPH DPL
0 1 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0 0
15 8 7 0 15 8 7 0
62CCH 62CCH
1 0 1 1 1 0 0 0 0 0 0 0 0 1 0 1
7 0 7 0
0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1
7 0 7 0
331
MSM80C154S/83C154S/85C154HVS
73. MOVX @Rr, A

(Move accumulator to external memory addressed by register)
7 0
Operation : ((Rr))←(A) r=0 or 1
Number of bytes :1
Number of cycles :2
(PSW)
Description : The accumulator contents are stored in external data memory
addressed by the register r contents.
Example MOVX @R0, A
7 0

1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0
7 0 7 0
0A0H 0A0H
0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 1
7 0 7 0
1 0 1 1 1 1 0 1 1 0 1 1 1 1 0 1
7 0 7 0
332
74. MOVX A, @DPTR

(Move external memory addressed by data pointer to accumulator)
7 0
Operation : (A)←((DPTR))
Number of bytes :1
Number of cycles :2
(PSW) •
Description : External data memory (RAM) contents addressed by the data
pointer are stored in the accumulator, and the flag is updated.
Example MOVX A, @DPTR
7 0

1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 0
7 0 7 0
DPH DPL DPH DPL
0 1 0 1 0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 1 1 1 0 1 0 1 1 1 1
15 8 7 0 15 8 7 0
57AFH 57AFH
1 0 1 1 1 0 1 0 1 0 1 1 1 0 1 0
7 0 7 0
333
MSM80C154S/83C154S/85C154HVS
75. MOVX A, @Rr (Move external memory addressed by register to accumulator)
7 0
Operation : (A)←((Rr)) r=0 or 1
Number of bytes :1
Number of cycles :2
(PSW) •
Description : External data memory (RAM) contents addressed by the
register r contents are stored in the accumulator, and the flag is
updated.
Example MOVX A, @R1
7 0

0 1 1 1 1 0 1 0 0 0 1 0 1 0 0 0
7 0 7 0
1 0 1 1 1 1 1 0 1 0 1 1 1 1 1 0
7 0 7 0
0BEH 0BEH
0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0
7 0 7 0
334
76. MUL AB (Multiply accumulator by B)
7 0
Operations : (A)0~7←(A) × (B)
(B)8~15
Number of bytes :1
Number of cycles :4
(PSW) • • •
Description : The accumulator contents are multiplied by the arithmetic
operation register (B) contents. The operand is always handled
as an integer without sign. The lower order byte of the result is
placed in the accumulator, and the higher order byte is placed
in the arithmetic operation register (B). The carry flag is always
cleared. The overflow flag is set to 1 if the product is greater
than 00FFH, and to 0 in all other cases.
Example MUL AB(6AH × 15H=8B2H)
7 0

0 1 1 0 1 0 1 0 1 0 1 1 0 0 1 0
7 0 7 0
Register B Register B
0 0 0 1 0 1 0 1 0 0 0 0 1 0 0 0
7 0 7 0
Overflow flag Overflow flag
0 1
335
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77. NOP (No operation)
7 0
Operation : (PC)←(PC)+1
Number of bytes :1
Number of cycles :1
(PSW)
Description : The program counter is incremented by 1 without any other
change in the CPU. Control is shifted to the next instruction.
336
78. ORL A, #data (Logical OR immediate data to accumulator)
7 0
7 0
Operation : (A)←(A) OR #data
Number of bytes :2
Number of cycles :1
(PSW) •
Description : The logical OR between an 8-bit immediate data value and the
accumulator contents is determined. The result is placed in the
Example ORL A, #5FH
7 0
7 0
0 1 0 1 1 1 1 1 Byte 2

1 0 0 0 0 1 0 0 1 1 0 1 1 1 1 1
7 0 7 0
337
MSM80C154S/83C154S/85C154HVS
79. ORL A, @Rr (Logical OR indirect address to accumulator)
7 0
Operation : (A)←(A) OR ((Rr)) r=0 or 1
Number of bytes :1
Number of cycles :1
(PSW) •
Description : The logical OR between the accumulator contents and the data
memory location contents addressed by the register r contents
is determined. The result is placed in the accumulator and the
flag is updated.
Example ORL A, @R0
7 0

0 0 0 1 1 0 0 0 1 0 1 1 1 1 1 1
7 0 7 0
0 1 1 0 1 1 0 1 0 1 1 0 1 1 0 1
7 0 7 0
6DH 6DH
1 0 1 0 0 1 1 1 1 0 1 0 0 1 1 1
7 0 7 0
338
80. ORL A, Rr (Logical OR register to accumulator)
7 0
Operation : (A)←(A) OR (Rr) r=0 thru 7
Number of bytes :1
Number of cycles :1
(PSW) •
Description : The logical OR between the accumulator contents and the
register r contents is determined. The result is placed in the
Example ORL A, R5
7 0

0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1
7 0 7 0
0 1 1 1 0 1 0 1 0 1 1 1 0 1 0 1
7 0 7 0
339
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81. ORL A, data address (Logical OR memory to accumulator)
7 0
7 0
Operation : (A)←(A) OR (data address)
Number of bytes :2
Number of cycles :1
(PSW) •
Description : The logical OR between the accumulator contents and the
Example ORL A, 33H
7 0
7 0
0 0 1 1 0 0 1 1 Byte 2

0 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1
7 0 7 0
33H 33H
1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1
7 0 7 0
340
82. ORL C, bit address (Logical OR bit to carry flag)
7 0
7 0
Operation : (C)←(C) OR (bit address)
Number of bytes :2
Number of cycles :2
(PSW) •
Description : The logical OR between the carry flag and the specified bit
address content is determined. The result is placed in the carry
flag.
Example ORL C, ACC.6
7 0
7 0
1 1 1 0 0 1 1 0 Byte 2

0 1
0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 0
7 6 0 7 6 0
341
MSM80C154S/83C154S/85C154HVS
83. ORL C,/bit address (Logical OR complement of bit to carry flag)
7 0
7 0
Operation : (C)←(C) OR (bit address)
Number of bytes :2
Number of cycles :2
(PSW) •
Description : The logical OR between the carry flag and the complement of
specified bit address content is determined. The result is placed
in the carry flag.
Example ORL C,/25H.5
7 0
7 0
0 0 1 0 1 1 0 1 Byte 2

0 1
25H 25H
1 0 0 0 1 0 1 0 1 0 0 0 1 0 1 0
7 5 0 7 5 0
342
84. ORL data address, #data (Logical OR immediate data to memory)
7 0
7 0
7 0
Operation : (data address)←(data address) OR #data
Number of bytes :3
Number of cycles :2
(PSW)
Description : The logical OR between an 8-bit immediate data value and the
Example ORL 55H, #11H
7 0
7 0
0 1 0 1 0 1 0 1 Byte 2
7 0
0 0 0 1 0 0 0 1 Byte 3

55H 55H
1 0 0 0 0 1 0 0 1 0 0 1 0 1 0 1
7 0 7 0
343
MSM80C154S/83C154S/85C154HVS
85. ORL data address, A (Logical OR accumulator to memory)
7 0
7 0
Operation : (data address)←(data address) OR (A)
Number of bytes :2
Number of cycles :1
(PSW)
Description : The logical OR between the accumulator and the specified data
address contents is determined. The result is placed in the
Example ORL 50H, A
7 0
7 0
0 1 0 1 0 0 0 0 Byte 2

1 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1
7 0 7 0
50H 50H
0 0 1 0 0 1 0 1 1 0 1 0 1 1 1 1
7 0 7 0
344
86. POP data address (Pop stack to memory)
7 0
7 0
Operations : (data address)←((SP))
(SP)←(SP)–1
Number of bytes :2
Number of cycles :2
(PSW)
Description : Stack contents addressed by the stack pointer are popped in
the specified data address, and the stack pointer is
decremented by 1.
Example POP PSW:No change to parity bit.
7 0
7 0
1 1 0 1 0 0 0 0 Byte 2

1 0 1 0 1 1 0 0 1 0 1 0 1 1 0 0
7 0 7 0
PSW (0D0H) PSW (0D0H)
1 0 1 0 1 1 0 0 1 1 1 1 0 0 1 0
7 0 7 0
Stack pointer Stack pointer
0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1
7 0 7 0
10H 10H
1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1
7 0 7 0
345
MSM80C154S/83C154S/85C154HVS
87. PUSH data address (Push memory onto stack)
7 0
7 0
Operations : (SP)←(SP)+1
((SP))←(data address)
Number of bytes :2
Number of cycles :2
(PSW)
Description : The stack pointer is incremented by 1, and the specified data
address contents are pushed in the stack addressed by the
stack pointer.
Example PUSH P1
7 0
7 0
1 0 0 1 0 0 0 0 Byte 2

Port 1(90H) Port 1(90H)
1 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1
7 0 7 0
Stack pointer Stack pointer
0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1
7 0 7 0
11H (Stack) 11H (Stack)
0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1
7 0 7 0
346
88. RET (Return from subroutine, non interrupt)
7 0
Operations : (PC8~15)←((SP))
(SP)←(SP)–1
(PC0~7)←((SP))
(SP)←(SP)–1
Number of bytes :1
Number of cycles :2
(PSW)
Description : The stack contents addressed by the stack pointer are popped
in the upper order 8 thru 15 of the program counter, and the
stack pointer is decremented by 1. Then the stack contents
addressed by the updated stack pointer are popped in the lower
order 0 thru 7 of the program counter, again decrementing the
stack pointer by 1. The program counter is updated with the
stack contents, and control is shifted to the address after
updating.
347
MSM80C154S/83C154S/85C154HVS
89. RETI (Return from interrupt routine)
7 0
Operations : (PC8~15)←((SP))
(SP)←(SP)–1
(PC0~7)←((SP))
(SP)←(SP)–1
*INTERRUPT ENABLE
Number of bytes :1
Number of cycles :2
(PSW)
Description : This return instruction functions as an interrupt routine terminat-
ing instruction. If a priority interrupt is generated while a non
priority interrupt routine is being executed, the CPU commences
to process the priority interrupt. And once processing of this
interrupt is commenced, no other interrupts can be processed
until the RETI instruction is executed.
Stack contents addressed by the stack pointer are popped in

the upper order 8 thru 15 of the program counter, and the stack
pointer is decremented by 1. Then the stack contents address-
ed by the updated stack pointer are popped in the lower order 0
thru 7 of the program counter, again decrementing the stack
pointer by 1. The program counter is updated with the stack
contents, and control is shifted to the address after updating. If
a new interrupt is generated, the CPU commences to process
the interrupt.
348
90. RL A (Rotate accumulator left)
7 0
Operation : Accumulator
C ← ← ← ← ← ← ← ←
7 0
Number of bytes :1
Number of cycles :1
(PSW)
Description : All accumulator bits are shifted by one bit to the left. The MSB
(bit 7) is shifted to the LSB bit position (bit 0).
Example RL A
7 0

1 0 0 1 0 1 1 0 0 0 1 0 1 1 0 1
7 0 7 0
349
MSM80C154S/83C154S/85C154HVS
91. RLC A (Rotate accumulator and carry flag left)
7 0
Operation : Carry Accumulator
C ← ← ← ← ← ← ← ←
7 0
Number of bytes :1
Number of cycles :1
(PSW) • •
Description : The accumulator and the carry flag are connected, and all bits
are shifted by one bit to the left. The carry flag is shifted to the
accumulator LSB (bit 0), and the accumulator MSB (bit 7) is
shifted to the carry flag.
Example RLC A
7 0

0 1 1 0 1 0 1 1 1 1 0 1 0 1 1 1
7 0 7 0
1 0
350
92. RR A (Rotate accumulator right)
7 0
Operation : Accumulator
C ← ← ← ← ← ← ← ←
7 0
Number of bytes :1
Number of cycles :1
(PSW)
Description : All accumulator bits are shifted by one bit to the right. The LSB
(bit 0) is shifted to the MSB bit position (bit 7).
Example RR A
7 0

0 1 1 1 0 0 1 1 1 0 1 1 1 0 0 1
7 0 7 0
351
MSM80C154S/83C154S/85C154HVS
93. RRC A (Rotate accumulator and carry flag right)
7 0
Operation : Carry Accumulator
C ← ← ← ← ← ← ← ←
7 0
Number of bytes :1
Number of cycles :1
(PSW) • •
Description : The accumulator and the carry flag are connected, and all bits
are shifted by one bit to the right. The carry flag is shifted to the
accumulator MSB (bit 7), and the accumulator LSB (bit 0) is
shifted to the carry flag.
Example RRC A
7 0

0 0 1 1 0 1 0 0 1 0 0 1 1 0 1 0
7 0 7 0
1 0
352
94. SETB C (Set carry flag)
7 0
Operation : (C)←1
Number of bytes :1
Number of cycles :1
(PSW) •
Description : The carry flag is cleared to 1.
Example SETB C
7 0

0 1
353
MSM80C154S/83C154S/85C154HVS
95. SETB bit address (Set bit)
7 0
7 0
Operation : (bit address)←1
Number of bytes :2
Number of cycles :1
(PSW)
Description : The specified bit address content is set to 1.
Example SETB IE.7
7 0
7 0
1 0 1 0 1 1 1 1 Byte 2

IE (0A8H) IE (0A8H)
0 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1
7 0 7 0
354
96. SJMP code address (Short jump)
7 0
7 0
Number of bytes :2
Number of cycles :2
(PSW)
Description : Relative offset jump data is added/subtracted to/from the
program counter contents following an increment. The program
counter contents are updated, and control is then shifted to the
updated address. The range in which relative jumps can be
executed by this instruction is +127 to –128 in respect to the
incremented program counter contents. There is no page field
restrictions.
355
MSM80C154S/83C154S/85C154HVS
Example SJMP CHECK

LOC OBJ SOURCE
0111 8010 SJUMP:SJMP CHECK
0123 33 CHECK:RLC A
7 0
7 0
0 0 0 1 0 0 0 0 Byte 2

0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1
15 8 7 0 15 8 7 0
356
97. SUBB A, #data (Substract immediate data from accumulator with borrow)
7 0
7 0
Operation : (A)←(A)–((C)+#data)
Number of bytes :2
Number of cycles :1
(PSW) • • • •
Description : The carry flag content and an immediate data value are
substracted from the accumulator contents. The result is placed
in the accumulator, and the flags are updated.
Example SUBB A, #05H
7 0
7 0
0 0 0 0 0 1 0 1 Byte 2

1 0
Auxiliary carry flag Auxiliary carry flag

0 0

1 0
1 0 1 0 1 0 0 1 1 0 1 0 0 0 1 1
7 0 7 0
357
MSM80C154S/83C154S/85C154HVS
98. SUBB A, @Rr (Substract indirect address from accumulator with borrow)
7 0
Operation : (A)←(A)–((C)+((Rr))) r=0 or 1
Number of bytes :1
Number of cycles :1
(PSW) • • • •
Description : The carry flag content and the data memory location contents
addressed by the register r contents are substracted from the
accumulator contents. The result is placed in the accumulator,
and the flags are updated.
Example SUBB A, @R0
7 0

0 1

0 0

0 1
0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1
7 0 7 0
47H 47H
1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0
7 0 7 0
0 1 0 1 0 1 0 0 1 0 0 0 0 0 1 0
7 0 7 0
358
99. SUBB A, Rr (Substract register from accumulator with borrow)
7 0
Operation : (A)←(A)–((C)+(Rr))
Number of bytes :1
Number of cycles :1
(PSW) • • • •
Description : The carry flag content and the register r contents are
substracted from the accumulator contents. The result is placed
in the accumulator, and the flags are updated.
Example SUBB A, R7
7 0

1 0

0 1

0 1
0 1 0 1 1 0 0 0 0 1 0 1 1 0 0 0
7 0 7 0
1 0 0 0 0 1 0 0 0 0 1 0 1 0 1 1
7 0 7 0
359
MSM80C154S/83C154S/85C154HVS
100. SUBB A, data address (Substract memory from accumulator with borrow)
7 0
7 0
Operation : (A)←(A)–((C)+(data address))
Number of bytes :2
Number of cycles :1
(PSW) • • • •
Description : The carry flag contents and the specified data address contents
are substracted from the accumulator contents. The result is
placed in the accumulator, and the flags are updated.
Example SUBB A, DPH
7 0
7 0
1 0 0 0 0 0 1 1 Byte 2

0 1

0 1

0 0
DPH DPH
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
7 0 7 0
0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1
7 0 7 0
360
101. SWAP A (Exchange nibble in accumulator)
7 0
Operation : (A4~7)→
←(A0~3)
Number of bytes :1
Number of cycles :1
(PSW)
Description : The contents of the four higher order bits (4 thru 7) of the
accumulator are exchanged with the contents of the four lower
order bits (0 thru 3)
Example SWAP A
7 0

1 0 1 1 0 1 0 0 0 1 0 0 1 0 1 1
7 0 7 0
361
MSM80C154S/83C154S/85C154HVS
102. XCH A, @Rr (Exchange indirect address with accumulator)
7 0
Operation : (A)→
←((Rr)) r=0 or 1
Number of bytes :1
Number of cycles :1
(PSW) •
Description : The accumulator contents are exchanged with the data memory
location contents addressed by the register r, and the flag is
updated.
Example XCH A, @R0
7 0

1 0 0 1 1 1 0 0 0 1 1 1 0 1 1 0
7 0 7 0
0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1
7 0 7 0
4BH 4BH
0 1 1 1 0 1 1 0 1 0 0 1 1 1 0 0
7 0 7 0
362
103. XCH A, Rr (Exchange register with accumulator)
7 0
Operation : (A)→
←(Rr) r=0 thru 7
Number of bytes :1
Number of cycles :1
(PSW) •
Description : The accumulator contents are exchanged with the register r
contents, and the flag is updated.
Example XCH A, R5
7 0

0 1 1 1 0 0 1 0 1 0 1 0 0 0 0 1
7 0 7 0
1 0 1 0 0 0 0 1 0 1 1 1 0 0 1 0
7 0 7 0
363
MSM80C154S/83C154S/85C154HVS
104. XCH A, data address (Exchange memory with accumulator)
7 0
7 0
Operation : (A)→
←(data address)
Number of bytes :2
Number of cycles :1
(PSW) •
Description : The accumulator contents are exchanged with the specified
data address contents, and the flag is updated.
Example XCH A, 7AH
7 0
7 0
0 1 1 1 1 0 1 0 Byte 2

1 0 1 1 1 1 0 1 1 1 0 1 1 1 0 0
7 0 7 0
7AH 7AH
1 1 0 1 1 1 0 0 1 0 1 1 1 1 0 1
7 0 7 0
364
105. XCHD A, @Rr (Exchange low nibbles of indirect address with accumulator)
7 0
Operation : (A0~3)→
←((Rr0~3)) r=0 or 1
Number of bytes :1
Number of cycles :1
(PSW) •
Description : The lower order bits (0 thru 3) of the accumulator contents are
exchanged with contents of the lower order bits (0 thru 3) of the
data memory location addressed by the register r contents. The
flag is updated.
Example XCHD A, @R0
7 0

1 1 1 1 0 1 1 0 1 1 1 1 1 1 0 1
7 0 7 0
0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0
7 0 7 0
60H 60H
0 0 0 0 1 1 0 1 0 0 0 0 0 1 1 0
7 0 7 0
365
MSM80C154S/83C154S/85C154HVS
106. XRL A, #data (Logical exclusive OR immediate data to accumulator)
7 0
7 0
Operation : (A)←(A) XOR #data
Number of bytes :2
Number of cycles :1
(PSW) •
Description : The exclusive OR operation is executed between an immediate
data value and the accumulator contents. The result is placed in
the accumulator, and the flag is updated.
Example XRL A, #15H
7 0
7 0
0 0 0 1 0 1 0 1 Byte 2

0 1 0 0 1 0 1 0 0 1 0 1 1 1 1 1
7 0 7 0
366
107. XRL A, @Rr (Logical exclusive OR indirect address to accumulator)
7 0
Operation : (A)←(A) XOR ((Rr)) r=0 or 1
Number of bytes :1
Number of cycles :1
(PSW) •
Description : The exclusive OR operation is executed between the
accumulator contents and the data memory location contents
addressed by the register r contents. The result is placed in the
accumulator, and the flag is updated.
Example XRL A, @R1
7 0

0 1 0 0 1 0 0 1 1 1 0 1 1 0 0 0
7 0 7 0
0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0
7 0 7 0
36H 36H
1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 1
7 0 7 0
367
MSM80C154S/83C154S/85C154HVS
108. XRL A, Rr (Logical exclusive OR register to accumulator)
7 0
Operation : (A)←(A) XOR (Rr) r=0 thru 7
Number of bytes :1
Number of cycles :1
(PSW) •
Description : The exclusive OR between the accumulator contents and the
register r contents is determined. The result is stored in the
Example XRL A, R3
7 0

1 0 1 0 0 0 1 0 1 0 0 0 0 1 1 1
7 0 7 0
0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 1
7 0 7 0
368
109. XRL A, data address (Logical exclusive OR memory to accumulator)
7 0
7 0
Operation : (A)←(A) XOR (data address)
Number of bytes :2
Number of cycles :1
(PSW) •
Description : The exclusive OR between the accumulator contents and the
Example XRL A, 70H
7 0
7 0
0 1 1 1 0 0 0 0 Byte 2

1 1 1 1 0 1 1 0 1 1 0 1 1 0 0 1
7 0 7 0
70H 70H
0 0 1 0 1 1 1 1 0 0 1 0 1 1 1 1
7 0 7 0
369
MSM80C154S/83C154S/85C154HVS
110. XRL data address, #data (Logical exclusive OR immediate data to memory)
7 0
7 0
7 0
Operation : (data address)←(data address) XOR #data
Number of bytes :3
Number of cycles :2
(PSW)
Description : The exclusive OR between an immediate data value and the
Example XRL ACC, #5AH
7 0
7 0
1 1 1 0 0 0 0 0 Byte 2
7 0
0 1 0 1 1 0 1 0 Byte 3

1 1 1 1 1 0 1 0 1 0 1 0 0 0 0 0
7 0 7 0
370
111. XRL data address, A (Logical exclusive OR accumulator to memory)
7 0
7 0
Operation : (data address)←(data address) XOR (A)
Number of bytes :2
Number of cycles :1
(PSW) •
Description : The exclusive OR between the accumulator and the specified
data address contents is determined. The result is placed in the
Example XRL 20H, A
7 0
7 0
0 0 1 0 0 0 0 0 Byte 2

0 1 1 1 0 1 0 1 0 1 1 1 0 1 0 1
7 0 7 0
20H 20H
1 1 0 1 0 0 1 1 1 0 1 0 0 1 1 0
7 0 7 0
371
8051 Cross Assembler User's Manual
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Chapter 1
8051 Overview
1.1 Introduction
The 8051 series of microcontrollers are highly integrated single chip microcomputers with
an 8-bit CPU, memory, interrupt controller, timers, serial I/O and digital I/O on a single
piece of silicon. The current members of the 8051 family of components include:
80C152JA/JB/JC/JD, 83C152JA/JC, 80C157

80C154, 83C154, 85C154
8044, 8344, 8744
80C451, 83C451, 87C451
80C452, 83C452, 87C452
8051, 8031, 8751, 80C51, 80C31, 87C51
80512, 80532
80515, 80535, 80C535, 80C515
80C517, 80C537
80C51FA, 83C51FA, 87C51FA, 83C51FB, 87C51FB, 83C51FC, 87C51FC
8052, 8032, 8752
80C321, 80C521, 87C521, 80C541, 87C541
8053, 9761, 8753
80C552, 83C552, 87C552
80C652, 83C652, 87C652
83C654, 87C654
83C751, 87C751
83C752, 87C752
80C851, 83C851
4 Chap. 1: 8051 Overview
All members of the 8051 series of microcontrollers share a common architecture. They all
have the same instruction set, addressing modes, addressing range and memory spaces. The
primary dierences between dierent 8051 based products are the amount of memory on
chip, the amount and types of I/O and peripheral functions, and the component's technology
(see Table 1.1).
In the brief summary of the 8051 architecture that follows, the term 8051 is used to mean
collectively all available members of the 8051 family. Please refer to reference (1) for a
complete description of the 8051 architecture and the specications for all the currently
available 8051 based products.
1.2 8051 Architecture

The 8051 is an 8-bit machine. Its memory is organized in bytes and practically all its
instruction deal with byte quantities. It uses an Accumulator as the primary register for
instruction results. Other operands can be accessed using one of the four dierent addressing
modes available: register implicit, direct, indirect or immediate. Operands reside in one of
the ve memory spaces of the 8051.
The ve memory spaces of the 8051 are: Program Memory, External Data Memory, Internal
Data Memory, Special Function Registers and Bit Memory.
The Program Memory space contains all the instructions, immediate data and constant
tables and strings. It is principally addressed by the 16-bit Program Counter (PC), but
it can also be accessed by a few instructions using the 16-bit Data Pointer (DPTR). The
maximum size of the Program Memory space is 64K bytes. Several 8051 family members
integrate on-chip some amount of either masked programmed ROM or EPROM as part of
this memory space (refer to Table 1.1).
The External Data Memory space contains all the variables, buers and data structures that
can't t on-chip. It is principally addressed by the 16-bit Data Pointer (DPTR), although
the rst two general purpose register (R0,R1) of the currently selected register bank can
access a 256-byte bank of External Data Memory. The maximum size of the External Data
Memory space is 64Kbytes. External data memory can only be accessed using the indirect
addressing mode with the DPTR, R0 or R1.
The Internal Data Memory space is functionally the most important data memory space.
In it resides up to four banks of general purpose registers, the program stack, 128 bits of the
256-bit memory, and all the variables and data structures that are operated on directly by
the program. The maximum size of the Internal Data Memory space is 256-bytes. However,
dierent 8051 family members integrate dierent amounts of this memory space on chip (see
Amnt of RAM in Table 1.1). The register implicit, indirect and direct addressing modes
can be used in dierent parts of the Internal Data Memory space.
The Special Function Register space contains all the on-chip peripheral I/O registers as well
as particular registers that need program access. These registers include the Stack Pointer,
the PSW and the Accumulator. The maximum number of Special Function Registers (SFRs)
is 128, though the actual number on a particular 8051 family member depends on the
number and type of peripheral functions integrated on-chip (see Table 1.1). The SFRs all
have addresses greater than 127 and overlap the address space of the upper 128 bytes of
the Internal Data Memory space. The two memory spaces are dierentiated by addressing
Chap. 1: 8051 Overview 5
mode. The SFRs can only be accessed using the Direct addressing mode while the upper
128 bytes of the Internal Data Memory (if integrated on-chip) can only be accessed using
the Indirect addressing mode.
The Bit Memory space is used for storing bit variables and ags. There are specic instruc-
tions in the 8051 that operate only in the Bit Memory space. The maximum size of the
Bit Memory space is 256-bits. 128 of the bits overlap with 16-bytes of the Internal Data
Memory space and 128 of the bits overlap with 16 Special Function Registers. Bits can only
be accessed using the bit instructions and the Direct addressing mode.
The 8051 has a fairly complete set of arithmetic and logical instructions. It includes an 8X8
multiply and an 8/8 divide. The 8051 is particularly good at processing bits (sometimes
called Boolean Processing). Using the Carry Flag in the PSW as a single bit accumulator,
the 8051 can move and do logical operations between the Bit Memory space and the Carry
Flag. Bits in the Bit Memory space can also be used as general purpose ags for the test
bit and jump instructions.
Except for the MOVE instruction, the 8051 instructions can only operate on either the
Internal Data Memory space or the Special Function Registers. The MOVE instruction
operates in all memory spaces, including the External Memory space and Program Memory
space.
Program control instructions include the usual unconditional calls and jumps as well as
conditional relative jumps based on the Carry Flag, the Accumulator's zero state, and the
state of any bit in the Bit Memory space. Also available is a Compare and Jump if Not
Equal instruction and a Decrement Counter and Jump if Not Zero loop instruction. See
Chapter 4 for a description of the complete 8051 instruction set.
1.3 Summary of the 8051 Family of Components
1.4 References
1. Intel Corp., 8-Bit Embedded Controllers, 1990.
2. Siemens Corp., Microcontroller Component 80515, 1985.
3. AMD Corp., Eight-Bit 80C51 Embedded Processors, 1990.
4. Signetics Corp., Microcontroller Users' Guide, 1989.
6 Chap. 1: 8051 Overview
Component Tech. ROM ROM RAM # of Serial I/O Type

(Kbytes) Type (bytes) SFRs Serial I/O Type
8031 HMOS 0 { 128 21 Start/Stop Async
8051 HMOS 4 Masked 128 21 Start/Stop Async
8751 HMOS 4 EPROM 128 21 Start/Stop Async
80C31 CMOS 0 { 128 21 Start/Stop Async
80C51 CMOS 4 Masked 128 21 Start/Stop Async
87C51 CMOS 4 EPROM 128 21 Start/Stop Async
8044 HMOS 4 Masked 192 34 HDLC/SDLC
8344 HMOS 0 { 192 34 HDLC/SDLC
8744 HMOS 4 EPROM 192 34 HDLC/SDLC
80C535 CHMOS 0 { 256 41 Start/Stop Async
80C515 CHMOS 8 Masked 256 41 Start/Stop Async
80C152 CHMOS 0 { 256 56 CSMA/CD
83C152 CHMOS 8 Masked 256 56 CSMA/CD
80C51FA CHMOS 0 { 256 47 Start/Stop Async
83C51FA CHMOS 8 Masked 256 47 Start/Stop Async
87C51FA CHMOS 8 EPROM 256 47 Start/Stop Async
83C51FB CHMOS 16 Masked 256 47 Start/Stop Async
87C51FB CHMOS 16 EPROM 256 47 Start/Stop Async
83C51FB CHMOS 32 Masked 256 47 Start/Stop Async
87C51FB CHMOS 32 EPROM 256 47 Start/Stop Async
80C537 CHMOS 0 { 256 41 Start/Stop Async
80C517 CHMOS 8 Masked 256 82 Start/Stop Async
80C451 CMOS 0 { 128 24 Parallel I/F
83C451 CMOS 4 Masked 128 24 Parallel I/F
87C451 CMOS 4 EPROM 128 24 Parallel I/F
80C452 CHMOS 0 { 256 55 U.P.I.
83C452 CHMOS 8 { 256 55 U.P.I.
87C452 CHMOS 8 { 256 55 U.P.I.
83C752 CMOS 2 Masked 64 25 I2C
87C752 CMOS 2 EPROM 64 25 I2C
83C751 CMOS 2 Masked 64 20 I2C
87C751 CMOS 2 EPROM 64 20 I2C
Table 1.1: 8051 variants.

Chapter 2
8051 CROSS ASSEMBLER OVERVIEW
2.1 Introduction
The 8051 Cross Assembler takes an assembly language source le created with a text editor
and translates it into a machine language object le. This translation process is done in
two passes over the source le. During the rst pass, the Cross Assembler builds a symbol
table from the symbols and labels used in the source le. It's during the second pass that
the Cross Assembler actually translates the source le into the machine language object
le. It is also during the second pass that the listing is generated.
The following is a discussion of the syntax required by the Cross Assembler to generate
error free assemblies.
2.2 Symbols
Symbols are alphanumeric representations of numeric constants, addresses, macros, etc. The
legal character set for symbols is the set of letters, both upper and lower case (A..Z,a..z), the
set of decimal numbers (0..9) and the special characters, question mark (?) and underscore
( ). To ensure that the Cross Assembler can distinguish between a symbol and a number,
all symbols must start with either a letter or special character (? or ). The following are
examples of legal symbols:
PI
Serial_Port_Buffer
LOC_4096
?_?_?
In using a symbol, the Cross Assembler converts all letters to upper case. As a result, the
Cross Assembler makes no distinction between upper and lower case letters. For example,
the following two symbols would be seen as the same symbol by the Cross Assembler:
Serial_Port_Buffer
SERIAL_PORT_BUFFER
Symbols can be dened only once. Symbols can be up to 255 characters in length, though
only the rst 32 are signicant. Therefore, for symbols to be unique, they must have a
unique character pattern within the rst 32 characters. In the following example, the rst
two symbols would be seen by the Cross Assembler as duplicate symbols, while the third
and fourth symbols are unique.
BEGINNING_ADDRESS_OF_CONSTANT_TABLE_1
8 Chap. 2: 8051 CROSS ASSEMBLER OVERVIEW
BEGINNING_ADDRESS_OF_CONSTANT_TABLE_2
CONSTANT_TABLE_1_BEGINNING_ADDRESS
CONSTANT_TABLE_2_BEGINNING_ADDRESS
There are certain symbols that are reserved and can't be dened by the user. These reserved
symbols are listed in Appendix C and include the assembler directives, the 8051 instruction
mnemonics, implicit operand symbols, and the following assembly time operators that have
alphanumeric symbols: EQ, NE, GT, GE, LT, LE, HIGH, LOW, MOD, SHR, SHL, NOT,
AND, OR and XOR.
The reserved implicit operands include the symbols A, AB, C, DPTR, PC, R0, R1, R2, R3,
R4, R5, R6, R7, AR0, AR1, AR2, AR3, AR4, AR5, AR6 and AR7. These symbols are used
primarily as instruction operands. Except for AB, C, DPTR or PC, these symbols can also
be used to dene other symbols (see EQU directive in Chapter 5).
The following are examples of illegal symbols with an explanation of why they are illegal:
1ST_VARIABLE (Symbols can not start with a number.)
ALPHA# (Illegal character "#" in symbol.)
MOV (8051 instruction mnemonic)
LOW (Assembly operator)
DATA (Assembly directive)
2.3 Labels
Labels are special cases of symbols. Labels are used only before statements that have phys-
ical addresses associated with them. Examples of such statements are assembly language
instructions, data storage directives (DB and DW), and data reservation directives (DS and
DBIT). Labels must follow all the rules of symbol creation with the additional requirement
that they be followed by a colon. The following are legal examples of label uses:
TABLE_OF_CONTROL_CONSTANTS:
DB 0,1,2,3,4,5 (Data storage)
MESSAGE: DB 'HELP' (Data storage)
VARIABLES: DS 10 (Data reservation)
BIT_VARIABLES: DBIT 16 (Data reservation)
START: MOV A,#23 (Assembly language instruction)
2.4 Assembler Controls

Assembler controls are used to control where the Cross Assembler gets its input source le,
where it puts the object le, and how it formats the listing le. Table 2.1 summarizes the
assembler controls available. Refer to Chapter 6 for a detailed explanation of the controls.
As can be seen in Table 2.1, all assembler controls are prefaced with a dollar sign ($). No
spaces or tabs are allowed between the dollar sign and the body of the control. Also, only
one control per line is permitted. However, comments can be on the same line as a control.
The following are examples of assembler controls:
$TITLE(8051 Program Ver. 1.0)
$LIST
$PAGEWIDTH(132)
Chap. 2: 8051 CROSS ASSEMBLER OVERVIEW 9
$DATE(date) Places date in page header

$EJECT Places a form feed in listing
$INCLUDE(le) Inserts le in source program
$LIST Allows listing to be output
$NOLIST Stops outputting the listing
$MOD51 Uses 8051 predened symbols
$NOMOD No predened symbols used
$OBJECT(le) Places object output in le
$NOOBJECT No object le is generated
$PAGING Break output listing into pages
$NOPAGING Print listing w/o page breaks
$PAGELENGTH(n) No. of lines on a listing page
$PAGEWIDTH(n) No. of columns on a listing page
$PRINT(le) Places listing output in le
$NOPRINT Listing will not be output
$SYMBOLS Append symbol table to listing
$NOSYMBOLS Symbol table will not be output
$TITLE(string) Places string in page header
Table 2.1: Cross Assembler controls.

EQU Dene symbol
DATA Dene internal memory symbol
IDATA Dene indirectly addressed internal memory symbol
XDATA Dene external memory symbol
BIT Dene internal bit memory symbol
CODE Dene program memory symbol
DS Reserve bytes of data memory
DBIT Reserve bits of bit memory
DB Store byte values in program memory
DW Store word values in program memory
ORG Set segment location counter
END End of assembly language source le
CSEG Select program memory space
DSEG Select internal memory data space
XSEG Select external memory data space
ISEG Select indirectly addressed internal
BSEG Select bit addressable memory space memory space
USING Select register bank
IF Begin conditional assembly block
ELSE Alternative conditional assembly block
ENDIF End conditional assembly block
Table 2.2: Cross Assembler directives.
2.5 Assembler Directives

Assembler directives are used to dene symbols, reserve memory space, store values in
program memory and switch between dierent memory spaces. There are also directives
that set the location counter for the active segment and identify the end of the source le.
Table 2.2 summarizes the assembler directives available. These directives are fully explained
in Chapter 5.
Only one directive per line is allowed, however comments may be included. The following
are examples of assembler directives:
TEN EQU 10
RESET CODE 0
ORG 4096
2.6 8051 Instruction Mnemonics

The standard 8051 Assembly Language Instruction mnemonics plus the generic CALL and
JMP instructions are recognized by the Cross Assembler and are summarized in Table 2.3.
See Chapter 4 for the operation of the individual instructions.
When the Cross Assembler sees a generic CALL or JMP instruction, it will try to translate
the instruction into its most byte ecient form. The Cross Assembler will translate a CALL
into one of two instructions (ACALL or LCALL) and it will translate a generic JMP into one
ACALL Absolute call ADD Add

ADDC Add with carry AJMP Absolute jump
ANL Logical and CJNE Compare & jump if not equal
CLR Clear CPL Complement
DA Decimal adjust DEC Decrement
DIV Divide DJNZ Decrement & jump if not zero
INC Increment JB Jump if bit set
JBC Jump & clear bit if bit set JC Jump if carry set
JMP Jump JNB Jump if bit not set
JNC Jump if carry not set JNZ Jump if accum. not zero
JZ Jump if accumulator zero LCALL Long call
LJMP Long jump MOV Move
MOVC Move code MOVX Move external
MUL Multiply NOP No operation
ORL Inclusive or POP Pop stack
PUSH Push stack RET Return
RETI Return from interrupt RL Rotate left
RLC Rotate left thru carry RR Rotate right
RRC Rotate right thru carry SETB Set bit
SJMP Short jump SUBB Subtract with borrow
SWAP Swap nibbles XCH Exchange bytes
XCHD Exchange digits XRL Exclusive or
CALL Generic call
Table 2.3: 8051 instruction set mnemonics.

of three instructions (SJMP, AJMP or LJMP). The choice of instructions is based on which
one is most byte ecient. The generic CALL or JMP instructions saves the programmer
the trouble of determining which form is best.
However, generic CALLs and JMPs do have their limitations. While the byte eciency
algorithm works well for previously dened locations, when the target location of the CALL
or JMP is a forward location (a location later on in the program), the assembler has no
way of determining the best form of the instruction. In this case the Cross Assembler
simply puts in the long version (LCALL or LJMP) of the instruction, which may not be
the most byte ecient. NOTE that the generic CALLs and JMPs must not be used for the
751/752 device as LCALL and LJMP are not legal instructions for those devices. Instead
use ACALL and AJMP explicitly.
For instructions that have operands, the operands must be separated from the mnemonic
by at least one space or tab. For instructions that have multiple operands, each operand
must be separated from the others by a comma.
Two addressing modes require the operands to be preceded by special symbols to designate
the addressing mode. The AT sign (@) is used to designate the indirect addressing mode. It
is used primarily with Register 0 and Register 1 (R0, R1), but is can also be used with the
DPTR in the MOVX and the Accumulator in MOVC and JMP @A+DPTR instructions.
The POUND sign (#) is used to designate an immediate operand. It can be used to preface
either a number or a symbol representing a number.
A third symbol used with the operands actually species an operation. The SLASH (/) is
used to specify that the contents of a particular bit address is to be complemented before
the instruction operation. This is used with the ANL and ORL bit instructions.
Only one assembly language instruction is allowed per line. Comments are allowed on the
same line as an instruction, but only after all operands have been specied. The following
are examples of instruction statements:
START: LJMP INIT
MOV @R0,Serial_Port_Buffer
CJNE R0 , #TEN, INC_TEN
ANL C,/START_FLAG
CALL GET_BYTE
RET
2.7 Bit Addressing

The period (.) has special meaning to the Cross Assembler when used in a symbol. It is
used to explicitly specify a bit in a bit-addressable symbol. For example, it you wanted to
specify the most signicant bit in the Accumulator, you could write ACC.7, where ACC
was previously dened as the Accumulator address. The same bit can also be selected using
the physical address of the byte it's in. For example, the Accumulator's physical address
is 224. The most signicant bit of the Accumulator can be selected by specifying 224.7. If
the symbol ON was dened to be equal to the value 7, you could also specify the same bit
by either ACC.ON or 224.ON.
2.8 ASCII Literals

Printable characters from the ASCII character set can be used directly as an immediate
operand, or they can used to dene symbols or store ASCII bytes in Program Memory.
Such use of the ASCII character set is called ASCII literals. ASCII literals are identied
by the apostrophe (') delimiter. The apostrophe itself can be used as an ASCII literal. In
this case, use two apostrophes in a row. Below are examples of using ASCII literals.
MOV A,#'m' ;Load A with 06DH (ASCII m)
QUOTE EQU '''' ;QUOTE defined as 27H (ASCII single quote)
DB '8051' ;Store in Program Memory
2.9 Comments
Comments are user dened character strings that are not processed by the Cross Assembler.
A comment begins with a semicolon ( ; ) and ends at the carriage return/line feed pair that
terminates the line. A comment can appear anywhere in a line, but it has to be the last
eld. The following are examples of comment lines:
; Begin initialization routine here
$TITLE(8051 Program Vers. 1.0) ;Place version number here
TEN EQU 10 ;Constant
; Comment can begin anywhere in a line
MOV A,Serial_Port_Buffer ; Get character
2.10 The Location Counter

The Cross Assembler keeps a location counter for each of the ve segments (code, internal
data, external data, indirect internal data and bit data). Each location counter is initialized
to zero and can be modied using Assembler Directives described in Chapter 5.
The dollar sign ($) can be used to specify the current value of the location counter of the
active segment. The following are examples of how this can be used:
JNB FLAG,$ ;Jump on self until flag is reset
CPYRGHT: DB 'Copyright, 1983'
CPYRGHT_LENGTH
EQU $-CPYRGHT-1 ;Calculate length of copyright message
2.11 Syntax Summary

Since the Cross Assembler essentially translates the source le on a line by line basis, certain
rules must be followed to ensure the translation process is done correctly. First of all, since
the Cross Assembler's line buer is 256 characters deep, there must always be a carriage
return/line feed pair within the rst 256 columns of the line.
A legal source le line must begin with either a control, a symbol, a label, an instruction
mnemonic, a directive, a comment or it can be null (just the carriage return/line feed pair).
Any other beginning to a line will be agged as an error.
Radix Designator Legal Digits Maximum Legal Number

Binary B 0,1 1111111111111111B
Octal O,Q 0,1,2,3,4,5, 177777O
6,7 177777Q
Decimal D,(default) 0,1,2,3,4,5, 65535D
6,7,8,9 65535
Hexadecimal H 0,1,2,3,4,5, 0FFFFH
6,7,8,9,A,B,
C,D,E,F
Table 2.4: Cross Assembler number representations.
While a legal source le line must begin with one of the above items, the item doesn't have
to begin in the rst column of the line. It only must be the rst eld of the line. Any
number (including zero) of spaces or tabs, up to the maximum line size, may precede it.
Comments can be placed anywhere, but they must be the last eld in any line.
2.12 Numbers and Operators

The Cross Assembler accepts numbers in any one of four radices: binary, octal, decimal and
hexadecimal. To specify a number in a specic radix, the number must use the correct digits
for the particular radix and immediately following the number with its radix designator.
Decimal is the default radix and the use of its designator is optional. An hexadecimal
number that would begin with a letter digit must be preceded by a 0 (zero) to distinguish it
from a symbol. The internal representation of numbers is 16-bits, which limits the maximum
number possible. Table 2.4 summarizes the radices available.
No spaces or tabs are allowed between the number and the radix designator. The letter
digits and radix designators can be in upper or lower case. The following examples list the
decimal number 2957 in each of the available radices:
101110001101B (Binary)
5615o or 5615Q (Octal)
2957 or 2957D (Decimal)
0B8DH, 0b8dh (Hexadecimal)
When using radices with explicit bit symbols, the radix designator follows the byte portion
of the address as shown in the following examples:
0E0H.7 Bit seven of hexadecimal address 0E0
200Q.ON Bit ON of octal address 200
The Cross Assembler also allows assembly time evaluation of arithmetic expressions up to
thirty-two levels of embedded parentheses. All calculations use integer numbers and are
done in sixteen bit precision.
The relational operators test the specied values and return either a True or False. False
is represented by a zero value, True is represented by a non zero value (the True condition
OPERATOR SYMBOL OPERATION

+ Addition
Unary positive
- Subtraction
Unary negation (2's complement)
Multiplication
/ Integer division (no remainder)
MOD Modulus (remainder of integer division)
SHR Shift right
SHL Shift left
NOT Logical negation (1's complement)
AND Logical and
OR Inclusive or
XOR Exclusive or
LOW Low order 8-bits
HIGH High order 8-bits
EQ, = Relational equal
NE, <> Relational not equal
GT, > Relational greater than
GE, >= Relational greater than or equal
LT, < Relational less than
LE, <= Relational less than or equal
() Parenthetical statement
Table 2.5: Cross Assembler arithmetic and relational operations.
actually returns a 16-bit value with every bit set; i.e., 0FFFFH). The relational operators
are used primarily with the Conditional Assembly capability of the Cross Assembler.
Table 2.5 lists the operations available while Table 2.6 lists the operations precedence in
descending order. Operations with higher precedence are done rst. Operations with equal
precedence are evaluated from left to right.
OPERATION PRECEDENCE
(,) HIGHEST
HIGH,LOW
,/,MOD,SHR,SHL
+,-
EQ,LT,GT,LE,GE,NE,=,<,>,<=,>=,<>
NOT
AND
OR,XOR LOWEST
Table 2.6: Cross Assembler operator precedence.

The following are examples of all the available operations and their result:
HIGH(0AADDH) will return a result of 0AAH
LOW(0AADDH) will return a result of 0DDH
7*4 will return a result of 28
7/4 will return a result of 1
7 MOD 4 will return a result of 3
1000B SHR 2 will return a result of 0010B
1010B SHL 2 will return a result of 101000B
10+5 will return a result of 15
+72 will return a result of 72
25-17 will return a result of 8
-1 will return a result of 1111111111111111B
NOT 1 will return a result of 1111111111111110B
7 EQ 4, 7 = 4 will return a result of 0
7 LT 4, 7 < 4 will return a result of 0
7 GT 4, 7 > 4 will return a result of 0FFFFH
7 LE 4, 7 <= 4 will return a result of 0
7 GE 4, 7 >= 4 will return a result of 0FFFFH
7 NE 4, 7 <> 4 will return a result of 0FFFFH
1101B AND 0101B will return a result of 0101B
1101B OR 0101B will return a result of 1101B
1101B XOR 0101B will return a result of 1000B
2.13 Source File Listing

The source le listing displays the results of the Cross Assembler translation. Every line of
the listing includes a copy of the original source line as well as a line number and the Cross
Assembler translation.
For example, in translating the following line taken from the middle of a source le:
TRANS: MOV R7,#32 ;Set up pointer
the listing will print:

002F 7920 152 TRANS: MOV R1,#32 ;Set up pointer
The '002F' is the current value of the location counter in hexadecimal. The '7920' is the
translated instruction, also in hexadecimal. The '152' is the decimal line number of the
current assembly. After the line number is a copy of the source le line that was translated.
Another example of a line in the listing le is as follows:
015B 13 =1 267 +2 RRC A
Here we see two additional elds. The '=1' before the line number gives the current nesting
of include les. The '+2' after the line number gives the current macro nesting. This line
essentially says that this line comes from a second level nesting of a macro that is part of
an include le.
Another line format that is used in the listing is that of symbol denition. In this case the
location counter value and translated instruction elds described above are replaced with
the denition of the symbol. The following are examples of this:
00FF 67 MAX_NUM EQU 255

REG 68 COUNTER EQU R7
The '00FF' is the hexadecimal value of the symbol MAX NUM. Again, '67'is the decimal
line number of the source le and the remainder of the rst line is a copy of the source le.
In the second line above, the 'REG' shows that the symbol COUNTER was dened to be
a general purpose register.
Optionally, a listing can have a page header that includes the name of the le being assem-
bled, title of program, date and page number. The header and its elds are controlled by
specic Assembler Controls (see Chapter 6).
The default case is for a listing to be output as a le on the default drive with the same name
as the entered source le and an extension of .LST. For example, if the source le name
was PROGRAM.ASM, the listing le would be called PROGRAM.LST. Or if the source
le was called MODULE1, the listing le would be stored as MODULE1.LST. The default
can be changed using the $NOPRINT and $PRINT() Assembler Controls (see Chapter 6).
2.14 Object File

The 8051 Cross Assembler also creates a machine language object le. The format of the
object le is standard Intel Hexadecimal. This Hexadeciaml le can be used to either
program EPROMs using standard PROM Programmers for prototyping, or used to pattern
masked ROMs for production.
The default case is for the object le to be output on the default drive with the same name
as the rst source le and an extension of .HEX. For example, if the source le name was
PROGRAM.ASM, the object le would be called PROGRAM.HEX. Or if the source le
was called MODULE1, the object le would be stored as MODULE1.HEX. The default can
be changed using the $NOOBJECT and $OBJECT() Assembler Controls (see Chapter 6).
Chapter 3
RUNNING THE 8051 CROSS ASSEMBLER ON PC-DOS/MS-DOS
SYSTEMS
3.1 Cross Assembler Files

The oppy disk you receive with this manual is an 8 sector, single-sided, double density
disk. This distribution disk will contain the following les:
ASM51.EXE The Cross Assembler program itself
MOD152 Source le for the $MOD152 control
There will also be one or more les with an extension of .ASM. These are sample programs.
Listings of these programs can be found in Appendix A.
DON'T USE THE DISTRIBUTION DISK. MAKE WORKING AND BACKUP COPIES
FROM THE DISTRIBUTION DISK AND THEN STORE THE DISTRIBUTION DISK
IN A SAFE PLACE.
3.2 Minimum System Requirements

With DOS 2.0 or later - 96K RAM 1 Floppy Disk Drive
20 Chap. 3: RUNNING THE 8051 CROSS ASSEMBLER ON PC-DOS/MS-DOS SYSTEMS
3.3 Running the Cross Assembler

Once you've created an 8051 assembly language source text le in accordance with the
guidelines in Chapter 2, you are now ready to run the Cross Assembler. Make sure your
system is booted and the DOS prompt ( A> ) appears on the screen. Place the disk with
the 8051 Cross Assembler on it in the drive and simply type (in all the following examples,
the symbol <CR> is used to show where the ENTER key was hit):
ASM51<CR>
If the 8051 Cross Assembler disk was placed in a drive other than the default drive, the
drive name would have to be typed rst. For example, if the A drive is the default drive,
and the 8051 Cross Assembler is in the B drive, you would then type:
B:ASM51<CR>
After loading the program from the disk, the program's name, its version number and
general copyright information will be displayed on the screen. The Cross Assembler then
asks for the source le name to begin the assembly process.
Source file drive and name [.ASM]:
At this point, if you have only one oppy disk drive and the 8051 Cross Assembler and
source les are on separate disks, remove the disk with the 8051 Cross Assembler on it and
replace it with your source le disk.
Next, enter the source le name. If no extension is given, the Cross Assembler will assume
an extension of .ASM. If no drive is given, the Cross Assembler will assume the default
drive. Since in every case where no drive is given, the Cross Assembler assumes the default
drive, it is generally a good practice to change the default drive to the drive with your
source les.
An alternative method for entering the source le is in the command line. In this case, after
typing in ASM51, type in a space and the source le name (again if no extension is given,
source le on the command line:
A>ASM51 B:CONTROL.A51<CR>
After the source le name has been accepted, the Cross Assembler will begin the translation
process. As it starts the rst pass of its two pass process, it will print on the screen:
First pass
At the completion of the rst pass, and as it starts its second pass through the source le,
the Cross Assembler will display:
Second pass
When second pass is completed, the translation process is done and the Cross Assembler
will print the following message:
ASSEMBLY COMPLETE, XX ERRORS FOUND
XX is replaced with the actual number of errors that were found. Disk I/O may continue
for a while as the Cross Assembler appends the symbol table to the listing le.
Chap. 3: RUNNING THE 8051 CROSS ASSEMBLER ON PC-DOS/MS-DOS SYSTEMS 21
3.4 Example Running the Cross Assembler

The following is an example of an actual run. The Cross Assembler will take the source le
SAMPLE.ASM from Drive A (default drive).
Again, the symbol <CR> is used to show where the ENTER key was hit.
A>ASM51<CR>
8 0 5 1 C R O S S A S S E M B L E R
Version 1.2
(c) Copyright 1984, 1985, 1986, 1987, 1988, 1989, 1990
Source file drive and name [.ASM]: sample<CR>
First pass
Second pass
ASSEMBLY COMPLETE, 0 ERRORS FOUND
3.5 DOS Hints and Suggestions

If you are using DOS 2.0 or later, you may want to use the BREAK ON command before you
run the Cross Assembler. This will allow you to abort (Ctrl-Break) the Cross Assembler at
any time. Otherwise, you will only be able to abort the Cross Assembler after it completes
a pass through the source le. If you are assembling a large le, this could cause you a
several minute wait before the Cross Assembler aborts.
The reason for this it that the default condition for DOS to recognizes a Ctrl-Break is
when the program (in this case the Cross Assembler) does keyboard, screen or printer I/O.
Unfortunately, the assembler does this very rarely (once each pass). By using the BREAK
ON command, DOS will recognize a Ctrl- Break for all I/O, including disk I/O. Since the
Cross Assembler is constantly doing disk I/O, with BREAK ON you can abort almost
immediately by hitting the Ctrl-Break keys.
So much for the good news. However, aborting a program can cause some undesirable
side-eects. Aborting a program while les are open causes DOS to drop some information
about the open les. This results in disk sectors being allocated when they are actually
free. Your total available disk storage shrinks. You should make the practice of running
CHKDSK with the /F switch periodically to recover these sectors.
The Cross Assembler run under DOS 2.0 or later supports redirection. You can specify the
redirection on the command line. Use the following form:
22 Chap. 3: RUNNING THE 8051 CROSS ASSEMBLER ON PC-DOS/MS-DOS SYSTEMS
ASM51 <infile >outfile
"inle" and "outle" can be any legal le designator. The Cross Assembler will take its
input from the "inle" instead of the keyboard and will send its output to "outle" instead
of the screen.
Note that redirection of input in ASM51 is redundant since the assembler is an absolute
assembler and has no command line options other than the le name argument.
Output redirection is useful for speeding up the assembly process. Because assembly-time
errors are directed to std err in DOS, an error listing cannot be redirected to a le
To make the .lst le serve as an error-only le, use the Cross Assembler Controls $PRINT
(create a list le) $NOLIST (turn the listing o). Use the Cross Assembler Controls
$NOSYMBOLS to further compress the error-only listing resulting from the manipula-
tion of the list le controls. See Chapter 6 for more information. The errors will be listed
in the .lst le, as usual.
If the control $NOPRINT (see Chapter 6) is active, all error messages are send to the screen.
3.6 References
1. IBM Corp., Disk Operating System, Version 1.10, May 1982.
2. IBM Corp., Disk Operating System, Version 2.00, January 1983.
Chapter 4
8051 INSTRUCTION SET
4.1 Notation
Below is an explanation of the column headings and column contents of the 8051 Instruction
Set Summary Table Table 4.1 that follows in this chapter.
MNEMONIC: The MNEMONIC column contains the 8051 Instruction Set Mnemonic
and a brief description of the instruction's operation.
OPERATION: The OPERATION column describes the 8051 Instruction Set in unam-
biguous symbology. Following are the denitions of the symbols used in this column.
24 Chap. 4: 8051 INSTRUCTION SET
<n:m> Bits of a register inclusive. For example, PC<10:0>

means bits 0 through 10 inclusive of the PC. Bit 0 is
always the least signicant bit.
+ Binary addition
- Binary 2s complement subtraction
/ Unsigned integer division
X Unsigned integer multiplication
Binary complement (1s complement)
^ Logical And
v Inclusive Or
v Exclusive Or
> Greater than
<> Not equal to
= Equals
( Is written into. For example, A + SOper -> A means
the result of the binary addition between A and the
Source Operand is written into A.
A The 8-bit Accumulator Register
AC The Auxiliary Carry Flag in the Program Status Word
CF The Carry Flag in the Program Status Word
DOper The Destination Operand used in the instruction
DPTR 16-bit Data Pointer
Intrupt Active Flag Internal Flag that holds o interrupts until the Flag is
cleared
Jump Relative to PC A Jump that can range between -128 bytes and +127
bytes from the PC value of the next instruction
Paddr A 16-bit Program Memory address
PC The 8051 Program Counter. This 16-bit register points
to the byte in the Program Memory space that is
fetched as part of the instruction stream.
PM(addr) Byte in Program Memory space pointed to by addr
Remainder Integer remainder of unsigned integer division
SOper The Source Operand used in the instruction
SP 8-bit Stack Pointer
STACK The Last In First Out data structure that is controlled
by the 8-bit Stack Pointer (SP). Sixteen bit quantities
are pushed on the stack low byte rst.
DEST ADDR MODE/SRC ADDR MODE: These two columns specify the Destina-
tion and Source Addressing Modes, respectively, that are available for each instruction.
Chap. 4: 8051 INSTRUCTION SET 25
AB The Accumulator-B Register pair.

Accumulator Operand resides in the accumulator.
Bit Direct Operand is the state of the bit specied by the Bit
Memory address.
Carry Flag Operand is the state of the 1-bit Carry ag in the Pro-
gram Status Word (PSW).
Data Pointer Operand resides in the 16-bit Data Pointer Register.
Direct Operand is the contents of the specied 8-bit Internal
Data Memory address from 0 (00H) to 127 (7FH) or a
Special Function Register address.
Indirect Operand is the contents of the address contained in the
register specied.
Immediate Operand is the next sequential byte after the instruc-
tion in Program Memory space.
Prog Direct 16-bit address in Program Memory Space.
Prog Indir Operand in Program Memory Space is the address con-
tained in the register specied.
Register Operand is the contents of the register specied.
Stack Operand is on the top of the Stack.
ASSEMBLY LANGUAGE FORM: This column contains the correct format of the
instructions that are recognized by the Cross Assembler.
A Accumulator.
AB Accumulator-B Register pair.
C Carry Flag.
Baddr Bit Memory Direct Address.
Daddr Internal Data Memory or Special Function Register Di-
rect Address.
data 8-bit constant data.
data16 16-bit constant data.
DPTR 16-bit Data Pointer Register.
PC 16-bit Program Counter.
Paddr 16-bit Program Memory address.
Ri Indirect Register. R0 or R1 are the only indirect
registers.
Ro 8-bit oset for Relative Jump.
Rn Implicit Register. Each register bank has 8 general
purpose registers, designated R0, R1, R2, R3, R4, R5,
R6, R7.
HEX OPCODE: This column gives the machine language hexadecimal opcode for each
8051 instruction.
B: This column gives the number of bytes in each 8051 instruction.
C: This column gives the number of cycles of each 8051 instruction. The time value of a
cycle is dened as 12 divided by the oscillator frequency. For example, if running an
8051 family component at 12 MHz, each cycle takes 1 microsecond.
PSW: This column identies which condition code ags are aected by the operation of
the individual instructions. The condition code ags available on the 8051 are the
Carry Flag, CF, the Auxiliary Carry Flag, AC, and the Over ow Flag, OV.
It should be noted that the PSW is both byte and bit directly addressable. Should
the PSW be the operand of an instruction that modies it, the condition codes could
be changed even if this column states that the instruction doesn't aect them.
0 Condition code is cleared
1 Condition code is set
Condition code is modied by instruction
- Condition code is not aected by instruction
4.2 8051 Instruction Set Summary

Mnemonic Operation Dest Src Assembly Hex B C PSW
Addr Addr Language Code CF AC OV
Mode Mode Form
ACALL
2K in Page (11 bits) PC + 2 )STACK Prog Dir ACALL Paddr see 2 2 - - -
Absolute Call SP + 2 )SP note 1
Paddr<10:0>)PC<10:0>
PC<15:11>)PC<15:11>
ADD
Add Operand to A + SOper )A Accum Immed ADD A,#data 24 2 1 * * *
Accum Accum Direct ADD A,Daddr 25 2 1
Accum Indirect ADD A,@Ri 26,27 1 1
Accum Reg ADD A,Rn 28-2F 1 1
ADDC
Add Operand with A + SOper + C )A Accum Immed ADDC A,#data 34 2 1 * * *
Carry to Accum Accum Direct ADDC A,Daddr 35 2 1
Accum Indirect ADDC A,@Ri 36,37 1 1
Accum Reg ADDC A,Rn 38-3F 1 1
AJMP see
2K in Page (11 bits) Paddr<10:0>)PC<10:0> Prog Dir AJMP Paddr note 2 2 2 - - -
Absolute Jump PC<15:11>)PC<15:11>
ANL
Logical AND of Source SOper ^ DOper )DOper Direct Accum ANL Daddr,A 52 2 1 - - -
Operand with Direct Immed ANL Daddr,#data 53 3 2
Destination Operand Accum Immed ANL A,#data 54 2 1
Accum Direct ANL A,Daddr 55 2 1
Accum Indirect ANL A,@Ri 56,57 1 1
Accum Reg ANL A,Rn 58-5F 1 1
Logical AND of Source SOper ^ CF )CF CF Bit Dir ANL C,Baddr 82 2 2 * - -
Operand with CF SOper ^ CF )CF
Logical AND of Source CF Bit Dir ANL C,/Baddr B0 2 2 * - -
Operand Complemented
with CF
CJNE
Compare Operands and Jump Relative to PC if Accum Immed CJNE A,#data,Ro B4 3 2 * - -
Jump Relative if not DOper <>SOper Accum Direct CJNE A,Daddr,Ro B5 3 2 see
Equal Indirect Immed CJNE @Ri,#data,Ro B6,B7 3 2 note 3
Reg Immed CJNE Rn,#data,Ro B8-BF 3 2
CLR
Clear Accum 0 )A Accum CLR A E4 1 1 - - -
Clear CF 0 )CF CF CLR C C3 1 1 0 - -
Clear Bit Operand 0 )DOper Bit Dir CLR Baddr C2 2 1 - - -
CPL A )A
Complement Accum CF )CF Accum CPL A F4 1 1 - - -
Complement CF CF CPL C B3 1 1 * - -
Complement Bit Operand DOper )DOper Bit Dir CPL Baddr B2 2 1 - - -
DA
Decimal Adjust If (A<3:0>>9) v AC Accum DA A D4 1 1 * - -
Accum for then A<3:0>+6 )A<3:0> see
Addition If (A<7:4>>9) v CF note 4
then A<7:4>+6 )A<7:4>
DEC
Decrement Operand DOper - 1 )DOper Accum DEC A 14 1 1 - - -
Direct DEC Daddr 15 2 1
Indirect DEC @Ri 16,17 1 1
Reg DEC Rn 18-1F 1 1
Table 4.1: 8051 instruction set.

Chap. 4: 8051 INSTRUCTION SET 27

Mode Mode Form
DIV
Divide Accum by A / B )A AB DIV AB 84 1 4 0 - *
B Reg Remainder )B see
note 5
DJNZ
Decrement Operand and DOper - 1 )DOper Direct DJNZ Daddr,Ro D5 3 2 - - -
Jump Relative if Not If DOper <>0 then Jump Reg DJNZ Rn,Ro D8-DF 2 2
Zero Relative to PC
INC
Increment Operand DOper + 1 )DOper Accum INC A 04 1 1 - - -
Direct INC Daddr 05 2 1
Indirect INC @Ri 06,07 1 1
Reg INC Rn 08-0F 1 1
Data Ptr INC DPTR A3 1 2
JB
Jump Relative if Bit If DOper = 1 then Jump Bit Dir JB Baddr,Ro 20 3 2 - - -
Operand is Set Relative to PC
JBC
Jump Relative if Bit If DOper = 1 then Bit Dir JBC Baddr,Ro 10 3 2 * * *
Operand is Set and 0 )DOper and Jump see
Clear Bit Operand Relative to PC note 6
JC
Jump Relative if If CF = 1 then Jump CF JC Ro 40 2 2 - - -
CF is Set Relative to PC
JMP
Jump Indirect DPTR<15:0>+ A<7:0> Prog Indir JMP @A+DPTR 73 1 2 - - -
)PC<15:0>
JNB
Jump Relative if Bit If DOper = 0 then Jump Bit Dir JNB Baddr,Ro 30 3 2 - - -
Operand is Clear Relative to PC
JNC
Jump Relative if If CF = 0 then Jump CF JNC Ro 50 2 2 - - -
CF is Clear Relative to PC
JNZ
Jump Relative if the If A<7:0><>0 then Accum JNZ Ro 70 2 2 - - -
Accum is Not Jump Relative to PC
Zero
JZ
Jump Relative if the If A<7:0>= 0 then Accum JZ Ro 60 2 2 - - -
Accum is Zero Jump Relative to PC
LCALL
Long (16 bits) Call PC + 3 )STACK Prog Dir LCALL Paddr 12 3 2 - - -
SP + 2 )SP
Paddr<15:0>)PC<15:0>
LJMP
Long (16 bits) Paddr<15:0>)PC<15:0> Prog Dir LJMP Paddr 02 3 2 - - -
Absolute Jump
MOV
Move Source Operand SOper )DOper Accum Immed MOV A,#data 74 2 1 - - -
to Destination Accum Direct MOV A,Daddr E5 2 1
Operand Accum Indirect MOV A,@Ri E6,E7 1 1
Accum Reg MOV A,Rn E8-EF 1 1
Direct Accum MOV Daddr,A F5 2 1
Direct Immed MOV Daddr,#data 75 3 2
Direct Direct MOV Daddr,Daddr 85 3 2
Direct Indirect MOV Daddr,@Ri 86,87 2 2
Direct Reg MOV Daddr,Rn 88-8F 2 2
Indirect Accum MOV @Ri,A F6,F7 1 1
SOper )DOper Indirect Immed MOV @Ri,#data 76,77 2 1
Indirect Direct MOV @Ri,Daddr A6,A7 2 2
Reg Accum MOV Rn,A F8-FF 1 1
Reg Immed MOV Rn,#data 78-7F 2 1
Reg Direct MOV Rn,Daddr A8-AF 2 2
Data Ptr Immed MOV DPTR,#data16 90 3 2
Move CF to Bit CF )DOper Bit Dir CF MOV Baddr,C 92 2 2 - - -
Destination Operand
Move Bit Destination DOper )CF CF Bit Dir MOV C,Baddr A2 2 1 * - -
Operand to CF
MOVC
Move byte from PM(DPTR<15:0>+ A<7:0>) Accum Prog Ind MOVC A,@A+DPTR 93 1 2 - - -
Program Memory to )A<7:0>
PM(PC<15:0>+ A<7:0>) Accum Prog Ind MOVC A,@A+PC 83 1 2 - - -
)A<7:0>
MOVX
Move byte from SOper )A Accum Indirect MOVX A,@Ri E2,E3 1 2 - - -
External Data Memory Accum Indirect MOVX A,@DPTR E0 1 2
to the Accum
Move byte in the A )DOper Indirect Accum MOVX @Ri,A F2,F3 1 2 - - -
Accum to Indirect Accum MOVX @DPTR,A F0 1 2
External Data Memory
MUL
Multiply Accum A X B )B,A AB MUL AB A4 1 4 0 - *
by B Reg (see note 7)
Table 4.1: 8051 instruction set (continued).


Mode Mode Form
NOP
No Operation NOP 00 1 1 - - -
ORL
Logical Inclusive OR SOper v DOper )DOper Direct Accum ORL Daddr,A 42 2 1 - - -
of Source Operand Direct Immed ORL Daddr,#data 43 3 2
with Destination Accum Immed ORL A,#data 44 2 1
Operand Accum Direct ORL A,Daddr 45 2 1
Accum Indirect ORL A,@Ri 46,47 1 1
Accum Reg ORL A,Rn 48-4F 1 1
Logical Inclusive OR SOper v CF )CF CF Bit Dir ORL C,Baddr 72 2 2 * - -
of Source Operand
with CF
Logical Inclusive OR SOper v CF )CF CF Bit Dir ORL C,/Baddr A0 2 2 * - -
of Source Operand
Complemented with CF
POP
Pop Stack and Place STACK )DOper Direct Stack POP Daddr D0 2 2 - - -
in Destination Operand SP - 1 )SP
PUSH
Push Source Operand SP + 1 )SP Stack Direct PUSH Daddr C0 2 2 - - -
onto Stack SOper )STACK
RET
Return from STACK )PC<15:8> RET 22 1 2 - - -
Subroutine SP - 1 )SP
STACK )PC<7:0>
SP - 1 )SP
RETI
Return from STACK )PC<15:8> RETI 32 1 2 - - -
Interrupt Routine SP - 1 )SP
STACK )PC<7:0>
SP - 1 )SP
0 )Intrupt Active Flag
RL
Rotate Accum A<6:0>)A<7:1> Accum RL A 23 1 1 - - -
Left One Bit A<7>)A<0>
RLC
Rotate Accum A<6:0>)A<7:1> Accum RLC A 33 1 1 * - -
Left One Bit Thru CF )A<0>
the CF A<7>)CF
RR
Rotate Accum A<7:1>)A<6:0> Accum RR A 03 1 1 - - -
Right One Bit A<0>)A<7>
RRC
Rotate Accum A<7:1>)A<6:0> Accum RRC A 13 1 1 * - -
Right One Bit Thru CF )A<7>
the CF A<0>)CF
SETB
Set Bit Operand 1 )CF CF SETB C D3 1 1 1 - -
1 )DOper Bit Dir SETB Baddr D2 2 1 - - -
SJMP
Short (8 bits) Jump Relative to PC SJMP Ro 80 2 2 - - -
Relative Jump
SUBB
Subtract Operand with A - SOper - CF )A Accum Immed SUBB A,#data 94 2 1 * * *
Borrow from the Accum Direct SUBB A,Daddr 95 2 1
Accum Accum Indirect SUBB A,@Ri 96,97 1 1
Accum Reg SUBB A,Rn 98-9F 1 1
SWAP
Swap Nibbles within A<7:4>)A<3:0> Accum SWAP A C4 1 1 - - -
the Accum A<3:0>)A<7:4>
XCH
Exchange bytes of the SOper<7:0>)A<7:0> Accum Direct XCH A,Daddr C5 2 1 - - -
Accum and the A<7:0>)SOper<7:0> Accum Indirect XCH A,@Ri C6,C7 1 1
Source Operand Accum Reg XCH A,Rn C8-CF 1 1
XCHD
Exchange the Least SOper<3:0>)A<3:0> Accum Indirect XCHD A,@Ri D6,D7 1 1 - - -
Signicant Nibble of A<3:0>)SOper<3:0>
the Accum and
the Source Operand
XRL
Logical Exclusive OR SOper v DOper )DOper Direct Accum XRL Daddr,A 62 2 1 - - -
of Source Operand Direct Immed XRL Daddr,#data 63 3 2
with Destination Accum Immed XRL A,#data 64 2 1
Operand Accum Direct XRL A,Daddr 65 2 1
Accum Indirect XRL A,@Ri 66,67 1 1
Accum Reg XRL A,Rn 68-6F 1 1
Table 4.1: 8051 instruction set (continued).

Chapter 5
8051 CROSS ASSEMBLER DIRECTIVES
5.1 Introduction
The 8051 Cross Assembler Directives are used to dene symbols, reserve memory space,
store values in program memory, select various memory spaces, set the current segment's
location counter and identify the end of the source le.
Only one directive per line is allowed, however comments may be included. The remaining
part of this chapter details the function of each directive.
5.2 Symbol Denition Directives

5.2.1 EQU Directive
The EQUate directive is used to assign a value to a symbol. It can also be used to specify
user dened names for the implicit operand symbols predened for the Accumulator (i.e.,
A) and the eight General Purpose Registers (i.e., R0 thru R7).
The format for the EQU directive is: symbol, followed by one or more spaces or tabs,
followed by EQU, followed by one or more spaces or tabs, followed by a number, arithmetic
expression, previously dened symbol (no forward references allowed) or one of the allowed
implicit operand symbols (e.g., A, R0, R1, R2, R3, R4, R5, R6, R7), followed by an optional
comment.
Below are examples of using the EQU Directive:
TEN EQU 10 ;Symbol equated to a number
COUNTER EQU R7 ;User defined symbol for the implicit
;operand symbol R7. COUNTER can now
;be used wherever it is legal to use
;R7. For example the instruction
;INC R7 could now be written INC COUNTER.
ALSO_TEN EQU TEN ;Symbol equated to a previously defined
;symbol.
FIVE EQU TEN/2 ;Symbol equated to an arithmetic exp.
A_REG EQU A ;User defined symbol for the implicit
;operand symbol A.
ASCII_D EQU 'D' ;Symbol equated to an ASCII literal
30 Chap. 5: 8051 CROSS ASSEMBLER DIRECTIVES
5.2.2 SET Directive

Similar to the EQU directive, the SET directive is used to assign a value or implicit operand
to a user dened symbol. The dierence however, is that with the EQU directive, a symbol
can only be dened once. Any attempt to dene the symbol again will cause the Cross
Assembler to ag it as an error. On the other hand, with the SET directive, symbols are
redeneable. There is no limit to the number of times a symbol can be redened with the
SET directive.
The format for the SET directive is: symbol, followed by one or more spaces or tabs,
followed by SET, followed by one or more spaces or tabs, followed by a number, arithmetic
expression, previously dened symbol (no forward references allowed) or one of the allowed
implicit operand symbols (e.g., A, R0, R1, R2, R3, R4, R5, R6, R7), followed by an optional
comment.
Below are examples of using the SET Directive:
POINTER SET R0 ;Symbol equated to register 0
POINTER SET R1 ;POINTER redefined to register 1
COUNTER SET 1 ;Symbol initialized to 1

COUNTER SET COUNTER+1 ;An incrementing symbol
5.2.3 BIT Directive

The BIT Directive assigns an internal bit memory direct address to the symbol. If the
numeric value of the address is between 0 and 127 decimal, it is a bit address mapped in
the Internal Memory Space. If the numeric value of the address is between 128 and 255, it
is an address of a bit located in one of the Special Function Registers. Addresses greater
than 255 are illegal and will be agged as an error.
The format for the BIT Directive is: symbol, followed by one or more spaces or tabs,
followed by BIT, followed by one or more spaces or tabs, followed by a number, arithmetic
expression, or previously dened symbol (no forward references allowed), followed by an
optional comment.
Below are examples of using the BIT Directive:
CF BIT 0D7H ;The single bit Carry Flag in PSW
OFF_FLAG BIT 6 ;Memory address of single bit flag
ON_FLAG BIT OFF_FLAG+1 ;Next bit is another flag
5.2.4 CODE Directive

The CODE Directive assigns an address located in the Program Memory Space to the
symbol. The numeric value of the address cannot exceed 65535.
The format for the CODE Directive is: symbol, followed by one or more spaces or tabs,
followed by CODE, followed by one or more spaces or tabs, followed by a number, arithmetic
optional comment.
Chap. 5: 8051 CROSS ASSEMBLER DIRECTIVES 31
Below are examples of using the CODE Directive:

RESET CODE 0
EXTI0 CODE RESET + (1024/16)
5.2.5 DATA Directive

The DATA Directive assigns a directly addressable internal memory address to the symbol.
If the numeric value of the address is between 0 and 127 decimal, it is an address of an
Internal Data Memory location. If the numeric value of the address is between 128 and 255,
it is an address of a Special Function Register. Addresses greater than 255 are illegal and
will be agged as an error.
The format for the DATA Directive is: symbol, followed by one or more spaces or tabs,
followed by DATA, followed by one or more spaces or tabs, followed by a number, arithmetic
optional comment.
Below are examples of using the DATA Directive:
PSW DATA 0D0H ;Defining the Program Status address
BUFFER DATA 32 ;Internal Data Memory address
FREE_SPAC DATA BUFFER+16 ;Arithmetic expression.
5.2.6 IDATA Directive

The IDATA Directive assigns an indirectly addressable internal data memory address to the
symbol. The numeric value of the address can be between 0 and 255 decimal. Addresses
greater than 255 are illegal and will be agged as an error.
The format for the IDATA Directive is: symbol, followed by one or more spaces or tabs,
followed by IDATA, followed by one or more spaces or tabs, followed by a number, arithmetic
optional comment.
Below are examples of using the IDATA Directive:
TOKEN IDATA 60
BYTE_CNT IDATA TOKEN + 1
ADDR IDATA TOKEN + 2
5.2.7 XDATA Directive

The XDATA Directive assigns an address located in the External Data Memory Space to
the symbol. The numeric value of the address cannot exceed 65535.
The format for the XDATA Directive is: symbol, followed by one or more spaces or tabs,
followed by XDATA, followed by one or more spaces or tabs, followed by a number, arith-
metic expression, or previously dened symbol (no forward references allowed), followed by
an optional comment.
Below are examples of using the XDATA Directive:
USER_BASE XDATA 2048

HOST_BASE XDATA USER_BASE + 1000H
5.3 Segment Selection Directives

There are ve Segment Selection Directives: CSEG, BSEG, DSEG, ISEG, XSEG, one for
each of the ve memory spaces in the 8051 architecture. The CSEG Directive is used to
select the Program Memory Space. The BSEG Directive is used to select the Bit Memory
Space. The DSEG Directive is used to select the directly addressable Internal Data Memory
Space. The ISEG is used to select the indirectly addressable Internal Data Memory Space.
The XSEG is used to select the External Data Memory Space.
Each segment has its own location counter that is reset to zero during the Cross Assembler
program initialization. The contents of the location counter can be overridden by using the
optional AT after selecting the segment.
The Program Memory Space, or CSEG, is the default segment and is selected when the
Cross Assembler is run.
The format of the Segment Selection Directives are: zero or more spaces or tabs, followed
by the Segment Selection Directive, followed by one or more spaces or tabs, followed by the
optional segment location counter override AT command and value, followed by an optional
comment.
The value of the AT command can be a number, arithmetic expression or previously dened
symbol (forward references are not allowed). Care should be taken to ensure that the
location counter does not advance beyond the limit of the selected segment.
Below are examples of the Segment Selection Directives:
DSEG ;Select direct data segment using
;current location counter value.
BSEG AT 32 ;Select bit data segment forcing
;location counter to 32 decimal.
XSEG AT (USER_BASE * 5) MOD 16 ;Arithmetic expressions can be
;used to specify location.
5.4 Memory Reservation and Storage Directives

5.4.1 DS Directive
The DS Directive is used to reserve space in the currently selected segment in byte units.
It can only be used when ISEG, DSEG or XSEG are the currently active segments. The
location counter of the segment is advanced by the value of the directive. Care should be
taken to ensure that the location counter does not advance beyond the limit of the segment.
The format for the DS Directive is: optional label, followed by one or more spaces or tabs,
followed by DS, followed by one or more spaces or tabs, followed by a number, arithmetic
optional comment.
Below is an example of using the DS Directive in the internal Data Segment. If, for example,
the Data Segment location counter contained 48 decimal before the example below, it would
contain 104 decimal after processing the example.
DSEG ;Select the data segment
DS 32 ;Label is optional
SP_BUFFER: DS 16 ;Reserve a buffer for the serial port
IO_BUFFER: DS 8 ;Reserve a buffer for the I/O
5.4.2 DBIT Directive

The DBIT Directive is used to reserve bits within the BIT segment. It can only be used
when BSEG is the active segment. The location counter of the segment is advanced by the
value of the directive. Care should be taken to ensure that the location counter does not
advance beyond the limit of the segment.
The format for the DBIT Directive is: optional label, followed by one or more spaces or tabs,
followed by DBIT, followed by one or more spaces or tabs, followed by a number, arithmetic
optional comment.
Below is an example of using the DBIT Directive:
BSEG ;Select the bit segment
DBIT 16 ;Label is optional
IO_MAP: DBIT 32 ;Reserve a bit buffer for I/O
5.4.3 DB Directive
The DB Directive is used to store byte constants in the Program Memory Space. It can
only be used when CSEG is the active segment.
The format for the DB Directive is: optional label, followed by one or more spaces or tabs,
followed by DB, followed by one or more spaces or tabs, followed by the byte constants that
are separated by commas, followed by an optional comment.
The byte constants can be numbers, arithmetic expressions, symbol values or ASCII literals.
ASCII literals have to be delimited by apostrophes ( ' ), but they can be strung together
up to the length of the line.
Below are examples of using the DB Directive. If an optional label is used, its value will
point to the rst byte constant listed.
COPYRGHT_MSG:
DB '(c) Copyright, 1984' ;ASCII Literal
RUNTIME_CONSTANTS:
DB 127,13,54,0,99 ;Table of constants
DB 17,32,239,163,49 ;Label is optional
MIXED: DB 2*8,'MPG',2*16,'abc' ;Can mix literals & no.
5.4.4 DW Directive
The DW Directive is used to store word constants in the Program Memory Space. It can
only be used when CSEG is the active segment.
The format for the DW Directive is: optional label, followed by one or more spaces or tabs,
followed by DW, followed by one or more spaces or tabs, followed by the word constants
that are separated by commas, followed by an optional comment.
The word constants can be numbers, arithmetic expressions, symbol values or ASCII literals.
ASCII literals must be delimited by apostrophes ( ' ), but unlike the DB Directive, only a
maximum of two ASCII characters can be strung together. The rst character is placed in
the high byte of the word and the second character is placed in the low byte. If only one
character is enclosed by the apostrophes, a zero will be placed in the high byte of the word.
Below are examples of using the DW Directive. If an optional label is used, its value will
point to the high byte of the rst word constant listed.
JUMP_TABLE: DW RESET,START,END ;Table of addresses
DW TEST,TRUE,FALSE ;Optional label
RADIX: DW 'H',1000H ;1st byte contains 0
;2nd byte contains 48H (H)
;3rd byte contains 10H
;4th byte contains 0
5.5 Miscellaneous Directives

5.5.1 ORG Directive
The ORG Directive is used to specify a value for the currently active segment's location
counter. It cannot be used to select segments like the directives above. It can only be used
within a segment when the location counter needs to be changed. Care should be taken to
ensure that the location counter does not advance beyond the limit of the selected segment.
The format of the ORG Directive is: zero or more spaces or tabs, followed by ORG, followed
by one or more spaces or tabs, followed by a number, arithmetic expression, or previously
dened symbol (no forward references are allowed), followed by an optional comment.
Below are examples of the ORG directive.
ORG 1000H ;Location counter set at 4096 decimal
ORG RESET ;Previously defined symbol
ORG BASE + MODULE_NO ;Arithmetic expression
5.5.2 USING DIRECTIVE

The USING Directive is used to specify which of the four General Purpose Register banks
is used in the code that follows the directive. It allows the use of the predened register
symbols AR0 thru AR7 instead of the register's direct addresses. It should be noted that
the actual register bank switching must still be done in the code. This directive simplies
the direct addressing of a specied register bank.
The format of the USING Directive is: zero or more spaces or tabs, followed by USING,
followed by one or more spaces or tabs, followed by a number, arithmetic expression, or
previously dened symbol (no forward references are allowed), followed by an optional
comment.
The number, arithmetic expression, or previously dened symbol must result in a number
between 0 and 3 in order to specify one of the four register banks in the 8051.
The following table maps the specied value in the USING directive with the direct addresses
of the predened symbols.
Predened USING Value
Symbol 0 1 2 3
AR0 0 8 16 24
AR1 1 9 17 25
AR2 2 10 18 26
AR3 3 11 19 27
AR4 4 12 20 28
AR5 5 13 21 29
AR6 6 14 22 30
AR7 7 15 23 31
Below are examples of the USING Directive:
USING 0 ;Select addresses for Bank 0
USING 1+1+1 ;Arithmetic expressions
5.5.3 END Directive

The END Directive is used to signal the end of the source program to the Cross Assembler.
Every source program must have one and only one END Directive. A missing END Direc-
tive, as well as text beyond the occurrence of the END Directive are not allowed and will
be agged as errors.
The format of the END Directive is: zero or more spaces or tabs, followed by END, followed
by an optional comment. All text must appear in the source program before the occurrence
of the END Directive.
Below is an example of the END Directive:
END ;This is the End
5.6 Conditional Assembly Directives

5.6.1 IF, ELSE and ENDIF Directive
The IF, ELSE and ENDIF directives are used to dene conditional assembly blocks. A
conditional assembly block begins with an IF statement and must end with the ENDIF
directive. In between the IF statement and ENDIF directive can be any number of assembly
language statements, including directives, controls, instructions, the ELSE directive and
nested IF-ENDIF conditional assembly blocks.
The IF statement starts with the keyword IF, followed by one or more spaces or tabs,
followed by a number, arithmetic expression, or previously dened symbol (no forward ref-
erences are allowed), followed by an optional comment. The number, arithmetic expression
or symbol is evaluated and if found to be TRUE (non- zero), the assembly language state-
ments are translated up to the next ELSE or ENDIF directives. If the IF statement was
evaluated FALSE (zero), the assembly language statements are considered null up to the
next ELSE or ENDIF directives.
If an optional ELSE appears in the conditional assembly block, the assembly language state-
ments following are handled oppositely from the assembly language statements following
the IF statement. In other words, if the IF statement was evaluated TRUE, the statements
following it are translated, while the statements following the ELSE will be handled as if
they were null. On the other hand, if the IF statement was evaluated FALSE, only the
assembly language statements following the ELSE directive would be translated.
IF-ELSE-ENDIF conditional assembly blocks can be nested up to 255 levels deep. The
following are some examples of conditional assembly blocks. This rst conditional assembly
block simply checks the symbol DEBUG. If DEBUG is non-zero, the MOV and CALL
instructions will be translated by the Cross Assembler.
IF (DEBUG)
MOV A,#25
CALL OUTPUT
ENDIF
The next example used the optional ELSE directive. If SMALL MODEL is zero, only the
statements following the ELSE directive will be translated.
IF (SMALL_MODEL)
MOV R0,#BUFFER
MOV A,@R0
ELSE
MOV R0,#EXT_BUFFER
MOVX A,@R0
ENDIF
The last example shows nested conditional assembly blocks. Conditional assembly blocks
can be nested up to 255 levels deep. Every level of nesting must have balanced IF-ENDIF
statements.
IF (VERSION > 10) \
CALL DOUBLE_PRECISION |
CALL UPDATE_STATUS _ |
IF (DEBUG) \ |
CALL DUMP_REGISTERS > Nested |
ENDIF _/ Block |
ELSE > Outer Block
CALL SINGLE_PRECISION |
CALL UPDATE_STATUS _ |
IF (DEBUG) \ |
CALL DUMP_REGISTERS > Nested |
ENDIF _/ Block |
ENDIF _/
Chapter 6
8051 CROSS ASSEMBLER CONTROLS
6.1 Introduction
Assembler controls are used to control where the Cross Assembler gets its input source le,
where it stores the object le, how it formats and where it outputs the listing.
All Assembler controls are prefaced with a dollar sign, ($). No spaces or tabs are allowed
between the dollar sign and the body of the control. Also, only one control per line is
permitted. Comments are allowed on the same line as an Assembler control.
There are two types of controls, Primary controls and General controls. Primary controls
can be invoked only once per assembly. If an attempt is made to change a previously invoked
primary control, the attempt is ignored. For example, if $NOPRINT is put on line 1 of
the source le and $PRINT is put on line 2, the $PRINT control will be ignored and the
listing will not be output. General controls can be invoked any number of times in a source
program.
There are two legal forms for each Assembler control, the full form and the abbreviated
form. The two forms can be used inter- changeable in the source program.
Below is a description of each Assembler control. Assembler controls with common func-
tionality are grouped together.
6.2 Assembler Control Descriptions

6.2.1 $DATE(date)
Places the ASCII string enclosed by parenthesis in the date eld of the page header. The
ASCII string can be from 0 to 9 characters long.
CONTROL: $DATE(date)
ABBREV: $DA(date)
TYPE: Primary
DEFAULT: No date in page header
EXAMPLES: $DATE(1-JUL-84)
$DA(7/22/84)
38 Chap. 6: 8051 CROSS ASSEMBLER CONTROLS
6.2.2 $DEBUG(le) and $NODEBUG

These controls determine whether or not a MetaLink Absolute Object Module format le
is created. The MetaLink Absolute Object Module format le is used in conjunction with
MetaLink's MetaICE series of in-circuit-emulators. Among other advantages, it provides
powerful symbolic debug capability in the emulator debug environment. $NODEBUG spec-
ies that a MetaLink Absolute Object Module le will not be created. $DEBUG species
that a MetaLink Absolute Object Module le will be created. The $DEBUG control allows
any legal le name to be specied as the MetaLink Absolute Object Module lename. If no
lename is specied, a default name is used. The default name used for the le is the source
le name root with a .DBG extension. If the $DEBUG control is used, both a MetaLink
Absolute Object Module le and a standard Intel Hexadecimal format object le can be
generated at the same time. Refer to the $OBJECT control description later in this chapter
for information on controlling the Hexadecimal format object le output.
CONTROL: $DEBUG(file)
$NODEBUG
ABBREV: $DB(file)
$NODB
DEFAULT: $NODEBUG
TYPE: Primary
EXAMPLES: $DB(A:NEWNAME.ICE)
$DEBUG
$NOOBJECT
6.2.3 $EJECT
Places a form feed (ASCII 0CH) in the listing output. The $NOPAGING control will
override this control.
CONTROL: $EJECT
ABBREV: $EJ
DEFAULT: No form feeds in listing output
TYPE: General
EXAMPLES: $EJECT
$EJ
6.2.4 $INCLUDE(le)

Inserts a le in source program as part of the input source program. The le eld in this
control can be any legal le designator. No extension is assumed, so the whole le name
must be specied. Any number of les can be included in a source program. Includes can
be nested up to 8 level deep. It is important to note that this control inserts les, it does
not chain or concatenate les.
CONTROL: $INCLUDE(file)
ABBREV: $IC(file)
DEFAULT: No file included in source program
TYPE: General
EXAMPLES: $INCLUDE(B:COMMON.EQU
$IC(TABLES.ASM) ;Uses default drive
Chap. 6: 8051 CROSS ASSEMBLER CONTROLS 39
6.2.5 $LIST and $NOLIST

These controls determine whether or not the source program listing is output or not. $LIST
will allow the source program listing to be output. $NOLIST stops the source program
listing from being output. The $NOPRINT control overrides the $LIST control.
CONTROL: $LIST
$NOLIST
ABBREV: $LI
$NOLI
DEFAULT: $LIST
TYPE: General
EXAMPLES: $NOLIST ;This will cause the included
$INCLUDE(COMMON.TBL) ;file not to be listed
$LI ;Listing continues
6.2.6 $MOD and $NOMOD

Recognizes predened special function register symbols in the source program. This saves
the user from having to dene all the registers in the source program. Appendix B lists the
symbols that are dened by these controls. $NOMOD disables the recognizing function.
These controls access les of the same name that are included with the MetaLink 8051
CROSS ASSEMBLER distribution diskette. When a $MOD control is used in a source
program, it is important that the $MOD le be available to the Cross Assembler. The
Cross Assembler rst looks for the $MOD le on the default drive, if it isn't found there,
the Cross Assembler looks for it on the A: drive. The components supported by each switch
are:
$MOD51: 8051, 8751, 8031, 80C51, 80C31, 87C51, 9761, 8053
$MOD52: 8052, 8032, 8752
$MOD44: 8044, 8344, 8744
$MOD515: 80515, 80535, 80C515, 80C535
$MOD512: 80512, 80532
$MOD517: 80C517, 80C537
$MOD152: 80C152, 83C152, 80C157
$MOD451: 80C451. 83C451, 87C451
$MOD452: 80C452, 83C452, 87C452
$MOD752: 83C752, 87C752
$MOD751: 83C751, 87C751
$MOD154: 83C514, 80C154, 85C154
$MOD252: 80C252, 83C252, 87C252, 80C51FA, 83C51FA, 87C51FA,
83C51FB, 87C51FB
$MOD521: 80C521, 80C321, 87C521, 80C541, 87C541
$MOD552: 80C552, 83C552, 87C552
$MOD652: 80C652, 83C652
$MOD851: 80C851, 83C851
CONTROL: $MOD51 $MOD52 $MOD44 $MOD152 $MOD515

$MOD512 $MOD451 $MOD452 $MOD751
$MOD752 $MOD154 $MOD252 $MOD521
$MOD552 $MOD652 $MOD517 $MOD851
$NOMOD
ABBREV:
DEFAULT: $NOMOD
TYPE: Primary
EXAMPLES: $MOD51 $MOD52 $MOD44 $MOD515 $MOD512
$MOD152 $MOD451 $MOD452 $MOD751
$MOD752 $MOD154 $MOD252 $MOD521
$MOD552 $MOD652 $MOD517 $MOD851
$NOMOD
6.2.7 $OBJECT(le) and $NOOBJECT

These controls determine whether or not a standard Intel Hexadecimal format object le is
created. $NOOBJECT species that an object le will not be created. $OBJECT species
that an object le will be created. If other than the default name is to be used for the
object le, the $OBJECT control allows any legal le name to be specied as the object
lename. The default name used for the object le is the source le name root with a .HEX
extension.
CONTROL: $OBJECT(file)
$NOOBJECT
ABBREV: $OJ(file)
$NOOJ
DEFAULT: $OBJECT(source.HEX)
TYPE: Primary
EXAMPLES: $OJ(A:NEWNAME.OBJ)
$NOOBJECT
6.2.8 $PAGING and $NOPAGING

These controls specify whether or not the output listing will be broken into pages or will
be output as one continuous listing. When the $NOPAGING control is used, the $EJECT
and $PAGELENGTH controls are ignored. With the $PAGING control, a form feed and
header line is inserted into the output listing whenever an $EJECT control is met, or
whenever the number of lines output on the current page exceeds the value specied by
the $PAGELENGTH control. The header line contains source le name, title (if $TITLE
control was used), date (if $DATE control was used) and page number.
CONTROL: $PAGING
$NOPAGING
ABBREV: $PI
$NOPI
DEFAULT: $PAGING
TYPE: Primary
EXAMPLES: $PAGING
$NOPI
6.2.9 $PAGELENGTH(n)
Sets the maximum number of lines, (n), on a page of the output listing. If the maximum is
exceeded, a form feed and page header is inserted in the output listing. This control allows
the number of lines per page to be set anywhere between 10 and 255. If the number of lines
specied is less than 10, pagelength will be set to 10. If the number of lines specied is
greater than 255, pagelength will be set to 255.
Chap. 6: 8051 CROSS ASSEMBLER CONTROLS 41
The $NOPAGING control will override this control.

CONTROL: $PAGELENGTH(n)
ABBREV: $PL(n)
DEFAULT: $PAGELENGTH(60)
TYPE: Primary
EXAMPLES: $PAGELENGTH(48)
$PL(58)
6.2.10 $PAGEWIDTH(n)
Sets the maximum number of characters, (n), on a line of the output listing. This control
allows the number of characters per line to be set anywhere between 72 and 132. If the
number specied is less than 72, the pagewidth is set at 72. If the number specied is
greater than 132, the pagewidth is set at 132. If the pagewidth is specied between 72 and
100 and the line being output exceeds the pagewidth specication, the line is truncated at
the specied pagewidth and a carriage return/line feed pair is inserted in the listing. If the
pagewidth is specied to be greater than 100 and the line being output exceed the pagewidth
specication, a carriage return/line feed pair is inserted at the specied pagewidth and the
line will continue to be listed on the next line beginning at column 80.
CONTROL: $PAGEWIDTH(n)
ABBREV: $PW(n)
DEFAULT $PAGEWIDTH(72)
TYPE: Primary
EXAMPLES: $PAGEWIDTH(132)
$PW(80)
6.2.11 $PRINT(le) and $NOPRINT

These controls determine whether or not a listing le is created. $NOPRINT species that
a listing le will not be created. $PRINT species that an listing le will be created. If
other than the default name is to be used for the listing le, the $PRINT control allows any
legal le name to be specied as the listing lename. The default name used for the listing
le is the source le name root with a .LST extension.
CONTROL: $PRINT(file)
$NOPRINT
ABBREV: $PR
$NOPR
DEFAULT: $PRINT(source.LST)
TYPE: Primary
EXAMPLES: $PRINT(A:CONTROL.OUT)
$NOPR
6.2.12 $SYMBOLS and $NOSYMBOLS

Selects whether or not the symbol table is appended to the listing output. $SYMBOLS
causes the symbol table to be sorted alphabetically by symbol, formatted and output to the
listing le. Along with the symbol name, its value and type are output. Values are output
in hexadecimal. Types include NUMB (number), ADDR (address), REG (register symbol)
and ACC (accumulator symbol). If a symbol was of type ADDR, it segment is also output
as either C (code), D (data) or X (external). Other information listed with the symbols is
NOT USED (symbol dened but never referenced), UNDEFINED (symbol referenced but
never dened) and REDEFINEABLE (symbol dened using the SET directive). The type
and value listed for a REDEFINABLE symbol is that of its last denition in the source
program. $NOSYMBOLS does not output the symbol table.
CONTROL: $SYMBOLS
$NOSYMBOLS
ABBREV: $SB
$NOSB
DEFAULT: $SYMBOLS
TYPE: Primary
EXAMPLES: $SB
$NOSYMBOLS
6.2.13 $TITLE(string)
Places the ASCII string enclosed by the parenthesis in the title eld of the page header. The
ASCII string can be from 0 to 64 characters long. If the string is greater than 64 characters
or if the width of the page will not support such a long title, the title will be truncated. If
parentheses are part of the string, they must be balanced.
CONTROL: $TITLE(string)
ABBREV: $TT(string)
DEFAULT: No title in page header
TYPE: Primary
EXAMPLES: $TITLE(SAMPLE PROGRAM V1.2)
$TT(METALINK (TM) CROSS ASSEMBLER)
Chapter 7
8051 CROSS ASSEMBLER MACRO PROCESSOR
7.1 Introduction
Macros are useful for code that is used repetitively throughout the program. It saves the
programmer the time and tedium of having to specify the code every time it is used. The
code is written only once in the macro denition and it can be used anywhere in the source
program any number of times by simply using the macro name.
Sometimes there is confusion between macros and subroutines. Subroutines are common
routines that are written once by the programmer and then accessed by CALLing them.
Subroutines are usually used for longer and more complex routines where the call/return
overhead can be tolerated. Macros are commonly used for simpler routines or where the
speed of in-line code is required.
7.2 Macro Denition

Before a macro can be used, it rst must be dened. The macro denition species a
template that is inserted into the source program whenever the macro name is encountered.
Macro denitions can not be nested, but once a macro is dened, it can be used in other
macro denitions. Macros used this way can be nested up to nine levels deep.
The macro denition has three parts to it: 1) the macro header which species the macro
name and its parameter list, 2) the macro body which is the part that is actually inserted
into the source program, and 3) the macro terminator.
The macro header has the following form:
name MACRO <parameter list>
The name eld contains a unique symbol that it used to identify the macro. Whenever that
symbol is encountered in the source program, the Cross Assembler will automatically insert
the macro body in the source program at that point. The name must be a unique symbol
that follows all the rules of symbol formation as outlined in Chapter 2.
The MACRO eld of the macro header contains the keyword MACRO. This is used to
notify the Cross Assembler that this is the beginning of a macro denition.
The <parameter list> eld of the macro header lists anywhere from zero to 16 parameters
that are used in the macro body and are dened at assembly time. The symbols used in
the parameter list are only used by the Cross Assembler during the storing of the macro
denition. As a result, while symbols used in the parameter list must be unique symbols
44 Chap. 7: 8051 CROSS ASSEMBLER MACRO PROCESSOR
that follow all the the rules of symbol formation as outlined in Chapter 2, they can be
reissued in the parameter list of another macro denition without con ict. Parameter list
items are separated from one another by a comma. The following are examples of macro
denition headers:
MULT_BY_16 MACRO (no parameters)
DIRECT_ADD MACRO DESTINATION,SOURCE (two parameters)
The macro body contains the template that will replace the macro name in the source pro-
gram. The macro body can contain instructions, directives, conditional assembly statements
or controls. As a matter of fact, the macro body can contain any legal Cross Assembler
construct as dened in Chapters 2, 4, 5 and 6.
There are two macro denition terminators: ENDM and EXITM. Every macro denition
must have an ENDM at the end of its denition to notify the Cross Assembler that the
macro denition is complete. The EXITM terminator is an alternative ending of the macro
that is useful with conditional assembly statements. When a EXITM is encountered in a
program, all remaining statements (to the ENDM) are ignored.
The following is an example of a macro denition that multiplies the Accumulator by 16:
MULT_BY_16 MACRO
RL A ;* 2
RL A ;* 4
RL A ;* 8
RL A ;* 16
ENDM
The following is an example of a macro that adds two numbers together. This could be
used by the programmer to do direct memory to memory adds of external variables (create
a virtual instruction).
DIRECT_ADDX MACRO DESTINATION,SOURCE (two parameters)
MOV R0,#SOURCE
MOVX A,@R0
MOV R1,A
MOV R0,#DESTINATION
MOVX A,@R0
ADD A,R1
MOVX @R0,A
ENDM
A nal macro denition example shows the use of the EXITM macro terminator. If CMOS is
non-zero, the MOV and only the MOV instruction will be translated by the Cross Assembler.
IDLE MACRO
IF (CMOS)
MOV PCON,#IDL
EXITM
ENDIF
JMP $
ENDM
7.3 Special Macro Operators

There are four special macro operators that are dened below:
Chap. 7: 8051 CROSS ASSEMBLER MACRO PROCESSOR 45
%: when the PERCENT sign prefaces a symbol in the parameter list, the symbol's value
is passed to the macro's body instead of the symbol itself.
!: when the EXCLAMATION POINT precedes a character, that character is handled as a
literal and is passed to the macro body with the EXCLAMATION POINT removed.
This is useful when it is necessary to pass a delimiter to the macro body. For example,
in the following parameter list, the second parameter passed to the macro body would
be a COMMA ( , ):
GENERATE_INST 75,!,,STK_VALUE
&: when the AMPERSAND is used in the macro body, the symbols on both sides of it are
concatenated together and the AMPERSAND is removed.
;;: when double SEMI-COLONS are used in a macro denition, the comment preceded by
the double SEMI-COLONS will not be saved and thus will not appear in the listing
whenever the macro is invoked. Using the double SEMI-COLONS lowers the memory
requirement in storing the macro denitions and should be used whenever possible.
Examples of using the above special macro operators follow in the "Using Macros" section.
7.4 Using Macros

This section section discusses several situations that arise using macros and how to handle
them. In general the discussion uses examples to get the point across. First the macro
denition is listed, then the source line program that will invoke the macro and nally how
the macro was expanded by the Cross Assembler.
7.4.1 NESTING MACROS

The following shows a macro nested to a depth of three. Remember, denitions cannot be
nested. Macros must be dened before they are used in other macro denitions.
;MACRO DEFINITIONS
GET_EXT_BYTE MACRO EXT_ADDR

MOV R0,#EXT_ADDR
MOVX A,@R0
ENDM
ADD_EXT_BYTES MACRO EXT_DEST,EXT_SRC

GET_EXT_BYTE EXT_DEST
MOV R1,A
GET_EXT_BYTE EXT_SRC
ADD A,R1
ENDM
ADD_DIRECT_BYTES MACRO DESTINATION,SOURCE

IF (SMALL_MODEL)
MOV A,SOURCE
ADD A,DESTINATION
MOV DESTINATION
ELSE
ADD_EXT_BYTES DESTINATION,SOURCE
MOVX @R0,A
ENDIF
ENDM
;USAGE IN PROGRAM
ADD_DIRECT_BYTES 127,128
;TRANSLATED MACRO
30 +1 ADD_DIRECT_BYTES 127,128
31 +1 IF (SMALL_MODEL)
32 +1 MOV A,128
33 +1 ADD A,127
34 +1 MOV 127
35 +1 ELSE
36 +2 ADD_EXT_BYTES 127,128
37 +3 GET_EXT_BYTE 127
0100 787F 38 +3 MOV R0,#127
0102 E2 39 +3 MOVX A,@R0
0103 F9 40 +2 MOV R1,A
41 +3 GET_EXT_BYTE 128
0104 7880 42 +3 MOV R0,#128
0106 E2 43 +3 MOVX A,@R0
0107 29 44 +2 ADD A,R1
0108 F2 45 +1 MOVX @R0,A
46 +1 ENDIF
48
Two things should be pointed out from the above example. First, the order of the parameter
list is important. You must maintain the the order of parameters from the macro denition
if the Cross Assembler is to translate the macro correctly.
Secondly, in order to pass parameters to nested macros, simply use the same parameter
symbol in the parameter list of the denition. For example, the parameter DESTINA-
TION was passed properly to the nested macros ADD EXT BYTES and GET EXT BYTE.
This occurred because in the macro denition of ADD DIRECT BYTES, the parame-
ter DESTINATION was specied in the parameter lists of both ADD EXT BYTES and
GET EXT BYTE.
LABELS IN MACROS You have two choices for specifying labels in a macro body. A
label can either be passed to the body as a parameter or it can be generated within the
body. The following example shows both ways.
;MACRO DEFINITION
MULTIPLE_SHIFT MACRO LABEL,LABEL_SUFFIX,COUNTER,N

COUNTER SET COUNTER+1 ;INCREMENT SUFFIX FOR NEXT
USAGE
LABEL: MOV R0,#N

Chap. 7: 8051 CROSS ASSEMBLER MACRO PROCESSOR 47
SHIFT&LABEL_SUFFIX: RL A
DJNZ R0,SHIFT&LABEL_SUFFIX
ENDM
;USAGE IN PROGRAM
MULTIPLE_SHIFT LOOP_SHIFT,%COUNT,COUNT,4
;TRANSLATED MACRO
15 +1 MULTIPLE_SHIFT LOOP_SHIFT,%COUNT,COUNT,4
0006 16 +1 COUNT SET COUNT+1
17 +1
0100 7804 18 +1 LOOP_SHIFT: MOV R0,#4
0102 23 19 +1 SHIFT5: RL A
0103 D8FD 20 +1 DJNZ R0,SHIFT5
22
Points to note in the above example: 1) the double semi-colon caused the comment not
to be listed in the translated macro; 2) the percent sign caused the value of COUNT (in
this case the value 5) to be passed to the macro body instead of the symbol; and 3) the
ampersand allowed two symbols to be concatenated to form the label SHIFT5.
Chapter 8
8051 CROSS ASSEMBLER ERROR CODES
8.1 Introduction
When the Cross Assembler encounters an error in the source program, it will emit an error
message in the listing le. If the $NOPRINT control has been invoked, the error message
will be output to the screen.
There are basically two types of errors that are encountered by the Cross Assembler, trans-
lation errors and I/O errors. I/O errors are usually fatal errors. However, whenever an error
is detected, the Cross Assembler makes every eort possible to continue with the assembly.
If it is possible to recover from the error and continue assembling, the Cross Assembler will
report the error, use a default condition and continue on its way. However, when a fatal
error is encountered, it is impossible for the Cross Assembler to proceed. In this case, the
Cross Assembler reports the error and then aborts the assembly process.
Fatal I/O error messages are displayed on the screen and are of the form:
FATAL ERROR opening <filename>
where <lename> would be replaced with the le designator initially entered or read from
the source program. The cause of this error is usually obvious, typically a typographical
error or the wrong drive specication.
Another fatal I/O error message is:
FATAL ERROR writing to <type> file
where <type> would be replaced with either "listing" or "object". The cause of this error is
usually either a write protected disk or a full disk.
Translation error reports contain at least three lines. The rst line is the source line in which
the error was detected, the second line is a pointer to the character, symbol, expression or
line that caused the error. The nal line is the error message itself. There may be more
than one error message, depending on the number of errors in the source line. An example
of a source line with two errors in it follows:
0100 2323 26 START: MOV AB,@35
****----------------------------------------^---^
****ERROR #20: Illegal operand
****ERROR #20: Illegal operand
The errors are pointed out by the up-arrows ( ^). For every up- arrow there will be an
error message. Errors are ordered left to right, so the rst error message corresponds to
50 Chap. 8: 8051 CROSS ASSEMBLER ERROR CODES
the left-most up-arrow and so on. The error message includes an error number and an
description of the error. The error number can be used as an index to the more detailed
error explanations that follow in this chapter.
After the Cross Assembler has completed its translation process, it will print an assembly
complete message:
ASSEMBLY COMPLETE, nn ERRORS FOUND
If it was an error free assembly, in place of the "nn" above the word "NO" will be output.
However, if errors were encountered during the assembly process, the "nn" will be replaced
with the number of errors that were found (up to a maximum of 50). In this case, an error
summary will follow in the listing le with all the errors that were reported during the
assembly. An error summary looks like the following:
ERROR SUMMARY:
Line #26, ERROR #20: Illegal operand
Line #26, ERROR #20: Illegal operand
The same error message that occurred after the source line appears again prefaced by the
source line number to aid in tracking down the error in the source listing.
8.2 Explanation of Error Messages

8.2.1 ERROR #1: Illegal character
This error occurs when the Cross Assembler encounters a character that is not part of its
legal character set. The Cross Assembler character set can be found in Appendix D.
8.2.2 ERROR #2: Undened symbol

This error occurs when the Cross Assembler tries to use a symbol that hasn't been dened.
The two most common reasons for this error are typographical errors and forward references.
8.2.3 ERROR #3: Duplicate symbol

This error occurs when a previously dened symbol or a reserved symbol is attempted to
be dened again. Refer to Appendix C for the reserved words. Also inspect the symbol in
the symbol table listing. If the symbol doesn't appear there, you are using a reserved word.
If the symbol does appear, its original denition will be listed.
8.2.4 ERROR #4: Illegal digit for radix

A digit was encountered that is not part of the legal digits for the radix specied. Chapter
2 lists the legal digits for each radix available. Often this error occurs because a symbol
was started with a number instead of a letter, question mark, or underscore.
Chap. 8: 8051 CROSS ASSEMBLER ERROR CODES 51
8.2.5 ERROR #5: Number too large

The number specied, or the returned value of the expression, exceeds 16-bit precision. The
largest value allowed is 65,535.
8.2.6 ERROR #6: Missing END directive

The source program must end with one and only one END directive. The END is placed
after all the assembly line statements.
8.2.7 ERROR #7: Illegal opcode/directive after label

The symbol after a label is not an opcode nor a directive that allows labels. The only
thing permitted on a line after a label is an instruction, the DS, DB or DW directives, or
a comment. If none of these are found, this error will be reported.
8.2.8 ERROR #8: Illegal assembly line

The assembly line doesn't begin with a symbol, label, instruction mnemonic, control, direc-
tive, comment or null line. No attempt is made to translate such a line.
8.2.9 ERROR #9: Text beyond END directive

The END directive must be the last line of the source program. Any text beyond the END
line will cause this error. Any such text is ignore. Text here is dened as any printable
ASCII characters.
8.2.10 ERROR #10: Illegal or missing expression

A number, symbol or arithmetic expression was expected, but it was either found to be
missing or the Cross Assembler was unable to evaluate it properly.
8.2.11 ERROR #11: Illegal or missing expression operator

An arithmetic operator was expected but it is either missing or it is not one of the legal
operators specied in Chapter 2.
8.2.12 ERROR #12: Unbalanced parentheses

In evaluating an expression, the parentheses in the expression were found not to balance.
8.2.13 ERROR #13: Illegal or missing expression value

In evaluating an expression, the Cross Assembler expected to nd either a number or a
symbol, but it was either missing or illegal.
8.2.14 ERROR #14: Illegal literal expression

This error occurs when a null ASCII literal string is found. A null ASCII literal is nothing
more than two apostrophes together ( " ) and is illegal.
8.2.15 ERROR #15: Expression stack over ow

The expression stack has a depth of 32 values. The expression being evaluated exceeds this
depth. This is a very rare error. However, if you ever get it, divide the expression into two
or more expressions using the EQU directive.
8.2.16 ERROR #16: Division by zero

The expression being evaluated includes an attempt to divide by zero.
8.2.17 ERROR #17: Illegal bit designator

A bit designator address was specied in the source program and it points to an illegal
bit address. A bit designator contains a byte address, followed by a PERIOD, followed by
the bit index into the byte address (e.g., ACC.7) as discussed in Chapter 2. This error
can occur for one of two reasons. First, if the number or a symbol that is used to specify
the byte address part of the bit designator is not a legal bit addressable address, ERROR
#17 will occur. Second, if the bit index into the byte address exceeds the number 7, again
ERROR #17 will be output.
8.2.18 ERROR #18: Target address exceeds relative address range

A Program Counter relative jump instruction (e.g., SJMP, JZ, JNC, etc.) was decoded
with the target address of the jump exceeding the maximum possible forward jump of 127
bytes or the maximum possible backward jump of 128 bytes.
8.2.19 ERROR #20: Illegal operand

The operand specied is not a legal operand for the instruction. Review the legal operands
allowed for the instruction.
8.2.20 ERROR #21: Illegal indirect register

R0 and R1 are the only primary legal indirect register. This error occurs when the indirect
addressing mode designator (@) is not followed by either R0, R1 or symbols that were
dened to be equivalent to either R0 or R1. This error can also occur in the MOVC
A,@A+DPTR, MOVC A,@A+PC, MOVX A,@DPTR, MOVX @DPTR,A and the JMP
@A+DPTR instructions if the operands after the indirect addressing mode designator ( @
) aren't specied properly.
8.2.21 ERROR #22: Missing operand delimiter

A COMMA operand delimiter is missing from the operand elds of the instruction.
8.2.22 ERROR #23: Illegal or missing directive

This error occurs when the Cross Assembler cannot nd a legal directive. The most common
cause of this error is due to leaving the COLON o a label. As a result, the following opcode
mnemonic is attempted to be decoded as a directive.
8.2.23 ERROR #24: Attempting to EQUate a previously SET symbol

Once a symbol is dened using the SET directive, it cannot be later redened using the
EQU directive.
8.2.24 ERROR #25: Attempting to SET a previously EQUated symbol

Once a symbol is dened using the EQU directive, it cannot be redened. If you want the
symbol to be redeneable, use the SET directive.
8.2.25 ERROR #26: Illegal SET/EQU expression

The expression following the SET or EQU directive is illegal. This typically occurs when
an attempt is made to dene a symbol to be equivalent to an implicit register other than
A, R0, R1, R2, R3, R4, R5, R6 or R7.
8.2.26 ERROR #27: Illegal expression with forward reference

This error occurs when an expression contains a symbol that hasn't been dened yet. Move
the symbol denition earlier in the source le.
8.2.27 ERROR #28: Address exceeds segment range

The address specied exceeds 255 and you are in the DSEG, BSEG, or ISEG.
8.2.28 ERROR #29: Expecting an EOL or COMMENT

The Cross Assembler has completed processing a legal assembly language line and expected
the line to be terminated with either a COMMENT or a carriage return/line feed pair.
8.2.29 ERROR #30: Illegal directive with current active segment

The specied directive is not legal in the active segment. This can happen by trying to use
the DBIT directive in other than the BSEG, or using the DS directive in the BSEG.
8.2.30 ERROR #31: Only two character string allowed

This error occurs using the DW directive. The maximum ASCII literal allowed in a DW
specication is a two character string.
8.2.31 ERROR #32: Byte denition exceeds 255

This error occurs using the DB directive. The value specied in the DB specication cannot
t into a byte.
8.2.32 ERROR #33: Premature end of string

An ASCII literal string was not terminated properly with an apostrophe.
8.2.33 ERROR #34: Illegal register bank number

This error occurs when the number specied with the USING directive exceed 3. Legal
register bank numbers are: 0, 1, 2, 3.
8.2.34 ERROR #35: Include le nesting exceeds 8

The maximum number of nested include les is eight. You will get this error if you exceed
this limit.
8.2.35 ERROR #36: Illegal or missing argument

This error occurs when the syntax of a Cross Assembler control requires an argument and
it was either incorrectly specied or is missing all together.
8.2.36 ERROR #37: Illegal control statement

The Cross Assembler does not recognize the specied control. The legal controls are detailed
in Chapter 6.
8.2.37 ERROR #38: Unable to open le

The Cross Assembler is unable to open the le as specied. This is a fatal error which will
abort the assembly process.
8.2.38 ERROR #39: Illegal le specication

The le specication is not a legal le designator. Refer to your DOS manual for a descrip-
tion of legal le designators. This is a fatal error which will abort the assembly process.
8.2.39 ERROR #40: Program synchronization error

This error occurs when the Cross Assembler is generating the object hex le and nds that
the code segment location counter is not advancing properly. There are two cases where
this can happen. First, if the source program uses ORG directives and they are not placed
in ascending order. Second, if a generic CALL or JMP is made to a forward reference
that is actually dened later in the program to be a backward reference. For example, the
following code sequence will cause this error due to the second reason:
BACK_REF: NOP
CALL FORWARD_REF
FORWARD_REF EQU BACK_REF
During the rst pass, the generic CALL will be replaced with a 3-byte LCALL instruction.
During the second pass, the generic CALL will be replaced with a 2-byte ACALL instruction.
To prevent this kind of problem, use the generic CALLs and JMPs with labeled targets,
not EQU or SET dened symbols.
8.2.40 ERROR #41: Insucient memory

This error occurs when there isn't enough memory to hold all the symbols that have been
generated by the source program. If you have 96 Kbytes or more of RAM this will be a
very rare error. Only a massive source program or numerous large macros could potentially
cause this error. However, if this error does occur, your best bet is to either buy more
memory or to break up your program into smaller pieces and share common symbols with
a common $INCLUDE le.
8.2.41 ERROR #42: More errors detected, not listed

The internal error buer can hold 50 errors. If more than 50 errors occur, only the rst 50
will be reported.
8.2.42 ERROR #43: ENDIF without IF

The terminator of a conditional assembly block (ENDIF) was recognized without seeing a
matching IF.
8.2.43 ERROR #44: Missing ENDIF

A conditional assembly block was begun with an IF statement, but no matching ENDIF
was detected.
8.2.44 ERROR #45: Illegal or missing macro name

The MACRO keyword was recognized, but the symbol that is supposed to precede the
MACRO keyword was missing, an illegal symbol or a duplicate symbol.
8.2.45 ERROR #46: Macro nesting too deep

Macros can be nested to a depth of 9 levels. Exceeding this limit will cause this error.
8.2.46 ERROR #47: Number of parameters doesn't match denition

In attempting to use a macro, the number of parameters in the parameter list does not
equal the number of parameters specied in the macro denition. They must match.
8.2.47 ERROR #48: Illegal parameter specication

This error typically occurs when a previously dened symbol is used in the parameter list
of the macro denition.
8.2.48 ERROR #49: Too many parameters

The maximum number of parameters in a macro parameter list is sixteen. This error occurs
when you exceed that limit.
8.2.49 ERROR #50: Line exceeds 255 characters

The maximum length of a source line is 255 characters. If a carriage return/line feed pair
is not detected in the rst 256 characters of a line, this error is reported and the line is
truncated at 255 characters.
Appendix A
SAMPLE PROGRAM AND LISTING
A.1 Source File

;
; 8-bit by 8-bit signed multiply--byte signed multiply
;
; This routine takes the signed byte in multiplicand and
; multiplies it by the signed byte in multiplier and places
; the signed 16-bit product in product_high and product_low.
;
; This routine assumes 2s complement representation of signed
; numbers. The maximum numbers possible are then -128 and
; +127. Multiplying the possible maximum numbers together
; easily fits into a 16-bit product, so no overflow test is
; done on the answer.
;
; Registers altered by routine: A, B, PSW.
;
;
; Primary controls
$MOD51
$TITLE(BYTE SIGNED MULTIPLY)
$DATE(JUL-30-84)
$PAGEWIDTH(132)
$OBJECT(B:BMULB.OBJ)
;
;
; Variable declarations
;
sign_flag BIT 0F0H ;sign of product
multiplier DATA 030H ;8-bit multiplier
multiplicand DATA 031H ;8-bit multiplicand
product_high DATA 032H ;high byte of 16-bit answer
product_low DATA 033H ;low byte of answer
;
;
;
ORG 100H ;arbitrary start
;
byte_signed_multiply:
CLR sign_flag ;reset sign
MOV A,multiplier ;put multiplier in accumulator
JNB ACC.7,positive ;test sign bit of multiplier
CPL A ;negative--complement and
INC A ;add 1 to convert to positive
58 Chap. A: SAMPLE PROGRAM AND LISTING
SETB sign_flag ;and set sign flag

;
positive: MOV B,multiplicand ;put multiplicand in B register
JNB B.7,multiply ;test sign bit of multiplicand
XRL B,#0FFh ;negative--complement and
INC B ;add 1 to convert to positive
CPL sign_flag ;complement sign flag
;
multiply: MUL AB ;do unsigned multiplication
;
sign_test: JNB sign_flag,byte_signed_exit ;if positive,done
XRL B,#0FFh ;else have to complement both
CPL A ;bytes of the product and inc
ADD A,#1 ;add here because inc doesn't
JNC byte_signed_exit ;set the carry flag
INC B ;if add overflowed A, inc the
;high byte
byte_signed_exit:
MOV product_high,B ;save the answer
MOV product_low,A
;
RET ;and return
END
A.2 Source File Listing

BMULB BYTE SIGNED MULTIPLY
1 ;
2 ; 8-bit by 8-bit signed multiply--byte signed multiply
3 ;
4 ; This routine takes the signed byte in multiplicand and
5 ; multiplies it by the signed byte in multiplier and places
6 ; the signed 16-bit product in product_high and product_low.
7 ;
8 ; This routine assumes 2s complement representation of signed
9 ; numbers. The maximum numbers possible is then -128 and +127.
10 ; Multiplying the possible maximum numbers together easily fits
11 ; in a 16-bit product, so no overflow test is done on the answer.
12 ;
13 ; Registers altered by routine: A, B, PSW.
14 ;
15 ;
16 ; Primary controls
17 $MOD51
18 $TITLE(BYTE SIGNED MULTIPLY)
19 $DATE(JUL-30-84)
20 $PAGEWIDTH(132)
21 $OBJECT(B:BMULB.OBJ)
22 ;
23 ;
24 ; Variable declarations
25 ;
00F0 26 sign_flag BIT 0F0H ;sign of product
0030 27 multiplier DATA 030H ;8-bit multiplier
Chap. A: SAMPLE PROGRAM AND LISTING 59
0031 28 multiplicand DATA 031H ;8-bit multiplicand

0032 29 product_high DATA 032H ;high byte of 16-bit answer
0033 30 product_low DATA 033H ;low byte of answer
31 ;
32 ;
33 ;
0100 34 ORG 100H ;arbitrary start
35 ;
0100 36 byte_signed_multiply:
0100 C2F0 37 CLR sign_flag ;reset sign
0102 E530 38 MOV A,multiplier ;put multiplier in accumulator
0104 30E704 39 JNB ACC.7,positive ;test sign bit of multiplier
0107 F4 40 CPL A ;negative--complement and
0108 04 41 INC A ;add 1 to convert to positive
0109 D2F0 42 SETB sign_flag ;and set sign flag
43 ;
010B 8531F0 44 positive: MOV B,multiplicand ;put multiplicand in B register
010E 30F707 45 JNB B.7,multiply ;test sign bit of multiplicand
0111 63F0FF 46 XRL B,#0FFh ;negative--complement and
0114 05F0 47 INC B ;add 1 to convert to positive
0116 B2F0 48 CPL sign_flag ;complement sign flag
49 ;
0118 A4 50 multiply: MUL AB ;do unsigned multiplication
51 ;
0119 30F00A 52 sign_test: JNB sign_flag,byte_signed_exit ;if positive,done
011C 63F0FF 53 XRL B,#0FFh ;else have to complement both
011F F4 54 CPL A ;bytes of the product and inc
0120 2401 55 ADD A,#1 ;need add here because inc
0122 5002 56 JNC byte_signed_exit ; doesn't set the carry flag
0124 05F0 57 INC B ;if add overflowed A,
58 ; inc the high byte
0126 59 byte_signed_exit:
0126 85F032 60 MOV product_high,B ;save the answer
0129 F533 61 MOV product_low,A
62 ;
012B 22 63 RET ;and return
64 END
ASSEMBLY COMPLETE, 0 ERRORS FOUND

ACC D ADDR 00E0H PREDEFINED
B D ADDR 00F0H PREDEFINED
BYTE_SIGNED_EXIT C ADDR 0126H
BYTE_SIGNED_MULTIPLY C ADDR 0100H NOT USED
MULTIPLICAND D ADDR 0031H
MULTIPLIER D ADDR 0030H
MULTIPLY C ADDR 0118H
POSITIVE C ADDR 010BH
PRODUCT_HIGH D ADDR 0032H
PRODUCT_LOW D ADDR 0033H
SIGN_FLAG B ADDR 00F0H
SIGN_TEST C ADDR 0119H NOT USED
60 Chap. A: SAMPLE PROGRAM AND LISTING
Appendix B
PRE-DEFINED BYTE AND BIT ADDRESSES
The following tables detail the pre-dened byte and bit addresses for the 8051/8031 micro-
controllers supported by the MetaLink family of emulators. Proliferation parts are delimited
from the standard MCS-51 denitions by asterisk ("*") boxes.
This list covers these microcontrollers:
8044 8031 8032 8051 8052 8053 80C154 80C321
8344 80C31 80C32 8751 8752 8753 83C154 80C521
8744 80C51 80C52 85C154 87C521
87C51
80C321 80C51FA(80C252) 80C452 80C152JA/JB/JC/JD 80C851

80C541 83C51FA(83C252) 83C452 83C152JA/JC 83C851
87C541 87C51FA(87C252) 87C452
80C451 80C652 80C552 83C751 83C752 80512 80515 80C515 80C517

83C451 83C652 83C552 87C751 87C752 80532 80535 80C535 80C537
87C451 87C652 87C552
B.1 Pre-dened Byte Addresses

P0 DATA 080H ;PORT 0
SP DATA 081H ;STACK POINTER
DPL DATA 082H ;DATA POINTER - LOW BYTE
DPH DATA 083H ;DATA POINTER - HIGH BYTE
************************************************************************
for the 80C321/80C521
DPL1 DATA 084H ;DATA POINTER LOW 1
DPH1 DATA 085H ;DATA POINTER HIGH 1
DPS DATA 086H ;DATA POINTER SELECTION
************************************************************************
************************************************************************
for the 83C152/80C152
GMOD DATA 084H ;GSC MODE
TFIFO DATA 085H ;GSC TRANSMIT BUFFER
************************************************************************
************************************************************************
for the 80C517/80C537
WDTREL DATA 086H ;WATCHDOG TIMER RELOAD REG
************************************************************************
PCON DATA 087H ;POWER CONTROL

62 Chap. B: PRE-DEFINED BYTE AND BIT ADDRESSES
TCON DATA 088H ;TIMER CONTROL

TMOD DATA 089H ;TIMER MODE
TL0 DATA 08AH ;TIMER 0 - LOW BYTE
TL1 DATA 08BH ;TIMER 1 - LOW BYTE
************************************************************************
for the 83C751/83C752
RTL DATA 08BH ;TIMER 0 - LOW BYTE RELOAD
************************************************************************
TH0 DATA 08CH ;TIMER 0 - HIGH BYTE

TH1 DATA 08DH ;TIMER 1 - HIGH BYTE
************************************************************************
for the 83C751/83C752
RTH DATA 08DH ;TIMER 0 - HIGH BYTE RELOAD
************************************************************************
************************************************************************
for the 83C752
PWM DATA 08EH ;PULSE WIDTH MODULATION
************************************************************************
************************************************************************
for the 83C152/80C152
DCON0 DATA 092H ;DMA CONTROL 0
BAUD DATA 094H ;GSC BAUD RATE
ADR0 DATA 095H ;GSC MATCH ADDRESS 0
************************************************************************
************************************************************************
for the 80C452/83C452
************************************************************************
************************************************************************
for the 80C517/80C537
DPSEL DATA 092H ;DATA POINTER SELECT REGISTER
************************************************************************
SCON DATA 098H ;SERIAL PORT CONTROL

SBUF DATA 099H ;SERIAL PORT BUFFER
************************************************************************
for the 83C751/83C752
I2CON DATA 098H ;I2C CONTROL
I2DAT DATA 099H ;I2C DATA
************************************************************************
************************************************************************
for the 80C517/80C537
IEN2 DATA 09AH ;INTERRUPT ENABLE REGISTER 2
S1CON DATA 09BH ;SERIAL PORT CONTROL 1
S1BUF DATA 09CH ;SERIAL PORT BUFFER 1
S1REL DATA 09DH ;SERIAL RELOAD REG 1
************************************************************************
Chap. B: PRE-DEFINED BYTE AND BIT ADDRESSES 63
P2 DATA 0A0H ;PORT 2

IE DATA 0A8H ;INTERRUPT ENABLE
************************************************************************
for the 80C51FA/83C51FA(83C252/80C252)
SADDR DATA 0A9H ;SLAVE INDIVIDUAL ADDRESS
************************************************************************
************************************************************************
for the 80515/80535 and 80C517/80C537
IP0 DATA 0A9H ;INTERRUPT PRIORITY REGISTER 0
************************************************************************
************************************************************************
for the 80C321/80C521
WDS DATA 0A9H ;WATCHDOG SELECTION
WDK DATA 0AAH ;WATCHDOG KEY
************************************************************************
************************************************************************
for the 83C152/80C152
P6 DATA 0A1H ;PORT 6
SARL0 DATA 0A2H ;DMA SOURCE ADDR. 0 (LOW)
SARH0 DATA 0A3H ;DMA SOURCE ADDR. 0 (HIGH)
IFS DATA 0A4H ;GSC INTERFRAME SPACING
ADR1 DATA 0A5H ;GSC MATCH ADDRESS 1
************************************************************************
************************************************************************
for the 80C452/83C452
SARL0 DATA 0A2H ;DMA SOURCE ADDR. 0 (LOW)
SARH0 DATA 0A3H ;DMA SOURCE ADDR. 0 (HIGH)
************************************************************************
************************************************************************
for the 80C552/83C552
CML0 DATA 0A9H ;COMPARE 0 - LOW BYTE
CML1 DATA 0AAH ;COMPARE 1 - LOW BYTE
CML2 DATA 0ABH ;COMPARE 2 - LOW BYTE
CTL0 DATA 0ACH ;CAPTURE 0 - LOW BYTE
CTL1 DATA 0ADH ;CAPTURE 1 - LOW BYTE
CTL2 DATA 0AEH ;CAPTURE 2 - LOW BYTE
CTL3 DATA 0AFH ;CAPTURE 3 - LOW BYTE
************************************************************************
P3 DATA 0B0H ;PORT 3
************************************************************************
for the 83C152/80C152
SARL1 DATA 0B2H ;DMA SOURCE ADDR. 1 (LOW)
SARH1 DATA 0B3H ;DMA SOURCE ADDR. 1 (HIGH)
SLOTTM DATA 0B4H ;GSC SLOT TIME
ADR2 DATA 0B5H ;GSC MATCH ADDRESS 2
************************************************************************
************************************************************************
for the 80C452/83C452
SARL1 DATA 0B2H ;DMA SOURCE ADDR. 1 (LOW)
SARH1 DATA 0B3H ;DMA SOURCE ADDR. 1 (HIGH)
************************************************************************
IP DATA 0B8H ;INTERRUPT PRIORITY

************************************************************************
for the 80C51FA/83C51FA(83C252/80C252)
SADEN DATA 0B9H ;SLAVE ADDRESS ENABLE
************************************************************************
************************************************************************
for the 80515/80535 and 80C517/80C537
IP1 DATA 0B9H ;INTERRUPT PRIORITY REGISTER 1
IRCON DATA 0C0H ;INTERRUPT REQUEST CONTROL
CCEN DATA 0C1H ;COMPARE/CAPTURE ENABLE
CCL1 DATA 0C2H ;COMPARE/CAPTURE REGISTER 1 - LOW BYTE
CCH1 DATA 0C3H ;COMPARE/CAPTURE REGISTER 1 - HIGH BYTE
T2CON DATA 0C8H ;TIMER 2 CONTROL
CRCL DATA 0CAH ;COMPARE/RELOAD/CAPTURE - LOW BYTE
CRCH DATA 0CBH ;COMPARE/RELOAD/CAPTURE - HIGH BYTE
TL2 DATA 0CCH ;TIMER 2 - LOW BYTE
TH2 DATA 0CDH ;TIMER 2 - HIGH BYTE
************************************************************************
************************************************************************
for the 80C517/80C537
CC4EN DATA 0C9H ;COMPARE/CAPTURE 4 ENABLE
CCL4 DATA 0CEH ;COMPARE/CAPTURE REGISTER 4 - LOW BYTE
CCH4 DATA 0CFH ;COMPARE/CAPTURE REGISTER 4 - HIGH BYTE
************************************************************************
************************************************************************
for the RUPI-44
STS DATA 0C8H ;SIU STATUS REGISTER
SMD DATA 0C9H ;SERIAL MODE
RCB DATA 0CAH ;RECEIVE CONTROL BYTE
RBL DATA 0CBH ;RECEIVE BUFFER LENGTH
RBS DATA 0CCH ;RECEIVE BUFFER START
RFL DATA 0CDH ;RECEIVE FIELD LENGTH
STAD DATA 0CEH ;STATION ADDRESS
DMA_CNT DATA 0CFH ;DMA COUNT
************************************************************************
************************************************************************
for the 8052/8032, 80C51FA/83C51FA(83C252/80C252), 80C154/83C154
T2CON DATA 0C8H ;TIMER 2 CONTROL
************************************************************************
************************************************************************
for the 80C51FA/83C51FA(83C252/80C252)
T2MOD DATA 0C9H ;TIMER 2 MODE CONTROL
************************************************************************
************************************************************************
for the 8052/8032, 80C51FA/83C51FA(83C252/80C252), 80C154/83C154
RCAP2L DATA 0CAH ;TIMER 2 CAPTURE REGISTER, LOW BYTE
RCAP2H DATA 0CBH ;TIMER 2 CAPTURE REGISTER, HIGH BYTE
TL2 DATA 0CCH ;TIMER 2 - LOW BYTE
TH2 DATA 0CDH ;TIMER 2 - HIGH BYTE
************************************************************************
************************************************************************
for the 83C152/80C152
P4 DATA 0C0H ;PORT 4
DARL0 DATA 0C2H ;DMA DESTINATION ADDR. 0 (LOW)

DARH0 DATA 0C3H ;DMA DESTINATION ADDR. 0 (HIGH)
BKOFF DATA 0C4H ;GSC BACKOFF TIMER
ADR3 DATA 0C5H ;GSC MATCH ADDRESS 3
IEN1 DATA 0C8H ;INTERRUPT ENABLE REGISTER 1
************************************************************************
************************************************************************
for the 80C452/83C452
DARL0 DATA 0C2H ;DMA DESTINATION ADDR. 0 (LOW)
DARH0 DATA 0C3H ;DMA DESTINATION ADDR. 0 (HIGH)
************************************************************************
************************************************************************
for the 80C451/83C451
************************************************************************
************************************************************************
for the 80512/80532
IRCON DATA 0C0H ;INTERRUPT REQUEST CONTROL
************************************************************************
************************************************************************
for the 80C552/83C552
ADCON DATA 0C5H ;A/D CONVERTER CONTROL
ADCH DATA 0C6H ;A/D CONVERTER HIGH BYTE
TM2IR DATA 0C8H ;T2 INTERRUPT FLAGS
CMH0 DATA 0C9H ;COMPARE 0 - HIGH BYTE
CMH1 DATA 0CAH ;COMPARE 1 - HIGH BYTE
CMH2 DATA 0CBH ;COMPARE 2 - HIGH BYTE
CTH0 DATA 0CCH ;CAPTURE 0 - HIGH BYTE
CTH1 DATA 0CDH ;CAPTURE 1 - HIGH BYTE
CTH2 DATA 0CEH ;CAPTURE 2 - HIGH BYTE
CTH3 DATA 0CFH ;CAPTURE 3 - HIGH BYTE
************************************************************************
PSW DATA 0D0H ;PROGRAM STATUS WORD
************************************************************************
for the RUPI-44
NSNR DATA 0D8H ;SEND COUNT/RECEIVE COUNT
SIUST DATA 0D9H ;SIU STATE COUNTER
TCB DATA 0DAH ;TRANSMIT CONTROL BYTE
TBL DATA 0DBH ;TRANSMIT BUFFER LENGTH
TBS DATA 0DCH ;TRANSMIT BUFFER START
FIFO0 DATA 0DDH ;THREE BYTE FIFO
FIFO1 DATA 0DEH
FIFO2 DATA 0DFH
************************************************************************
************************************************************************
for the 80C51FA/83C51FA(83C252/80C252)
CCON DATA 0D8H ;CONTROL COUNTER
CMOD DATA 0D9H ;COUNTER MODE
CCAPM0 DATA 0DAH ;COMPARE/CAPTURE MODE FOR PCA MODULE 0
CCAPM1 DATA 0DBH ;COMPARE/CAPTURE MODE FOR PCA MODULE 1
CCAPM2 DATA 0DCH ;COMPARE/CAPTURE MODE FOR PCA MODULE 2
CCAPM3 DATA 0DDH ;COMPARE/CAPTURE MODE FOR PCA MODULE 3

CCAPM4 DATA 0DEH ;COMPARE/CAPTURE MODE FOR PCA MODULE 4
************************************************************************
************************************************************************
for the 80515/80535
ADCON DATA 0D8H ;A/D CONVERTER CONTROL
ADDAT DATA 0D9H ;A/D CONVERTER DATA
DAPR DATA 0DAH ;D/A CONVERTER PROGRAM REGISTER
************************************************************************
************************************************************************
for the 83C152/80C152
DARL1 DATA 0D2H ;DMA DESTINATION ADDR. 1 (LOW)
DARH1 DATA 0D3H ;DMA DESTINATION ADDR. 1 (HIGH)
TCDCNT DATA 0D4H ;GSC TRANSMIT COLLISION COUNTER
AMSK0 DATA 0D5H ;GSC ADDRESS MASK 0
TSTAT DATA 0D8H ;TRANSMIT STATUS (DMA & GSC)
************************************************************************
************************************************************************
for the 80C452/83C452
DARL1 DATA 0D2H ;DMA DESTINATION ADDR. 1 (LOW)
DARH1 DATA 0D3H ;DMA DESTINATION ADDR. 1 (HIGH)
************************************************************************
************************************************************************
for the 80C451/83C451
P6 DATA 0D8H ;PORT 6
************************************************************************
************************************************************************
for the 80512/80532
ADCON DATA 0D8H ;A/D CONVERTER CONTROL
P6 DATA 0DBH ;PORT 6
************************************************************************
************************************************************************
for the 83C751/83C752
I2CFG DATA 0D8H ;I2C CONFIGURATION
************************************************************************
************************************************************************
for the 80C552/83C552 and 80C652/83C652
S1CON DATA 0D8H ;SERIAL 1 CONTROL
S1STA DATA 0D9H ;SERIAL 1 STATUS
S1DAT DATA 0DAH ;SERIAL 1 DATA
S1ADR DATA 0DBH ;SERIAL 1 SLAVE ADDRESS
************************************************************************
************************************************************************
for the 80C517/80C537
CML0 DATA 0D2H ;COMPARE REGISTER 0 - LOW BYTE
CMH0 DATA 0D3H ;COMPARE REGISTER 0 - HIGH BYTE
ADCON0 DATA 0D8H ;A/D CONVERTER CONTROL 0
P7 DATA 0DBH ;PORT 7
ADCON1 DATA 0DCH ;A/D CONVERTER CONTROL 1
P8 DATA 0DDH ;PORT 8

CTRELL DATA 0DEH ;COM TIMER REL REG - LOW BYTE
CTRELH DATA 0DFH ;COM TIMER REL REG - HIGH BYTE
************************************************************************
ACC DATA 0E0H ;ACCUMULATOR
************************************************************************
for the 83C152/80C152
BCRL0 DATA 0E2H ;DMA BYTE COUNT 0 (LOW)
BCRH0 DATA 0E3H ;DMA BYTE COUNT 0 (HIGH)
PRBS DATA 0E4H ;GSC PSEUDO-RANDOM SEQUENCE
AMSK1 DATA 0E5H ;GSC ADDRESS MASK 1
RSTAT DATA 0E8H ;RECEIVE STATUS (DMA & GSC)
************************************************************************
************************************************************************
for the 80C452/83C452
BCRL0 DATA 0E2H ;DMA BYTE COUNT 0 (LOW)
BCRH0 DATA 0E3H ;DMA BYTE COUNT 0 (HIGH)
HSTAT DATA 0E6H ;HOST STATUS
HCON DATA 0E7H ;HOST CONTROL
SLCON DATA 0E8H ;SLAVE CONTROL
SSTAT DATA 0E9H ;SLAVE STATUS
IWPR DATA 0EAH ;INPUT WRITE POINTER
IRPR DATA 0EBH ;INPUT READ POINTER
CBP DATA 0ECH ;CHANNEL BOUNDARY POINTER
FIN DATA 0EEH ;FIFO IN
CIN DATA 0EFH ;COMMAND IN
************************************************************************
************************************************************************
for the 80515/80535
P4 DATA 0E8H ;PORT 4
************************************************************************
************************************************************************
for the 80C451/83C451
CSR DATA 0E8H ;CONTROL STATUS
************************************************************************
************************************************************************
for the 80512/80532
************************************************************************
************************************************************************
for the 80C552/83C552
IEN1 DATA 0E8H ;INTERRUPT ENABLE REGISTER 1
TM2CON DATA 0EAH ;T2 COUNTER CONTROL
CTCON DATA 0EBH ;CAPTURE CONTROL
TML2 DATA 0ECH ;TIMER 2 - LOW BYTE
TMH2 DATA 0EDH ;TIMER 2 - HIGH BYTE
STE DATA 0EEH ;SET ENABLE
RTE DATA 0EFH ;RESET/TOGGLE ENABLE
************************************************************************
************************************************************************
for the 80C51FA/83C51FA(83C252/80C252)
CL DATA 0E9H ;CAPTURE BYTE LOW
CCAP0L DATA 0EAH ;COMPARE/CAPTURE 0 LOW BYTE
CCAP1L DATA 0EBH ;COMPARE/CAPTURE 1 LOW BYTE
CCAP2L DATA 0ECH ;COMPARE/CAPTURE 2 LOW BYTE
CCAP3L DATA 0EDH ;COMPARE/CAPTURE 3 LOW BYTE

CCAP4L DATA 0EEH ;COMPARE/CAPTURE 4 LOW BYTE
************************************************************************
************************************************************************
for the 80C517/80C537
CTCON DATA 0E1H ;COM TIMER CONTROL REG
CML3 DATA 0E2H ;COMPARE REGISTER 3 - LOW BYTE
CMH3 DATA 0E3H ;COMPARE REGISTER 3 - HIGH BYTE
MD0 DATA 0E9H ;MUL/DIV REG 0
MD1 DATA 0EAH ;MUL/DIV REG 1
MD2 DATA 0EBH ;MUL/DIV REG 2
MD3 DATA 0ECH ;MUL/DIV REG 3
MD4 DATA 0EDH ;MUL/DIV REG 4
MD5 DATA 0EEH ;MUL/DIV REG 5
ARCON DATA 0EFH ;ARITHMETIC CONTROL REG
************************************************************************
B DATA 0F0H ;MULTIPLICATION REGISTER
************************************************************************
for the 80C154/83C154
IOCON DATA 0F8H ;I/O CONTROL REGISTER
************************************************************************
************************************************************************
for the 83C152/80C152
BCRL1 DATA 0F2H ;DMA BYTE COUNT 1 (LOW)
BCRH1 DATA 0F3H ;DMA BYTE COUNT 1 (HIGH)
RFIFO DATA 0F4H ;GSC RECEIVE BUFFER
MYSLOT DATA 0F5H ;GSC SLOT ADDRESS
IPN1 DATA 0F8H ;INTERRUPT PRIORITY REGISTER 1
************************************************************************
************************************************************************
for the 83C851/80C851
EADRL DATA 0F2H ;EEPROM Address Register - Low Byte
EADRH DATA 0F3H ;EEPROM Address Register - High Byte
EDAT DATA 0F4H ;EEPROM Data Register
ETIM DATA 0F5H ;EEPROM Timer Register
ECNTRL DATA 0F6H ;EEPROM Control Register
************************************************************************
************************************************************************
for the 80C452/83C452
BCRL1 DATA 0F2H ;DMA BYTE COUNT 1 (LOW)
BCRH1 DATA 0F3H ;DMA BYTE COUNT 1 (HIGH)
ITHR DATA 0F6H ;INPUT FIFO THRESHOLD
OTHR DATA 0F7H ;OUTPUT FIFO THRESHOLD
IEP DATA 0F8H ;INTERRUPT PRIORITY
MODE DATA 0F9H ;MODE
ORPR DATA 0FAH ;OUTPUT READ POINTER
OWPR DATA 0FBH ;OUTPUT WRITE POINTER
IMIN DATA 0FCH ;IMMEDIATE COMMAND IN
IMOUT DATA 0FDH ;IMMEDIATE COMMAND OUT
FOUT DATA 0FEH ;FIFO OUT
COUT DATA 0FFH ;COMMAND OUT

************************************************************************
************************************************************************
for the 80515/80535
P5 DATA 0F8H ;PORT 5
************************************************************************
************************************************************************
for the 80512/80532
************************************************************************
************************************************************************
for the 83C751/83C752
I2STA DATA 0F8H ;I2C STATUS
************************************************************************
************************************************************************
for the 80C552/83C552
IP1 DATA 0F8H ;INTERRUPT PRIORITY REGISTER 1
PWM0 DATA 0FCH ;PULSE WIDTH REGISTER 0
PWM1 DATA 0FDH ;PULSE WIDTH REGISTER 1
PWMP DATA 0FEH ;PRESCALER FREQUENCY CONTROL
T3 DATA 0FFH ;T3 - WATCHDOG TIMER
************************************************************************
************************************************************************
for the 80C517/80C537
CMEN DATA 0F6H ;COMPARE ENABLE
CML6 DATA 0F2H ;COMPARE REGISTER 6 - LOW BYTE
CMH6 DATA 0F3H ;COMPARE REGISTER 6 - HIGH BYTE
CML7 DATA 0F4H ;COMPARE REGISTER 7 - LOW BYTE
CMH7 DATA 0F5H ;COMPARE REGISTER 7 - HIGH BYTE
CMSEL DATA 0F7H ;COMPARE INPUT REGISTER
P6 DATA 0FAH ;PORT 6
************************************************************************
************************************************************************
for the 80C51FA/83C51FA(83C252/80C252)
CH DATA 0F9H ;CAPTURE HIGH BYTE
CCAP0H DATA 0FAH ;COMPARE/CAPTURE 0 HIGH BYTE
CCAP1H DATA 0FBH ;COMPARE/CAPTURE 1 HIGH BYTE
CCAP2H DATA 0FCH ;COMPARE/CAPTURE 2 HIGH BYTE
CCAP3H DATA 0FDH ;COMPARE/CAPTURE 3 HIGH BYTE
CCAP4H DATA 0FEH ;COMPARE/CAPTURE 4 HIGH BYTE
************************************************************************
************************************************************************
for the 83C752
PWENA DATA 0FEH ;PULSE WIDTH ENABLE
************************************************************************
B.2 Pre-dened Bit Addresses

************************************************************************
for the 83C751/83C752
SCL BIT 080H ;P0.0 - I2C SERIAL CLOCK
SDA BIT 081H ;P0.1 - I2C SERIAL DATA
************************************************************************
IT0 BIT 088H ;TCON.0 - EXT. INTERRUPT 0 TYPE

IE0 BIT 089H ;TCON.1 - EXT. INTERRUPT 0 EDGE FLAG
IT1 BIT 08AH ;TCON.2 - EXT. INTERRUPT 1 TYPE

IE1 BIT 08BH ;TCON.3 - EXT. INTERRUPT 1 EDGE FLAG
TR0 BIT 08CH ;TCON.4 - TIMER 0 ON/OFF CONTROL
TF0 BIT 08DH ;TCON.5 - TIMER 0 OVERFLOW FLAG
TR1 BIT 08EH ;TCON.6 - TIMER 1 ON/OFF CONTROL
TF1 BIT 08FH ;TCON.7 - TIMER 1 OVERFLOW FLAG
************************************************************************
for the 83C751/83C752
C/T BIT 08EH ;TCON.6 - COUNTER OR TIMER OPERATION
GATE BIT 08FH ;TCON.7 - GATE TIMER
************************************************************************
************************************************************************
for the 80515/80535
INT3 BIT 090H ;P1.0 - EXT. INTERRUPT 3/CAPT & COMP 0
INT2 BIT 094H ;P1.4 - EXT. INTERRUPT 2
T2EX BIT 095H ;P1.5 - TIMER 2 EXT. RELOAD TRIGGER INP
CLKOUT BIT 096H ;P1.6 - SYSTEM CLOCK OUTPUT
T2 BIT 097H ;P1.7 - TIMER 2 INPUT
************************************************************************
************************************************************************
for the 83C152/80C152
GRXD BIT 090H ;P1.0 - GSC RECEIVER DATA INPUT
GTXD BIT 091H ;P1.1 - GSC TRANSMITTER DATA OUTPUT
DEN BIT 092H ;P1.2 - DRIVE ENABLE TO ENABLE EXT DRIVE
TXC BIT 093H ;P1.3 - GSC EXTERNAL TRANSMIT CLOCK INPU
RXC BIT 094H ;P1.4 - GSC EXTERNAL RECEIVER CLOCK INPU
************************************************************************
************************************************************************
for the 83C552/80C552
CT0I BIT 090H ;P1.0 - CAPTURE/TIMER INPUT 0
T2 BIT 094H ;P1.4 - T2 EVENT INPUT
RT2 BIT 095H ;P1.5 - T2 TIMER RESET SIGNAL
SCL BIT 096H ;P1.6 - SERIAL PORT CLOCK LINE I2C
SDA BIT 097H ;P1.7 - SERIAL PORT DATA LINE I2C
************************************************************************
************************************************************************
for the 80C517/80C537
INT2 BIT 094H ;P1.4 - EXT. INTERRUPT 2
T2EX BIT 095H ;P1.5 - TIMER 2 EXT. RELOAD TRIGGER INPU
CLKOUT BIT 096H ;P1.6 - SYSTEM CLOCK OUTPUT
T2 BIT 097H ;P1.7 - TIMER 2 INPUT
************************************************************************
************************************************************************
for the 80C452/83C452 and 80C152/83C152
HLD BIT 095H ;P1.5 - DMA HOLD REQUEST I/O
HLDA BIT 096H ;P1.6 - DMA HOLD ACKNOWLEDGE OUTPUT
************************************************************************
************************************************************************
for the 83C751/83C752
INT0 BIT 095H ;P1.5 - EXTERNAL INTERRUPT 0 INPUT
INT1 BIT 096H ;P1.6 - EXTERNAL INTERRUPT 1 INPUT
T0 BIT 096H ;P1.7 - TIMER 0 COUNT INPUT
************************************************************************
RI BIT 098H ;SCON.0 - RECEIVE INTERRUPT FLAG

TI BIT 099H ;SCON.1 - TRANSMIT INTERRUPT FLAG
RB8 BIT 09AH ;SCON.2 - RECEIVE BIT 8
TB8 BIT 09BH ;SCON.3 - TRANSMIT BIT 8
REN BIT 09CH ;SCON.4 - RECEIVE ENABLE
SM2 BIT 09DH ;SCON.5 - SERIAL MODE CONTROL BIT 2
SM1 BIT 09EH ;SCON.6 - SERIAL MODE CONTROL BIT 1
SM0 BIT 09FH ;SCON.7 - SERIAL MODE CONTROL BIT 0
************************************************************************
for the 83C751/83C752
MASTER BIT(READ) 099H ;I2CON.1 - MASTER
STP BIT(READ) 09AH ;I2CON.2 - STOP
STR BIT(READ) 09BH ;I2CON.3 - START
ARL BIT(READ) 09CH ;I2CON.4 - ARBITRATION LOSS
DRDY BIT(READ) 09DH ;I2CON.5 - DATA READY
ATN BIT(READ) 09EH ;I2CON.6 - ATTENTION
RDAT BIT(READ) 09FH ;I2CON.7 - RECEIVE DATA
XSTP BIT(WRITE)098H ;I2CON.0 - TRANSMIT STOP
XSTR BIT(WRITE)099H ;I2CON.1 - TRANSMIT REPEATED START
CSTP BIT(WRITE)09AH ;I2CON.2 - CLEAR STOP
CSTR BIT(WRITE)09BH ;I2CON.3 - CLEAR START
CARL BIT(WRITE)09CH ;I2CON.4 - CLEAR ARBITRATION LOSS
CDR BIT(WRITE)09DH ;I2CON.5 - CLEAR DATA READY
IDLE BIT(WRITE)09EH ;I2CON.6 - GO IDLE
CXA BIT(WRITE)09FH ;I2CON.7 - CLEAR TRANSMIT ACTIVE
************************************************************************
EX0 BIT 0A8H ;IE.0 - EXTERNAL INTERRUPT 0 ENABLE

ET0 BIT 0A9H ;IE.1 - TIMER 0 INTERRUPT ENABLE
EX1 BIT 0AAH ;IE.2 - EXTERNAL INTERRUPT 1 ENABLE
ET1 BIT 0ABH ;IE.3 - TIMER 1 INTERRUPT ENABLE
ES BIT 0ACH ;IE.4 - SERIAL PORT INTERRUPT ENABLE
************************************************************************
for the 83C751/83C752
EI2 BIT 0ACH ;IE.4 - SERIAL PORT INTERRUPT ENABLE
************************************************************************
************************************************************************
for the 8052/8032, 80C154/83C154, 80C252(80C51FA), 80515/80535
ET2 BIT 0ADH ;TIMER 2 INTERRUPT ENABLE
************************************************************************
************************************************************************
for the 80C652/83C652
ES1 BIT 0ADH ;IE.5 - SERIAL PORT 1 INTERRUPT ENABLE
************************************************************************
************************************************************************
for the 80C252(80C51FA)
EC BIT 0AEH ;IE.6 - ENABLE PCA INTERRUPT
************************************************************************
************************************************************************
for the 80515/80535
WDT BIT 0AEH ;IEN0.6 - WATCHDOG TIMER RESET
************************************************************************
************************************************************************
for the 83C552/80C552
ES1 BIT 0ADH ;IEN0.5 - SERIAL PORT 1 INTERRUPT ENABLE
EAD BIT 0AEH ;IEN0.6 - ENABLE A/D INTERRUPT
************************************************************************
************************************************************************
for the 80C517/80C537
ET2 BIT 0ADH ;IEN0.5 - TIMER 2 INTERRUPT ENABLE
WDT BIT 0AEH ;IEN0.6 - WATCHDOG TIMER RESET
************************************************************************
EA BIT 0AFH ;IE.7 - GLOBAL INTERRUPT ENABLE

RXD BIT 0B0H ;P3.0 - SERIAL PORT RECEIVE INPUT
TXD BIT 0B1H ;P3.1 - SERIAL PORT TRANSMIT OUTPUT
INT0 BIT 0B2H ;P3.2 - EXTERNAL INTERRUPT 0 INPUT
INT1 BIT 0B3H ;P3.3 - EXTERNAL INTERRUPT 1 INPUT
T0 BIT 0B4H ;P3.4 - TIMER 0 COUNT INPUT
T1 BIT 0B5H ;P3.5 - TIMER 1 COUNT INPUT
WR BIT 0B6H ;P3.6 - WRITE CONTROL FOR EXT. MEMORY
RD BIT 0B7H ;P3.7 - READ CONTROL FOR EXT. MEMORY
PX0 BIT 0B8H ;IP.0 - EXTERNAL INTERRUPT 0 PRIORITY
PT0 BIT 0B9H ;IP.1 - TIMER 0 PRIORITY
PX1 BIT 0BAH ;IP.2 - EXTERNAL INTERRUPT 1 PRIORITY
PT1 BIT 0BBH ;IP.3 - TIMER 1 PRIORITY
PS BIT 0BCH ;IP.4 - SERIAL PORT PRIORITY
************************************************************************
for the 80C154/83C154
PT2 BIT 0BCH ;IP.5 - TIMER 2 PRIORITY
PCT BIT 0BFH ;IP.7 - INTERRUPT PRIORITY DISABLE
************************************************************************
************************************************************************
for the 80C652/83C652
PS1 BIT 0BDH ;IP.5 - SERIAL PORT 1 PRIORITY
************************************************************************
************************************************************************
for the 80C51FA/83C51FA(83C252/80C252)
PT2 BIT 0BDH ;IP.5 - TIMER 2 PRIORITY
PPC BIT 0BEH ;IP.6 - PCA PRIORITY
************************************************************************
************************************************************************
for the 80515/80535 and 80C517/80C537
EADC BIT 0B8H ;IEN1.0 - A/D CONVERTER INTERRUPT EN
EX2 BIT 0B9H ;IEN1.1 - EXT. INTERRUPT 2 ENABLE
EX3 BIT 0BAH ;IEN1.2 - EXT. INT 3/CAPT/COMP INT 0 EN
EX4 BIT 0BBH ;IEN1.3 - EXT. INT 4/CAPT/COMP INT 1 EN
EX5 BIT 0BCH ;IEN1.4 - EXT. INT 5/CAPT/COMP INT 2 EN
EX6 BIT 0BDH ;IEN1.5 - EXT. INT 6/CAPT/COMP INT 3 EN
SWDT BIT 0BEH ;IEN1.6 - WATCHDOG TIMER START
EXEN2 BIT 0BFH ;IEN1.7 - T2 EXT. RELOAD INTER START
IADC BIT 0C0H ;IRCON.0 - A/D CONVERTER INTER REQUEST
IEX2 BIT 0C1H ;IRCON.1 - EXT. INTERRUPT 2 EDGE FLAG

TF2 BIT 0C6H ;IRCON.6 - TIMER 2 OVERFLOW FLAG
EXF2 BIT 0C7H ;IRCON.7 - TIMER 2 EXT. RELOAD FLAG
T2IO BIT 0C8H ;T2CON.0 - TIMER 2 INPUT SELECT BIT 0
T2I1 BIT 0C9H ;T2CON.1 - TIMER 2 INPUT SELECT BIT 1
T2CM BIT 0CAH ;T2CON.2 - COMPARE MODE
T2R0 BIT 0CBH ;T2CON.3 - TIMER 2 RELOAD MODE SEL BIT 0
T2R1 BIT 0CCH ;T2CON.4 - TIMER 2 RELOAD MODE SEL BIT 1
I2FR BIT 0CDH ;T2CON.5 - EXT. INT 2 F/R EDGE FLAG
I3FR BIT 0CEH ;T2CON.6 - EXT. INT 3 F/R EDGE FLAG
T2PS BIT 0CFH ;T2CON.7 - PRESCALER SELECT BIT
************************************************************************
************************************************************************
for the 83C552/80C552
PS1 BIT 0BDH ;IP0.5 - SIO1
PAD BIT 0BEH ;IP0.6 - A/D CONVERTER
CMSR0 BIT 0C0H ;P4.0 - T2 COMPARE AND SET/RESET OUTPUTS
CMT0 BIT 0C6H ;P4.6 - T2 COMPARE AND TOGGLE OUTPUTS
CMT1 BIT 0C7H ;P4.7 - T2 COMPARE AND TOGGLE OUTPUTS
CTI0 BIT 0C8H ;TM2IR.0 - T2 CAPTURE 0
CTI1 BIT 0C9H ;TM2IR.1 - T2 CAPTURE 1
CTI2 BIT 0CAH ;TM2IR.2 - T2 CAPTURE 2
CTI3 BIT 0CBH ;TM2IR.3 - T2 CAPTURE 3
CMI0 BIT 0CCH ;TM2IR.4 - T2 COMPARATOR 0
CMI1 BIT 0CDH ;TM2IR.5 - T2 COMPARATOR 1
CMI2 BIT 0CEH ;TM2IR.6 - T2 COMPARATOR 2
T2OV BIT 0CFH ;TM2IR.7 - T2 OVERFLOW
************************************************************************
************************************************************************
for the RUPI-44
RBP BIT 0C8H ;STS.0 - RECEIVE BUFFER PROTECT
AM BIT 0C9H ;STS.1 - AUTO/ADDRESSED MODE SELECT
OPB BIT 0CAH ;STS.2 - OPTIONAL POLL BIT
BOV BIT 0CBH ;STS.3 - RECEIVE BUFFER OVERRUN
SI BIT 0CCH ;STS.4 - SIU INTERRUPT FLAG
RTS BIT 0CDH ;STS.5 - REQUEST TO SEND
RBE BIT 0CEH ;STS.6 - RECEIVE BUFFER EMPTY
TBF BIT 0CFH ;STS.7 - TRANSMIT BUFFER FULL
************************************************************************
************************************************************************
for the 8052/8032, 80C154/83C154, 80C51FA/83C51FA(83C252/80C252)
CAP2 BIT 0C8H ;T2CON.0 - CAPTURE OR RELOAD SELECT
CNT2 BIT 0C9H ;T2CON.1 - TIMER OR COUNTER SELECT
TR2 BIT 0CAH ;T2CON.2 - TIMER 2 ON/OFF CONTROL
EXEN2 BIT 0CBH ;T2CON.3 - TIMER 2 EXTERNAL ENABLE FLAG
TCLK BIT 0CCH ;T2CON.4 - TRANSMIT CLOCK SELECT
RCLK BIT 0CDH ;T2CON.5 - RECEIVE CLOCK SELECT
EXF2 BIT 0CEH ;T2CON.6 - EXTERNAL TRANSITION FLAG
TF2 BIT 0CFH ;T2CON.7 - TIMER 2 OVERFLOW FLAG
************************************************************************
************************************************************************
for the 83C152/80C152
EGSRV BIT 0C8H ;IEN1.0 - GSC RECEIVE VALID
EGSRE BIT 0C9H ;IEN1.1 - GSC RECEIVE ERROR
EDMA0 BIT 0CAH ;IEN1.2 - DMA CHANNEL REQUEST 0
EGSTV BIT 0CBH ;IEN1.3 - GSC TRANSMIT VALID
EDMA1 BIT 0CCH ;IEN1.4 - DMA CHANNEL REQUEST 1
EGSTE BIT 0CDH ;IEN1.5 - GSC TRANSMIT ERROR
************************************************************************
************************************************************************
for the 80512/80532
IADC BIT 0C0H ;IRCON.0 - A/D CONVERTER INTERRUPT REQ
************************************************************************
P BIT 0D0H ;PSW.0 - ACCUMULATOR PARITY FLAG
************************************************************************
for the 83C552/80C552
F1 BIT 0D1H ;PSW.1 - FLAG 1
************************************************************************
************************************************************************
for the 80512/80532
MX0 BIT 0D8H ;ADCON.0 - ANALOG INPUT CH SELECT BIT 0
MX2 BIT 0DAH ;ADCON.2 - ANALOG INPUT CH SELECT BIT 2
ADM BIT 0DBH ;ADCON.3 - A/D CONVERSION MODE
BSY BIT 0DCH ;ADCON.4 - BUSY FLAG
BD BIT 0DFH ;ADCON.7 - BAUD RATE ENABLE
************************************************************************
OV BIT 0D2H ;PSW.2 - OVERFLOW FLAG

RS0 BIT 0D3H ;PSW.3 - REGISTER BANK SELECT 0
RS1 BIT 0D4H ;PSW.4 - REGISTER BANK SELECT 1
AC BIT 0D6H ;PSW.6 - AUXILIARY CARRY FLAG
CY BIT 0D7H ;PSW.7 - CARRY FLAG
************************************************************************
for the 80C51FA/83C51FA(83C252/80C252)
CCF0 BIT 0D8H ;CCON.0 -PCA MODULE 0 INTERRUPT FLAG
CCF1 BIT 0D9H ;CCON.1 -PCA MODULE 1 INTERRUPT FLAG
CCF2 BIT 0DAH ;CCON.2 -PCA MODULE 2 INTERRUPT FLAG
CCF3 BIT 0DBH ;CCON.3 -PCA MODULE 3 INTERRUPT FLAG
CCF4 BIT 0DCH ;CCON.4 -PCA MODULE 4 INTERRUPT FLAG
CR BIT 0DEH ;CCON.6 - COUNTER RUN
CF BIT 0DFH ;PCA COUNTER OVERFLOW FLAG
************************************************************************
************************************************************************
for the RUPI-44
SER BIT 0D8H ;NSNR.0 - RECEIVE SEQUENCE ERROR
NR0 BIT 0D9H ;NSNR.1 - RECEIVE SEQUENCE COUNTER-BIT 0
NR1 BIT 0DAH ;NSNR.2 - RECEIVE SEQUENCE COUNTER-BIT 1
NR2 BIT 0DBH ;NSNR.3 - RECEIVE SEQUENCE COUNTER-BIT 2
SES BIT 0DCH ;NSNR.4 - SEND SEQUENCE ERROR
NS0 BIT 0DDH ;NSNR.5 - SEND SEQUENCE COUNTER-BIT 0
NS1 BIT 0DEH ;NSNR.6 - SEND SEQUENCE COUNTER-BIT 1
NS2 BIT 0DFH ;NSNR.7 - SEND SEQUENCE COUNTER-BIT 2

************************************************************************
************************************************************************
for the 80515/80535
MX2 BIT 0DAH ;ADCON.2 - ANALOG INPUT CH SELECT BIT 2
ADM BIT 0DBH ;ADCON.3 - A/D CONVERSION MODE
BSY BIT 0DCH ;ADCON.4 - BUSY FLAG
CLK BIT 0DEH ;ADCON.5 - SYSTEM CLOCK ENABLE
BD BIT 0DFH ;ADCON.7 - BAUD RATE ENABLE
************************************************************************
************************************************************************
for the 80C652/83C652
CR0 BIT 0D8H ;S1CON.0 - CLOCK RATE 0
AA BIT 0DAH ;S1CON.2 - ASSERT ACKNOWLEDGE
SI BIT 0DBH ;S1CON.3 - SIO1 INTERRUPT BIT
STO BIT 0DCH ;S1CON.4 - STOP FLAG
STA BIT 0DDH ;S1CON.5 - START FLAG
ENS1 BIT 0DEH ;S1CON.6 - ENABLE SIO1
************************************************************************
************************************************************************
for the 83C152/80C152
DMA BIT 0D8H ;TSTAT.0 - DMA SELECT
TEN BIT 0D9H ;TSTAT.1 - TRANSMIT ENABLE
TFNF BIT 0DAH ;TSTAT.2 - TRANSMIT FIFO NOT FULL
TDN BIT 0DBH ;TSTAT.3 - TRANSMIT DONE
TCDT BIT 0DCH ;TSTAT.4 - TRANSMIT COLLISION DETECT
UR BIT 0DDH ;TSTAT.5 - UNDERRUN
NOACK BIT 0DEH ;TSTAT.6 - NO ACKNOWLEDGE
LNI BIT 0DFH ;TSTAT.7 - LINE IDLE
HBAEN BIT 0E8H ;RSTAT.0 - HARDWARE BASED ACKNOWLEDGE EN
GREN BIT 0E9H ;RSTAT.1 - RECEIVER ENABLE
RFNE BIT 0EAH ;RSTAT.2 - RECEIVER FIFO NOT EMPTY
RDN BIT 0EBH ;RSTAT.3 - RECEIVER DONE
CRCE BIT 0ECH ;RSTAT.4 - CRC ERROR
AE BIT 0EDH ;RSTAT.5 - ALIGNMENT ERROR
RCABT BIT 0EEH ;RSTAT.6 - RCVR COLLISION/ABORT DETECT
OR BIT 0EFH ;RSTAT.7 - OVERRUN
PGSRV BIT 0F8H ;IPN1.0 - GSC RECEIVE VALID
PGSRE BIT 0F9H ;IPN1.1 - GSC RECEIVE ERROR
PDMA0 BIT 0FAH ;IPN1.2 - DMA CHANNEL REQUEST 0
PGSTV BIT 0FBH ;IPN1.3 - GSC TRANSMIT VALID
PDMA1 BIT 0FCH ;IPN1.4 - DMA CHANNEL REQUEST 1
PGSTE BIT 0FDH ;IPN1.5 - GSC TRANSMIT ERROR
************************************************************************
************************************************************************
for the 80C452/83C452
OFRS BIT 0E8H ;SLCON.0 - OUTPUT FIFO CH REQ SERVICE
IFRS BIT 0E9H ;SLCON.1 - INPUT FIFO CH REQ SERVICE
FRZ BIT 0EBH ;SLCON.3 - ENABLE FIFO DMA FREEZE MODE
ICOI BIT 0ECH ;SLCON.4 - GEN INT WHEN IMMEDIATE COMMAN
OUT REGISTER IS AVAILABLE
ICII BIT 0EDH ;SLCON.5 - GEN INT WHEN A COMMAND IS
WRITTEN TO IMMEDIATE COMMAND IN REG
OFI BIT 0EEH ;SLCON.6 - ENABLE OUTPUT FIFO INTERRUPT
IFI BIT 0EFH ;SLCON.7 - ENABLE INPUT FIFO INTERRUPT

EFIFO BIT 0F8H ;IEP.0 - FIFO SLAVE BUS I/F INT EN
PDMA1 BIT 0F9H ;IEP.1 - DMA CHANNEL REQUEST 1
PDMA0 BIT 0FAH ;IEP.2 - DMA CHANNEL REQUEST 0
EDMA1 BIT 0FBH ;IEP.3 - DMA CHANNEL 1 INTERRUPT ENABLE
EDMA0 BIT 0FCH ;IEP.4 - DMA CHANNEL 0 INTERRUPT ENABLE
PFIFO BIT 0FDH ;IEP.5 - FIFO SLAVE BUS I/F INT PRIORITY
************************************************************************
************************************************************************
for the 80C451/83C451
IBF BIT 0E8H ;CSR.0 - INPUT BUFFER FULL
OBF BIT 0E9H ;CSR.1 - OUTPUT BUFFER FULL
IDSM BIT 0EAH ;CSR.2 - INPUT DATA STROBE
OBFC BIT 0EBH ;CSR.3 - OUTPUT BUFFER FLAG CLEAR
MA0 BIT 0ECH ;CSR.4 - AFLAG MODE SELECT
MA1 BIT 0EDH ;CSR.5 - AFLAG MODE SELECT
MB0 BIT 0EEH ;CSR.6 - BFLAG MODE SELECT
MB1 BIT 0EFH ;CSR.7 - BFLAG MODE SELECT
************************************************************************
************************************************************************
for the 83C751/83C752
CTO BIT(READ) 0D8H ;I2CFG.0 - CLOCK TIMING 0
CT1 BIT(READ) 0D9H ;I2CFG.1 - CLOCK TIMING 1
T1RUN BIT(READ) 0DCH ;I2CFG.4 - START/STOP TIMER 1
MASTRQ BIT(READ) 0DEH ;I2CFG.6 - MASTER I2C
SLAVEN BIT(READ) 0DFH ;I2CFG.7 - SLAVE I2C
CT0 BIT(WRITE)0D8H ;I2CFG.0 - CLOCK TIMING 0
CT1 BIT(WRITE)0D9H ;I2CFG.1 - CLOCK TIMING 1
TIRUN BIT(WRITE)0DCH ;I2CFG.4 - START/STOP TIMER 1
CLRTI BIT(WRITE)0DDH ;I2CFG.5 - CLEAR TIMER 1 INTERRUPT FLAG
MASTRQ BIT(WRITE)0DEH ;I2CFG.6 - MASTER I2C
SLAVEN BIT(WRITE)0DFH ;I2CFG.7 - SLAVE I2C
RSTP BIT(READ) 0F8H ;I2STA.0 - XMIT STOP CONDITION
RSTR BIT(READ) 0F9H ;I2STA.1 - XMIT REPEAT STOP COND.
MAKSTP BIT(READ) 0FAH ;I2STA.2 - STOP CONDITION
MAKSTR BIT(READ) 0FBH ;I2STA.3 - START CONDITION
XACTV BIT(READ) 0FCH ;I2STA.4 - XMIT ACTIVE
XDATA BIT(READ) 0FDH ;I2STA.5 - CONTENT OF XMIT BUFFER
RIDLE BIT(READ) 0FEH ;I2STA.6 - SLAVE IDLE FLAG
************************************************************************
************************************************************************
for the 83C552/80C552
AA BIT 0DAH ;S1CON.2 - ASSERT ACKNOWLEDGE
SI BIT 0DBH ;S1CON.3 - SERIAL I/O INTERRUPT
STO BIT 0DCH ;S1CON.4 - STOP FLAG
STA BIT 0DDH ;S1CON.5 - START FLAG
ENS1 BIT 0DEH ;S1CON.6 - ENABLE SERIAL I/O
ECT0 BIT 0E8H ;IEN1.0 - ENABLE T2 CAPTURE 0
ECT1 BIT 0E9H ;IEN1.1 - ENABLE T2 CAPTURE 1
ECT2 BIT 0EAH ;IEN1.2 - ENABLE T2 CAPTURE 2
ECT3 BIT 0EBH ;IEN1.3 - ENABLE T2 CAPTURE 3
ECM0 BIT 0ECH ;IEN1.4 - ENABLE T2 COMPARATOR 0
ECM1 BIT 0EDH ;IEN1.5 - ENABLE T2 COMPARATOR 1
ECM2 BIT 0EEH ;IEN1.6 - ENABLE T2 COMPARATOR 2
ET2 BIT 0EFH ;IEN1.7 - ENABLE T2 OVERFLOW
PCT0 BIT 0F8H ;IP1.0 - T2 CAPTURE REGISTER 0

PCT1 BIT 0F9H ;IP1.1 - T2 CAPTURE REGISTER 1
PCT2 BIT 0FAH ;IP1.2 - T2 CAPTURE REGISTER 2
PCT3 BIT 0FBH ;IP1.3 - T2 CAPTURE REGISTER 3
PCM0 BIT 0FCH ;IP1.4 - T2 COMPARATOR 0
PCM1 BIT 0FDH ;IP1.5 - T2 COMPARATOR 1
PCM2 BIT 0FEH ;IP1.6 - T2 COMPARATOR 2
PT2 BIT 0FFH ;IP1.7 - T2 OVERFLOW
************************************************************************
************************************************************************
for the 80C517/80C537
MX0 BIT 0D8H ;ADCON0.0 - ANALOG INPUT CH SELECT BIT 0
MX1 BIT 0D9H ;ADCON0.1 - ANALOG INPUT CH SELECT BIT 1
MX2 BIT 0DAH ;ADCON0.2 - ANALOG INPUT CH SELECT BIT 2
ADM BIT 0DBH ;ADCON0.3 - A/D CONVERSION MODE
BSY BIT 0DCH ;ADCON0.4 - BUSY FLAG
CLK BIT 0DEH ;ADCON0.5 - SYSTEM CLOCK ENABLE
BD BIT 0DFH ;ADCON0.7 - BAUD RATE ENABLE
************************************************************************
************************************************************************
for the 80C154/83C154
ALF BIT 0F8H ;IOCON.0 - CPU POWER DOWN MODE CONTROL
P1F BIT 0F9H ;IOCON.1 - PORT 1 HIGH IMPEDANCE
P2F BIT 0FAH ;IOCON.2 - PORT 2 HIGH IMPEDANCE
P3F BIT 0FBH ;IOCON.3 - PORT 3 HIGH IMPEDANCE
IZC BIT 0FCH ;IOCON.4 - 10K TO 100 K OHM SWITCH (P1-3)
SERR BIT 0FDH ;IOCON.5 - SERIAL PORT RCV ERROR FLAG
T32 BIT 0FEH ;IOCON.6 - 32 BIT TIMER SWITCH
WDT BIT 0FFH ;IOCON.7 - WATCHDOG TIMER CONTROL
*************************************************************************
Appendix C
RESERVED SYMBOLS
The following is a list of reserved symbols used by the Cross Assembler. These symbols
cannot be redened.
A AB ACALL ADD ADDC AJMP AND ANL
AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7
BIT BSEG C CALL CJNE CLR CODE CPL
CSEG DA DATA DB DBIT DEC DIV DJNZ
DPTR DS DSEG DW END EQ EQU GE
GT HIGH IDATA INC ISEG JB JBC JC
JMP JNB JNC JNZ JZ LCALL LE LJMP
LOW LT MOD MOV MOVC MOVX MUL NE
NOP NOT OR ORG ORL PC POP PUSH
R0 R1 R2 R3 R4 R5 R6 R7
RET RETI RL RLC RR RRC SET SETB
SHL SHR SJMP SUBB SWAP USING XCH XCHD
XDATA XOR XRL XSEG
80 Chap. C: RESERVED SYMBOLS
Appendix D
CROSS ASSEMBLER CHARACTER SET
---------------------------+----------------+-------------------
| PRINTABLE | ASCII CODE
CHARACTER NAME | FORM | HEX | DECIMAL
---------------------------+----------------+---------+----------
Horizontal Tab | | 09 | 9
Line Feed | | 0A | 10
Carriage Return | | 0D | 13
Space | | 20 | 32
Exclamation Point | ! | 21 | 33
Pound Sign | # | 23 | 35
Dollar Sign | $ | 24 | 36
Percent Sign | % | 25 | 37
Ampersand | & | 26 | 38
Apostrophe | ' | 27 | 39
Left Parenthesis | ( | 28 | 40
Right Parenthesis | ) | 29 | 41
Asterisk | * | 2A | 42
Plus sign | + | 2B | 43
Comma | , | 2C | 44
Hyphen | - | 2D | 45
Period | . | 2E | 46
Slash | / | 2F | 47
Number 0 | 0 | 30 | 48
" 1 | 1 | 31 | 49
" 2 | 2 | 32 | 50
" 3 | 3 | 33 | 51
" 4 | 4 | 34 | 52
" 5 | 5 | 35 | 53
" 6 | 6 | 36 | 54
" 7 | 7 | 37 | 55
" 8 | 8 | 38 | 56
" 9 | 9 | 39 | 57
Colon | : | 3A | 58
Semi-colon | ; | 3B | 59
Left Angle Bracket | < | 3C | 60
Equal Sign | = | 3D | 61
Right Angle Bracket | > | 3E | 62
Question Mark | ? | 3F | 63
At Sign | @ | 40 | 64
Upper Case A | A | 41 | 65
" " B | B | 42 | 66
" " C | C | 43 | 67
" " D | D | 44 | 68
" " E | E | 45 | 69
82 Chap. D: CROSS ASSEMBLER CHARACTER SET
" " F | F | 46 | 70
" " G | G | 47 | 71
" " H | H | 48 | 72
---------------------------+----------------+-------------------
| PRINTABLE | ASCII CODE
CHARACTER NAME | FORM | HEX | DECIMAL
---------------------------+----------------+---------+----------
Upper Case I | I | 49 | 73
" " J | J | 4A | 74
" " K | K | 4B | 75
" " L | L | 4C | 76
" " M | M | 4D | 77
" " N | N | 4E | 78
" " O | O | 4F | 79
" " P | P | 50 | 80
" " Q | Q | 51 | 81
" " R | R | 52 | 82
" " S | S | 53 | 83
" " T | T | 54 | 84
" " U | U | 55 | 85
" " V | V | 56 | 86
" " W | W | 57 | 87
" " X | X | 58 | 88
" " Y | Y | 59 | 89
" " Z | Z | 5A | 90
Underscore | _ | 5F | 95
Lower Case A | a | 61 | 97
" " B | b | 62 | 98
" " C | c | 63 | 99
" " D | d | 64 | 100
" " E | e | 65 | 101
" " F | f | 66 | 102
" " G | g | 67 | 103
" " H | h | 68 | 104
" " I | i | 69 | 105
" " J | j | 6A | 106
" " K | k | 6B | 107
" " L | l | 6C | 108
" " M | m | 6D | 109
" " N | n | 6E | 110
" " O | o | 6F | 111
" " P | p | 70 | 112
" " Q | q | 71 | 113
" " R | r | 72 | 114
" " S | s | 73 | 115
" " T | t | 74 | 116
" " U | u | 75 | 117
" " V | v | 76 | 118
" " W | w | 77 | 119
" " X | x | 78 | 120
" " Y | y | 79 | 121
" " Z | z | 7A | 122
XSA-100 Prototyping Board
XSA-100 The XSA-100 Board keeps the same form-factor as our popular XS40 Boards
while increasing the logic density to 100,000 gates with a SpartanII FPGA. The
FPGA is combined with a 16 MByte synchronous DRAM and 256 KByte Flash
● XC2S100 FPGA
to give you the resources for building a complete, soft-core RISC
● XC9572XL CPLD
microcontroller system! Or anything else you might think of...
● 16 MByte SDRAM
● 256 KByte Flash
● 100 MHz programmable The bitstream for the XSA-100 can be stored in the on-board 256 KByte Flash
oscillator so the FPGA loads its configuration as soon as power is applied. Or you can
● Parallel port download directly to the board through the parallel port with the XSTOOLs
● Keyboard/mouse PS/2 port utilities we provide. The interface CPLD on the XSA-100 also supports
● 64-color VGA port downloading with XILINX iMPACT and circuit test/debug with ChipScope
● 7-segment LED software using our simple downloading cable. No more expensive XILINX
● 1 pushbutton cables!
● 4 DIP switches
● 84-pin prototyping interface In addition to the large FPGA, SDRAM and Flash chips, you also get a VGA
(53 I/O pins) port that produces vivid graphics in 64 colors. And the prototyping header gives
● 5V-tolerant I/O you 53 general-purpose I/O pins for building interfaces to external devices.
● 5V / 3.3V / 2.5V regulators
And the XSA-100 helps you maintain your investment. Use your existing
XStend Boards to add a stereo codec, LEDs, switches, and a dedicated
● XSTOOLs utilities CDROM
prototyping area to the XSA-100. And keep your power supplies - the XSA-100
● Works with the XST-1.x and
has the same power connections as an XS40 Board.
XST-2.x Boards
● Works with XILINX ISE,
WebPACK, iMPACT and Think it will be a big switch to move from the XS40 Boards to the XSA-100?
ChipScope software Well, we provide all the software utilities for programming the FPGA, setting the
oscillator frequency, and downloading and uploading the RAM and Flash. And
we make all the source code available for you to play with! How about design
examples? We have parameterized modules for interfacing to the PS/2
keyboard port, displaying images through the VGA port, and reading/writing to
the synchronous DRAM as if it were a simple static RAM. And we will be
adapting all the chapters of our Pragmatic Logic Design online text to support
the XSA-100.
The XS40-010XL Board is perfect for experimenting with FPGA designs,
microcontroller programming, or hardware/software codesign. The 20,000-gate
XC4010XL FPGA operates at 3.3V but is 5V-tolerant so you can connect it to
commonly available TTL chips. Digital logic designs can be loaded into the
FPGA. The microcontroller can use the FPGA as a coprocessor. The SRAM
can store microcontroller programs/data or serve as general-purpose storage
for FPGA-based designs.
The XC4000XL series of FPGAs is supported by Xilinx's Foundation and

Alliance Series software. The XC4000XL series has better routing and
compilation of designs for these FPGAs is much faster. If you use Win95 or
NT, then you must use the Foundation or Alliance tools.
XSA-100 Board picture

XSA Board V1.1, V1.2
User Manual

your new XSA Board

Copyright © 2001-2004 by X Engineering Software Systems Corporation.
XSA BOARD V1.1, V1.2 USER MANUAL 1

Table of Contents
Table of Contents .............................................................................................2
Preliminaries .....................................................................................................4
Getting Help!.................................................................................................4
Take notice!! .................................................................................................4
Packing List ..................................................................................................5
Installation .........................................................................................................6
Installing the XSTOOLS Utilities and Documentation ................................6
Applying Power to Your XSA Board............................................................6
Using a 9VDC wall-mount power supply ....................................................6
Powering Through the PS/2 Connector......................................................6
Solderless Protoboard Installation...............................................................6
Connecting a PC to Your XSA Board .........................................................8
Connecting a VGA Monitor to Your XSA Board.........................................8
Connecting a Mouse or Keyboard to Your XSA Board..............................9
Inserting the XSA Board into an XStend Board..........................................9
Setting the Jumpers on Your XSA Board ...................................................9
Testing Your XSA Board............................................................................10
Setting the XSA Board Clock Oscillator Frequency .................................11
Programming ..................................................................................................13
Downloading Designs into the FPGA and CPLD of Your XSA Board ....13
Storing Non-Volatile Designs in Your XSA Board ....................................16
Downloading and Uploading Data to the SDRAM in Your XSA Board...18
Programmer's Models ....................................................................................20
XSA Board Organization............................................................................20
Programmable logic: Spartan-II FPGA and XC9572XL CPLD ...............21

100 MHz Programmable Oscillator ...........................................................21
Synchronous DRAM ..................................................................................23
Flash RAM..................................................................................................24
Seven-Segment LED .................................................................................25
Four-Position DIP Switch ...............................................................................25
PS/2 Port.....................................................................................................25
Pushbutton..................................................................................................26
VGA Monitor Interface ...............................................................................26
Parallel Port Interface.................................................................................26
Prototyping Header ....................................................................................29
XSA Pin Connections .....................................................................................31
XSA Schematics.............................................................................................32

1
Preliminaries
Getting Help!
If you can't get the XSA Board hardware to work, send an e-mail message describing
your problem to help@xess.com or submit a problem report at
http://www.xess.com/help.html. Our web site also has
answers to frequently-asked-questions,
example designs, application notes and tutorials for the XS Boards,
a place to sign-up for our email forum where you can post questions to other XS
Board users.
If you can't get your Xilinx WebPACK software tools installed properly, send an e-mail
message describing your problem to hotline@xilinx.com or check their web site at
http://www.xilinx.com/support/support.htm.
If you need help using the WebPACK software to create designs for your XSA Board,
then check out this tutorial.
Take notice!!
The XSA Board requires an external power supply to operate! It does not draw power
through the downloading cable from the PC parallel port.
If you are connecting a 9VDC power supply to your XSA Board, please make sure the
center terminal of the plug is positive and the outer sleeve is negative.
Do not power your XSA Board with a battery! This will not provide enough current to
insure reliable operation of the XSA Board.

Packing List
an XSA Board;
a 6' cable with a 25-pin male connector on each end;
an XSTOOLS CDROM with software utilities and documentation for using the XSA
Board.

2
Installation
Installing the XSTOOLS Utilities and Documentation
Xilinx currently provides the WebPACK tools for programming their CPLDs and Spartan-II
FPGAs. The XESS CDROM contains a version of WebPACK that will generate bitstream
configuration files compatible with your XSA Board. You can also download the most
current version of the WebPACK tools from the Xilinx website..
In addition, XESS Corp. provides the XSTOOLS utilities for interfacing a PC to your XSA
Board. Run the SETUP.EXE program on the XSTOOLS CDROM to install these utilities.
Applying Power to Your XSA Board
You can use your XSA Board in three ways, distinguished by the method you use to apply
power to the board.
Using a 9VDC wall-mount power supply
You can use your XSA Board all by itself to experiment with logic designs. Just place the
XSA Board on a non-conducting surface as shown in Figure 1. Then apply power to jack
J5 of the XSA Board from a 9V DC wall-mount power supply with a 2.1 mm female,
center-positive plug. (See Figure 2 for the location of jack J5 on your XSA Board.) The
on-board voltage regulation circuitry will create the voltages required by the rest of the
XSA Board circuitry. Be careful!! The voltage regulators on the XSA Board will
become hot. Attach a heat sink to them if necessary.
Powering Through the PS/2 Connector
You can use your XSA Board with a laptop PC by connecting a PS/2 male-to-male cable
from the PS/2 port of the laptop to the J4 connector. You must also have a shunt across
pins 1 and 2 of jumper J7. The on-board voltage regulation circuitry will create the
voltages required by the rest of the XSA Board circuitry. Many PS/2 ports cannot
supply more than 0.5A so large, fast FPGA designs may not work when using
this power source!
Solderless Protoboard Installation
The two rows of pins from your XSA Board can be plugged into a solderless protoboard
with holes spaced at 0.1" intervals. (One of the A.C.E. protoboards from 3M is a good
choice.) Once plugged in, many of the pins of the FPGA are accessible to other circuits
on the protoboard. (The numbers printed next to the rows of pins on your XSA Board

correspond to the pin numbers of the FPGA.) Power can still be supplied to your XSA
Board though jack J5, or power can be applied directly through several pins on the
underside of the board. Just connect +5V, +3.3V, +2.5V and ground to the pins of your
XSA Board listed in Table 1.
• Table 1: Power supply pins for the XSA Board.
Voltage Pin Note

+5V 2
+3.3V 22 Remove the shunt from jumper J7 if you wish
to use your own +3.3V supply.
Leave the shunt on jumper J7 to generate the
+3.3V supply from the +5V supply.
+2.5V 54 Remove the shunt from jumper J2 if you wish
to use your own +2.5V supply.
Leave the shunt on jumper J2 to generate the
+2.5V supply from the +3.3V supply.
GND 52
Parallel Port
PS/2
9V DC
VGA
• Figure 1: External connections to the XSA Board.

PC Parallel Port
J8
External
Clock Input J7
J9
100 MHz Osc. J6 9VDC Power Supply
J5
SW1 +3.3V
GND
Pushbutton U15
CPLD
Flash RAM
+5V
U10 Spartan-II FPGA

J10
J2
SDRAM
Pushbutton SW2 +2.5V
J4 J3
PS/2 Mouse VGA Monitor

or Keyboard
• Figure 2: Arrangement of components on the XSA Board.
Connecting a PC to Your XSA Board
The 6' DB25 male-to-male cable included with your XSA Board connects it to a PC. One
end of the cable attaches to the parallel port on the PC and the other connects to the
female DB-25 connector (J8) at the top of the XSA Board as shown in Figure 1.
Connecting a VGA Monitor to Your XSA Board
the bottom of your XSA Board (see Figure 1). You will have to create a VGA driver circuit
for your XSA Board to actually display an image. You can find an example VGA driver at
http://www.xess.com/ho03000.html.

Connecting a Mouse or Keyboard to Your XSA Board
connector at the bottom of your XSA Board (see Figure 1). You can find an example
keyboard driver at http://www.xess.com/ho03000.html.
Inserting the XSA Board into an XStend Board
If you purchased the optional XST-2.x Board, then the XSA Board is inserted as shown
below. Refer to the XST-2.x Board Manual for more details.
Setting the Jumpers on Your XSA Board
The default jumper settings shown in Table 2 configure your XSA Board for use in a logic
design environment. You will need to change the jumper settings only if you are:
downloading FPGA bitstreams to your XSA Board using the Xilinx iMPACT software;

reprogramming the clock frequency on your XSA Board (see page 11);
changing the power sources for the XSA supply voltages.
• Table 2: Jumper settings for XSA Boards.

J2 On A shunt should be installed if the +2.5V supply voltage is derived from the +3.3V supply.
(default)
Off The shunt should be removed if the +2.5V supply voltage is applied from an external source through
pin 22 of the XSA Board (labeled “+2.5V” at the lower right-hand corner of the board).
J6 1-2 (set) The shunt should be installed on pins 1 and 2 (set) when setting the frequency of the programmable
oscillator.
2-3 (osc) The shunt should be installed on pins 2 and 3 (osc) during normal operations when the programmable
(default) oscillator is generating a clock signal.
J7 1-2 The shunt should be installed on pins 1 and 2 if the +3.3V supply voltage is derived from the +5V
(default) supply.
2-3 The shunt should be installed on pins 2 and 3 if the +3.3V supply voltage is derived from the 9VDC
supply applied through jack J5.
J9 1-2 (xi) The shunt should be installed on pins 1 and 2 (xi) if the XSA Board is to be downloaded using the
Xilinx iMPACT software.
2-3 (xs) The shunt should be installed on pins 2 and 3 (xs) if the XSA Board is to be downloaded using the
(default) XESS GXSLOAD software.
J10 N/A This is a header that provides access to the +5V and GND references on the board. No shunt should
be placed on this header.
Testing Your XSA Board
Once your XSA Board is installed and the jumpers are in their default configuration, you
can test the board using the GUI-based GXSTEST utility as follows.
You start GXSTEST by clicking on the icon placed on the desktop during the
XSTOOLS installation. This brings up the window shown below.
Next you select the parallel port that your XSA Board is connected to from the Port
pulldown list. GXSTEST starts with parallel port LPT1 as the default, but you can also
After selecting the parallel port, you select either the XSA-50 or XSA-100 item in the Board
Type pulldown list. Then click on the TEST button to start the testing procedure.
GXSTEST will configure the FPGA to perform a test procedure on your XSA Board.

Within thirty seconds you will see a O displayed on the LED digit if the test completes
successfully. Otherwise an E will be displayed if the test fails. A status window will also
appear on your PC screen informing you of the success or failure of the test.
If your XSA Board fails the test, you will be shown a checklist of common causes for
failure. If none of these causes applies to your situation, then test the XSA Board using
another PC. In our experience, 99.9% of all problems are due to the parallel port. If you
cannot get your board to pass the test even after taking these steps, then contact XESS
Corp for further assistance.
As a result of testing the XSA Board, the CPLD is programmed with the standard parallel
port interface found in the dwnldpar.svf bitstream file located within the XSTOOLS\XSA
folder. This is the standard interface that should be loaded into the CPLD when you want
to use it with the GXSLOAD utility.
Setting the XSA Board Clock Oscillator Frequency
The XSA Board has a 100 MHz programmable oscillator (a Dallas Semiconductor
DS1075Z-100). The 100 MHz master frequency can be divided by factors of 1, 2, ... up to
2052 to get clock frequencies of 100 MHz, 50 MHz, ... down to 48.7 KHz, respectively.
The divided frequency is sent to the rest of the XSA Board circuitry as a clock signal.
operation at its programmed frequency whenever power is applied to the XSA Board. You
can store a particular divisor into the oscillator chip by using the GUI-based GXSSETCLK
as follows.
You start GXSSETCLK by clicking on the icon placed on the desktop during
the XSTOOLS installation. This brings up the window shown below.
Your next step is to select the parallel port that your XSA Board is connected to from the
Port pulldown list. Then select either XSA-50 or XSA-100 in the Board Type pulldown list.
Next you enter a divisor between 1 and 2052 into the Divisor text box and then click on the
SET button. Then follow the sequence of instructions given by XSSETCLK for moving
shunts and removing and restoring power during the oscillator programming process. At
the completion of the process, the new frequency will be programmed into the DS1075.
An external clock signal can be substituted for the internal 100 MHz oscillator of the
DS1075. Checking the External Clock checkbox will enable this feature in the

programmable oscillator chip. If this option is selected, you are then responsible for
providing the external clock to the XSA Board through pin 64 (labeled “CLK” at the upper
left-hand corner of the board).

3
Programming
This section will show you how to download a logic designs into the FPGA and CPLD of
your XSA Board and how to download and upload data to and from the SDRAM and
Flash devices on the board.
Downloading Designs into the FPGA and CPLD of Your XSA Board
During the development and testing phases, you will usually connect the XSA Board to the
parallel port of a PC and download your circuit each time you make changes to it. You
can download a Spartan-II FPGA design into your XSA Board using the GXSLOAD utility
as follows.
You start GXSLOAD by clicking on the icon placed on the desktop during the
XSTOOLS installation. This brings up the window shown below. Then select the type of
XS Board you are using and the parallel port to which it is connected as follows.

After setting the board type and parallel port, you can download .BIT or .SVF files to the
Spartan-II FPGA or XC9572XL CPLD on your XSA Board simply by dragging them to the
FPGA/CPLD area of the GXSLOAD window as shown below.
Once you release the left mouse button and drop the file, the highlighted file name
appears in the FPGA/CPLD area and the Load button in the GXSLOAD window is
enabled. Clicking on the Load button will begin sending the highlighted file to the XSA
Board through the parallel port connection. .BIT files contain configuration bitstreams that
are loaded into the FPGA while .SVF files will go to the CPLD. GXSLOAD will reject any
non-downloadable files (ones with a suffix other than .BIT or .SVF). During the
downloading process, GXSLOAD will display the name of the file and the progress of the
current download.

You can drag & drop multiple files into the FPGA/CPLD area. Clicking your mouse on a
filename will highlight the name and select it for downloading. Only one file at a time can
be selected for downloading.
Double-clicking the highlighted file will deselect it so no file will be downloaded Doing this
disables the Load button.

Storing Non-Volatile Designs in Your XSA Board
The Spartan-II FPGA on the XSA Board stores its configuration in an on-chip SRAM
which is erased whenever power is removed. Once your design is finished, you may want
to store the bitstream in the 256-KByte Flash device on the XSA Board which configures
the FPGA for operation as soon as power is applied.
Before downloading to the Flash, the FPGA .BIT file must be converted into a .EXO or
.MCS format using one of the following commands:
promgen –u 0 file.bit –p exo –s 256
promgen –u 0 file.bit –p mcs –s 256
In the commands shown above, the bitstream in the file.bit file is transformed into an .EXO
or .MCS file format starting at address zero and proceeding upward until an upper limit of
256 KBytes is reached.
Before attempting to program the Flash, you must place all four DIP switches
into the OFF position!
After the .EXO or .MCS file is generated, it is loaded into the Flash device by dragging it
into the Flash/EEPROM area and clicking on the Load button. This activates the following
sequence of steps:
1. The entire Flash device is erased.
2. The CPLD on the XSA Board is reprogrammed to create an interface between

the Flash device and the PC parallel port. (This interface is stored in the fintf.svf
bitstream file located within the XSTOOLS\XSA folder.)
3. The contents of the .EXO or .MCS file are downloaded into the Flash through the
parallel port.
4. The CPLD is reprogrammed to create a circuit that configures the FPGA with the
contents of the Flash when power is applied to the XSA Board. (This
configuration loader is stored in the fcnfg.svf bitstream file located within the
XSTOOLS\XSA folder.)
Multiple files can be stored in the Flash device just by dragging them into the
Flash/EEPROM area, highlighting the files to be downloaded and clicking the Load button.
(Note that anything previously stored in the Flash will be erased by each new download.)
This is useful if you need to store information in the Flash in addition to the FPGA
bitstream. Files are selected and de-selected for downloading just by clicking on their
names in the Flash/EEPROM area. The address ranges of the data in each file
should not overlap or this will corrupt the data stored in the Flash device!

You can also examine the contents of the Flash device by uploading it to the PC. To
upload data from an address range in the Flash, type the upper and lower bounds of the
range into the High Address and Low Address fields below the Flash/EEPROM area, and
select the format in which you would like to store the data using the Upload Format
pulldown list. Then click on the file icon and drag & drop it into any folder. This activates
the following sequence of steps:
1. The CPLD on the XSA Board is reprogrammed to create an interface between

the Flash device and the PC parallel port.
2. The Flash data between the high and low addresses (inclusive) is uploaded
through the parallel port.
3. The uploaded data is stored in a file named FLSHUPLD with an extension that
reflects the file format.
The uploaded data can be stored in the following formats:
MCS: Intel hexadecimal file format. This is the same format generated by the promgen
utility with the –p mcs option.
HEX: Identical to MCS format.
EXO-16: Motorola S-record format with 16-bit addresses (suitable for 64 KByte uploads
only).
EXO-24: Motorola S-record format with 24-bit addresses. This is the same format
generated by the promgen utility with the –p exo option.
EXO-32: Motorola S-record format with 32-bit addresses.
XESS-16: XESS hexadecimal format with 16-bit addresses. (This is a simplified file
format that does not use checksums.)
XESS-24: XESS hexadecimal format with 24-bit addresses.

XESS-32: XESS hexadecimal format with 32-bit addresses.
After the data is uploaded from the Flash, the CPLD on the XSA Board is left with the
Flash interface programmed into it. You will need to reprogram the CPLD with either the
parallel port or Flash configuration circuit before the board will function again. The CPLD
configuration bitstreams are stored in the following files:
XSTOOLS\XSA\dwnldpar.svf: Drag & drop this file into the FPGA/CPLD area and click on
the Load button to put the XSA in a mode where it will configure the FPGA through
the parallel port.
XSTOOLS\XSA\ fcnfg.svf: Drag & drop this file into the FPGA/CPLD area and click on the
Load button to put the XSA in a mode where it will configure the FPGA with the
contents of the Flash device upon power-up.
Downloading and Uploading Data to the SDRAM in Your XSA Board
The XSA-100 Board contains a 16-MByte synchronous DRAM (8M x 16 SDRAM) whose
contents can be downloaded and uploaded by GXSLOAD. (The XSA-50 has an 8-MByte
SDRAM organized as 4M x 16.) This is useful for initializing the SDRAM with data for use
by the FPGA and then reading the SDRAM contents after the FPGA has operated upon it.
The SDRAM is loaded with data by dragging & dropping one or more .EXO, .MCS, .HEX,
and/or .XES files into the RAM area of the GXSLOAD window and then clicking on the
Load button. This activates the following sequence of steps:
1. The Spartan-II FPGA on the XSA Board is reprogrammed to create an interface

between the RAM device and the PC parallel port. (This interface is stored in the
ram100.bit or ram50.bit bitstream file located within the XSTOOLS\XSA folder.
The CPLD must have previously been loaded with the dwnldpar.svf file
found in the same folder.)
2. The contents of the .EXO, .MCS, .HEX or .XES files are downloaded into the
SDRAM through the parallel port. The data in the files will overwrite each
other if their address ranges overlap.
3. If any file is highlighted in the FPGA/CPLD area, then this bitstream is loaded into
the FPGA or CPLD on the XSA Board. Otherwise the FPGA remains configured
as an interface between the PC and the SDRAM.
You can also examine the contents of the SDRAM device by uploading it to the PC. To
upload data from an address range in the SDRAM, type the upper and lower bounds of
the range into the High Address and Low Address fields below the RAM area, and select
the format in which you would like to store the data using the Upload Format pulldown list.
Then click on the file icon and drag & drop it into any folder. This activates the following
sequence of steps:
1. The Spartan-II FPGA on the XSA Board is reprogrammed to create an interface

between the RAM device and the PC parallel port. (This interface is stored in the
ram100.bit or ram50.bit bitstream file located within the XSTOOLS\XSA folder.)
2. The SDRAM data between the high and low addresses (inclusive) is uploaded
through the parallel port.

3. The uploaded data is stored in a file named RAMUPLD with an extension that
reflects the file format.
The 16-bit data words in the SDRAM are mapped into the eight-bit data format of the
.HEX, .MCS, .EXO and .XES files using a Big Endian style. That is, the 16-bit word at
address N in the SDRAM is stored in the eight-bit file with the upper eight bits at location
2N and the lower eight bits at location 2N+1. This byte-ordering applies for both RAM
uploads and downloads.

4
Programmer's
Models
This section describes the various sections of the XSA Board and shows how the I/O of
the FPGA and CPLD are connected to the rest of the circuitry. The schematics which
follow are less detailed so as to simplify the descriptions. Please refer to the complete
schematics at the end of this document if you need more details.
XSA Board Organization
The XSA Board contains the following components:
XC2S50 or XC2S100 Spartan-II FPGA: This is the main repository of programmable logic
on the XSA Board.
XC9572XL CPLD: This CPLD manages the interface between the PC parallel port and the
rest of the XSA Board.
Osc: A programmable oscillator generates the master clock for the XSA Board.
Flash: A 128 or 256-KByte Flash device provides non-volatile storage for data and
configuration bitstreams.
SDRAM: An 8 or 16-MByte SDRAM provides volatile data storage accessible by the

FPGA.
LED: A seven-segment LED allows visible feedback as the XSA Board operates.
DIP switch: A four-position DIP switch passes settings to the XSA Board or controls the
upper address bits of the Flash device.
Pushbutton: A single pushbutton sends momentary contact information to the FPGA.
Parallel Port: This is the main interface for passing configuration bitstreams and data to
and from the XSA Board.
PS/2 Port: A keyboard or mouse can interface to the XSA Board through this port.
VGA Port: The XSA Board can send signals to display graphics on a VGA monitor through
this port.

Prototyping Header: Many of the FPGA I/O pins are connected to the 84 pins on the
bottom of the XSA Board that are meant to mate with solderless breadboards.
FLASH
/RESET
A17-A0
D7-D0
/WE
/OE
/CE
Parallel Port
2 - PPD0
8
XC9572XL A17 - A0 XC2S100 D15 - D0 SDRAM
3 - PPD1
4 - PPD2 D7 - D0 D7-D0 BA1 - BA0, A12 - A0
5 - PPD3
6 - PPD4 RAS, CAS, /CS, /WE
7 - PPD5 DQMH
CCLK
8 - PPD6 DQML
/PROGRAM
9 - PPD7 CKE
/INIT
17 - PPC3 TDI CLK
M0
16 - PPC2 TMS GCLK
M1
14 - PPC1 TCK PS/2 Port
M2
11 - PPS7 TDO PSCLK
/CS
12 - PPS5 PSDATA
/WR
13 - PPS4
BSY/DOUT
15 - PPS3
DONE
TCK RED1 - RED0
TMS
GCLK GREEN1 - GREEN0
OSC TDI
TDO BLUE1 - BLUE0
GCLK /HSYNC
/VSYNC
1 - PPC0
10 - PPS6
VGA Connector
• Figure 3: XSA Board programmer’s model.
Programmable logic: Spartan-II FPGA and XC9572XL CPLD
The XSA Board contains two programmable logic chips:
A 50-Kgate XC2S50 or 100-Kgate Xilinx XC2S100 Spartan-II FPGA in a 144-pin

PQFP package. The FPGA is the main repository of programmable logic on the XSA
Board.
A Xilinx XC9572XL CPLD is used to manage the configuration of the FPGA via the
parallel port. The CPLD also controls the programming of the Flash RAM on the XSA
Board.
100 MHz Programmable Oscillator
A Dallas DS1075 programmable oscillator provides a clock signal to both the FPGA and
the CPLD. The DS1075 has a maximum frequency of 100 MHz that is divided to provide
frequencies of 100 MHz, 50 MHz, 33.3 MHz, 25 MHz, ..., 48.7 KHz. The clock signal from
the DS1075 is connected to a dedicated clock input of the CPLD. The CPLD passes the
clock signal on to the FPGA. This allows the CPLD to control the clock source for the
FPGA.

To set the divisor value, the DS1075 must be placed in its programming mode. This is
done by pulling the clock output to +5V on power-up with a shunt across pins 1 and 2 of
jumper J6. Then programming commands to set the divisor are sent to the DS1075
through control pin C0 of the parallel port. The divisor is stored in EEPROM in the
DS1075 so it will be retained even when power is removed from the XSA Board.
The shunt on jumper J6 must be across pins 2 and 3 to make the oscillator output a clock
signal upon power-up. The clock signal enters a dedicated clock input of the CPLD. Then
the CPLD can output a clock signal to a dedicated clock input of the FPGA.
To get a precise frequency value or to sync the XSA circuitry with an external system, you
can insert an external clock signal of up to 50 MHz through pin 64 of the prototyping
header. This external clock takes the place of the internal 100 MHz clock source in the
DS1075 oscillator. You must use the GXSSETCLK software utility to enable the external
clock input of the DS1075.
Clock signals can also be directly applied to two of the dedicated clock inputs of the FPGA
through the pins of the prototyping header.
+5V
PP-C0
1
J6
Pin 64 2
DS1075
3 17 42 88 18 Pin 1
100 MHz
Prog. Osc.
XC9572XL Spartan-II
CPLD FPGA
15 Pin 31

Synchronous DRAM
The various SDRAM organizations and manufacturers used on the XSA Boards are given
in the following table.
SDRAM
Board
Organization Manufacturer & Part No.
4M x 16 Hynix HY57V641620HGT-H
XSA-50
4M x 16 Samsung K4S641632F-TC75000
8M x 16 Hynix HY57V281620HCT-H
XSA-100
8M x 16 Samsung K4S281632E-TC75000
The SDRAM is connected to the FPGA as shown below. Currently, FPGA pin 133 drives
a no-connect pin of the SDRAM but this could be used in the future as the thirteenth
row/column address bit of a larger SDRAM. Also, the SDRAM clock signal is re-routed
back to a dedicated clock input of the FPGA to allow synchronization of the FPGA’s
internal operations with the SDRAM operations.
95 Q0
99 Q1
101 Q2
103 Q3
113 Q4
115 Q5
117 Q6
120 Q7
121 Q8
118 Q9
116 Q10
114 Q11
8M X 16 SDRAM (XSA-100)
112 Q12
4M X 16 SDRAM (XSA-50)
102 Q13
100 Q14
96 Q15
Spartan-II FPGA
141 A0
4 A1
6 A2
10 A3
11 A4
7 A5
5 A6
3 A7
140 A8
138 A9
139 A10
136 A11
133 NC
134 BA0
137 BA1
123 /WE
132 /CS
130 /RAS
126 /CAS
124 DQMH
122 DQML
131 CKE
129 CLK
91

Flash RAM
The Flash RAM organizations and manufacturer used on the XSA Boards are given in the
following table.
Flash RAM
Board
Organization Manufacturer & Part No.
XSA-50 128K x 8 Atmel AT49F001 Flash RAM
XSA-100 256K x 8 Atmel AT49F002 Flash RAM
The Flash RAM is connected so both the FPGA and CPLD have access. Typically, the
CPLD will program the Flash with data passed through the parallel port. If the data is an
FPGA configuration bitstream, then the CPLD can be configured to program the FPGA
with the bitstream from Flash whenever the XSA Board is powered up. (See the
application note XSA Flash Programming and SpartanII Configuration for more details on
this.) After power-up, the FPGA can read and/or write the Flash. (Of course, the CPLD
and FPGA have to be programmed such that they do not conflict if both are trying to
access the Flash.) The Flash is disabled by raising the /CE pin to a logic 1 thus making
the I/O lines connected to the Flash available for general-purpose communication
between the FPGA and the CPLD.
128K x 8 Flash RAM (XSA-50)

256K x 8 Flash RAM (XSA-100)
/RESET
A10
A11
A12
A13
A14
A15
A16
A17
/WE
/OE
/CE
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
11 41
12 43
49 58
50 59
1 40
64 29
63 28
62 27
61 74
60 75
XC9572XL CPLD
59 76
Spartan-II FPGA
58 66
45 50
44 48
57 42
43 47
56 65
46 51
47 54
52 64
51 63
48 56
2 39
4 44
5 46
6 49
7 57
8 60
9 62
10 67
+5V
S0
S2
S3 S6
S5
S6
S4
DP
S1
8
S5
S2 S3 S1
S0
S4
DP
DIPSW1
DIPSW2
DIPSW3
DIPSW4

Seven-Segment LED
The XSA Board has a 7-segment LED digit for use by the FPGA or the CPLD. The
segments of this LED are active-high meaning that a segment will glow when a logic-high
is applied to it.
The LED shares the same pins as the eight bits of the Flash RAM data bus.
Four-Position DIP Switch
The XSA Board has a bank of four DIP switches accessible from the CPLD and FPGA.
When closed or ON, each switch pulls the connected pin of the FPGA and CPLD to
ground. Otherwise, the pin is pulled high through a resistor when the switch is open or
OFF.
When not being used, the DIP switches should be left in the open or OFF
configuration so the pins of the FPGA and CPLD are not tied to ground and can
freely move between logic low and high levels.
The DIP switches also share the same pins as the uppermost four bits of the Flash RAM
address bus. If the Flash RAM is programmed with several FPGA bitstreams, then the
DIP switches can be used to select a particular bitstreams which will be loaded into the
FPGA by the CPLD on power-up. However, this feature is not currently supported by the
CPLD configuration that loads the FPGA from the Flash RAM (XSTOOLS\XSA\fcnfg.svf).
PS/2 Port
The XSA Board provides a PS/2-style interface (mini-DIN connector J4) to either a
keyboard or a mouse. The FPGA receives two signals from the PS/2 interface: a clock
signal and a serial data stream that is synchronized with the falling edge of the clock.
+5V
clk PS/2
Spartan-II 94
data Connector
FPGA 93
(J4)
Pushbutton
(SW2)

Pushbutton
The XSA Board has a single pushbutton that shares the FPGA pin connected to the data
line of the PS/2 port. The pushbutton applies a low level to the FPGA pin when pressed
and a resistor pulls the pin to a high level when the pushbutton is not pressed.
VGA Monitor Interface
The FPGA can generate a video signal for display on a VGA monitor. When the FPGA is
generating VGA signals, the FPGA outputs two bits each of red, green, and blue color
information to a simple resistor-ladder DAC. The outputs of the DAC are sent to the RGB
inputs of a VGA monitor along with the horizontal and vertical sync pulses (/HSYNC,
/VSYNC) from the FPGA.
26 vsync
23 hsync
RED0
12
Spartan-II 13
RED1 red VGA
FPGA 19
GREEN0 Connector
20
GREEN1 green (J3)
BLUE0
21
BLUE1
22 blue
Parallel Port Interface
The parallel port is the main interface for communicating with the XSA Board. Control line
C0 goes directly to the DS1075 oscillator and is used for setting the divisor as described
previously, and status line S6 connects directly to the FPGA for use as a communication
line from the FPGA back to the PC. The CPLD handles the fifteen remaining active lines
of the parallel port as follows.
Three of the parallel port control lines, C1–C3, connect to the JTAG pins through which
the CPLD is programmed. The C1 control line clocks configuration data presented on the
C3 line into the CPLD while the C2 signal steers the actions of the CPLD programming
state machine. Meanwhile, information from the CPLD returns to the PC through status
line S7.
The eight data lines, D0–D7, and the remaining three status lines, S3–S5, connect to
general-purpose pins of the CPLD. The CPLD can be programmed to act as an interface
between the FPGA and the parallel port (the dwnldpar.svf file is an example of such an
interface). Schmitt-trigger inverters are inserted into the D1 line so it can carry a clean
clock edge for use by any state machine programmed into the CPLD. The CPLD
connects to the configuration pins of the Spartan-II FPGA so it can pass bitstreams from
the parallel port to the FPGA. The actual configuration data is presented to the FPGA on
the same 8-bit bus that also connects to the Flash RAM and seven-segment LED. The
CPLD also drives the configuration pins (CCLK, /PROGRAM, /CS, and /WR) of the FPGA

that control the loading of a bitstream. The CPLD uses the M0 input of the FPGA to select
either the slave-serial or master-select configuration mode (M1 and M2 are already hard-
wired to VCC and GND, respectively.) The CPLD can monitor the status of the bitstream
download through the /INIT, DONE, and BSY/DOUT pins of the FPGA.
The CPLD also has access to the FPGA’s JTAG pins: TCK, TMS, TDI, TDO. The TMS,
TDI, and TDO pins share the connections with the BSY/DOUT, /CS, and /WR pins. With
these connections, the CPLD can be programmed with an interface that allows
configuration of the Spartan-II FPGA through the Xilinx iMPACT software. Jumper J9
allows the connection of status pin S7 to the general-purpose CPLD pin that also drives
status pin S5. This is required by the iMPACT software so it can check for the presence of
the downloading cable.
FLASH RAM
8
XC9572XL Spartan-II FPGA
Parallel Port D7 - D0
2 - PPD0 33
3 - PPD1 32
4 - PPD2 31 CCLK
16 37
5 - PPD3 27 /PROGRAM
39 69
6 - PPD4 25 /INIT
38 68
7 - PPD5 24 M0
36 109
8 - PPD6 23 M1
9 - PPD7 22 M2
17 - PPC3 TDI
28 /CS
TMS 15 31
16 - PPC2 29 /WR
TCK 19 30
14 - PPC1 30 BSY/DOUT
TDO 18 38
11 - PPS7 53 DONE
40 72
12 - PPS5 35 TCK
13 2
13 - PPS4 20 TMS
142
15 - PPS3 34 TDI
OSC 32
TDO
34
1 - PPC0 78
10 - PPS6
After the SpartanII FPGA is configured with a bitstream and the DONE pin goes high, the
CPLD switches into a mode that connects the parallel port data and status pins to the
FPGA. This lets you pass data to the FPGA over the parallel port data lines while

receiving data from the FPGA over the status lines. The connections between the FPGA
and the parallel port are shown below.
256 KByte Flash RAM
/RESET
A10
A11
A12
A13
A14
A15
A16
A17
/WE
/OE
/CE
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
11 41
D7 22 12 43
D6 23 49 58
50 59
S3 34 1 40
S4 20 64 29
S5 35 63 28
62 27
61 74
60 75
XC9572XL CPLD
59 76
Spartan-II FPGA
58 66
D0 33 45 50
D1 32 44 48
D2 31 57 42
D3 27 43 47
D4 25 56 65
D5 24 46 51
47 54
52 64
51 63
48 56
2 39
4 44
5 46
6 49
7 57
8 60
9 62
10 67
+5V
S0
S2
S3 S6
S5
S6
S4
DP
S1
8
S5
S2 S3 S1
S0
S4
DP
DIPSW1
DIPSW2
DIPSW3
DIPSW4
The FPGA sends data back to the PC by driving logic levels onto pins 40, 29 and 28
which pass through the CPLD and onto the parallel port status lines S3, S4 and S5,
respectively. Conversely, the PC sends data to the FPGA on parallel port data lines D0–
D7 and the data passes through the CPLD and ends up on FPGA pins 50, 48, 42, 47, 65,
51, 58 and 43, respectively. The FPGA should never drive these pins unless it is
accessing the Flash RAM otherwise the CPLD and/or the FPGA could be damaged. The
CPLD can sense when the FPGA lowers the Flash RAM chip-enable and it will release
the data lines so the FPGA can drive the address, output-enable and write-enable pins of
the Flash RAM without contention.
The CPLD also drives the decimal-point of the LED display to indicate when the FPGA is
configured with a valid bitstream. Unless it is accessing the Flash RAM, the FPGA should
never drive pin 44 to a low logic level or it may damage itself or the CPLD. But when the

FPGA lowers the Flash RAM chip-enable, the CPLD will stop driving the LED decimal-
point to allow the FPGA access to data pin D1 of the Flash RAM.
For more details on how the CPLD manages the interface between the parallel port and
the SpartanII FPGA both before and after device configuration, see the XSA Parallel Port
Interface application note.
Prototyping Header
The pins of the FPGA are accessible through the 84-pin prototyping header on the
underside of the XSA Board. Pin 1 of the header (denoted by a square pad) is located in
the middle of the left-hand edge of the board and the remaining 83 pins are arranged
counter-clockwise around the periphery. The physical dimensions of the prototyping
header and the pin arrangement are shown below.
1.75"
64 63
0.1"
84 4.1"
1
21 22
A subset of the 144 pins on the FPGA’s TQFP package connects to the prototyping
header. The number of the FPGA pin connected to a given header pin is printed next to
the header pin on the board. This makes it easier to find a given FPGA pin when you
want to connect it to an external system. While most of the FPGA pins are already used
to support functions of the XSA Board, they can also be used to interface to external
systems through the prototyping header. The FPGA pins can be grouped into the various
categories shown below. (Pins denoted with * are useable as general-purpose I/O; pins
denoted with ** can be used as general-purpose I/O only if the CPLD interface is

reprogrammed with the alternate parallel port interface stored in the dwnldpa2.svf file; pins
with no marking cannot be used as general-purpose I/O at all.)
Configuration Pins (30*, 31*, 37, 38*, 39*, 44*, 46*, 49*, 57*, 60*, 62*, 67*, 68*, 69, 72,
106, 109, 111): These pins are used to load the SpartanII FPGA with a configuration
bitstream. Some of these pins are dedicated to the configuration process and cannot be
used as general-purpose I/O (37, 69, 72, 106, 109, 111). The rest can be used as
general-purpose I/O after the FPGA is configured. If external logic is connected to these
pins, you may have to disable it during the configuration process. The DONE pin (72) can
be used for this purpose since it goes to a logic high only after the configuration process is
completed.
Flash RAM Pins (27*, 28*, 29*, 39*, 40*, 41*, 42**, 43**, 44*, 46*, 47**, 48**, 49*, 50**,
51**, 54*, 56*, 57*, 58**, 59*, 60*, 62*, 63*, 64*, 65**, 66*, 67*, 74*, 75*, 76*): These pins
are used by the FPGA to access the Flash RAM. They can be used for general-purpose
I/O under the following conditions. When the FPGA is configured from the Flash, the
CPLD drives all these pins so any external logic should be disabled using the DONE pin.
Also, after the configuration, the Flash chip-enable (41) should be driven high to disable
the Flash RAM so it doesn’t drive the data bus pins. In addition, the standard parallel port
interface loaded into the CPLD (dwnldpar.svf) will drive eight of the Flash RAM pins (42,
43, 47, 48, 50, 51, 58, 65) with the logic values found on the eight data lines of the parallel
port. If this is not desired, then use the alternate parallel port interface (dwnldpa2.svf)
which does not drive these pins.
VGA Pins (12*, 13*, 19*, 20*, 21*, 22*, 23*, 26*): When not used to drive a VGA monitor,
these pins can be used for general-purpose I/O through the prototyping header. When
used as I/O, the RED0–RED1 (12–13), GREEN0–GREEN1 (19–20) and BLUE0–BLUE1
(21–22) pairs have an impedance of approximately 1 KΩ between them due to the
presence of the resistor-ladder DAC circuitry.
PS/2 Pins (93*, 94*): When not used to access the PS/2 keyboard/mouse port, these pins
can be used as general-purpose I/O through the prototyping header.
Global Clock Pins (15*, 18*): These pins can be used as global clock inputs or general-
purpose inputs. They cannot be used as outputs.
Free Pins (77*, 78*, 79*, 80*, 83*, 84*, 85*, 86*, 87*): These pins are not connected to
any other devices on the XSA Board so they can be used without restrictions as general-
purpose I/O through the prototyping header.
JTAG Pins (2, 32, 34, 142): These pins are used to access the JTAG features of the
FPGA. They cannot be used as general-purpose I/O pins.

A
XSA Pin Connections
The following tables list the pin numbers of the FPGA and CPLD along with the pin names
of the other chips that they connect to on the XSA Board and the XStend Board. The first
two tables correspond to an XSA Board + XST-2.x combination, while the last two tables
correspond to an XSA Board + XST-1.x combination. Pins marked with * are useable as
general-purpose I/O; pins denoted with ** can be used as general-purpose I/O only if the
CPLD interface is reprogrammed with the alternate parallel port interface stored in the
dwnldpa2.svf file; pins with no marking cannot be used as general-purpose I/O at all.

Connections Between the FPGA and Other XSA Board Components… and the XST-2.x Board
FPGA FPGA Pin CPLD Parallel Switch Switch
Net Name LEDs SDRAM Flash VGA PS/2 Proto. Pin LEDs SRAM IDE Intfc. Stereo Codec USB Serial Port
Pin Function Pin Port Button Button
1 VCCO +3.3V PROTO54
2 TCK FPGA-TCK 13 PROTO16
3* I/O SDRAM-A7
4* I/O SDRAM-A1
5* I/O-VREF0 SDRAM-A6
7* I/O SDRAM-A5
8 GND PROTO52
9 VCCINT +2.5V PROTO22
10 * I/O SDRAM-A3
11 * I/O SDRAM-A4
12 * I/O-VREF0 VGA-RED0 PROTO27
13 * I/O VGA-RED1 PROTO28
14 VCCINT
15 * I-GCK3 FPGA-GCK3 PROTO31
16 VCCO
17 GND
19 * I/O VGA-GREEN0 PROTO29
21 * I/O-VREF1 VGA-BLUE0 PROTO33
22 * I/O VGA-BLUE1 PROTO34
23 * I/O VGA-HSYNC# PROTO36 PUSHB4
24 VCCINT
25 GND
26 * I/O VGA-VSYNC# PROTO37 PUSHB3
27 * I/O-VREF1 62 FLASH-A3 PROTO50 LED2-B RAM-A0 IDE-DMARQ
28 * I/O-VREF1 63 PP-S5 FLASH-A2 PROTO51 LED2-E RAM-A10 USB-INT#
29 * I/O 64 PP-S4 FLASH-A1 PROTO56 LED2-G RAM-A11 USB-SUSPEND
30 * I/O-WRITE# FPGA-WR# 19 PROTO69 DIPSW1
31 * I/O-CS# FPGA-CS# 15 PROTO68 IDE-RESET#
32 TDI FPGA-TDI 15 PROTO15
33 GND
34 TDO FPGA-TDO 19 PROTO30
35 VCCO
36 VCCO
37 CCLK FPGA-CCLK 16 PROTO73
38 * I/O-DOUT/BSY FPGA-DOUT-BSY 18 PROTO45 LED2-DP RAM-A1 IDE-DMACK#
39 * I/O-D0 FPGA-DIN-D0 2 LED-S1 FLASH-D0 PROTO71 BARLED9 RAM-A16 IDE-IORDY
40 * I/O 1 PP-S3 FLASH-A0 PROTO57 LED2-C RAM-A9 IDE-INTRQ
41 * I/O-VREF2 11 FLASH-CE# PROTO65
42 ** I/O 57 PP-D2 FLASH-A10 PROTO58 LED2-F RAM-A8 IDE-D8
43 ** I/O-VREF2 12 PP-D7 FLASH-OE# PROTO61 RAM-OE# IDE-D9
44 * I/O-D1 FPGA-D1 4 LED-DP FLASH-D1 PROTO40 BARLED2 RAM-D6 IDE-D1
45 GND
46 * I/O-D2 FPGA-D2 5 LED-S4 FLASH-D2 PROTO39 BARLED3 RAM-D5 IDE-D2
47 ** I/O 43 PP-D3 FLASH-A11 PROTO59 LED2-D RAM-A13 IDE-D10
48 ** I/O-VREF2 44 PP-D1 FLASH-A9 PROTO60 LED2-A RAM-A15 IDE-D11
50 ** I/O 45 PP-D0 FLASH-A8 PROTO78 LED1-G RAM-A14 IDE-D12
51 ** I/O-IRDY 46 PP-D5 FLASH-A13 PROTO79 LED1-B RAM-A12 IDE-D13
52 GND
53 VCCO
54 * I/O-TRDY 47 DIPSW1A FLASH-A14 PROTO82 LED1-F RAM-A7 IDE-CS0#
55 VCCINT
56 * I/O 48 DIPSW1D FLASH-A17 PROTO83 LED1-A RAM-A6 IDE-CS1#
58 ** I/O-VREF3 49 PP-D6 FLASH-WE# PROTO62 DIPSW2 RAM-WE# IDE-D14
59 * I/O 50 FLASH-RESET# PROTO66 BARLED10 AUDIO-LRCK
60 * I/O-D5 FPGA-D5 8 LED-S3 FLASH-D5 PROTO80 BARLED7 RAM-D0 IDE-D6 RS232-RD
61 GND
62 * I/O-D6 FPGA-D6 9 LED-S2 FLASH-D6 PROTO81 BARLED6 RAM-D1 IDE-D5 RS232-CTS
63 * I/O-VREF3 51 DIPSW1C FLASH-A16 PROTO84 LED1-DP RAM-A5 IDE-DA2
64 * I/O 52 DIPSW1B FLASH-A15 PROTO3 LED1-D RAM-A4 IDE-DA0
65 ** I/O-VREF3 56 PP-D4 FLASH-A12 PROTO4 LED1-C RAM-A3 IDE-D15
66 * I/O 58 FLASH-A7 PROTO5 DIPSW5 RAM-A2 IDE-DA1
68 * I/O-INIT# FPGA-INIT# 38 PROTO41 BARLED1 RAM-D7 IDE-D0
69 PROG# FPGA-PROG# 39 PROTO55 PUSHB1
70 VCCO
71 VCCO
72 DONE FPGA-DONE 40 PROTO53
73 GND
74 * I/O 61 FLASH-A4 PROTO70 DIPSW3 AUDIO-SDTI
75 * I/O 60 FLASH-A5 PROTO77 DIPSW4 AUDIO-SCLK
76 * I/O 59 FLASH-A6 PROTO6 LED1-E AUDIO-SDTO
77 * I/O-VREF4 PROTO9 DIPSW6 AUDIO-MCLK
78 * I/O PP-S6 PROTO67 PUSHB2
79 * I/O-VREF4 PROTO7 DIPSW8 RAM-CE#
80 * I/O PROTO8 DIPSW7 RS232-RTS
81 GND
82 VCCINT
83 * I/O PROTO18 RS232-TD
FPGA FPGA Pin CPLD Parallel Switch Switch
Net Name LEDs SDRAM Flash VGA PS/2 Proto. Pin LEDs SRAM IDE Intfc. Stereo Codec USB Serial Port
Pin Function Pin Port Button Button
84 * I/O PROTO19 USB-SCL
85 * I/O-VREF4 PROTO20 USB-SDA
86 * I/O PROTO23 IDE-DIOR#
87 * I/O PROTO24 IDE-DIOW#
88 I-GCK0 MASTER-CLK 42 PROTO13
89 GND
90 VCCO
91 I-GCK1 FPGA-GCK1 SDRAM-CLKFB
92 VCCINT
93 * I/O PUSHB PS2-DATA PROTO25
94 * I/O-VREF5 PS2-CLK PROTO26
95 * I/O SDRAM-Q0
96 * I/O SDRAM-Q15
97 VCCINT
98 GND
99 * I/O SDRAM-Q1
100 * I/O-VREF5 SDRAM-Q14
101 * I/O SDRAM-Q2
103 * I/O SDRAM-Q3
104 N/C
105 N/C
106 M2 FPGA-M2 PROTO12
107 VCCO
108 VCCO
109 M0 FPGA-M0 36 PROTO14
110 GND
112 * I/O SDRAM-Q12
113 * I/O SDRAM-Q4
114 * I/O SDRAM-Q11
116 * I/O SDRAM-Q10
118 * I/O SDRAM-Q9
119 GND
120 * !/O SDRAM-Q7
121 * I/O SDRAM-Q8
122 * I/O-VREF6 SDRAM-QML
123 * I/O SDRAM-WE#
124 * I/O SDRAM-QMH
125 VCCINT
126 * I/O-TRDY SDRAM-CAS#
127 VCCO
128 GND
129 * I/O-IRDY SDRAM-CLK
130 * I/O SDRAM-RAS#
131 * I/O SDRAM-CKE
132 * I/O-VREF7 SDRAM-CS#
133 * I/O SDRAM-A12
134 * I/O SDRAM-BA0
135 GND
136 * I/O SDRAM-A11
137 * I/O-VREF7 SDRAM-BA1
138 * I/O SDRAM-A9
139 * I/O-VREF7 SDRAM-A10
140 * I/O SDRAM-A8
141 * I/O SDRAM-A0
142 TMS FPGA-TMS 18 PROTO17
143 GND
144 VCCO
Connections Between the CPLD and Other XSA Board Components… and the XST-2.x Board
Switch Switch
CPLD Pin CPLD Pin Function Net Name FPGA Pin Parallel Port LEDs Flash Proto. Pin LEDs SRAM IDE Intfc. Stereo Codec USB Serial Port
Button Button
1 40 * PP-S3 FLASH-A0 PROTO57 LED2-C RAM-A9 IDE-INTRQ
2 FPGA-DIN-D0 39 * LED-S1 FLASH-D0 PROTO71 BARLED9 RAM-A16 IDE-IORDY
3 VCCINT
4 FPGA-D1 44 * LED-DP FLASH-D1 PROTO40 BARLED2 RAM-D6 IDE-D1
5 FPGA-D2 46 * LED-S4 FLASH-D2 PROTO39 BARLED3 RAM-D5 IDE-D2
8 FPGA-D5 60 * LED-S3 FLASH-D5 PROTO80 BARLED7 RAM-D0 IDE-D6 RS232-RD
9 FPGA-D6 62 * LED-S2 FLASH-D6 PROTO81 BARLED6 RAM-D1 IDE-D5 RS232-CTS
11 41 * FLASH-CE# PROTO65
12 43 ** PP-D7 FLASH-OE# PROTO61 RAM-OE# IDE-D9
13 FPGA-TCK 2 PROTO16
14 GND
15 GCK1 FPGA-CS# 31 * PROTO68 IDE-RESET#
15 GCK1 FPGA-TDI 32 PROTO15
16 GCK2 FPGA-CCLK 37 PROTO73
17 GCK3 PROG-OSC
18 FPGA-DOUT-BSY 38 * PROTO45 LED2-DP RAM-A1 IDE-DMACK#
18 FPGA-TMS 142 PROTO17
19 FPGA-WR# 30 * PROTO69 DIPSW1
19 FPGA-TDO 34 PROTO30
20 PPORT-S4
21 GND
22 PPORT-D7
23 PPORT-D6
24 PPORT-D5
25 PPORT-D4
26 VCCIO
27 PPORT-D3
28 TDI PPORT-C3
29 TMS PPORT-C2
30 TCK PPORT-C1
31 PPORT-D2
32 PPORT-D1
33 PPORT-D0
34 PPORT-S3
35 PPORT-S5
36 FPGA-M0 109 PROTO14
37 VCCINT
38 FPGA-INIT# 68 * PROTO41 BARLED1 RAM-D7 IDE-D0
39 FPGA-PROG# 69 PROTO55 PUSHB1
40 FPGA-DONE 72 PROTO53
41 GND
42 MASTER-CLK 88 PROTO13
43 47 ** PP-D3 FLASH-A11 PROTO59 LED2-D RAM-A13 IDE-D10
44 48 ** PP-D1 FLASH-A9 PROTO60 LED2-A RAM-A15 IDE-D11
45 50 ** PP-D0 FLASH-A8 PROTO78 LED1-G RAM-A14 IDE-D12
46 51 ** PP-D5 FLASH-A13 PROTO79 LED1-B RAM-A12 IDE-D13
47 54 * DIPSW1A FLASH-A14 PROTO82 LED1-F RAM-A7 IDE-CS0#
48 56 * DIPSW1D FLASH-A17 PROTO83 LED1-A RAM-A6 IDE-CS1#
49 58 ** PP-D6 FLASH-WE# PROTO62 DIPSW2 RAM-WE# IDE-D14
50 59 * FLASH-RESET# PROTO66 BARLED10 AUDIO-LRCK
51 63 * DIPSW1C FLASH-A16 PROTO84 LED1-DP RAM-A5 IDE-DA2
52 64 * DIPSW1B FLASH-A15 PROTO3 LED1-D RAM-A4 IDE-DA0
53 TDO PPORT-S7
54 GND
55 VCCIO
56 65 ** PP-D4 FLASH-A12 PROTO4 LED1-C RAM-A3 IDE-D15
57 42 ** PP-D2 FLASH-A10 PROTO58 LED2-F RAM-A8 IDE-D8
58 66 * FLASH-A7 PROTO5 DIPSW5 RAM-A2 IDE-DA1
59 76 * FLASH-A6 PROTO6 LED1-E AUDIO-SDTO
60 75 * FLASH-A5 PROTO77 DIPSW4 AUDIO-SCLK
61 74 * FLASH-A4 PROTO70 DIPSW3 AUDIO-SDTI
62 27 * FLASH-A3 PROTO50 LED2-B RAM-A0 IDE-DMARQ
63 28 * PP-S5 FLASH-A2 PROTO51 LED2-E RAM-A10 USB-INT#
64 29 * PP-S4 FLASH-A1 PROTO56 LED2-G RAM-A11 USB-SUSPEND
FPGA FPGA Pin CPLD Parallel Switch
Net Name LEDs SDRAM Flash VGA PS/2 Proto. Pin LEDs Switch Button SRAM VGA Stereo Codec PS/2 Xchecker
Pin Function Pin Port Button
1 VCCO +3.3V PROTO54
2 TCK FPGA-TCK 13 PROTO16 XCHK-TCK
3* I/O SDRAM-A7
4* I/O SDRAM-A1
7* I/O SDRAM-A5
8 GND PROTO52
9 VCCINT +2.5V PROTO22
10 * I/O SDRAM-A3
11 * I/O SDRAM-A4
12 * I/O-VREF0 VGA-RED0 PROTO27
13 * I/O VGA-RED1 PROTO28 RLED-DP# RAM-A15
14 VCCINT
16 VCCO
17 GND
20 * I/O VGA-GREEN1 PROTO32 XCHK-RT
21 * I/O-VREF1 VGA-BLUE0 PROTO33
22 * I/O VGA-BLUE1 PROTO34
23 * I/O VGA-HSYNC# PROTO36
24 VCCINT
25 GND
26 * I/O VGA-VSYNC# PROTO37 PUSH-RESET#
27 * I/O-VREF1 62 FLASH-A3 PROTO50 RLED-S4# RAM-A12
28 * I/O-VREF1 63 PP-S5 FLASH-A2 PROTO51 RLED-S2# RAM-A10
29 * I/O 64 PP-S4 FLASH-A1 PROTO56 RLED-S3# RAM-A11
30 * I/O-WRITE# FPGA-WR# 19 PROTO69 DIPSW8 X-PS2-DATA
31 * I/O-CS# FPGA-CS# 15 PROTO68 X-PS2-CLK
32 TDI FPGA-TDI 15 PROTO15 XCHK-TDI
33 GND
34 TDO FPGA-TDO 19 PROTO30 XCHK-RD
35 VCCO
36 VCCO
37 CCLK FPGA-CCLK 16 PROTO73 XCHK-CCLK
38 * I/O-DOUT/BSY FPGA-DOUT-BSY 18 PROTO45
39 * I/O-D0 FPGA-DIN-D0 2 LED-S1 FLASH-D0 PROTO71 XCHK-DIN
40 * I/O 1 PP-S3 FLASH-A0 PROTO57 RLED-S1# RAM-A9
41 * I/O-VREF2 11 FLASH-CE# PROTO65 RAM-CE#
42 ** I/O 57 PP-D2 FLASH-A10 PROTO58 RLED-S5# RAM-A13
43 ** I/O-VREF2 12 PP-D7 FLASH-OE# PROTO61 RAM-OE#
44 * I/O-D1 FPGA-D1 4 LED-DP FLASH-D1 PROTO40 BARLED2 RAM-D1
45 GND
46 * I/O-D2 FPGA-D2 5 LED-S4 FLASH-D2 PROTO39 BARLED3 RAM-D2
47 ** I/O 43 PP-D3 FLASH-A11 PROTO59 RLED-S0# RAM-A8
48 ** I/O-VREF2 44 PP-D1 FLASH-A9 PROTO60 RLED-S6# RAM-A14
50 ** I/O 45 PP-D0 FLASH-A8 PROTO78 LLED-S3# RAM-A3
51 ** I/O-IRDY 46 PP-D5 FLASH-A13 PROTO79 LLED-S4# RAM-A4
52 GND
53 VCCO
54 * I/O-TRDY 47 DIPSW1A FLASH-A14 PROTO82 LLED-S5# RAM-A5
55 VCCINT
56 * I/O 48 DIPSW1D FLASH-A17 PROTO83 LLED-S6# RAM-A6
58 ** I/O-VREF3 49 PP-D6 FLASH-WE# PROTO62 RAM-WE#
59 * I/O 50 FLASH-RESET# PROTO66 DIPSW7 CODEC-LRCK
61 GND
63 * I/O-VREF3 51 DIPSW1C FLASH-A16 PROTO84 LLED-DP# RAM-A7
64 * I/O 52 DIPSW1B FLASH-A15 PROTO3 LLED-S0# RAM-A0
65 ** I/O-VREF3 56 PP-D4 FLASH-A12 PROTO4 LLED-S1# RAM-A1
66 * I/O 58 FLASH-A7 PROTO5 LLED-S2# RAM-A2
68 * I/O-INIT# FPGA-INIT# 38 PROTO41 BARLED1 RAM-D0 XCHK-INIT#
69 PROG# FPGA-PROG# 39 PROTO55 PUSH-PROG# XCHK-PROG#
70 VCCO
71 VCCO
72 DONE FPGA-DONE 40 PROTO53 XCHK-DONE
73 GND
74 * I/O 61 FLASH-A4 PROTO70 DIPSW6 CODEC-SDIN
75 * I/O 60 FLASH-A5 PROTO77 DIPSW5 CODEC-SCLK
76 * I/O 59 FLASH-A6 PROTO6 DIPSW4 CODEC-SDOUT
77 * I/O-VREF4 PROTO9 DIPSW3 CODEC-MCLK XCHK-CLKO
78 * I/O PP-S6 PROTO67 PUSH-SPARE# X-VGA-VSYNC#
79 * I/O-VREF4 PROTO7 DIPSW1 RAM-LCE# XCHK-TRIG
80 * I/O PROTO8 DIPSW2 RAM-RCE# XCHK-RST
81 GND
82 VCCINT
83 * I/O PROTO18 X-VGA-RED1
84 * I/O PROTO19 X-VGA-HSYNC#
85 * I/O-VREF4 PROTO20 X-VGA-GREEN1
FPGA FPGA Pin CPLD Parallel Switch
Net Name LEDs SDRAM Flash VGA PS/2 Proto. Pin LEDs Switch Button SRAM VGA Stereo Codec PS/2 Xchecker
Pin Function Pin Port Button
86 * I/O PROTO23 X-VGA-RED0
87 * I/O PROTO24 X-VGA-GREEN0
88 I-GCK0 MASTER-CLK 42 PROTO13 XCHK-CLKI
89 GND
90 VCCO
91 I-GCK1 FPGA-GCK1 SDRAM-CLKFB
92 VCCINT
93 * I/O PUSHB PS2-DATA PROTO25 X-VGA-BLUE0
94 * I/O-VREF5 PS2-CLK PROTO26 X-VGA-BLUE1
95 * I/O SDRAM-Q0
96 * I/O SDRAM-Q15
97 VCCINT
98 GND
99 * I/O SDRAM-Q1
101 * I/O SDRAM-Q2
103 * I/O SDRAM-Q3
104 N/C
105 N/C
107 VCCO
108 VCCO
109 M0 FPGA-M0 36 PROTO14
110 GND
112 * I/O SDRAM-Q12
113 * I/O SDRAM-Q4
114 * I/O SDRAM-Q11
116 * I/O SDRAM-Q10
118 * I/O SDRAM-Q9
119 GND
120 * !/O SDRAM-Q7
121 * I/O SDRAM-Q8
122 * I/O-VREF6 SDRAM-QML
123 * I/O SDRAM-WE#
124 * I/O SDRAM-QMH
125 VCCINT
126 * I/O-TRDY SDRAM-CAS#
127 VCCO
128 GND
129 * I/O-IRDY SDRAM-CLK
130 * I/O SDRAM-RAS#
131 * I/O SDRAM-CKE
132 * I/O-VREF7 SDRAM-CS#
133 * I/O SDRAM-A12
134 * I/O SDRAM-BA0
135 GND
136 * I/O SDRAM-A11
137 * I/O-VREF7 SDRAM-BA1
138 * I/O SDRAM-A9
139 * I/O-VREF7 SDRAM-A10
140 * I/O SDRAM-A8
141 * I/O SDRAM-A0
142 TMS FPGA-TMS 18 PROTO17 XCHK-TMS
143 GND
144 VCCO
Connections Between the CPLD and Other XSA Board Components… and the XST-1.x Board
Switch
CPLD Pin CPLD Pin Function Net Name FPGA Pin Parallel Port LEDs Flash Proto. Pin LEDs Switch Button SRAM Stereo Codec PS/2 Xchecker
Button
1 40 * PP-S3 FLASH-A0 PROTO57 RLED-S1# RAM-A9
2 FPGA-DIN-D0 39 * LED-S1 FLASH-D0 PROTO71 XCHK-DIN
3 VCCINT
4 FPGA-D1 44 * LED-DP FLASH-D1 PROTO40 BARLED2 RAM-D1
5 FPGA-D2 46 * LED-S4 FLASH-D2 PROTO39 BARLED3 RAM-D2
11 41 * FLASH-CE# PROTO65 RAM-CE#
12 43 ** PP-D7 FLASH-OE# PROTO61 RAM-OE#
13 FPGA-TCK 2 PROTO16 XCHK-TCK
14 GND
15 GCK1 FPGA-CS# 31 * PROTO68 X-PS2-CLK
15 GCK1 FPGA-TDI 32 PROTO15 XCHK-TDI
16 GCK2 FPGA-CCLK 37 PROTO73 XCHK-CCLK
17 GCK3 PROG-OSC
18 FPGA-DOUT-BSY 38 * PROTO45
18 FPGA-TMS 142 PROTO17 XCHK-TMS
19 FPGA-WR# 30 * PROTO69 DIPSW8 X-PS2-DATA
19 FPGA-TDO 34 PROTO30 XCHK-RD
20 PPORT-S4
21 GND
22 PPORT-D7
23 PPORT-D6
24 PPORT-D5
25 PPORT-D4
26 VCCIO
27 PPORT-D3
28 TDI PPORT-C3
29 TMS PPORT-C2
30 TCK PPORT-C1
31 PPORT-D2
32 PPORT-D1
33 PPORT-D0
34 PPORT-S3
35 PPORT-S5
36 FPGA-M0 109 PROTO14
37 VCCINT
38 FPGA-INIT# 68 * PROTO41 BARLED1 RAM-D0 XCHK-INIT#
39 FPGA-PROG# 69 PROTO55 PUSH-PROG# XCHK-PROG#
40 FPGA-DONE 72 PROTO53 XCHK-DONE
41 GND
42 MASTER-CLK 88 PROTO13 XCHK-CLKI
43 47 ** PP-D3 FLASH-A11 PROTO59 RLED-S0# RAM-A8
45 50 ** PP-D0 FLASH-A8 PROTO78 LLED-S3# RAM-A3
47 54 * DIPSW1A FLASH-A14 PROTO82 LLED-S5# RAM-A5
48 56 * DIPSW1D FLASH-A17 PROTO83 LLED-S6# RAM-A6
49 58 ** PP-D6 FLASH-WE# PROTO62 RAM-WE#
50 59 * FLASH-RESET# PROTO66 DIPSW7 CODEC-LRCK
51 63 * DIPSW1C FLASH-A16 PROTO84 LLED-DP# RAM-A7
52 64 * DIPSW1B FLASH-A15 PROTO3 LLED-S0# RAM-A0
53 TDO PPORT-S7
54 GND
55 VCCIO
58 66 * FLASH-A7 PROTO5 LLED-S2# RAM-A2
59 76 * FLASH-A6 PROTO6 DIPSW4 CODEC-SDOUT
60 75 * FLASH-A5 PROTO77 DIPSW5 CODEC-SCLK
61 74 * FLASH-A4 PROTO70 DIPSW6 CODEC-SDIN
62 27 * FLASH-A3 PROTO50 RLED-S4# RAM-A12
B
XSA Schematics
The following pages show the detailed schematics for the XSA Board.

xsa1_2.sch-1 - Mon Feb 11 08:37:19 2002
xsa1_2.sch-2 - Mon Feb 11 08:37:19 2002
xsa1_2.sch-3 - Mon Feb 11 08:37:19 2002
xsa1_2.sch-4 - Mon Feb 11 08:37:19 2002
xsa1_2.sch-5 - Mon Feb 11 08:37:19 2002
xsa1_2.sch-6 - Mon Feb 11 08:37:19 2002
xsa1_2.sch-7 - Mon Feb 11 08:37:20 2002
xsa1_2.sch-8 - Mon Feb 11 08:37:20 2002
xsa1_2.sch-9 - Mon Feb 11 08:37:20 2002
XST-1 XStend Prototyping
Extender Board
XST-1 The XStend Board provides additional support circuitry that the XS40, XS95,
and CSoC Boards can access through their breadboard interfaces. This
circuitry extends the range of applications of the XS Boards into three new
● XS40/XS95/CSoC Board
areas:
connector
● prototyping area
● pushbuttons (3) ● The pushbuttons, DIP switches, LEDs, and prototyping area are useful
● DIP switch for basic lab experiments.
● LED digits (2) ● The VGA monitor interface, PS/2 interface and additional static RAM let
● LED bargraph you perform video and computing experiments.
● 20-bit stereo codec ● The stereo codec and dual-channel analog I/O circuitry are useful for
● stereo in/out ports processing audio signals in combination with DSP components
● VGA monitor port synthesized with XILINX's CORE generation software.
● mouse/keyboard PS/2 port
● daughterboard connector
● optional 64K SRAM
XST-2 XStend Prototyping
Extender Board
XST-2
● Not compatible with XS95, the XStend Board provides additional support circuitry that the XSA Boards can
XS40 or CSoC Boards!! access through their prototyping interfaces. This circuitry extends the range of
● XSA Board connector applications of the XSA Boards into these new areas:
● pushbuttons (4)
● DIP switch ● The pushbuttons, DIP switches, LEDs, and prototyping area are useful
● LED digits (2) for basic lab experiments.
● LED bargraph ● The static RAM can be used when the larger SDRAM on the XSA
● 128 KByte SRAM Board is overkill for a particular application.
● 20-bit stereo codec ● The stereo codec and dual-channel analog I/O circuitry are useful for
● stereo in/out ports processing audio signals in combination with DSP components
● USB 1.1 peripheral-mode synthesized with XILINX's CORE generation software.
interface ● The USB 1.1 interface lets the XSA Board appear as a low-speed or full-
● RS-232 serial port speed USB peripheral to a PC.
● IDE hard disk interface ● The RS-232 interface is useful when the XSA Board needs to send
● prototyping area information over a low-speed serial communication link.
● daughterboard connector ● The IDE interface provides the XSA Board with access to a hard disk
for data storage and retrieval.
XST-2.0 Board picture
picture of XST-2.0 Board mated with XSA Board
XStend Board V1.2 Manual
XESS Corporation
Copyright ©1998 by X Engineering Software Systems Corporation.
All XS-prefix product designations are trademarks of X Engineering Software Systems.
All XC-prefix product designations are trademarks of Xilinx
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in
any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior
written permission of the publisher. Printed in the United States of America.
Limited Warranty
X Engineering Software Systems Corp. (XESS) warrants that the Product, in the course of its normal use, will be
free from defects in material and workmanship for a period of one (1) year and will conform to XESS’s
specification therefor. This limited warranty shall commence on the date appearing on your purchase receipt.
XESS shall have no liability for any Product returned if XESS determines that the asserted defect a) is not present,
b) cannot reasonably be rectified because of damage occurring before XESS receives the Product, or c) is
attributable to misuse, improper installation, alteration, accident or mishandling while in your possession. Subject
to the limitations specified above, your sole and exclusive warranty shall be, during the period of warranty
specified above and at XESS’s option, the repair or replacement of the product. The foregoing warranty of XESS
shall extend to repaired or replaced Products for the balance of the applicable period of the original warranty or
thirty (30) days from the date of shipment of a repaired or replaced Product, whichever is longer.
THE FOREGOING LIMITED WARRANTY IS XESS’S SOLE WARRANTY AND IS APPLICABLE ONLY TO
PRODUCTS SOLD AS NEW. THE REMEDIES PROVIDED HEREIN ARE IN LIEU OF a) ANY AND ALL
OTHER REMEDIES AND WARRANTIES, WHETHER EXPRESSED OR IMPLIED OR STATUTORY,
INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS
FOR A PARTICULAR PURPOSE, AND b) ANY AND ALL OBLIGATIONS AND LIABILITIES OF XESS
FOR DAMAGES INCLUDING, BUT NOT LIMITED TO ACCIDENTAL, CONSEQUENTIAL, OR SPECIAL
DAMAGES, OR ANY FINANCIAL LOSS, LOST PROFITS OR EXPENSES, OR LOST DATA ARISING OUT
OF OR IN CONNECTION WITH THE PURCHASE, USE OR PERFORMANCE OF THE PRODUCT, EVEN IF
In the United States, some statutes do not allow exclusion or limitations of incidental or consequential damages,
so the limitations above may not apply to you. This warranty gives you specific legal rights, and you may also
have other rights which vary from state to state.
Table of Contents
1 XStend Overview ......................................................... 3
2 XStend Board Features ................................................... 4
2.1 XS40/XS95 Board Mounting Area ........................................ 6
2.2 LEDs ................................................................. 6
2.3 Switches ............................................................. 9
2.4 VGA Interface ....................................................... 10
2.5 PS/2 Keyboard Interface ............................................. 11
2.6 RAMs ................................................................ 11
2.7 Stereo Codec ........................................................ 13
2.8 XILINX Xchecker Interface ........................................... 15
2.9 Prototyping Area .................................................... 17
2.10 Daughterboard Connector ............................................. 18
3 XStend Board Programmer’s Model ........................................ 18
4 Example Designs for the XStend Board ................................... 23
4.1 Displaying Switch Settings on the LEDs .............................. 23
4.2 Displaying Graphics from RAM Through the VGA Interface .............. 27
4.2.1 VGA Color Signals................................................ 27
4.2.2 VGA Signal Timing................................................ 28
4.2.3 VGA Signal Generator Algorithm................................... 29
4.2.4 VGA Signal Generator in VHDL..................................... 31
4.3 Reading Keyboard Scan Codes Through the PS/2 Interface .............. 39
4.4 Inputing and Outputing Stereo Signals Through the Codec ............. 44
5 XStend V1.2 Schematics ................................................. 61

Getting Help!
If you follow the instructions in this manual and you encounter problems, here are some places to
get help:
• If you can't get the XStend Board hardware to work, send an e-mail message describing your
problem to fpga-bugs@xess.com or check our web site at
http://www.xess.com/FPGA.
• If you can't get your XILINX software tools installed properly, send an e-mail message
describing your problem to hotline@xilinx.com or check their web site at
http://www.xilinx.com/support/searchtd.htm.
1 XStend Overview
The XS40 and XS95 Boards offer a flexible, low-cost method of prototyping FPGA and CPLD
designs. However, their small physical size limits the amount of support circuitry they can hold.
The XStend Board removes this limitation by providing additional support circuitry that the
XS40 and XS95 Boards can access through their breadboard interfaces.
The XStend Board contains resources that extend the range of applications of the XS Boards
into three areas:
• The pushbuttons, DIP switches, LEDs, and prototyping area are useful for basic lab
experiments. These features in combination with the XS Boards replicates the functionality
of the older HW/UW FPGABOARD.
• The VGA monitor interface, PS/2 keyboard/mouse interface, and static RAM let the XS
Boards be used in video and computing experiments.
• The stereo codec and dual-channel analog input/output circuitry are useful for processing of
audio signals in combination with DSP circuits synthesized with XILINX's CORE generation
software.
2 XStend Board Features
The XStend Board extends the capabilities of the XS40 and XS95 Boards by providing:
• mounting sockets for both an XS40 and an XS95 Board;
• additional bargraph LED and LED digits;
• pushbutton and DIP switches;
• an interface to VGA monitors;
• an interface to a PS/2-style keyboard or mouse;
• an additional 64 Kbytes of static RAM (optional);
• a stereo codec with left/right input and output channels.
• an interface to the XILINX Xchecker cable;
• a 2.75"×3.5" prototyping area with selectable 3.3V or 5V supply;
• a 42×2 header connector for add-on daughterboards.
These resources are shown in the simplified view of the XStend Board (Figure 1). Each of these
resources will be described below.
Figure 1: XStend Board layout.
2.1 XS40/XS95 Board Mounting Area
An XS40 or XS95 Board is mounted on the XStend Board using the XS Board mounting
sockets. These sockets mate with the breadboard interface pins of the XS Boards to give them
access to all the resources of the XStend Board. To use an XS40 Board with the XStend Board,
insert it into the right-most columns of the socket strips. When using an XS95 Board, you
should insert it into the left-most columns of the sockets. There are markings on the XStend
Board to indicate the appropriate column for each type of XS Board.
If the XS Board is connected to a power supply through jack J9, then its power regulation
circuitry will supply VCC and GND to the XStend Board through the mounting sockets. XS40
Boards with 3.3V FPGAs will supply both 3.3V and 5V to the XStend Board, while XS40
Boards with 5V FPGAs and XS95 Boards will supply only 5V.
*Warning: Version 1.0 of the XS40 Board with a 3.3V XC4000XL FPGA will not work with
the XStend Board because it supplies 3.3V but no 5V! You must replace the XC4000XL
FPGA with an XC4000E FPGA and remove the J8 jumper to switch the board to 5V
operation.
External voltage supplies can also be used with the XStend Board. A 5V power supply can be
connected to header J12 and a 3.3V supply can be attached to header J14 as shown in Figure 2.
These supplies will power the attached XS Board as well as the XStend electronics.
Figure 2: Connection of external power supplies to the XStend Board.
*Warning: Do not attach external voltage supplies while also supplying power to the XStend
Board with an XS Board.
*Warning: Never place shunts on either J12 or J14 or you will short the power supplies to
ground and damage the XStend Board and the attached XS Board..
2.2 LEDs
The XStend Board provides a bargraph LED with eight LEDs (D1—D8) and two more LED
displays (U1 and U2) for use by an XS Board. All of these LEDs are active-low meaning that an
LED segment will glow when a logic-low is applied to it.
The LEDs are enabled and disabled by setting the shunts on the 3-pin jumpers as described in
Table 1 and as shown in Figure 3.
Table 1: Jumper settings for XStend LEDs.
Jumper Setting
J8 Removing the shunt on this jumper disconnects the

power from bargraph LEDs D1—D8. Placing the shunt
on the lower two pins of the jumper enables the LEDs
for use with an XS95 Board inserted in the XStend
Board. The LEDs can be used with an XS40 Board if
the shunt is placed on the upper two pins.

power from left LED digit U1. Placing the shunt on the
lower two pins of the jumper enables the LED digit for
use with an XS95 Board inserted in the XStend Board.
The LED digit can be used with an XS40 Board if the
shunt is placed on the upper two pins.

power from right LED digit U2. Placing the shunt on
the lower two pins of the jumper enables the LED digit
for use with an XS95 Board inserted in the XStend
Board. The LED digit can be used with an XS40 Board
if the shunt is placed on the upper two pins.
Figure 3: Shunt placement for setting the XStend Board LED supply voltages.
Listings 1 and 2 show the connections from the XS40 and XS95 Boards to the LEDs on the
XStend Board expressed as UCF constraints (for the UCF syntax and usage tips, check out
http://www.xilinx.com/techdocs/2449.htm).
Listing 1: Connections between the XStend LEDs and the XS40.
# LEFT LED DIGIT SEGMENT CONNECTIONS (ACTIVE-LOW)
NET LSB<0> LOC=P3;
NET LSB<1> LOC=P4;
NET LSB<2> LOC=P5;
NET LSB<3> LOC=P78;
NET LSB<4> LOC=P79;
NET LSB<5> LOC=P82;
NET LSB<6> LOC=P83;
NET LDPB LOC=P84;
#
# RIGHT LED DIGIT SEGMENT CONNECTIONS (ACTIVE-LOW)
NET RSB<0> LOC=P59;
NET RSB<1> LOC=P57;
NET RSB<2> LOC=P51;
NET RSB<3> LOC=P56;
NET RSB<4> LOC=P50;
NET RSB<5> LOC=P58;
NET RSB<6> LOC=P60;
NET RDPB LOC=P28;
#
# INDIVIDUAL LED CONNECTIONS (ACTIVE-LOW)
NET DB<1> LOC=P41;
NET DB<2> LOC=P40;
NET DB<3> LOC=P39;
NET DB<4> LOC=P38;
NET DB<5> LOC=P35;
NET DB<6> LOC=P81;
NET DB<7> LOC=P80;
NET DB<8> LOC=P10;
NET LSB<0> LOC=P1;
NET LSB<1> LOC=P2;
NET LSB<2> LOC=P3;
NET LSB<3> LOC=P75;
NET LSB<4> LOC=P79;
NET LSB<5> LOC=P82;
NET LSB<6> LOC=P83;
NET LDPB LOC=P84;
#
NET RSB<0> LOC=P58;
NET RSB<1> LOC=P56;
NET RSB<2> LOC=P54;
NET RSB<3> LOC=P55;
NET RSB<4> LOC=P53;
NET RSB<5> LOC=P57;
NET RSB<6> LOC=P61;
NET RDPB LOC=P34;
#
NET DB<1> LOC=P44;
NET DB<2> LOC=P43;
NET DB<3> LOC=P41;
NET DB<4> LOC=P40;
NET DB<5> LOC=P39;
NET DB<6> LOC=P37;
NET DB<7> LOC=P36;
NET DB<8> LOC=P35;
2.3 Switches
The XStend has a bank of eight DIP switches and two pushbuttons (labeled SPARE and RESET)
that are accessible from an XS Board. (There is a third pushbutton labeled PROGRAM which is
used to initiate the programming of the XS40 Board. It is not intended to be a general-purpose
input.)
When closed or ON, each DIP switch pulls the connected pin of the XS Board to ground. When
the DIP switch is open or OFF, the pin is pulled high through a 10KΩ resistor.
*When not being used, the DIP switches should be left in the open or OFF configuration so
the pins of the XS Board are not tied to ground and can freely move between logic low and
high levels.
When pressed, each pushbutton pulls the connected pin of the XS Board to ground. Otherwise,
the pin is pulled high through a 10 KΩ resistor.
Listings 3 and 4 show the connections from the XS40 and XS95 Boards to the switches on the
XStend Board expressed as UCF constraints.
Listing 3: Connections between the XStend DIP and pushbutton switches and the XS40.
# DIP SWITCH CONNECTIONS
NET DIPSW<1> LOC=P7;
#
# PUSHBUTTON SWITCH CONNECTIONS (ACTIVE-LOW)
NET SPAREB LOC=P67;
NET RESETB LOC=P37;
#
NET SPAREB LOC=P67;
NET RESETB LOC=P10;
2.4 VGA Interface

The XStend Board provides an XS Board with an interface to a VGA monitor through connector
J5. (Version 1.2 and higher of the XS Boards already have their own VGA interfaces, so the
XStend circuitry is redundant for them.) The XS Board can drive the active-low horizontal and
vertical sync signals that control the width and height of the video frame. The XS Board also has
access to two bits each of red, green, and blue color signals so it can generate pixels in any of
22×22×22=64 different colors.
Listings 5 and 6 show the connections from the XS40 and XS95 Boards to the VGA interface of
the XStend Board. (These pin assignments are identical to the pin assignments for the XS
Boards which have their own VGA interfaces.)
Listing 5: Connections between the XStend VGA interface and the XS40.
# VGA CONNECTIONS
NET VSYNCB LOC=P67;
NET HSYNCB LOC=P19;
NET RED<1> LOC=P18;
NET RED<0> LOC=P23;
NET GREEN<1> LOC=P20;
NET BLUE<1> LOC=P26;
# VGA CONNECTIONS
NET VSYNCB LOC=P24;
NET HSYNCB LOC=P15;
NET RED<1> LOC=P14;
NET RED<0> LOC=P18;
2.5 PS/2 Keyboard Interface

The XStend Board provides an XS Board with a PS/2-style interface (mini-DIN connector J6) to
either a keyboard or a mouse. The XS Board receives two signals from the PS/2 interface: a
clock signal and a serial data stream that is synchronized with the falling edges on the clock
signal.
Listings 7 and 8 show the connections from the XS40 and XS95 Boards to the PS/2 interface of
the XStend Board (expressed as UCF constraints):
Listing 7: Connections between the XStend PS/2 interface and the XS40.
# PS/2 KEYBOARD CONNECTIONS
NET KB_CLK LOC=P68;
NET KB_DATA LOC=P69;
NET KB_CLK LOC=P26;
2.6 RAMs
The XStend Board adds an additional 64 KBytes of RAM to the 32 KBytes already on the XS
Board. The XStend RAM connects to the same pins as the XS Board RAM for the address bus,
data bus, write-enable, and output-enable. The chip-selects of the XStend Board RAMs are
connected to different pins so all the RAMs can be individually selected.
Here are the connections from the XS40 and XS95 Boards to their own RAMs and the RAMs of
Listing 9: Connections between the XStend RAMs and the XS40.

NET D<0> LOC=P41; # DATA BUS
NET D<1> LOC=P40;
NET D<2> LOC=P39;
NET D<3> LOC=P38;
NET D<4> LOC=P35;
NET D<5> LOC=P81;
NET D<6> LOC=P80;
NET D<7> LOC=P10;
NET A<0> LOC=P3; # LOWER BYTE OF ADDRESS
NET A<1> LOC=P4;
NET A<2> LOC=P5;
NET A<3> LOC=P78;
NET A<4> LOC=P79;
NET A<5> LOC=P82;
NET A<6> LOC=P83;
NET A<7> LOC=P84;
NET A<8> LOC=P59; # UPPER BYTE OF ADDRESS
NET A<9> LOC=P57;
NET A<10> LOC=P51;
NET A<11> LOC=P56;
NET A<12> LOC=P50;
NET A<13> LOC=P58;
NET A<14> LOC=P60;
NET WEB LOC=P62; # ACTIVE-LOW WRITE-ENABLE FOR ALL RAMS
NET OEB LOC=P61; # ACTIVE-LOW OUTPUT-ENABLE FOR ALL RAMS
NET CEB LOC=P65; # ACTIVE-LOW CHIP-ENABLE FOR XS40 RAM
NET LCEB LOC=P7; # ACTIVE-LOW CHIP-ENABLE FOR LEFT XSTEND RAM
NET RCEB LOC=P8; # ACTIVE-LOW CHIP-ENABLE FOR RIGHT XSTEND RAM
NET D<1> LOC=P43;
NET D<2> LOC=P41;
NET D<3> LOC=P40;
NET D<4> LOC=P39;
NET D<5> LOC=P37;
NET D<6> LOC=P36;
NET D<7> LOC=P35;
NET A<1> LOC=P79;
NET A<2> LOC=P82;
NET A<3> LOC=P84;
NET A<4> LOC=P1;
NET A<5> LOC=P3;
NET A<6> LOC=P83;
NET A<7> LOC=P2;
NET A<9> LOC=P56;
NET A<10> LOC=P54;
NET A<11> LOC=P55;
NET A<12> LOC=P53;
NET A<13> LOC=P57;
NET A<14> LOC=P61;
2.7 Stereo Codec

The XStend Board has a stereo codec that accepts two analog input channels from jack J9,
digitizes the analog values, and sends the digital values to the XS Board as a serial bit stream.
The codec also accepts a serial bit stream from the XS Board and converts it into two analog
output signals which exit the XStend Board through jack J10.
The codec is configured by placing shunts on the jumpers as indicated in Table 2 and Figure 4.
Table 2: Jumper settings for XStend codec.
Jumper Setting
J11 Placing a shunt on this jumper disables the codec by

holding it in the reset state.
J13, J15 Placing shunts across two of the three pins of these
jumpers selects the digital de-emphasis for different
sampling rates:
0 0 De-emphasis for 32 KHz
0 1 De-emphasis for 44.1 KHz
1 0 De-emphasis for 48 KHz
1 1 De-emphasis off
J17 Removing this shunt prevents the codec’s serial data

output from reaching the XS Board.
J20-J27 Removing these shunts interrupts the flow of the analog

signals into and out of the codec.
J28 This header provides access to the analog VCC and

GND signals. A shunt should never be placed on this
header!
Figure 4: Shunt placement for setting the codec sampling rate de-emphasis.
Listings 11 and 12 show the connections from the XS40 Board to the codec interface on the
XStend Board (expressed as UCF constraints):
Listing 11: Connections between the XStend stereo codec and the XS40.
# STEREO CODEC CONNECTIONS
NET MCLK LOC=P9; # MASTER CLOCK TO CODEC
NET LRCK LOC=P66; # LEFT/RIGHT CODEC CHANNEL SELECT
NET SCLK LOC=P77; # SERIAL DATA CLOCK
NET SDOUT LOC=P6; # SERIAL DATA OUTPUT FROM CODEC
NET SDIN LOC=P70; # SERIAL DATA INPUT TO CODEC
NET CCLK LOC=P44; # CONTROL SIGNAL CLOCK
NET CDIN LOC=P45; # SERIAL CONTROL INPUT TO CODEC
NET CSB LOC=P46; # SERIAL CONTROL CHIP SELECT
Listing 12: Connections between the XStend codec and the XS95.
The analog stereo input and output signals enter and exit the XStend Board through the 1/8”
jacks J9 and J10, respectively. The output of an audio CD player can be input through J9 and a
set of small stereo headphones can be connected to J10 for listening to the processed output.
The analog signals that go in and out of the codec chip pass through jumpers J20-J27. Shunts
should be placed on all these jumpers so that the analog signals are not interrupted. The digitized
data output from the codec passes through jumper J17 on its way to the XS Board inserted in the
XStend Board. A shunt should be placed on J17 when the codec is being used. Because the
serial data output of the codec is not tristatable and because it shares the input to the XS Board
with other resources on the XStend Board, the shunt on J17 should be removed when the codec
is not being used.
*Never place a shunt on header J28! J28 provides access to the VCC and GND of the
analog section of the XStend Board. Placing a shunt on J28 will damage the XStend
Board.
2.8 XILINX Xchecker Interface

The XS Board inserted in the XStend Board can be configured and tested using a XILINX
Xchecker cable attached to header J19. When using the Xchecker cable, you must not connect
the cable between the XS Board and the parallel port of the PC. In addition, when using the
Xchecker cable with an XStend/XS40 combination, you must make the following adjustments to
the XS40 Board:
• Remove the shunts from jumpers J4, J6, J10 and J11 of the XS40 Board;
• Remove the serial EPROM from socket U7.
The connections between the Xchecker cable and the XS40 and XS95 Boards are listed in Table
3. The configuration and readback signals are not applicable to the XS95 Board, so only the
JTAG and VCC/GND signals are listed for it.
Table 3: Connections between the XStend Board Xchecker interface and the XS40 and XS95
Boards.
Xchecker Pin XS40 Pin XS95 Pin
1 – VCC (+5V) 2 78
2 – RT 32 N/A
3 – GND 52 49
4 – RD 30 N/A
6 – TRIG 7 N/A
7 – CCLK 73 N/A
9 – DONE 53 N/A
10 – TDI 15 28
11 – DIN 71 N/A
12 – TCK 16 30
13 – PROGRAM 55 N/A
14 – TMS 17 29
15 – INIT 41 N/A
16 – CLKI 13 N/A
17 – RST 8 N/A
18 – CLKO 9 N/A
2.9 Prototyping Area
The XStend Board has a prototyping area consisting of component through-holes on an
0.1"×0.1" grid interspersed with a network of alternating VCC and GND buses as shown in
Figure 5. The buses carrying VCC run on the top side of the XStend Board while the GND
buses run on the bottom side. The VCC and GND buses have connection holes in which a small
wire can be soldered to make a connection to a nearby component through-hole.
Figure 5: Top-side view of the network of VCC and GND buses around the component
through-holes in the XStend Board prototyping area.
The placement of the shunt on jumper J16 will determine whether the VCC buses in the
prototyping area carry either 5V or 3.3V (see Figure 6). Of course the jumper selection will have
no effect unless you have both these voltages supplied to the XStend Board either by the XS
Board or by connecting external power supplies.
Figure 6: Shunt placement for setting the VCC bus voltage..
Connections from the XS Board to the prototyping area are made through connector J3. The
arrangement of pins on this connector exactly matches the arrangement of pins on the XS40
Board. For example, the pin at the bottom-left of J3 on the XStend Board corresponds to pin 21
at the bottom-left of the XS40 Board.
The XS95 Board has a completely different pin arrangement than the XS40. Therefore each pin
on J3 is explicitly labelled with the corresponding pin number on the XS95 Board. For example,
the pin at the bottom-left of J3 on the XStend Board is connected to pin 68 near the top-left of
the XS95 Board.
2.10 Daughterboard Connector
Daughterboards with specialized circuitry can be connected to the XStend board through
connector J18. This 42×2 connector brings all the I/O and VCC/GND from the XS40 or XS95
Board to the daughterboard.
3 XStend Board Programmer’s Model

The interconnections of the XStend Board resources and an XS40 or XS95 Board are shown in
Figure 7 and Figure 8, respectively. These figures remove much of the extraneous detail of the
actual schematics, so we refer to them as programmer’s models.
Items within the shaded area in each figure correspond to circuitry housed on the XS Board. The
remaining items are XStend Board resources.
A cursory glance at the figures reveals that many of the resources share connections. For
example, the codec, DIP switch, and microcontroller port P1 are all connected to the same set of
pins on the FPGA or CPLD. So any design has to ensure that only one of these resources is
outputing data at any particular time. (Hence the need in some designs to place the DIP switches
in the OPEN position, or remove the shunt through which the codec SDOUT drives serial data,
or keep the microcontroller in the reset state.)
Table 4 and Table 5 list the same interconnection data for the XS40 and XS95 Boards,
respectively, in a tabular format which makes it easier to see which resources share common
connections.
Figure 7: Programmer's model of the XS40/XStend Board combination.
Table 4: Connections between the XS40 Board and the XStend Board resources.
Stereo Codec
Push-buttons
Power/ GND
BOARD Pin
PC Parallel
DIP Switch
(J1,J3,J18)
UW-FPGA
Oscillator
XS40 Pin
Interface
Interface
8051 uC
RAMs
LEDs
VGA
PS/2
Port
Function
2 +5V +5V power source
3 LSB0 A0 Left LED segment; RAM address line P35
6 DIPSW4 SDOUT P1.3 DIP switch; codec serial data output; uC I/O P24
7 DIPSW1 LCEB P1.0 DIP switch; left RAM chip-enable, uC I/O port P19
8 DIPSW2 RCEB P1.1 DIP switch; right RAM chip-enable, uC I/O port P20
9 DIPSW3 MCLK P1.2 DIP switch; codec master clock; uC I/O port P23
10 DB8 D7 P0.7 LED; RAM data line; uC muxed address/data line P61
13 CLK XS Board oscillator
14 PSENB uC program store-enable
15 JTAG TDI; DIN
16 JTAG TCK; CCLK
17 JTAG TMS
18 S5 RED1 XS Board LED segment; VGA color signal
19 S6 HSYNCB XS Board LED segment; VGA horiz. sync.
20 S3 GREEN1 XS Board LED segment; VGA color signal
25 S0 BLUE0 XS Board LED segment; VGA color signal
27 P3.7 (RD_) uC read line
28 RDPB P2.7 Right LED decimal-point; uC I/O port P41
29 ALEB uC address-latch-enable
30 Serial EEPROM chip-enable
32 PC_D6 PC parallel port data output
36 RST uC reset
37 RESETB XTAL1 Pushbutton; uC clock P56
44 CCLK PC_D0 Codec control line; PC parallel port data output
45 CDIN PC_D1 Codec control line; PC parallel port data output
46 CSB PC_D2 Codec control line; PC parallel port data output
50 RSB4 A12 P2.4 Right LED segment; RAM address line; uC I/O port P48
52 GND Power supply ground
54 5.0V/3.3V 5V/3.3V power supply (4000E/4000XL)
55 PROGRAM XS40 configuration control P55
61 OEB RAM output-enable
62 WEB P3.6 (WR_) RAM write-enable; uC I/O port
65 CEB XS Board RAM chip-enable
66 DIPSW7 LRCK P1.6 PC_S5 DIP switch; codec left-right channel switch; uC I/O port; PC parallel
P27 port status input
67 SPAREB VSYNCB P1.7 Pushbutton; VGA vert. sync.; uC I/O port P18
68 KB_CLK P3.4 (T0) PS/2 keyboard clock; uC I/O port
69 DIPSW8 KB_DATA P3.1 (TXD)
PC_S6 DIP switch; PS/2 keyboard serial data; uC I/O port; PC parallelP28port status input
70 DIPSW6 SDIN P1.5 PC_S3 DIP switch; codec serial input data; uC I/O port; PC parallel port
P26 status input
71 JTAG TDI; DIN
72 JTAG TDO; DOUT
73 JTAG TCK; CCLK
75 PC_S7 JTAG TDO; DOUT; PC parallel port status input
77 DIPSW5 SCLK P1.4 PC_S4 DIP switch; codec serial I/O clock; uC I/O port; PC parallel port
P25status input
84 LDPB A7 Left LED decimal-point; RAM address line P37
Stereo Codec
Push-buttons
Power/ GND
BOARD Pin
PC Parallel
DIP Switch
XS95 Pins
UW-FPGA
Oscillator
Interface
Interface
8051 Uc
RAMs
LEDs
VGA
PS/2
Port
(J2)
Function
4 Uncommitted XS95 I/O pin
28 JTAG TDI; DIN
29 JTAG TMS
30 JTAG TCK; CCLK
31 P3.0 (RXD) uC I/O port
32 P3.7 (RD_) uC I/O port
33 P3.5 (T1) uC I/O port
34 RDPB P2.7 Right LED decimal-point; RAM address line; uC I/O port P41
45 RST uC reset
59 JTAG TDO; DOUT
66 DIPSW7 LRCK P1.6 PC_S5 DIP switch; codec left-right channel select; uC I/O port; PC parallel
68 P3.3 (INT1_) uC I/O port
PC_S6 DIP switch; PS/2 keyboard serial data; uC I/O port; PC parallelP28
port status input
P26status input
72 DIPSW5 SCLK P1.4 PC_S4 DIP switch; codec serial clock; uC I/O port; PC parallel port status
P25 input
24,67 SPAREBDP VSYNCB P1.7 Pushbutton; XS Board LED decimal-point; VGA horiz. sync.; uC P18I/O port
4 Example Designs for the XStend Board
With the programmer’s models in hand, several example designs can be built using the XStend
Board coupled with an XS40 or XS95 Board.
4.1 Displaying Switch Settings on the LEDs

This example creates a circuit that displays the settings of the DIP switches on the LEDs and
LED digits of the XStend and XS Boards. The particular set of LEDs which is activated is
selected by the SPARE and RESET pushbuttons. The VHDL code for this example is shown in
Listing 13.
The steps for compiling and testing the design using an XS40 combined with an XStend Board
are as follows:
• Synthesize the VHDL code in the SWTCH40\SWITCHES.VHD file for an XC4005XL

FPGA.
• Compile the synthesized netlist using the SWTCH40.UCF constraint file (Listing 14).
• Mount an XS40 Board in the XStend Board and attach the downloading cable from the
XS40 to the PC parallel port. Apply 9VDC though jack J9 of the XS40. Place shunts on
jumpers J4, J7, and J8 of the XStend Board to enable the LED displays. Remove the shunt
on jumper J17 to keep the XStend codec serial output from interfering with the DIP switch
logic levels.
• Download the SWTCH40.BIT file into the XS40/XStend combination with the command:
XSLOAD SWTCH40.BIT.
• Set the DIP switches and press the SPARE and RESET pushbuttons. Observe the results on
the LEDs.
are as follows:
• Synthesize the VHDL code in the SWTCH95\SWITCHES.VHD file for an XC95108 CPLD.
• Compile the synthesized netlist using the SWTCH95.UCF constraint file (

Listing 15).
• Generate an SVF file for the design.
logic levels.
• Download the SWTCH95.SVF file into the XS95/XStend combination with the command:
XSLOAD SWTCH95.SVF.
the LEDs.
Listing 13: VHDL code for using the XStend LEDs and switches.
001- LIBRARY IEEE;
002- USE IEEE.STD_LOGIC_1164.ALL;
003-
004- ENTITY switches IS
005- PORT
006- (
007- dipsw: IN STD_LOGIC_VECTOR(8 DOWNTO 1); -- DIP switches
008- spareb: IN STD_LOGIC; -- SPARE pushbutton
009- resetb: IN STD_LOGIC; -- RESET pushbutton
010-
011- s: OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -- XS Board LED digit
012- lsb: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- XStend left LED digit
013- rsb: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- XStend right LED digit
014- db: OUT STD_LOGIC_VECTOR(8 DOWNTO 1); -- XStend bargraph LED
015-
016- oeb: OUT STD_LOGIC; -- output enable for all RAMs
017- rst: OUT STD_LOGIC -- microcontroller reset
018- );
019- END switches;
020-
021- ARCHITECTURE switches_arch OF switches IS
022- BEGIN
023- -- this prevents accidental activation of the RAMs or microcontroller
024- oeb <= '1'; -- disable all the RAM output drivers
025- rst <= '1'; -- disable the microcontroller
026-
027- -- light the XS Board LED digit with the pattern from the
028- -- DIP switches if both pushbuttons are pressed.
029- -- these LED segments are active-high.
030- s <= dipsw(7 DOWNTO 1) WHEN (spareb='0' AND resetb='0') ELSE
031- "0000000"; -- otherwise keep LED digit dark
032-
033- -- light the XStend left LED digit with the pattern from the
034- -- DIP switches if the RESET pushbutton is pressed.
035- -- these LED segments are active low.
036- lsb <= NOT(dipsw) WHEN (spareb='1' AND resetb='0') ELSE
037- "11111111"; -- otherwise keep the LED digit dark
038-
039- -- light the XStend right LED digit with the pattern from the
040- -- DIP switches if the SPARE pushbutton is pressed.
042- rsb <= NOT(dipsw) WHEN (spareb='0' AND resetb='1') ELSE
044-
045- -- light the XStend bargraph LED with the pattern from the
046- -- DIP switches if neither pushbutton is pressed
048- db <= NOT(dipsw) WHEN (spareb='1' AND resetb='1') ELSE
049- "11111111"; -- otherwise keep the bargraph LED dark
050- END switches_arch;
Listing 14: XS40 UCF file for the LED/switch example.

001- net s<0> loc=p25; // XS40 board led digit segments
002- net s<1> loc=p26;
003- net s<2> loc=p24;
004- net s<3> loc=p20;
005- net s<4> loc=p23;
006- net s<5> loc=p18;
007- net s<6> loc=p19;
008- net rst loc=p36; // microcontroller reset
009- net oeb loc=p61; // RAM output enable
010- net dipsw<1> loc=p7; // DIP switch inputs
011- net dipsw<2> loc=p8;
018- net spareb loc=p67; // SPARE pushbutton input
019- net resetb loc=p37; // RESET pushbutton input
020- net lsb<0> loc=p3; // XStend left led digit segments
021- net lsb<1> loc=p4;
028- net rsb<0> loc=p59; // XStend right led digit segments
029- net rsb<1> loc=p57;
036- net db<1> loc=p41; // XStend bargraph led segments
037- net db<2> loc=p40;
038- net db<3> loc=p39;
039- net db<4> loc=p38;
040- net db<5> loc=p35;
041- net db<6> loc=p81;
042- net db<7> loc=p80;
043- net db<8> loc=p10;
001- net s<0> loc=p21; // XS Board LED digit segments
002- net s<1> loc=p23;
003- net s<2> loc=p19;
004- net s<3> loc=p17;
005- net s<4> loc=p18;
006- net s<5> loc=p14;
007- net s<6> loc=p15;
020- net lsb<0> loc=p1; // XStend left LED digit segments
028- net rsb<0> loc=p58; // XStend right LED digit segments
036- net db<1> loc=p44; // XStend bargraph LED segments
037- net db<2> loc=p43;
038- net db<3> loc=p41;
039- net db<4> loc=p40;
040- net db<5> loc=p39;
041- net db<6> loc=p37;
042- net db<7> loc=p36;
043- net db<8> loc=p35;
4.2 Displaying Graphics from RAM Through the VGA Interface
This section discusses the timing for the signals that drive a VGA monitor and describes a VHDL
module that will let you drive a monitor with a picture stored in RAM.
4.2.1 VGA Color Signals

There are three signals -- red, green, and blue -- that send color information to a VGA monitor.
These three signals each drive an electron gun that emits electrons which paint one primary color
at a point on the monitor screen. Analog levels between 0 (completely dark) and 0.7 V
(maximum brightness) on these control lines tell the monitor what intensities of these three
primary colors to combine to make the color of a dot (or pixel) on the monitor’s screen.
Each analog color input can be set to one of four levels by two digital outputs using a simple
two-bit digital-to-analog converter (see Figure 9). The four possible levels on each analog input
are combined by the monitor to create a pixel with one of 4 × 4 × 4 = 64 different colors. So the
six digital control lines let us select from a palette of 64 colors.
Figure 9: Digital-to-analog interface to a VGA monitor.

4.2.2 VGA Signal Timing
A single dot of color on a video monitor doesn’t impart much information. A horizontal line of
pixels carries a bit more information. But a frame composed of multiple lines can present an
image on the monitor screen. A frame of VGA video typically has 480 lines and each line usually
contains 640 pixels. In order to paint a frame, there are deflection circuits in the monitor that
move the electrons emitted from the guns both left-to-right and top-to-bottom across the screen.
These deflection circuits require two synchronization signals in order to start and stop the
deflection circuits at the right times so that a line of pixels is painted across the monitor and the
lines stack up from the top to the bottom to form an image. The timing for the VGA
synchronization signals is shown in Figure 10.
Negative pulses on the horizontal sync signal mark the start and end of a line and ensure that the
monitor displays the pixels between the left and right edges of the visible screen area. The actual
pixels are sent to the monitor within a 25.17 µs window. The horizontal sync signal drops low a
minimum of 0.94 µs after the last pixel and stays low for 3.77 µs. A new line of pixels can begin
a minimum of 1.89 µs after the horizontal sync pulse ends. So a single line occupies 25.17 µs of
a 31.77 µs interval. The other 6.6 µs of each line is the horizontal blanking interval during
which the screen is dark.
In an analogous fashion, negative pulses on a vertical sync signal mark the start and end of a
frame made up of video lines and ensure that the monitor displays the lines between the top and
bottom edges of the visible monitor screen. The lines are sent to the monitor within a 15.25 ms
window. The vertical sync signal drops low a minimum of 0.45 ms after the last line and stays
low for 64 µs. The first line of the next frame can begin a minimum of 1.02 ms after the vertical
sync pulse ends. So a single frame occupies 15.25 ms of a 16.784 ms interval. The other 1.534
ms of the frame interval is the vertical blanking interval during which the screen is dark.
Figure 10: VGA signal timing.
4.2.3 VGA Signal Generator Algorithm

Now we have to figure out a process that will send pixels to the monitor with the correct timing
and framing. We can store a picture in the RAM of the XS Board. Then we can retrieve the
data from the RAM, format it into lines of pixels, and send the lines to the monitor with the
appropriate pulses on the horizontal and vertical sync pulses.
The pseudocode for a single frame of this process is shown in Listing 16. The pseudocode has
two outer loops: one which displays the L lines of visible pixels, and another which inserts the V
blank lines and the vertical sync pulse. Within the first loop, there are two more loops: one
which sends the P pixels of each video line to the monitor, and another which inserts the H blank
pixels and the horizontal sync pulse.
Within the pixel display loop, there are statements to get the next byte from the RAM. Each byte
contains four two-bit pixels. A small loop iteratively extracts each pixel to be displayed from the
lower two bits of the byte. Then the byte is shifted by two bits so the next pixel will be in the
right position during the next iteration of the loop. Since it has only two bits, each pixel can store
one of four colors. The mapping from the two-bit pixel value to the actual values required by the
monitor electronics is done by the COLOR_MAP() routine.
Listing 16: VGA signal generation pseudocode.

/* send L lines of video to the monitor */
for line_cnt=1 to L
/* send P pixels for each line */
for pixel_cnt=1 to P
/* get pixel data from the RAM */
data = RAM(address)
address = address + 1
/* RAM data byte contains 4 pixels */
for d=1 to 4
/* mask off pixel in the lower two bits */
pixel = data & 00000011
/* shift next pixel into lower two bits */
data = data>>2
/* get the color for the two-bit pixel */
color = COLOR_MAP(pixel)
send color to monitor
d = d + 1
/* increment by four pixels */
pixel_cnt = pixel_cnt + 4
/* blank the monitor for H pixels */
for horiz_blank_cnt=1 to H
color = BLANK
/* pulse the horizontal sync at the right time */
if horiz_blank_cnt>HB0 and horiz_blank_cnt<HB1
hsync = 0
else
hsync = 1
horiz_blank_cnt = horiz_blank_cnt + 1
line_cnt = line_cnt + 1
/* blank the monitor for V lines and insert vertical sync */
for vert_blank_cnt=1 to V
color = BLANK
/* pulse the vertical sync at the right time */
if vert_blank_cnt>VB0 and vert_blank_cnt<VB1
vsync = 0
else
vsync = 1
vert_blank_cnt = vert_blank_cnt + 1
/* go back to start of picture in RAM */
address = 0
Figure 11 shows how to pipeline certain operations to account for delays in accessing data from
the RAM. The pipeline has three stages:
Stage 1: The circuit uses the horizontal and vertical counters to compute the address where the
next pixel is found in RAM. The counters are also used to determine the firing of the sync
pulses and whether the video should be blanked. The pixel data from the RAM, blanking
signal, and sync pulses are latched at the end of this stage so they can be used in the next
stage.
Stage 2: The circuit uses the pixel data and the blanking signal to determine the binary color
outputs. These outputs are latched at the end of this stage.
Stage 3: The binary color outputs are applied to the DAC, which sets the intensity levels for the
monitor’s color guns. The actual pixel is painted on the screen during this stage.
Figure 11: Pipelining of VGA signal generation tasks.
4.2.4 VGA Signal Generator in VHDL

The pseudocode and pipeline timing in the last section will help us to understand the VHDL code
for a VGA signal generator shown in Listing 17. The inputs and outputs of the circuit as defined
in the entity declaration are as follows:
clk: The input for the 12 MHz clock of the XS Board is declared here. This clock sets the
maximum rate at which pixels can be sent to the monitor. The time interval within each line
for transmitting viewable pixels is 25.17 µs, so this VGA generator circuit can only put a
maximum of 25.17 ms × 12 MHz = 302 pixels on each line. For purposes of storing images
in the RAM, it is convenient to reduce this to 256 pixels per line and blank the remaining 46
pixels. Half of these blank pixels are placed before the 256 viewable pixels and half are
placed after them on a line. This centers the viewable pixels between the left and right edges
of the monitor screen.
reset: This line declares an input, which will reset all the other circuitry to a known state.
hsyncb, vsyncb: The outputs for the horizontal and vertical sync pulses are declared. The
hsyncb output is declared as a buffer because it will also be referenced within the architecture
section as a clock for the vertical line counter.
rgb: The outputs that control the red, green, and blue color guns of the monitor are declared
here. Each gun is controlled by two bits, so there are four possible intensities for each color.
Thus, this circuit can produce 4 × 4 × 4 = 64 different colors.
address, data: These lines declare the outputs for driving the address lines of the RAM and the
inputs for receiving the data from the RAM.
ceb, oeb, web: These are the declarations for the outputs which drive the chip-select, output-
enable, and write-enable control lines of the RAM.
The preamble of the architecture section declares the following resources:
hcnt, vcnt: The counters that store the current horizontal position within a line of pixels and the
vertical position of the line on the screen are declared on these lines. We will call these the
horizontal or pixel counter, and the vertical or line counter, respectively. The line period is
31.77 µs that is 381 clock cycles, so the pixel counter needs at least nine bits of resolution.
Each frame is composed of 528 video lines (only 480 are visible, the other 48 are blanked), so
a ten bit counter is needed for the line counter.
pixrg: This is the declaration for the eight-bit register that stores the four pixels received from
the RAM.
blank, pblank: This line declares the video blanking signal and its registered counterpart that is
used in the next pipeline stage.
Within the main body of the architecture section, these following processes are executed:
inc_horiz_pixel_counter: This process describes the operation of the horizontal pixel counter.
The counter is asynchronously set to zero when the reset input is high. The counter
increments on the rising edge of each pixel clock. The range for the horizontal pixel counter
is [0,380]. When the counter reaches 380, it rolls over to zero on the next cycle. Thus, the
counter has a period of 381 pixel clocks. With a pixel clock of 12 MHz, this translates to a
period of 31.75 µs.
inc_vert_line_counter: This process describes the operation of the vertical line counter. The
counter is asynchronously set to zero when the reset input is high. The counter increments
on the rising edge of the horizontal sync pulse after a line of pixels is completed. The range
for the horizontal pixel counter is [0,527]. When the counter reaches 527, it rolls over to
zero on the next cycle. Thus, the counter has a period of 528 lines. Since the duration of a
line of pixels is 31.75 µs, this makes the frame interval equal to 16.76 ms.
generate_horiz_sync: This process describes the operation of the horizontal sync pulse
generator. The horizontal sync is set to its inactive high level when the reset is activated.
During normal operations, the horizontal sync output is updated on every pixel clock. The
sync signal goes low on the cycle after the pixel counter reaches 291 and continues until the
cycle after the counter reaches 337. This gives a low horizontal sync pulse of (337-291)=46
pixel clocks. With a pixel clock of 12 MHz, this translates to a low-going horizontal sync
pulse of 3.83 µs. The sync pulse starts 292 clocks after the line of pixels begin, which
translates to 24.33 µs. This is less than the 26.11 µs we stated before. The difference of 1.78
ms translates to 21 pixel clocks. This time interval corresponds to the 23 blank pixels that are
placed before the 256 viewable pixels (minus two clock cycles for pipelining delays).
generate_vert_sync: This process describes the operation of the vertical sync pulse generator.
The vertical sync is set to its inactive high level when the reset is activated. During normal
operations, the vertical sync output is updated after every line of pixels is completed. The
sync signal goes low on the cycle after the line counter reaches 493 and continues until the
cycle after the counter reaches 495. This gives a low vertical sync pulse of (495-493)= 2
lines. With a line interval of 31.75 µs, this translates to a low-going vertical sync pulse of
63.5 µs. The vertical sync pulse starts 494 × 31.75 µs = 15.68 ms after the beginning of the
first video line.
Line 91: This line describes the computation of the combinatorial blanking signal. The video is
blanked after 256 pixels on a line are displayed, or after 480 lines are displayed.
pipeline_blank: This process describes the operation of the pipelined video blanking signal.
Within the process, the blanking signal is stored in a register so it can be used during the next
stage of the pipeline when the color is computed.
Lines 104 -- 106: On these lines, the RAM is permanently selected and writing to the RAM is
disabled. This makes the RAM look like a ROM, which stores video data. In addition, the
outputs from the RAM are disabled when the video is blanked since there is no need for
pixels during the blanking intervals. This isn’t really necessary since no other circuit is trying
to access the RAM.
Line 113: The address in RAM where the next four pixels are stored is calculated by
concatenating the lower nine bits of the line counter with bits 7,6,5,4,3 and 2 of the pixel
counter. With this arrangement, the line counter stores the address of one of 29 = 512 pages.
Each page contains 26 = 64 bytes. Each byte contains four pixels, so each page stores one
line of 256 pixels. The pixel counter increments through the bytes of a page to get the pixels
for the current line. (Note that we don’t need to use bits 1 and 0 of the pixel counter when
computing the RAM address since each byte contains four pixels.) After the line is displayed,
the line counter is incremented to point to the next page.
update_pixel_register: This process describes the operation of the register that holds the byte of
pixel data read from RAM. The register is asynchronously cleared when the VGA circuit is
reset. The register is updated on the rising edge of each pixel clock. The pixel register is
loaded with data from the RAM whenever the lowest two bits of the pixel counter are both
zero. The active pixel is always in the lower two bits of the register. Each pixel in the RAM
data byte is shifted into the active position by right shifting the register two bits on each rising
clock edge.
map_pixel_to_rgb: this process describes the process by which the current active pixel is
mapped into the six bits that drive the red, green and blue color guns. The register is set to
zero (which displays as the color black) when the reset input is high. The color register is
clocked on the rising edge of the pixel clock since this is the rate at which new pixel values
arrive. The value clocked into the register is a function of the pixel value and the blanking
input. When the pipelined blanking input is low (inactive), the color displayed on the monitor
is red, green, blue, or white depending upon whether the pixel value is 00, 01, 10, or 11,
respectively. When the pipelined blanking input is high, the color register is loaded with zero
(black).
Listing 17: VHDL code for a VGA generator.

001- LIBRARY IEEE;
003- USE IEEE.std_logic_unsigned.ALL;
004-
005- ENTITY vga_generator IS
006- PORT
007- (
008- clk: IN STD_LOGIC; -- VGA dot clock
009- reset: IN STD_LOGIC; -- asynchronous reset
010- hsyncb: OUT STD_LOGIC; -- horizontal (line) sync
011- vsyncb: OUT STD_LOGIC; -- vertical (frame) sync
012- rgb: OUT STD_LOGIC_VECTOR(5 DOWNTO 0); -- red,green,blue colors
013- address: OUT STD_LOGIC_VECTOR(14 DOWNTO 0);-- address into video RAM
014- data: IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from video RAM
015- ceb: OUT STD_LOGIC; -- video RAM chip enable
016- oeb: OUT STD_LOGIC; -- video RAM output enable
017- web: OUT STD_LOGIC -- video RAM write enable
018- );
019- END vga_generator;
020-
021- ARCHITECTURE vga_generator_arch OF vga_generator IS
022- SIGNAL hcnt: STD_LOGIC_VECTOR(8 DOWNTO 0); -- horizontal pixel counter
023- SIGNAL vcnt: STD_LOGIC_VECTOR(9 DOWNTO 0); -- vertical line counter
024- SIGNAL pixrg: STD_LOGIC_VECTOR(7 DOWNTO 0); -- byte register for 4 pix
025- SIGNAL blank: STD_LOGIC; -- video blanking signal
026- SIGNAL pblank: STD_LOGIC; -- pipelined video blanking signal
027- SIGNAL int_hsyncb: STD_LOGIC; -- internal horizontal sync.
028- BEGIN
029-
030- inc_horiz_pixel_counter:
031- PROCESS(clk,reset)
032- BEGIN
033- IF reset='1' THEN -- reset asynchronously clears pixel counter
034- hcnt <= "000000000";
035- ELSIF (clk'EVENT AND clk='1') THEN
036- IF hcnt<380 THEN -- pixel counter resets after 381 pixels
037- hcnt <= hcnt + 1;
038- ELSE
039- hcnt <= "000000000";
040- END IF;
041- END IF;
042- END PROCESS;
043-
044- inc_vert_line_counter:
045- PROCESS(int_hsyncb,reset)
046- BEGIN
047- IF reset='1' THEN -- reset asynchronously clears line counter
048- vcnt <= "0000000000";
049- ELSIF (int_hsyncb'EVENT AND int_hsyncb='1') THEN
050- IF vcnt<527 THEN -- vert. line counter rolls-over after 528 lines
051- vcnt <= vcnt + 1;
052- ELSE
053- vcnt <= "0000000000";
054- END IF;
055- END IF;
056- END PROCESS;
057-
058- generate_horiz_sync:
060- BEGIN
061- IF reset='1' THEN -- reset asynchronously inactivates horiz sync
062- int_hsyncb <= '1';
064- IF (hcnt>=291 AND hcnt<337) THEN
065- -- horiz. sync is low in this interval to signal start of new line
066- int_hsyncb <= '0';
067- ELSE
068- int_hsyncb <= '1';
069- END IF;
070- END IF;
071- hsyncb <= int_hsyncb; -- output the horizontal sync signal
072- END PROCESS;
073-
074- generate_vert_sync:
076- BEGIN
077- IF reset='1' THEN -- reset asynchronously inactivates vertical sync
078- vsyncb <= '1';
079- -- vertical sync is recomputed at the end of every line of pixels
081- IF (vcnt>=490 AND vcnt<492) THEN
082- -- vert. sync is low in this interval to signal start of new frame
083- vsyncb <= '0';
084- ELSE
085- vsyncb <= '1';
086- END IF;
087- END IF;
088- END PROCESS;
089-
090- -- blank video outside of visible region: (0,0) -> (255,479)
091- blank <= '1' WHEN (hcnt>=256 OR vcnt>=480) ELSE '0';
092- -- store the blanking signal for use in the next pipeline stage
093- pipeline_blank:
095- BEGIN
096- IF reset='1' THEN
097- pblank <= '0';
099- pblank <= blank;
100- END IF;
101- END PROCESS;
102-
103- -- video RAM control signals
104- ceb <= '0'; -- enable the RAM
105- web <= '1'; -- disable writing to the RAM
106- oeb <= blank; -- enable the RAM outputs when video is not blanked
107-
108- -- The video RAM address is built from the lower 9 bits of the vert
109- -- line counter and bits 7-2 of the horizontal pixel counter.
110- -- Each byte of the RAM contains four 2-bit pixels. As an example,
111- -- the byte at address ^h1234=^b0001,0010,0011,0100 contains the pixls
112- -- at (row,col)=(^h048,^hD0),(^h048,^hD1),(^h048,^hD2),(^h048,^hD3).
113- address <= vcnt(8 DOWNTO 0) & hcnt(7 DOWNTO 2);
114-
115- update_pixel_register:
117- BEGIN
118- IF reset='1' THEN -- clear the pixel register on reset
119- pixrg <= "00000000";
120- -- pixel clock controls changes in pixel register
122- -- the pixel register is loaded with the contents of the video
123- -- RAM location when the lower two bits of the horiz. counter
124- -- are both zero. The active pixel is in the lower two bits
125- -- of the pixel register. For the next 3 clocks, the pixel
126- -- register is right-shifted by two bits to bring the other
127- -- pixels in the register into the active position.
128- IF hcnt(1 DOWNTO 0)="00" THEN
129- pixrg <= data; -- load 4 pixels from RAM
130- ELSE
131- pixrg <= "00" & pixrg(7 DOWNTO 2); -- right-shift pixel register
132- END IF;
133- END IF;
134- END PROCESS;
135-
136- -- the color mapper translates each 2-bit pixel into a 6-bit
137- -- color value. When the video signal is blanked, the color
138- -- is forced to zero (black).
139- map_pixel_to_rgb:
141- BEGIN
142- IF reset='1' THEN -- blank the video on reset
143- rgb <= "000000";
144- ELSIF (clk'EVENT AND clk='1') THEN -- update the color every clock
145- -- map the pixel to a color if the video is not blanked
146- IF pblank='0' THEN
147- CASE pixrg(1 DOWNTO 0) IS
148- WHEN "00" => rgb <= "110000"; -- red
149- WHEN "01" => rgb <= "001100"; -- green
150- WHEN "10" => rgb <= "000011"; -- blue
151- WHEN OTHERS => rgb <= "111111"; -- white
152- END CASE;
153- ELSE -- otherwise, output black if the video is blanked
154- rgb <= "000000"; -- black
155- END IF;
156- END IF;
157- END PROCESS;
158-
159- END vga_generator_arch;
Listing 18: XS40 UCF file for the VGA signal generator.
001- net clk loc=p13;
002- net reset loc=p44;
003- net data<0> loc=p41;
011- net address<0> loc=p3;
026- net ceb loc=p65;
027- net web loc=p62;
028- net oeb loc=p61;
029- net rgb<0> loc=p25;
035- net hsyncb loc=p19;
036- net vsyncb loc=p67;
The steps for compiling and testing the VGA design using an XS40 combined with an XStend
Board are as follows:
• Synthesize the VHDL code in the VGA40\VGA.VHD file for an XC4005XL FPGA.
• Compile the synthesized netlist using the VGA40.UCF constraint file (Listing 18).
logic levels. Set all the DIP switches to the OPEN position.
• Attach a VGA monitor to the DB-HD15 connector (J5).
• Download the VGA40.BIT file and a video test pattern into the XS40/XStend combination
with the command: XSLOAD TESTPATT.HEX VGA40.BIT.
• Release the reset to the VGA circuitry with the command: XSPORT 0.
• Observe the color bars on the monitor screen.
are as follows:
• Synthesize the VHDL code in the VGA95\VGA.VHD file for an XC95108 CPLD.
on jumper J17 to keep the XStend codec serial output from interfering. Set all the DIP
switches to the OPEN position.
• Download the VGA95.SVF file and a video test pattern into the XS95/XStend combination
with the command: XSLOAD TESTPATT.HEX VGA95.SVF.
4.3 Reading Keyboard Scan Codes Through the PS/2 Interface

This example creates a circuit that accepts scan codes from a keyboard attached to the PS/2
interface of the XStend Board. The binary pattern of the scan code is displayed on the bargraph
LEDs. In addition, if a scan code for one of the keys '0'—'9' arrives, then the numeral will be
displayed on the right LED display of the XStend Board.
The format of the scan code transmissions from the keyboard are shown in Figure 12. The
keyboard electronics drive the clock and data lines. The start of a scan code transmission is
indicated by a low level on the data line on the falling edge of the clock. The eight bits of the
scan code follow (starting with the least-significant bit) on successive falling clock edges. These
are followed by an odd-parity bit and then a high-level stop bit.
When the clock line goes high after the stop bit, the receiver (in this case, the FPGA or CPLD on
the XS Board inserted in the XStend Board) can pull the clock line low to inhibit any further
transmissions. After the clock line is released and it returns to a high level, the keyboard can
send another scan code. If the receiver never pulls the clock line low, then the keyboard will
send scan codes whenever a key is pressed.
Figure 12: Keyboard data transmission waveforms.
The VHDL code for this example is shown in

Listing 20. The inputs and outputs of the circuit as defined in the entity declaration are as
follows:
rst: This output drives the reset pin of the microcontroller on the XS Board.
oeb: This output drives the output-enable pin of the RAM on the XS Board.
kb_data: The scan code bits enter through this input.
kb_clk: The keyboard clock signal enters through this input.
db: These outputs drive the segments of the bargraph LED on the XStend Board.
rsb: These outputs drive the segments of the right LED digit on the XStend Board.
Within the main body of the architecture section, these operations occur:
Lines 22 & 23: The microcontroller reset pin and the RAM output-enable pin are driven high so
these chips cannot interfere while receiving data from the keyboard.
Lines 25 & 26: The keyboard clock passes through an input buffer and then a global clock buffer
before it reaches the rest of the circuitry. (These buffers are declared on lines 18 and 19,
respectively.) The global clock buffer distributes the clock signal with minimal skew in the
XS40 Board FPGA. These statements are not used with the CPLD in the XS95 Board.
gather_scancode: On every falling edge of kb_clk, this process shifts the data bit on the kb_data
input into the most-significant bit of a 10-bit shift register. After 11 clock cycles, the lower 8
bits of the register will contain the scan code, the upper 2 bits will store the stop and parity
bits, and the start bit will have been shifted through the entire register and discarded.
Line 38: The value in the shift register is inverted and applied to the segments of the LED
bargraph. Since the bargraph segments are active-low, a segment will light for every ‘1’ bit
in the shift register. The LED segment drivers are not registered so there will be some
flickering as the shift register contents change.
Lines 40-51: If the scan code in the shift register matches the codes for the digits 0-9, then the
right LED digit segments will be activated to display the corresponding digit. If the scan
code does not match one of these codes, the letter ‘E’ is displayed.
are as follows:
• Synthesize the VHDL code in the KEYBRD40\KEYBRD.VHD for an XC4005XL FPGA.
• Compile the synthesized netlist using the KEYBRD40.UCF constraint file (

Listing 21).
jumpers J4, J7, and J8 to enable the LEDs. Remove the shunt on jumper J17 to keep the
XStend codec from interfering. Set all the DIP switches to the OPEN position.
• Attach a keyboard to the PS/2 connector of the XStend Board.
• Download the KEYBRD40.BIT file into the XS40/XStend combination with the command:
XSLOAD KEYBRD40.BIT.
• Press keys on the keyboard and observe the results on the LED displays.
are as follows:
• Synthesize the VHDL code in the KEYBRD95\KEYBRD.VHD for an XC95108 CPLD.
• Compile the synthesized netlist using the KEYBRD95.UCF constraint file (Listing 23).
• Download the KEYBRD95.SVF file into the XS95/XStend combination with the command:
XSLOAD KEYBRD95.SVF.
Listing 20: VHDL code for receiving keyboard scan codes from the PS/2 interface.
001- LIBRARY IEEE;
003-
004- ENTITY kbd_read IS
005- PORT
006- (
007- rst: OUT STD_LOGIC; -- uC reset
008- oeb: OUT STD_LOGIC; -- RAM output enable
009- kb_data: IN STD_LOGIC; -- serial data from the keyboard
010- kb_clk: IN STD_LOGIC; -- clock from the keyboard
011- db: OUT STD_LOGIC_VECTOR(8 DOWNTO 1); -- bargraph LED
012- rsb: OUT STD_LOGIC_VECTOR(6 DOWNTO 0) -- right LED digit
013- );
014- END kbd_read;
015-
016- ARCHITECTURE kbd_read_arch OF kbd_read IS
017- SIGNAL scancode: STD_LOGIC_VECTOR(9 DOWNTO 0);
018- COMPONENT ibuf PORT(i: IN STD_LOGIC; o: OUT STD_LOGIC); END COMPONENT;
019- COMPONENT bufg PORT(i: IN STD_LOGIC; o: OUT STD_LOGIC); END COMPONENT;
020- SIGNAL buf_clk0, buf_clk1: STD_LOGIC;
021- BEGIN
022- rst <= '1'; -- keep the uC in the reset state
023- oeb <= '1'; -- disable the RAM output drivers
024-
025- b0: ibuf PORT MAP(i=>kb_clk,o=>buf_clk0); -- buffer the clock from
026- b1: bufg PORT MAP(i=>buf_clk0,o=>buf_clk1); -- the keyboard
027-
028- -- shift keyboard data into the MSb of the scancode register
029- -- on the falling edge of the keyboard clock
030- gather_scancode:
031- PROCESS(buf_clk1,scancode)
032- BEGIN
033- IF(buf_clk1'EVENT AND buf_clk1='0') THEN
034- scancode <= kb_data & scancode(9 DOWNTO 1);
035- END IF;
036- END PROCESS;
037-
038- db <= NOT(scancode(7 DOWNTO 0)); -- show the scancode on the bargraph
039-
040- -- display the key that was pressed on the right LED digit
041- rsb <= "1101101" WHEN scancode(7 DOWNTO 0)="00010110" ELSE -- 1
042- "0100010" WHEN scancode(7 DOWNTO 0)="00011110" ELSE -- 2
044- “1000101" WHEN scancode(7 DOWNTO 0)="00100101" ELSE -- 4
051- "0010010"; -- E
052- END kbd_read_arch;
Listing 21: XS40 UCF file for the PS/2 keyboard interface.
001- net rst loc=p36;
003- net kb_data loc=p69;
004- net kb_clk loc=p68;
012- net db<1> loc=p41;
013- net db<2> loc=p40;
014- net db<3> loc=p39;
015- net db<4> loc=p38;
016- net db<5> loc=p35;
017- net db<6> loc=p81;
018- net db<7> loc=p80;
019- net db<8> loc=p10;
012- net db<1> loc=p44;
013- net db<2> loc=p43;
014- net db<3> loc=p41;
015- net db<4> loc=p40;
016- net db<5> loc=p39;
017- net db<6> loc=p37;
018- net db<7> loc=p36;
019- net db<8> loc=p35;
4.4 Inputing and Outputing Stereo Signals Through the Codec
The stereo codec on the XStend Board is capable of digitizing two analog signals to 20 bits of
resolution while simultaneously generating two analog signals from 20-bit values. A high-level
view of the codec chip is shown on the right-half of Figure 13. Two analog inputs (which are
tpically the left and right channels of a stereo audio signal) enter the codec and are digitized into
two 20-bit values by analog-to-digital converters (ADCs). These values are loaded into shift
registers which are shifted out of a single pin of the codec under control of a shift clock and a
left/right channel selector control input. At the same time, 20-bit values are alternately shifted
into two shift registers in the codec which feed digital-to-analog converters (DACs) that drive
two analog outputs. Signals on these outputs are typically the left and right channels of a stereo
audio signal.
If the FPLD is handling these values in a bit-parallel manner, then the FPLD must contain a set of
shift registers which convert the serial input stream into 20-bit values and another set which
converts 20-bit values into a serial output stream. This is shown in the left-half of Figure 13.
The gating of these shift registers onto the serial input and output pins is synchronized with the
same left/right channel select signal used by the codec chip.
In addition to the shift registers, the FPLD needs circuitry to read and write them and to indicate
when they are full and empty. Since the codec ADCs and DACs generate and consume data at a
set sample rate, it is also necessary to build circuitry which detects overflow and underflow of the
FPLD shift registers if they are not read or written in time.
Figure 13: Connections between the XStend codec chip and the XS Board FPGA or CPLD.
The FPLD circuitry can be decomposed into three modules:
• a clock generator module which outputs the serial data shift clock and the left/right channel
select signals;
• a channel module which contains the shift registers, buffers, read/write control, and
overflow/underflow detection circuitry for a single input/output stream of data;
• a top-level module which combines the clock generator module with two channel modules to
form a complete codec interface circuit.
The VHDL code for the clock generator module is detailed in Listing 24. The inputs and outputs
of the clock generator as defined in the entity declaration are as follows:
clk: This is the main clock input which is typically the 12 MHz clock from the XS Board.
reset: This input synchronously resets the counter the clock generator.
mclk: This output is the master clock for the codec chip.
sclk: This output is the clock for synchronizing serial data transfers between the FPLD and the
codec.
lrck: This output controls the activation of the left and right channel circuitry in the codec and
the FPLD.
bit_cntr: These outputs indicate the current bit being transmitted and received in the serial data
streams.
subcycle_cntr: The duration of each serial data bit is divided into four phases and these outputs
indicate the current phase.
Within the main body of the clock generator architecture section, these operations occur:
gen_clock: This process increments the sequencing counter and toggles the left/right channel
selector when the count reaches the duration for which a channel is active. The codec chip
requires that the channel duration be either 128, 192, or 256 master clock periods in length.
Thus, the total time to handle both channels is 256, 384, or 512 clock periods. This sets the
sampling rate. So using a channel duration of 128 with a 12 MHz clock gives a sampling rate
of 46.875 KHz that is sufficient for audio.
Lines 45-47: The various clocks are output on these lines. The master clock and left/right
selector have already been discussed. The serial data shift clock is one-quarter of the master
clock. So transmitting or receiving a 20-bit value will require 4 × 20 = 80 clock periods, and
this will fit within the shortest possible channel duration.
Line 48: The position of the current data bit in the serial stream for a channel is output here.
Since each bit has a duration of four clock periods, the position of the bit in the stream is just
the sequence counter with the two least-significant bits removed.
Line 49: The position within a bit is output on this line. This is given by the two least-significant
bits of the sequence counter.
Listing 24: VHDL code for the codec clock generator module.
001- LIBRARY IEEE,codec;
004- USE codec.codec.ALL;
005-
006- ENTITY clkgen IS
007- GENERIC
008- (
009- channel_duration: POSITIVE := 128 -- must be 128, 192, or 256
010- );
011- PORT
012- (
013- -- interface I/O signals
014- clk: IN STD_LOGIC; -- clock input
015- reset: IN STD_LOGIC; -- synchronous active-high reset
016- -- codec chip clock signals
017- mclk: OUT STD_LOGIC; -- master clock output to codec
018- sclk: OUT STD_LOGIC; -- serial data clock to codec
019- lrck: OUT STD_LOGIC; -- left/right codec channel select
020- bit_cntr: OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
021- subcycle_cntr: OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
022- );
023- END clkgen;
024-
025- ARCHITECTURE clkgen_arch OF clkgen IS
026- SIGNAL lrck_int: STD_LOGIC;
027- SIGNAL seq: STD_LOGIC_VECTOR(7 DOWNTO 0);
028- BEGIN
029- gen_clock:
030- PROCESS(clk,seq,lrck_int)
031- BEGIN
032- IF (clk'EVENT AND clk='1') THEN
033- IF(reset=yes) THEN -- synchronous reset
034- seq <= (OTHERS=>'0');
035- lrck_int <= left; -- start with left channel of codec
036- ELSIF(seq=channel_duration-1) THEN
037- seq <= (OTHERS=>'0'); -- reset seq every channel period
038- lrck_int <= NOT(lrck_int); -- toggle chan select every period
039- ELSE
040- seq <= seq+1; -- normally, just inc the sequencer
041- lrck_int <= lrck_int; -- don’t change channel selector
042- END IF;
043- END IF;
044- END PROCESS;
045- lrck <= lrck_int; -- output the channel selector to the codec
046- mclk <= clk; -- codec master clock equals input clock
047- sclk <= seq(1); -- serial shift clock is 1/4 of the master clock
048- bit_cntr <= seq(7 DOWNTO 2); -- which bit period is being processed
049- subcycle_cntr <= seq(1 DOWNTO 0); -- position within bit
050- END clkgen_arch;
The VHDL code for the channel module is shown in Listing 25. The inputs and outputs of the
clock generator as defined in the entity declaration are as follows:
reset: This input synchronously resets the channel.
chan_on: A high level on this input activates the channel. This input is usually controlled by the
left/right channel selector.
bit_cntr: These inputs inform the channel of the index of the serial data bit currently being
transmitted and received.
chan_sel: A high level on this input enables the interface that lets the shift registers be read and
written. (Note that despite its name, this input is not controlled by the left/right channel
selector.)
rd: A high level on this input outputs the value stored in the shift register connected to the ADC.
wr: A high level on this input writes a new value into the shift register connected to the DAC.
adc_out: The bits stored in the ADC shift register are read out in parallel through these outputs..
dac_in: The DAC shift register is loaded in parallel with bits passed through these inputs.
adc_out_rdy: This output goes high after all the bits have been shifted from the codec into the
ADC shift register.
adc_overrun: This output goes high if new serial data is shifted into the ADC shift register
before the old contents have been read out through the parallel outputs.
dac_in_rdy: This output goes high after all the bits in the DAC shift register have been shifted
over to the codec.
dac_underrun: This output goes high if the DAC shift register starts shifting data over to the
codec before it has been written through the parallel inputs.
sdin: The serial data stream for the codec DAC is shifted out through this output. (Note that
this output takes its name from the pin it is connected to on the codec chip; it is not an input.)
sdout: The serial data stream from the codec ADC is shifted in through this input. (Note that
this input takes its name from the pin it is connected to on the codec chip; it is not an output.)
Within the main body of the channel module architecture section, these operations occur:
rcv_adc: This process receives serial data from the ADC in the codec. The ADC shift register is
cleared upon reset and a flag is set which indicates the shift register does not contain all the
bits from the ADC. Once the reset is removed and the channel is active, bits are shifted into
the register during the second subcycle of each bit period (the subcycles are numbered 0, 1, 2
and 3). Accepting data on the second subcycle gives the serial data bit plenty of time to
stabilize. The first bit of the serial data (when the bit counter equals 0) contains no data and
is discarded. Then bits 1,2,..., up to the width of the ADC data value are pushed into the shift
register. Then the shifting stops. The shift register is marked as ‘not full’ as soon as a single
bit is shifted in so that the value will not be inadvertently read. The shift register status
changes to full as soon as the last bit enters the shift register.
Line 66: The contents of the shift register are output in a parallel format on this line. These
outputs are not latched and will change as bits are shifted into the register.
Line 69: A flag is maintained that indicates whether the contents of the ADC shift register have
been read. The flag is set when the ADC register for the channel is full and it is selected for a
read operation. The flag will stay set after the read operation is complete. Reading the
register does not empty it. The shift register is no longer full only when the first bit of the
next sample is shifted into it. This will reset the read flag.
read_adc: This process updates the flag that indicates whether the ADC shift register has been
read.
Lines 84—85: A status output is asserted when the data in the ADC shift register is ready for
reading. Reads are permitted when the register is full and has not yet been read. This output
is cleared as soon as a read occurs or new data is shifted into the register.
detect_adc_overrun: This process monitors the ADC shift register and flags an error condition
if the register begins accepting bits from the current sample period but the data from the
previous period has not yet been read.
tx_dac: This process transmits serial data to the DAC in the codec. The DAC shift register is
cleared upon reset and a flag is set which indicates the shift register contains no bits for the
DAC. After the reset is removed, the register can be loaded in parallel if the channel is
selected for a write operation. If no write operation is in process but the channel is active,
then data is shifted out to the codec on the second subcycle. (This gives the data some hold
time so the codec chip can clock it in reliably.) No data is output during the first bit period
because the codec discards this bit, but a flag is set which indicates the register is no longer
empty and a serial transmission is in process. Then bits 1,2,..., up to the width of the DAC
data value are shifted out. As the last bit is output, the flag is set to show the shift register is
now empty.
Line 124: The DAC serial data input of the codec chip is driven by the most-significant bit of the
DAC shift register.
Line 127: A flag is maintained that indicates whether the DAC shift register has been written.
The flag is set when the DAC register for the channel is empty and it is selected for a write
operation. The flag will stay set after the write operation is complete. Writing the register
does not fill it. The shift register is full only when the first bit of the next sample period is
shifted out of it. This will reset the write flag.
write_dac: This process updates the flag that indicates whether the DAC shift register has been
written.
Lines 142—143: A status output is asserted when the DAC shift register is ready to be written
with new input data. Writes are permitted when the register is empty and has not yet been
written. This output is cleared as soon as a write occurs or when data bits start shifting out
of the register.
detect_dac_underrun: This process monitors the DAC shift register and flags an error condition
if the register starts shifting out data but has not yet been written with a new data value for
the current sample period.
Listing 25: VHDL code for the codec channel module.

005-
006- ENTITY channel IS
007- GENERIC
008- (
009- dac_width: POSITIVE := 20;
010- adc_width: POSITIVE := 20
011- );
012- PORT
013- (
017- chan_on: IN STD_LOGIC;
018- bit_cntr: IN STD_LOGIC_VECTOR(5 DOWNTO 0);
019- subcycle_cntr: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
020- chan_sel: IN STD_LOGIC; -- select left/right codec chan for rd/wr
021- rd: IN STD_LOGIC; -- read from the codec ADC
022- wr: IN STD_LOGIC; -- write to the codec DAC
023- adc_out: OUT STD_LOGIC_VECTOR(adc_width-1 DOWNTO 0);-- frm codec ADC
024- dac_in: IN STD_LOGIC_VECTOR(dac_width-1 DOWNTO 0); -- to codec DAC
025- adc_out_rdy: OUT STD_LOGIC; -- ADC output is ready to be read
026- adc_overrun: OUT STD_LOGIC; -- output from ADC channel overwritten
027- dac_in_rdy: OUT STD_LOGIC; -- DAC input is ready to be written
028- dac_underrun: OUT STD_LOGIC; -- input to DAC did not arrive in time
029- -- codec chip I/O signals
030- sdin: OUT STD_LOGIC; -- serial output to codec DAC
031- sdout: IN STD_LOGIC -- serial input from codec ADC
032- );
033- END channel;
034-
035- ARCHITECTURE channel_arch OF channel IS
036- SIGNAL dac_shfreg: STD_LOGIC_VECTOR(dac_width-1 DOWNTO 0);
037- SIGNAL dac_empty: STD_LOGIC; -- DAC shift register is empty
038- SIGNAL dac_wr: STD_LOGIC; -- DAC channel has been written
039- SIGNAL dac_wr_nxt: STD_LOGIC; -- DAC channel has been written
040- SIGNAL dac_in_rdy_int: STD_LOGIC; -- int. ver. DAC is ready for input
041- SIGNAL adc_shfreg: STD_LOGIC_VECTOR(adc_width-1 DOWNTO 0);
042- SIGNAL adc_full: STD_LOGIC; -- ADC shift register is full
043- SIGNAL adc_rd: STD_LOGIC; -- ADC channel has been read
044- SIGNAL adc_rd_nxt: STD_LOGIC; -- the ADC channel has been read
045- SIGNAL adc_out_rdy_int: STD_LOGIC; -- int. ver. ADC ready for output
046- BEGIN
047- -- receives data from codec ADC
048- rcv_adc:
049- PROCESS(clk,chan_on,subcycle_cntr,bit_cntr,adc_shfreg,sdout)
050- BEGIN
051- IF(clk'EVENT AND (clk=yes)) THEN
052- IF(reset='1') THEN
053- adc_shfreg <= (OTHERS=>'0');
054- adc_full <= no;
055- ELSIF((chan_on=yes) AND (subcycle_cntr=1)) THEN
056- IF((bit_cntr>=1) AND (bit_cntr<adc_width)) THEN
057- adc_full <= no;
058- adc_shfreg <= adc_shfreg(adc_width-2 DOWNTO 0) & sdout;
059- ELSIF(bit_cntr=adc_width) THEN
060- adc_full <= yes;
061- adc_shfreg <= adc_shfreg(adc_width-2 DOWNTO 0) & sdout;
062- END IF;
063- END IF;
064- END IF;
065- END PROCESS;
066- adc_out <= adc_shfreg;
067-
068- -- handle reading of ADC data from codec interface
069- adc_rd_nxt <= yes WHEN (adc_full=yes AND chan_sel=yes AND rd=yes) OR
070- (adc_full=yes AND adc_rd=yes)
071- ELSE no;
072- read_adc:
073- PROCESS(clk,adc_rd_nxt)
074- BEGIN
075- IF(clk'EVENT AND clk='1') THEN
076- IF(reset=yes) THEN
077- adc_rd <= no;
078- ELSE
079- adc_rd <= adc_rd_nxt;
080- END IF;
081- END IF;
082- END PROCESS;
083- -- ADC data is ready for reading if reg is full and not read yet
084- adc_out_rdy_int <= yes WHEN adc_full=yes AND adc_rd=no ELSE no;
085- adc_out_rdy <= adc_out_rdy_int;
086-
087- -- detect and signal overwriting of data from the codec ADC channels
088- detect_adc_overrun:
089- PROCESS(clk,reset,bit_cntr,chan_on,adc_out_rdy_int)
090- BEGIN
093- adc_overrun <= no;
094- ELSIF(bit_cntr=1 AND chan_on=yes AND adc_out_rdy_int=yes) THEN
095- adc_overrun <= yes;
096- END IF;
097- END IF;
098- END PROCESS;
099-
100- -- transmits data to codec DAC
101- tx_dac:
102- PROCESS(clk,reset,chan_on,subcycle_cntr,bit_cntr,dac_shfreg)
103- BEGIN
106- dac_shfreg <= (OTHERS=>'0');
107- dac_empty <= yes;
108- ELSIF(chan_sel=yes AND wr=yes) THEN
109- dac_shfreg <= dac_in;
110- ELSIF(chan_on=yes AND subcycle_cntr=1) THEN
111- IF(bit_cntr=0) THEN
112- dac_empty <= no;
113- ELSIF(bit_cntr<dac_width) THEN
114- dac_shfreg <= dac_shfreg(dac_width-2 DOWNTO 0) & '0';
115- ELSIF(bit_cntr=dac_width) THEN
116- dac_empty <= yes;
117- dac_shfreg <= dac_shfreg(dac_width-2 DOWNTO 0) & '0';
118- END IF;
119- END IF;
120- END IF;
121- END PROCESS;
122-
123- -- output the serial data to the SDIN pin of the codec DAC
124- sdin <= dac_shfreg(dac_width-1) WHEN chan_on=yes ELSE '0';
125-
126- -- handle writing of DAC data from codec interface
127- dac_wr_nxt <= yes WHEN (dac_empty=yes AND chan_sel=yes AND wr=yes) OR
128- (dac_empty=yes AND dac_wr=yes)
129- ELSE no;
130- write_dac:
131- PROCESS(clk,reset,dac_wr_nxt)
132- BEGIN
135- dac_wr <= no;
136- ELSE
137- dac_wr <= dac_wr_nxt;
138- END IF;
139- END IF;
140- END PROCESS;
141- -- DAC is ready for writing if reg is empty and not written yet
142- dac_in_rdy_int <= yes WHEN dac_empty=yes AND dac_wr=no ELSE no;
143- dac_in_rdy <= dac_in_rdy_int;
144-
145- -- detect and signal underflow of data to the codec DAC channels
146- detect_dac_underrun:
147- PROCESS(clk,reset,bit_cntr,chan_on,dac_in_rdy_int)
148- BEGIN
151- dac_underrun <= no;
152- ELSIF(bit_cntr=1 AND chan_on=yes AND dac_in_rdy_int=yes) THEN
153- dac_underrun <= yes;
154- END IF;
155- END IF;
156- END PROCESS;
157- END channel_arch;
The VHDL code for the top-level module that combines the clock generator module with two
channel modules is detailed in Listing 26. The inputs and outputs of the top-level module as
defined in the entity declaration are as follows:
reset: This input synchronously resets the two channel modules and the clock generator.
lrsel: This input selects either the right or left channel for parallel read or write operations.
rd: A high level on this input outputs the value stored in the selected shift register connected to
the ADC.
wr: A high level on this input writes a new value into the selected shift register connected to the
DAC.
ladc_out, radc_out: The bits stored in the left and right ADC shift registers are read out in
parallel through these outputs..
ldac_in, rdac_in: The DAC shift registers are loaded in parallel with bits passed through these
inputs.
ladc_out_rdy, rdac_out_rdy: These outputs go high after all the bits have been shifted from the
codec into the left or right ADC shift register, respectively.
adc_overrun: This output goes high if new serial data is shifted into either the left or right ADC
shift register before the old contents have been read out through the parallel outputs.
ldac_in_rdy, rdac_in_rdy: These outputs go high after all the bits in the left or right DAC shift
register have been shifted over to the codec, respectively.
dac_underrun: This output goes high if either the left or right DAC shift register starts shifting
data over to the codec before it has been written through the parallel inputs.
codec.
lrck: This output controls the activation of the left and right channel circuitry in the codec.
sdin: The serial data stream for the codec DAC is shifted out through this output.
sdout: The serial data stream from the codec ADC is shifted in through this input.
Within the main body of the top-level module architecture section, the following modules are
instantiated:
u0: One clock generator module is instantiated. It receives the 12 MHz clock as an input and
generates the master clock, left/right clock, and serial shift clock for the codec. It also
outputs the position of the current bit in the serial stream and the current cycle within each bit
period.
u_left: The module which handles the left channel of the codec is instantiated. This module is
activated during one half of the left/right clock period. It is selected for reading or writing by
the left/right selection input.
u_right: The module which handles the right channel of the codec is instantiated. This module is
activated during the other half of the left/right clock period. It is selected for reading and
writing by the opposite polarity of the left/right selection input.
Lines 129—130: The overrun and underrun error indicators for the total codec interface are
formed by the logical-OR of the associated error outputs of the left and right channel
modules. Thus an error is reported if either channel reports an error.
Line 134: The serial data stream that is transmitted to the codec chip is selected from the output
data stream of the currently-active channel module.
Listing 26: VHDL code for the top-level codec interface module.
005-
006- ENTITY codec_intfc IS
007- GENERIC
008- (
009- dac_width: POSITIVE := 20;
010- adc_width: POSITIVE := 20;
011- channel_duration: POSITIVE := 128 -- must be 128, 192, or 256
012- );
013- PORT
014- (
018- lrsel: IN STD_LOGIC; -- select the left/right chan for rd/wr
019- rd: IN STD_LOGIC; -- read from the codec ADC
020- wr: IN STD_LOGIC; -- write to the codec DAC
021- ladc_out: OUT STD_LOGIC_VECTOR(adc_width-1 DOWNTO 0); -- left ADC
022- radc_out: OUT STD_LOGIC_VECTOR(adc_width-1 DOWNTO 0); -- right ADC
023- ldac_in: IN STD_LOGIC_VECTOR(dac_width-1 DOWNTO 0); -- left DAC
024- rdac_in: IN STD_LOGIC_VECTOR(dac_width-1 DOWNTO 0); -- right DAC
025- ladc_out_rdy: OUT STD_LOGIC; -- left ADC output is ready to be read
026- radc_out_rdy: OUT STD_LOGIC; -- right ADC output is ready to be read
027- adc_overrun: OUT STD_LOGIC; -- ADC data overwritten before read
028- ldac_in_rdy: OUT STD_LOGIC; -- left DAC input ready to be written
029- rdac_in_rdy: OUT STD_LOGIC; -- right DAC input ready to be written
030- dac_underrun: OUT STD_LOGIC; -- DAC not written to in time
032- mclk: OUT STD_LOGIC; -- master clock output to codec
033- sclk: OUT STD_LOGIC; -- serial data clock to codec
034- lrck: OUT STD_LOGIC; -- left/right codec channel select
035- sdin: OUT STD_LOGIC; -- serial output to codec DAC
036- sdout: IN STD_LOGIC -- serial input from codec ADC
037- );
038- END codec_intfc;
039-
040- ARCHITECTURE codec_intfc_arch OF codec_intfc IS
041- SIGNAL lrck_int: STD_LOGIC; -- internal left/right codec channel select
042- SIGNAL bit_cntr: STD_LOGIC_VECTOR(5 DOWNTO 0);
043- SIGNAL subcycle_cntr: STD_LOGIC_VECTOR(1 DOWNTO 0);
044- SIGNAL lsdin: STD_LOGIC;
045- SIGNAL rsdin: STD_LOGIC;
046- SIGNAL ladc_overrun: STD_LOGIC;
047- SIGNAL radc_overrun: STD_LOGIC;
048- SIGNAL ldac_underrun: STD_LOGIC;
049- SIGNAL rdac_underrun: STD_LOGIC;
050- SIGNAL lchan_sel: STD_LOGIC;
051- SIGNAL rchan_sel: STD_LOGIC;
052- SIGNAL lchan_on: STD_LOGIC;
053- SIGNAL rchan_on: STD_LOGIC;
054- BEGIN
055-
056- u0: clkgen
057- GENERIC MAP
058- (
059- channel_duration=>channel_duration
060- )
061- PORT MAP
062- (
063- clk=>clk,
064- reset=>reset,
065- mclk=>mclk,
066- sclk=>sclk,
067- lrck=>lrck_int,
068- bit_cntr=>bit_cntr,
069- subcycle_cntr=>subcycle_cntr
070- );
071- lrck <= lrck_int;
072-
073- lchan_sel <= yes WHEN lrsel=left ELSE no;
074- lchan_on <= yes WHEN lrck_int=left ELSE no;
075- u_left: channel
076- GENERIC MAP
077- (
078- dac_width=>dac_width,
079- adc_width=>adc_width
080- )
081- PORT MAP
082- (
083- clk=>clk,
084- reset=>reset,
085- chan_on=>lchan_on,
087- subcycle_cntr=>subcycle_cntr,
088- chan_sel=>lchan_sel,
089- rd=>rd,
090- wr=>wr,
091- adc_out=>ladc_out,
092- dac_in=>ldac_in,
093- adc_out_rdy=>ladc_out_rdy,
094- adc_overrun=>ladc_overrun,
095- dac_in_rdy=>ldac_in_rdy,
096- dac_underrun=>ldac_underrun,
097- sdin=>lsdin,
098- sdout=>sdout
099- );
100-
101- rchan_sel <= yes WHEN lrsel=right ELSE no;
102- rchan_on <= yes WHEN lrck_int=right ELSE no;
103- u_right: channel
104- GENERIC MAP
105- (
106- dac_width=>dac_width,
107- adc_width=>adc_width
108- )
109- PORT MAP
110- (
111- clk=>clk,
112- reset=>reset,
113- chan_on=>rchan_on,
116- chan_sel=>rchan_sel,
117- rd=>rd,
118- wr=>wr,
119- adc_out=>radc_out,
120- dac_in=>rdac_in,
121- adc_out_rdy=>radc_out_rdy,
122- adc_overrun=>radc_overrun,
123- dac_in_rdy=>rdac_in_rdy,
124- dac_underrun=>rdac_underrun,
125- sdin=>rsdin,
126- sdout=>sdout
127- );
128-
129- dac_underrun <= yes WHEN ldac_underrun=yes OR rdac_underrun=yes ELSE no;
130- adc_overrun <= yes WHEN ladc_overrun=yes OR radc_overrun=yes ELSE no;
131-
132- -- generates the serial data output to the SDIN pin of the
133- -- codec DAC depending on which channel is active
134- sdin <= lsdin WHEN lrck_int=left ELSE rsdin;
135-
136- END codec_intfc_arch;
The interfaces to these three modules are placed into the package shown in
Listing 27. (The I/O declarations in the COMPONENT constructs have been removed for the
sake of brevity.) The declarations for the constants used in these modules are also included in the
package.
Listing 27 : VHDL code for the codec package.
001- LIBRARY IEEE;
004-
005- PACKAGE codec IS
006- CONSTANT yes: STD_LOGIC := '1';
007- CONSTANT no: STD_LOGIC := '0';
008- CONSTANT ready: STD_LOGIC := '1';
009- CONSTANT overrun: STD_LOGIC := '1';
010- CONSTANT underrun: STD_LOGIC := '1';
011- CONSTANT left: STD_LOGIC := '0';
012- CONSTANT right: STD_LOGIC := '1';
013-
014- COMPONENT clkgen
015- GENERIC
016- (
017- ...
018- );
019- PORT
020- (
021- ...
022- );
023- END COMPONENT;
024-
025- COMPONENT channel
026- GENERIC
027- (
028- ...
029- );
030- PORT
031- (
032- ...
033- );
034- END COMPONENT;
035-
036- COMPONENT codec_intfc
037- GENERIC
038- (
039- ...
040- );
041- PORT
042- (
043- ...
044- );
045- END COMPONENT;
046- END PACKAGE;
Once the codec interface module is completed and packaged, we can use it in an application.
The simplest use is to have the FPLD accept the left and right stereo inputs from the codec
ADCs and loop these back to the codec DACs so they can output the stereo signals.
The VHDL code for the loopback application is detailed in Listing 29. The inputs and outputs
of the loopback design are as follows:
clk: This is the 12 MHz clock from the XS Board.
reset: A high level on this input synchronously resets the codec interface module. The reset
input is driven from the parallel port of the PC.
the codec interface.
codec.
sdout: The serial data stream from the codec ADCs are shifted in through this input.
sdin: The serial data stream for the codec DACs are shifted out through this output.
The following modules and processes are placed within the main body of the loopback
application:
u0: This is the instantiation of the codec interface module. Note that the ADC output buses of
this module are connected back to the DAC input buses on lines 43—46.
loop: This process controls the reading of each ADC and the writing of the value back to the
associated DAC. For example, if the output of the left channel ADC is ready to be read and
the left channel DAC is ready to be written, then the left channel is selected and the read and
write control lines are asserted. This reads the data from the ADC shift register and writes it
into the DAC shift register during a single clock cycle. Then the ADC and DAC registers
will no longer be ready for reading or writing so the read and write signals will be deasserted.
Listing 29: VHDL code for a design that uses the codec interface module to do loopback.
004-
005- ENTITY loopback IS
006- PORT
007- (
008- clk: IN STD_LOGIC; -- 12 MHz clock
009- rst: IN STD_LOGIC; -- active-high reset
010- mclk: OUT STD_LOGIC; -- master clock to codec
011- lrck: OUT STD_LOGIC; -- left/right clock to codec
012- sclk: OUT STD_LOGIC; -- serial data shift clock to codec
013- sdout: IN STD_LOGIC; -- serial data from codec ADCs
014- sdin: OUT STD_LOGIC; -- serial data to codec DACs
015- s: OUT STD_LOGIC_VECTOR(1 DOWNTO 0) –- LED segments
016- );
017- END loopback;
018-
019- ARCHITECTURE loopback_arch OF loopback IS
020- SIGNAL lrsel,rd,wr: STD_LOGIC;
021- SIGNAL left_channel,right_channel: STD_LOGIC_VECTOR(7 DOWNTO 0);
022- SIGNAL ldac_in_rdy,rdac_in_rdy: STD_LOGIC;
023- SIGNAL ladc_out_rdy,radc_out_rdy: STD_LOGIC;
024- BEGIN
025- u0: codec_intfc
026- GENERIC MAP
027- (
028- adc_width=>20,
029- dac_width=>20
030- )
031- PORT MAP
032- (
033- clk=>clk,
034- reset=>rst,
035- mclk=>mclk,
036- sclk=>sclk,
037- lrck=>lrck,
038- sdout=>sdout,
039- sdin=>sdin,
040- lrsel=>lrsel,
041- rd=>rd,
042- wr=>wr,
043- ladc_out=>left_channel, -- loop the left channel ADC
044- ldac_in=>left_channel, -- to the left channel DAC
045- radc_out=>right_channel, -- loop the right channel ADC
046- rdac_in=>right_channel, -- to the right channel DAC
047- ladc_out_rdy=>ladc_out_rdy,
048- radc_out_rdy=>radc_out_rdy,
049- ldac_in_rdy=>ldac_in_rdy,
050- rdac_in_rdy=>rdac_in_rdy,
051- dac_underrun=>s(0), -- connect underrun and overrun
052- adc_overrun=>s(1) -- error indicators to LEDs
053- );
054-
055- loop: PROCESS(ldac_in_rdy,ladc_out_rdy,rdac_in_rdy,radc_out_rdy)
056- BEGIN
057- IF(ladc_out_rdy=yes AND ldac_in_rdy=yes) THEN
058- lrsel<=left; -- loopback the left channel
059- rd<=yes; -- assert the read and
060- wr<=yes; -- write control signals
061- ELSIF(radc_out_rdy=yes AND rdac_in_rdy=yes) THEN
062- lrsel<=right; -- loopback the right channel
065- ELSE
066- lrsel<=left; -- default channel selection
067- rd<=no; -- but don’t read or
068- wr<=no; -- write the registers
069- END IF;
070- END PROCESS;
071- END loopback_arch;
Listing 30: XS40 UCF file for the stereo signal loopback application.
003- net sdout loc=p6;
004- net mclk loc=p9;
005- net lrck loc=p66;
006- net sdin loc=p70;
007- net sclk loc=p77;
008- net s<0> loc=p25;
009- net s<1> loc=p26;
001- net clk loc = p9
002- net rst loc = p46
003- net sdout loc = p5
004- net mclk loc = p11
005- net lrck loc = p66
006- net sdin loc = p71
007- net sclk loc = p72
008- net s<0> loc = p21
009- net s<1> loc = p23
are as follows:
• Synthesize the VHDL code in the LOOP40\LOOPBACK.VHD for an XC4005XL FPGA.
• Compile the synthesized netlist using the LOOP40.UCF constraint file (Listing 30).
XS40 to the PC parallel port. Apply 9VDC though jack J9 of the XS40. Remove the shunts
from jumpers J4, J7, and J8 to disable the LEDs. Place a shunt on jumper J17 so the codec
serial output data stream can reach the FPLD. Set all the DIP switches to the OPEN
position.
• Connect a stereo audio source (such as a CD player) to jack J9. Then plug a set of stereo
mini-headphones into jack J10.
• Download the LOOP40.BIT file into the XS40/XStend combination with the command:
XSLOAD LOOP40.BIT.
• Release the reset on the loopback circuit with the command XSPORT 0.
• Start the CD player and listen to the result with the headphones.
are as follows:
• Synthesize the VHDL code in the LOOP95\LOOP.VHD for an XC95108 CPLD.

position.
XSLOAD LOOP95.BIT.
5 XStend V1.2 Schematics
The detailed schematics for the XStend Board are on the following pages.
xstnd1_2.sch-1 - Thu Oct 15 00:58:19 1998
xstnd1_2.sch-2 - Thu Oct 15 00:58:22 1998
xstnd1_2.sch-3 - Thu Oct 15 00:58:24 1998
xstnd1_2.sch-4 - Thu Oct 15 00:58:26 1998
xstnd1_2.sch-5 - Thu Oct 15 00:58:27 1998
XStend Board V1.3 Manual
Revision 1.0, 3/19/1999
XESS Corporation
Copyright ©1999 by X Engineering Software Systems Corporation.
All XS-prefix product designations are trademarks of X Engineering Software Systems.
All XC-prefix product designations are trademarks of Xilinx
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in
any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior
written permission of the publisher. Printed in the United States of America.
Limited Warranty
X Engineering Software Systems Corp. (XESS) warrants that the Product, in the course of its normal use, will be
free from defects in material and workmanship for a period of one (1) year and will conform to XESS’s
specification therefor. This limited warranty shall commence on the date appearing on your purchase receipt.
XESS shall have no liability for any Product returned if XESS determines that the asserted defect a) is not present,
b) cannot reasonably be rectified because of damage occurring before XESS receives the Product, or c) is
attributable to misuse, improper installation, alteration, accident or mishandling while in your possession. Subject
to the limitations specified above, your sole and exclusive warranty shall be, during the period of warranty
specified above and at XESS’s option, the repair or replacement of the product. The foregoing warranty of XESS
shall extend to repaired or replaced Products for the balance of the applicable period of the original warranty or
thirty (30) days from the date of shipment of a repaired or replaced Product, whichever is longer.
THE FOREGOING LIMITED WARRANTY IS XESS’S SOLE WARRANTY AND IS APPLICABLE ONLY TO
PRODUCTS SOLD AS NEW. THE REMEDIES PROVIDED HEREIN ARE IN LIEU OF a) ANY AND ALL
OTHER REMEDIES AND WARRANTIES, WHETHER EXPRESSED OR IMPLIED OR STATUTORY,
INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS
FOR A PARTICULAR PURPOSE, AND b) ANY AND ALL OBLIGATIONS AND LIABILITIES OF XESS
FOR DAMAGES INCLUDING, BUT NOT LIMITED TO ACCIDENTAL, CONSEQUENTIAL, OR SPECIAL
DAMAGES, OR ANY FINANCIAL LOSS, LOST PROFITS OR EXPENSES, OR LOST DATA ARISING OUT
OF OR IN CONNECTION WITH THE PURCHASE, USE OR PERFORMANCE OF THE PRODUCT, EVEN IF
In the United States, some statutes do not allow exclusion or limitations of incidental or consequential damages,
so the limitations above may not apply to you. This warranty gives you specific legal rights, and you may also
have other rights which vary from state to state.
XStend Board V1.3 Manual 2
Table of Contents
1 XStend Overview ......................................................... 3
2 XStend Board Features ................................................... 3
2.1 XS40/XS95 Board Mounting Area ........................................ 6
2.2 LEDs ................................................................. 6
2.3 Switches ............................................................. 8
2.4 VGA Interface ........................................................ 9
2.5 PS/2 Keyboard Interface ............................................. 10
2.6 RAMs ................................................................ 11
2.7 Stereo Codec ........................................................ 12
2.8 XILINX Xchecker Interface ........................................... 13
2.9 Prototyping Area .................................................... 14
2.10 Daughterboard Connector ............................................. 15
3 XStend Board Programmer’s Model ........................................ 15
4 Example Designs for the XStend Board ................................... 20
4.1 Displaying Switch Settings on the LEDs .............................. 20
4.2 Displaying Graphics from RAM Through the VGA Interface .............. 24
4.2.1 VGA Color Signals................................................ 24
4.2.2 VGA Signal Timing................................................ 25
4.2.3 VGA Signal Generator Algorithm................................... 26
4.2.4 VGA Signal Generator in VHDL..................................... 28
4.3 Reading Keyboard Scan Codes Through the PS/2 Interface .............. 37
4.4 Inputing and Outputing Stereo Signals Through the Codec ............. 42
5 XStend V1.3 Schematics ................................................. 60
03/19/99 Revision 1.0

Getting Help!
If you follow the instructions in this manual and you encounter problems, here are some places to
get help:
• If you can't get the XStend Board hardware to work, send an e-mail message describing your
problem to fpga-bugs@xess.com or check our web site at
http://www.xess.com/FPGA.
• If you can't get your XILINX software tools installed properly, send an e-mail message
http://www.xilinx.com/support/searchtd.htm.
1 XStend Overview
The XS40 and XS95 Boards offer a flexible, low-cost method of prototyping FPGA and CPLD
designs. However, their small physical size limits the amount of support circuitry they can hold.
The XStend Board removes this limitation by providing additional support circuitry that the
XS40 and XS95 Boards can access through their breadboard interfaces.
The XStend Board contains resources that extend the range of applications of the XS Boards
into three areas:
• The pushbuttons, DIP switches, LEDs, and prototyping area are useful for basic lab
experiments. These features in combination with the XS Boards replicates the functionality
of the older HW/UW FPGABOARD.
• The VGA monitor interface, PS/2 keyboard/mouse interface, and static RAM let the XS
Boards be used in video and computing experiments.
• The stereo codec and dual-channel analog input/output circuitry are useful for processing of
audio signals in combination with DSP circuits synthesized with XILINX's CORE generation
software.
2 XStend Board Features

• mounting sockets for both an XS40 and an XS95 Board;
• additional bargraph LED and LED digits;
• pushbutton and DIP switches;
• an interface to VGA monitors;
03/19/99 Revision 1.0

• an interface to a PS/2-style keyboard or mouse;
• an additional 64 Kbytes of static RAM (optional);
• a stereo codec with left/right input and output channels.
• an interface to the XILINX Xchecker cable;
• a 2.75"×3.5" prototyping area with selectable 3.3V or 5V supply;
• a 42×2 header connector for add-on daughterboards.
These resources are shown in the simplified view of the XStend Board (Figure 1). Each of these
resources will be described below.
03/19/99 Revision 1.0

Figure 1: XStend Board layout.
03/19/99 Revision 1.0

2.1 XS40/XS95 Board Mounting Area

sockets. These sockets mate with the breadboard interface pins of the XS Boards to give them
access to all the resources of the XStend Board. To use an XS40 Board with the XStend Board,
insert it into the right-most columns of the socket strips. When using an XS95 Board, you
should insert it into the left-most columns of the sockets. There are markings on the XStend
Board to indicate the appropriate column for each type of XS Board.
circuitry will supply VCC and GND to the XStend Board through the mounting sockets. XS40
Boards with 3.3V FPGAs will supply both 3.3V and 5V to the XStend Board, while XS40
Boards with 5V FPGAs and XS95 Boards will supply only 5V.
*Warning: Version 1.0 of the XS40 Board with a 3.3V XC4000XL FPGA will not work with
the XStend Board because it supplies 3.3V but no 5V! You must replace the XC4000XL
FPGA with an XC4000E FPGA and remove the J8 jumper on the XS40 board to switch the
board to 5V operation. Ignore this warning if you have Version 1.1 or higher.
External voltage supplies can also be used with the XStend Board. A 5V power supply can be
connected to header J12 and a 3.3V supply can be attached to header J14 as shown in Figure 2.
These supplies will power the attached XS Board as well as the XStend electronics.
Figure 2: Connection of external power supplies to the XStend Board.
*Warning: Do not attach external voltage supplies while also supplying power to the XStend
Board with an XS Board.
*Warning: Never place shunts on either J12 or J14 or you will short the power supplies to
ground and damage the XStend Board and the attached XS Board..
2.2 LEDs
The XStend Board provides a bargraph LED with eight LEDs (D1—D8) and two more LED
displays (U1 and U2) for use by an XS Board. All of these LEDs are active-low meaning that an
LED segment will glow when a logic-low is applied to it.
03/19/99 Revision 1.0

The LEDs are enabled and disabled by setting the shunts on the 2-pin jumpers as described in
Table 1.
Table 1: Jumper settings for XStend LEDs.
Jumper Setting

power from bargraph LEDs D1—D8. Placing the shunt
on the jumper enables the bargraph LEDs.

power from left LED digit U1. Placing the shunt on the
jumper enables the LED digit.

power from right LED digit U2. Placing the shunt on
the jumper enables the LED digit.
J13 A shunt placed on this jumper will enable the LEDs

when you are using the XStend Board with an XS95
Board. This shunt must be removed if you are using
an XS40 Board with the XStend Board!!
Listing 1 and Listing 2: Connections between the XStend LEDs and the XS95. show the
connections from the XS40 and XS95 Boards to the LEDs on the XStend Board expressed as
UCF constraints (for the UCF syntax and usage tips, check out
http://www.xilinx.com/techdocs/2449.htm).

NET LSB<0> LOC=P3;
NET LSB<1> LOC=P4;
NET LSB<2> LOC=P5;
NET LSB<3> LOC=P78;
NET LSB<4> LOC=P79;
NET LSB<5> LOC=P82;
NET LSB<6> LOC=P83;
NET LDPB LOC=P84;
#
NET RSB<0> LOC=P59;
NET RSB<1> LOC=P57;
NET RSB<2> LOC=P51;
NET RSB<3> LOC=P56;
NET RSB<4> LOC=P50;
NET RSB<5> LOC=P58;
NET RSB<6> LOC=P60;
03/19/99 Revision 1.0

NET RDPB LOC=P28;

#
NET DB<1> LOC=P41;
NET DB<2> LOC=P40;
NET DB<3> LOC=P39;
NET DB<4> LOC=P38;
NET DB<5> LOC=P35;
NET DB<6> LOC=P81;
NET DB<7> LOC=P80;
NET DB<8> LOC=P10;

NET LSB<0> LOC=P1;
NET LSB<1> LOC=P2;
NET LSB<2> LOC=P3;
NET LSB<3> LOC=P75;
NET LSB<4> LOC=P79;
NET LSB<5> LOC=P82;
NET LSB<6> LOC=P83;
NET LDPB LOC=P84;
#
NET RSB<0> LOC=P58;
NET RSB<1> LOC=P56;
NET RSB<2> LOC=P54;
NET RSB<3> LOC=P55;
NET RSB<4> LOC=P53;
NET RSB<5> LOC=P57;
NET RSB<6> LOC=P61;
NET RDPB LOC=P34;
#
NET DB<1> LOC=P44;
NET DB<2> LOC=P43;
NET DB<3> LOC=P41;
NET DB<4> LOC=P40;
NET DB<5> LOC=P39;
NET DB<6> LOC=P37;
NET DB<7> LOC=P36;
NET DB<8> LOC=P35;
2.3 Switches
The XStend has a bank of eight DIP switches and two pushbuttons (labeled SPARE and RESET)
that are accessible from an XS Board. (There is a third pushbutton labeled PROGRAM which is
used to initiate the programming of the XS40 Board. It is not intended to be a general-purpose
input.)
When closed or ON, each DIP switch pulls the connected pin of the XS Board to ground. When
the DIP switch is open or OFF, the pin is pulled high through a 10KΩ resistor.
03/19/99 Revision 1.0

*When not being used, the DIP switches should be left in the open or OFF configuration so
the pins of the XS Board are not tied to ground and can freely move between logic low and
high levels.
When pressed, each pushbutton pulls the connected pin of the XS Board to ground. Otherwise,
the pin is pulled high through a 10 KΩ resistor.
Listing 3 and Listing 4 show the connections from the XS40 and XS95 Boards to the switches
on the XStend Board expressed as UCF constraints.
#
NET SPAREB LOC=P67;
NET RESETB LOC=P37;
#
NET SPAREB LOC=P67;
NET RESETB LOC=P10;
2.4 VGA Interface

The XStend Board provides an XS Board with an interface to a VGA monitor through connector
J5. (Version 1.2 and higher of the XS Boards already have their own VGA interfaces, so the
XStend circuitry is redundant for them.) The XS Board can drive the active-low horizontal and
vertical sync signals that control the width and height of the video frame. The XS Board also has
access to two bits each of red, green, and blue color signals so it can generate pixels in any of
22×22×22=64 different colors.
03/19/99 Revision 1.0

Listing 5 and Listing 6 show the connections from the XS40 and XS95 Boards to the VGA
interface of the XStend Board. (These pin assignments are identical to the pin assignments for
the XS Boards which have their own VGA interfaces.)
# VGA CONNECTIONS
NET VSYNCB LOC=P67;
NET HSYNCB LOC=P19;
NET RED<1> LOC=P18;
NET RED<0> LOC=P23;
# VGA CONNECTIONS
NET VSYNCB LOC=P24;
NET HSYNCB LOC=P15;
NET RED<1> LOC=P14;
NET RED<0> LOC=P18;
2.5 PS/2 Keyboard Interface

The XStend Board provides an XS Board with a PS/2-style interface (mini-DIN connector J6) to
either a keyboard or a mouse. The XS Board receives two signals from the PS/2 interface: a
clock signal and a serial data stream that is synchronized with the falling edges on the clock
signal.
Listing 7 and Listing 8 show the connections from the XS40 and XS95 Boards to the PS/2
interface of the XStend Board (expressed as UCF constraints):
NET KB_CLK LOC=P68;
NET KB_CLK LOC=P26;
03/19/99 Revision 1.0

2.6 RAMs
The XStend Board adds an additional 64 KBytes of RAM to the 32 KBytes already on the XS
Board. The XStend RAM connects to the same pins as the XS Board RAM for the address bus,
data bus, write-enable, and output-enable. The chip-selects of the XStend Board RAMs are
connected to different pins so all the RAMs can be individually selected.
Listing 9 and Listing 10 show the connections from the XS40 and XS95 Boards to their own
RAMs and the RAMs of the XStend Board (expressed as UCF constraints):

NET D<1> LOC=P40;
NET D<2> LOC=P39;
NET D<3> LOC=P38;
NET D<4> LOC=P35;
NET D<5> LOC=P81;
NET D<6> LOC=P80;
NET D<7> LOC=P10;
NET A<1> LOC=P4;
NET A<2> LOC=P5;
NET A<3> LOC=P78;
NET A<4> LOC=P79;
NET A<5> LOC=P82;
NET A<6> LOC=P83;
NET A<7> LOC=P84;
NET A<9> LOC=P57;
NET A<10> LOC=P51;
NET A<11> LOC=P56;
NET A<12> LOC=P50;
NET A<13> LOC=P58;
NET A<14> LOC=P60;
NET D<1> LOC=P43;
NET D<2> LOC=P41;
NET D<3> LOC=P40;
NET D<4> LOC=P39;
NET D<5> LOC=P37;
NET D<6> LOC=P36;
NET D<7> LOC=P35;
NET A<1> LOC=P79;
NET A<2> LOC=P82;
NET A<3> LOC=P84;
NET A<4> LOC=P1;
03/19/99 Revision 1.0

NET A<5> LOC=P3;

NET A<6> LOC=P83;
NET A<7> LOC=P2;
NET A<9> LOC=P56;
NET A<10> LOC=P54;
NET A<11> LOC=P55;
NET A<12> LOC=P53;
NET A<13> LOC=P57;
NET A<14> LOC=P61;
2.7 Stereo Codec

The XStend Board has a stereo codec that accepts two analog input channels from jack J9,
digitizes the analog values, and sends the digital values to the XS Board as a serial bit stream.
The codec also accepts a serial bit stream from the XS Board and converts it into two analog
output signals which exit the XStend Board through jack J10.
The codec is configured by placing shunts on the jumpers as indicated in Table 2.
Table 2: Jumper settings for XStend codec.
Jumper Setting
J11 Placing a shunt on this jumper disables the codec by

holding it in the reset state. No shunt should be placed
on this jumper when the codec is being used.
J17 Removing this shunt prevents the codec’s serial data

output from reaching the XS Board. A shunt should be
placed on this jumper when the codec is being used.
Listing 11 and Listing 12 show the connections from the XS40 Board to the codec interface on
Listing 11: Connections between the XStend stereo codec and the XS40 Board.
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Listing 12: Connections between the XStend stereo codec and the XS95 Board.
The analog stereo input and output signals enter and exit the XStend Board through the 1/8”
jacks J9 and J10, respectively. The output of an audio CD player can be input through J9 and a
set of small stereo headphones can be connected to J10 for listening to the processed output.
The digitized data output from the codec passes through jumper J17 on its way to the XS Board
inserted in the XStend Board. A shunt should be placed on J17 when the codec is being used.
Because the serial data output of the codec is not tristatable and because it shares the input to the
XS Board with other resources on the XStend Board, the shunt on J17 should be removed when
the codec is not being used.
2.8 XILINX Xchecker Interface

An XS40 Board inserted in the XStend Board can be configured and tested using a XILINX
Xchecker cable attached to header J19. When using the Xchecker cable, you must not connect
the cable between the XS Board and the parallel port of the PC. In addition, when using the
Xchecker cable with an XStend/XS40 combination, you must make the following adjustments to
the XS40 Board:
• Remove the shunts from jumpers J4, J6, J10 and J11 of the XS40 Board;
• Remove the serial EPROM from socket U7.
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The connections between the Xchecker cable and the XS40 Board is listed in Table 3.
Table 3: Connections between the XStend Board Xchecker interface and the XS40 Board.
Xchecker Pin XS40 Pin

1 – VCC (+5V) 2
2 – RT 32
3 – GND 52
4 – RD 30
6 – TRIG 7
7 – CCLK 73
9 – DONE 53
10 – TDI 15
11 – DIN 71
12 – TCK 16
13 – PROGRAM 55
14 – TMS 17
15 – INIT 41
16 – CLKI 13
17 – RST 8
18 – CLKO 9
2.9 Prototyping Area

buses run on the bottom side. The VCC and GND buses have connection holes in which a small
wire can be soldered to make a connection to a nearby component through-hole.
Figure 3: Top-side view of the network of VCC and GND buses around the component
through-holes in the XStend Board prototyping area.
prototyping area carry either 5V or 3.3V (see Figure 6). Of course the jumper selection will have
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no effect unless you have both these voltages supplied to the XStend Board either by the XS
Board or by connecting external power supplies.
Figure 4: Shunt placement for setting the VCC bus voltage..
Connections from the XS Board to the prototyping area are made through connector J3. The
arrangement of pins on this connector exactly matches the arrangement of pins on the XS40
Board. For example, the pin at the bottom-left of J3 on the XStend Board corresponds to pin 21
at the bottom-left of the XS40 Board.
The XS95 Board has a completely different pin arrangement than the XS40. Therefore each pin
on J3 is explicitly labelled with the corresponding pin number on the XS95 Board. For example,
the pin at the bottom-left of J3 on the XStend Board is connected to pin 68 near the top-left of
the XS95 Board.
2.10 Daughterboard Connector

connector J18. This 42×2 connector brings all the I/O and VCC/GND from the XS40 or XS95
Board to the daughterboard.
3 XStend Board Programmer’s Model

The interconnections of the XStend Board resources and an XS40 or XS95 Board are shown in
Figure 5 and Figure 6, respectively. These figures remove much of the extraneous detail of the
actual schematics, so we refer to them as programmer’s models.
Items within the shaded area in each figure correspond to circuitry housed on the XS Board. The
remaining items are XStend Board resources.
example, the codec, DIP switch, and microcontroller port P1 are all connected to the same set of
pins on the FPGA or CPLD. So any design has to ensure that only one of these resources is
outputing data at any particular time. (Hence the need in some designs to place the DIP switches
in the OPEN position, or remove the shunt through which the codec SDOUT drives serial data,
or keep the microcontroller in the reset state.)
respectively, in a tabular format which makes it easier to see which resources share common
connections.
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Stereo Codec
Push-buttons
Power/ GND
BOARD Pin
PC Parallel
DIP Switch
(J1,J3,J18)
UW-FPGA
Oscillator
XS40 Pin
Interface
Interface
8051 uC
RAMs
LEDs
VGA
PS/2
Port
Function
15 JTAG TDI; DIN
16 JTAG TCK; CCLK
17 JTAG TMS
36 RST uC reset
66 DIPSW7 LRCK P1.6 PC_S5 DIP switch; codec left-right channel switch; uC I/O port; PC parallel
PC_S6 DIP switch; PS/2 keyboard serial data; uC I/O port; PC parallelP28port status input
P26 status input
71 JTAG TDI; DIN
72 JTAG TDO; DOUT
73 JTAG TCK; CCLK
77 DIPSW5 SCLK P1.4 PC_S4 DIP switch; codec serial I/O clock; uC I/O port; PC parallel port
P25status input
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Stereo Codec
Push-buttons
Power/ GND
BOARD Pin
PC Parallel
DIP Switch
XS95 Pins
UW-FPGA
Oscillator
Interface
Interface
8051 Uc
RAMs
LEDs
VGA
PS/2
Port
(J2)
Function
28 JTAG TDI; DIN
29 JTAG TMS
30 JTAG TCK; CCLK
45 RST uC reset
59 JTAG TDO; DOUT
66 DIPSW7 LRCK P1.6 PC_S5 DIP switch; codec left-right channel select; uC I/O port; PC parallel
PC_S6 DIP switch; PS/2 keyboard serial data; uC I/O port; PC parallelP28
port status input
P26status input
72 DIPSW5 SCLK P1.4 PC_S4 DIP switch; codec serial clock; uC I/O port; PC parallel port status
P25 input
24,67 SPAREBDP VSYNCB P1.7 Pushbutton; XS Board LED decimal-point; VGA horiz. sync.; uC P18I/O port
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4 Example Designs for the XStend Board

With the programmer’s models in hand, several example designs can be built using the XStend
Board coupled with an XS40 or XS95 Board.
4.1 Displaying Switch Settings on the LEDs

This example creates a circuit that displays the settings of the DIP switches on the LEDs and
LED digits of the XStend and XS Boards. The particular set of LEDs which is activated is
selected by the SPARE and RESET pushbuttons. The VHDL code for this example is shown in
Listing 13.
are as follows:
• Synthesize the VHDL code in the SWTCH40\SWITCHES.VHD file for an XC4005XL

FPGA.
• Compile the synthesized netlist using the SWTCH40.UCF constraint file (Listing 14).
logic levels.
• Download the SWTCH40.BIT file into the XS40/XStend combination with the command:
XSLOAD SWTCH40.BIT.
the LEDs.
are as follows:
• Synthesize the VHDL code in the SWTCH95\SWITCHES.VHD file for an XC95108 CPLD.
• Compile the synthesized netlist using the SWTCH95.UCF constraint file (
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Listing 15).
logic levels.
• Download the SWTCH95.SVF file into the XS95/XStend combination with the command:
XSLOAD SWTCH95.SVF.
the LEDs.
Listing 13: VHDL code for using the XStend LEDs and switches.
001- LIBRARY IEEE;
003-
005- PORT
006- (
010-
015-
018- );
019- END switches;
020-
022- BEGIN
023- -- this prevents accidental activation of the RAMs or microcontroller
026-
032-
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038-
044-

002- net s<1> loc=p26;
003- net s<2> loc=p24;
004- net s<3> loc=p20;
005- net s<4> loc=p23;
006- net s<5> loc=p18;
007- net s<6> loc=p19;
037- net db<2> loc=p40;
038- net db<3> loc=p39;
039- net db<4> loc=p38;
040- net db<5> loc=p35;
041- net db<6> loc=p81;
042- net db<7> loc=p80;
043- net db<8> loc=p10;
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002- net s<1> loc=p23;
003- net s<2> loc=p19;
004- net s<3> loc=p17;
005- net s<4> loc=p18;
006- net s<5> loc=p14;
007- net s<6> loc=p15;
037- net db<2> loc=p43;
038- net db<3> loc=p41;
039- net db<4> loc=p40;
040- net db<5> loc=p39;
041- net db<6> loc=p37;
042- net db<7> loc=p36;
043- net db<8> loc=p35;
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4.2 Displaying Graphics from RAM Through the VGA Interface

This section discusses the timing for the signals that drive a VGA monitor and describes a VHDL
module that will let you drive a monitor with a picture stored in RAM.
4.2.1 VGA Color Signals

There are three signals -- red, green, and blue -- that send color information to a VGA monitor.
These three signals each drive an electron gun that emits electrons which paint one primary color
at a point on the monitor screen. Analog levels between 0 (completely dark) and 0.7 V
(maximum brightness) on these control lines tell the monitor what intensities of these three
primary colors to combine to make the color of a dot (or pixel) on the monitor’s screen.
Each analog color input can be set to one of four levels by two digital outputs using a simple
two-bit digital-to-analog converter (see Figure 7). The four possible levels on each analog input
are combined by the monitor to create a pixel with one of 4 × 4 × 4 = 64 different colors. So the
six digital control lines let us select from a palette of 64 colors.
Figure 7: Digital-to-analog interface to a VGA monitor.
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4.2.2 VGA Signal Timing

A single dot of color on a video monitor doesn’t impart much information. A horizontal line of
pixels carries a bit more information. But a frame composed of multiple lines can present an
image on the monitor screen. A frame of VGA video typically has 480 lines and each line usually
contains 640 pixels. In order to paint a frame, there are deflection circuits in the monitor that
move the electrons emitted from the guns both left-to-right and top-to-bottom across the screen.
These deflection circuits require two synchronization signals in order to start and stop the
deflection circuits at the right times so that a line of pixels is painted across the monitor and the
lines stack up from the top to the bottom to form an image. The timing for the VGA
synchronization signals is shown in Figure 8.
Negative pulses on the horizontal sync signal mark the start and end of a line and ensure that the
monitor displays the pixels between the left and right edges of the visible screen area. The actual
pixels are sent to the monitor within a 25.17 µs window. The horizontal sync signal drops low a
minimum of 0.94 µs after the last pixel and stays low for 3.77 µs. A new line of pixels can begin
a minimum of 1.89 µs after the horizontal sync pulse ends. So a single line occupies 25.17 µs of
a 31.77 µs interval. The other 6.6 µs of each line is the horizontal blanking interval during
which the screen is dark.
In an analogous fashion, negative pulses on a vertical sync signal mark the start and end of a
frame made up of video lines and ensure that the monitor displays the lines between the top and
bottom edges of the visible monitor screen. The lines are sent to the monitor within a 15.25 ms
window. The vertical sync signal drops low a minimum of 0.45 ms after the last line and stays
low for 64 µs. The first line of the next frame can begin a minimum of 1.02 ms after the vertical
sync pulse ends. So a single frame occupies 15.25 ms of a 16.784 ms interval. The other 1.534
ms of the frame interval is the vertical blanking interval during which the screen is dark.
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Figure 8: VGA signal timing.
4.2.3 VGA Signal Generator Algorithm

Now we have to figure out a process that will send pixels to the monitor with the correct timing
and framing. We can store a picture in the RAM of the XS Board. Then we can retrieve the
data from the RAM, format it into lines of pixels, and send the lines to the monitor with the
appropriate pulses on the horizontal and vertical sync pulses.
The pseudocode for a single frame of this process is shown in Listing 16. The pseudocode has
two outer loops: one which displays the L lines of visible pixels, and another which inserts the V
blank lines and the vertical sync pulse. Within the first loop, there are two more loops: one
which sends the P pixels of each video line to the monitor, and another which inserts the H blank
pixels and the horizontal sync pulse.
Within the pixel display loop, there are statements to get the next byte from the RAM. Each byte
contains four two-bit pixels. A small loop iteratively extracts each pixel to be displayed from the
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lower two bits of the byte. Then the byte is shifted by two bits so the next pixel will be in the
right position during the next iteration of the loop. Since it has only two bits, each pixel can store
one of four colors. The mapping from the two-bit pixel value to the actual values required by the
monitor electronics is done by the COLOR_MAP() routine.
Listing 16: VGA signal generation pseudocode.

for line_cnt=1 to L
data = RAM(address)
for d=1 to 4
pixel = data & 00000011
data = data>>2
d = d + 1
color = BLANK
hsync = 0
else
hsync = 1
color = BLANK
vsync = 0
else
vsync = 1
address = 0
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Figure 9 shows how to pipeline certain operations to account for delays in accessing data from
the RAM. The pipeline has three stages:
Stage 1: The circuit uses the horizontal and vertical counters to compute the address where the
next pixel is found in RAM. The counters are also used to determine the firing of the sync
pulses and whether the video should be blanked. The pixel data from the RAM, blanking
signal, and sync pulses are latched at the end of this stage so they can be used in the next
stage.
Stage 2: The circuit uses the pixel data and the blanking signal to determine the binary color
outputs. These outputs are latched at the end of this stage.
Stage 3: The binary color outputs are applied to the DAC, which sets the intensity levels for the
monitor’s color guns. The actual pixel is painted on the screen during this stage.
Figure 9: Pipelining of VGA signal generation tasks.
4.2.4 VGA Signal Generator in VHDL

The pseudocode and pipeline timing in the last section will help us to understand the VHDL code
for a VGA signal generator shown in Listing 17. The inputs and outputs of the circuit as defined
in the entity declaration are as follows:
maximum rate at which pixels can be sent to the monitor. The time interval within each line
for transmitting viewable pixels is 25.17 µs, so this VGA generator circuit can only put a
maximum of 25.17 ms × 12 MHz = 302 pixels on each line. For purposes of storing images
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in the RAM, it is convenient to reduce this to 256 pixels per line and blank the remaining 46
pixels. Half of these blank pixels are placed before the 256 viewable pixels and half are
placed after them on a line. This centers the viewable pixels between the left and right edges
of the monitor screen.
hsyncb, vsyncb: The outputs for the horizontal and vertical sync pulses are declared. The
hsyncb output is declared as a buffer because it will also be referenced within the architecture
section as a clock for the vertical line counter.
rgb: The outputs that control the red, green, and blue color guns of the monitor are declared
here. Each gun is controlled by two bits, so there are four possible intensities for each color.
Thus, this circuit can produce 4 × 4 × 4 = 64 different colors.
address, data: These lines declare the outputs for driving the address lines of the RAM and the
inputs for receiving the data from the RAM.
ceb, oeb, web: These are the declarations for the outputs which drive the chip-select, output-
enable, and write-enable control lines of the RAM.
hcnt, vcnt: The counters that store the current horizontal position within a line of pixels and the
vertical position of the line on the screen are declared on these lines. We will call these the
horizontal or pixel counter, and the vertical or line counter, respectively. The line period is
31.77 µs that is 381 clock cycles, so the pixel counter needs at least nine bits of resolution.
Each frame is composed of 528 video lines (only 480 are visible, the other 48 are blanked), so
a ten bit counter is needed for the line counter.
pixrg: This is the declaration for the eight-bit register that stores the four pixels received from
the RAM.
blank, pblank: This line declares the video blanking signal and its registered counterpart that is
used in the next pipeline stage.
inc_horiz_pixel_counter: This process describes the operation of the horizontal pixel counter.
increments on the rising edge of each pixel clock. The range for the horizontal pixel counter
is [0,380]. When the counter reaches 380, it rolls over to zero on the next cycle. Thus, the
counter has a period of 381 pixel clocks. With a pixel clock of 12 MHz, this translates to a
period of 31.75 µs.
inc_vert_line_counter: This process describes the operation of the vertical line counter. The
counter is asynchronously set to zero when the reset input is high. The counter increments
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on the rising edge of the horizontal sync pulse after a line of pixels is completed. The range
for the horizontal pixel counter is [0,527]. When the counter reaches 527, it rolls over to
zero on the next cycle. Thus, the counter has a period of 528 lines. Since the duration of a
line of pixels is 31.75 µs, this makes the frame interval equal to 16.76 ms.
generator. The horizontal sync is set to its inactive high level when the reset is activated.
During normal operations, the horizontal sync output is updated on every pixel clock. The
sync signal goes low on the cycle after the pixel counter reaches 291 and continues until the
cycle after the counter reaches 337. This gives a low horizontal sync pulse of (337-291)=46
pixel clocks. With a pixel clock of 12 MHz, this translates to a low-going horizontal sync
pulse of 3.83 µs. The sync pulse starts 292 clocks after the line of pixels begin, which
translates to 24.33 µs. This is less than the 26.11 µs we stated before. The difference of 1.78
ms translates to 21 pixel clocks. This time interval corresponds to the 23 blank pixels that are
placed before the 256 viewable pixels (minus two clock cycles for pipelining delays).
generate_vert_sync: This process describes the operation of the vertical sync pulse generator.
The vertical sync is set to its inactive high level when the reset is activated. During normal
operations, the vertical sync output is updated after every line of pixels is completed. The
sync signal goes low on the cycle after the line counter reaches 493 and continues until the
cycle after the counter reaches 495. This gives a low vertical sync pulse of (495-493)= 2
lines. With a line interval of 31.75 µs, this translates to a low-going vertical sync pulse of
63.5 µs. The vertical sync pulse starts 494 × 31.75 µs = 15.68 ms after the beginning of the
first video line.
Line 91: This line describes the computation of the combinatorial blanking signal. The video is
blanked after 256 pixels on a line are displayed, or after 480 lines are displayed.
pipeline_blank: This process describes the operation of the pipelined video blanking signal.
Within the process, the blanking signal is stored in a register so it can be used during the next
stage of the pipeline when the color is computed.
Lines 104 -- 106: On these lines, the RAM is permanently selected and writing to the RAM is
disabled. This makes the RAM look like a ROM, which stores video data. In addition, the
outputs from the RAM are disabled when the video is blanked since there is no need for
pixels during the blanking intervals. This isn’t really necessary since no other circuit is trying
to access the RAM.
concatenating the lower nine bits of the line counter with bits 7,6,5,4,3 and 2 of the pixel
counter. With this arrangement, the line counter stores the address of one of 29 = 512 pages.
Each page contains 26 = 64 bytes. Each byte contains four pixels, so each page stores one
line of 256 pixels. The pixel counter increments through the bytes of a page to get the pixels
for the current line. (Note that we don’t need to use bits 1 and 0 of the pixel counter when
computing the RAM address since each byte contains four pixels.) After the line is displayed,
the line counter is incremented to point to the next page.
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update_pixel_register: This process describes the operation of the register that holds the byte of
pixel data read from RAM. The register is asynchronously cleared when the VGA circuit is
reset. The register is updated on the rising edge of each pixel clock. The pixel register is
loaded with data from the RAM whenever the lowest two bits of the pixel counter are both
zero. The active pixel is always in the lower two bits of the register. Each pixel in the RAM
data byte is shifted into the active position by right shifting the register two bits on each rising
clock edge.
mapped into the six bits that drive the red, green and blue color guns. The register is set to
zero (which displays as the color black) when the reset input is high. The color register is
clocked on the rising edge of the pixel clock since this is the rate at which new pixel values
arrive. The value clocked into the register is a function of the pixel value and the blanking
input. When the pipelined blanking input is low (inactive), the color displayed on the monitor
is red, green, blue, or white depending upon whether the pixel value is 00, 01, 10, or 11,
respectively. When the pipelined blanking input is high, the color register is loaded with zero
(black).
Listing 17: VHDL code for a VGA generator.

001- LIBRARY IEEE;
004-
006- PORT
007- (
018- );
020-
022- SIGNAL hcnt: STD_LOGIC_VECTOR(8 DOWNTO 0); -- horizontal pixel counter
024- SIGNAL pixrg: STD_LOGIC_VECTOR(7 DOWNTO 0); -- byte register for 4 pix
025- SIGNAL blank: STD_LOGIC; -- video blanking signal
028- BEGIN
029-
032- BEGIN
034- hcnt <= "000000000";
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037- hcnt <= hcnt + 1;
038- ELSE
039- hcnt <= "000000000";
040- END IF;
041- END IF;
042- END PROCESS;
043-
046- BEGIN
048- vcnt <= "0000000000";
051- vcnt <= vcnt + 1;
052- ELSE
053- vcnt <= "0000000000";
054- END IF;
055- END IF;
056- END PROCESS;
057-
060- BEGIN
062- int_hsyncb <= '1';
066- int_hsyncb <= '0';
067- ELSE
068- int_hsyncb <= '1';
069- END IF;
070- END IF;
072- END PROCESS;
073-
076- BEGIN
077- IF reset='1' THEN -- reset asynchronously inactivates vertical sync
078- vsyncb <= '1';
083- vsyncb <= '0';
084- ELSE
085- vsyncb <= '1';
086- END IF;
087- END IF;
088- END PROCESS;
089-
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095- BEGIN
097- pblank <= '0';
100- END IF;
101- END PROCESS;
102-
107-
111- -- the byte at address ^h1234=^b0001,0010,0011,0100 contains the pixls
114-
117- BEGIN
119- pixrg <= "00000000";
130- ELSE
131- pixrg <= "00" & pixrg(7 DOWNTO 2); -- right-shift pixel register
132- END IF;
133- END IF;
134- END PROCESS;
135-
141- BEGIN
143- rgb <= "000000";
144- ELSIF (clk'EVENT AND clk='1') THEN -- update the color every clock
148- WHEN "00" => rgb <= "110000"; -- red
149- WHEN "01" => rgb <= "001100"; -- green
150- WHEN "10" => rgb <= "000011"; -- blue
152- END CASE;
154- rgb <= "000000"; -- black
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155- END IF;

156- END IF;
157- END PROCESS;
158-
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The steps for compiling and testing the VGA design using an XS40 combined with an XStend
• Synthesize the VHDL code in the VGA40\VGA.VHD file for an XC4005XL FPGA.
logic levels. Set all the DIP switches to the OPEN position.
• Download the VGA40.BIT file and a video test pattern into the XS40/XStend combination
with the command: XSLOAD TESTPATT.HEX VGA40.BIT.
are as follows:
• Synthesize the VHDL code in the VGA95\VGA.VHD file for an XC95108 CPLD.
Compile the synthesized netlist using the VGA95.UCF constraint file (
• Listing 19).
on jumper J17 to keep the XStend codec serial output from interfering. Set all the DIP
• Download the VGA95.SVF file and a video test pattern into the XS95/XStend combination
with the command: XSLOAD TESTPATT.HEX VGA95.SVF.
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4.3 Reading Keyboard Scan Codes Through the PS/2 Interface

This example creates a circuit that accepts scan codes from a keyboard attached to the PS/2
interface of the XStend Board. The binary pattern of the scan code is displayed on the bargraph
LEDs. In addition, if a scan code for one of the keys '0'—'9' arrives, then the numeral will be
displayed on the right LED display of the XStend Board.
The format of the scan code transmissions from the keyboard are shown in Figure 10. The
keyboard electronics drive the clock and data lines. The start of a scan code transmission is
indicated by a low level on the data line on the falling edge of the clock. The eight bits of the
scan code follow (starting with the least-significant bit) on successive falling clock edges. These
are followed by an odd-parity bit and then a high-level stop bit.
When the clock line goes high after the stop bit, the receiver (in this case, the FPGA or CPLD on
the XS Board inserted in the XStend Board) can pull the clock line low to inhibit any further
transmissions. After the clock line is released and it returns to a high level, the keyboard can
send another scan code. If the receiver never pulls the clock line low, then the keyboard will
send scan codes whenever a key is pressed.
Figure 10: Keyboard data transmission waveforms.
The VHDL code for this example is shown in . The inputs and outputs of the circuit as defined in
the entity declaration are as follows:
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Lines 22 & 23: The microcontroller reset pin and the RAM output-enable pin are driven high so
these chips cannot interfere while receiving data from the keyboard.
Lines 25 & 26: The keyboard clock passes through an input buffer and then a global clock buffer
before it reaches the rest of the circuitry. (These buffers are declared on lines 18 and 19,
respectively.) The global clock buffer distributes the clock signal with minimal skew in the
XS40 Board FPGA. These statements are not used with the CPLD in the XS95 Board.
gather_scancode: On every falling edge of kb_clk, this process shifts the data bit on the kb_data
input into the most-significant bit of a 10-bit shift register. After 11 clock cycles, the lower 8
bits of the register will contain the scan code, the upper 2 bits will store the stop and parity
bits, and the start bit will have been shifted through the entire register and discarded.
bargraph. Since the bargraph segments are active-low, a segment will light for every ‘1’ bit
in the shift register. The LED segment drivers are not registered so there will be some
flickering as the shift register contents change.
Lines 40-51: If the scan code in the shift register matches the codes for the digits 0-9, then the
right LED digit segments will be activated to display the corresponding digit. If the scan
code does not match one of these codes, the letter ‘E’ is displayed.
are as follows:
• Synthesize the VHDL code in the KEYBRD40\KEYBRD.VHD for an XC4005XL FPGA.
• Attach a keyboard to the PS/2 connector of the XStend Board.
• Download the KEYBRD40.BIT file into the XS40/XStend combination with the command:
XSLOAD KEYBRD40.BIT.
are as follows:
• Synthesize the VHDL code in the KEYBRD95\KEYBRD.VHD for an XC95108 CPLD.
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• Download the KEYBRD95.SVF file into the XS95/XStend combination with the command:
XSLOAD KEYBRD95.SVF.
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Listing 20: VHDL code for receiving keyboard scan codes from the PS/2 interface.
001- LIBRARY IEEE;
003-
005- PORT
006- (
009- kb_data: IN STD_LOGIC; -- serial data from the keyboard
013- );
014- END kbd_read;
015-
021- BEGIN
024-
027-
032- BEGIN
035- END IF;
036- END PROCESS;
037-
038- db <= NOT(scancode(7 DOWNTO 0)); -- show the scancode on the bargraph
039-
051- "0010010"; -- E
03/19/99 Revision 1.0

012- net db<1> loc=p41;
013- net db<2> loc=p40;
014- net db<3> loc=p39;
015- net db<4> loc=p38;
016- net db<5> loc=p35;
017- net db<6> loc=p81;
018- net db<7> loc=p80;
019- net db<8> loc=p10;
012- net db<1> loc=p44;
013- net db<2> loc=p43;
014- net db<3> loc=p41;
015- net db<4> loc=p40;
016- net db<5> loc=p39;
017- net db<6> loc=p37;
018- net db<7> loc=p36;
019- net db<8> loc=p35;
03/19/99 Revision 1.0

4.4 Inputing and Outputing Stereo Signals Through the Codec

The stereo codec on the XStend Board is capable of digitizing two analog signals to 20 bits of
resolution while simultaneously generating two analog signals from 20-bit values. A high-level
view of the codec chip is shown on the right-half of Figure 11. Two analog inputs (which are
tpically the left and right channels of a stereo audio signal) enter the codec and are digitized into
two 20-bit values by analog-to-digital converters (ADCs). These values are loaded into shift
registers which are shifted out of a single pin of the codec under control of a shift clock and a
left/right channel selector control input. At the same time, 20-bit values are alternately shifted
into two shift registers in the codec which feed digital-to-analog converters (DACs) that drive
two analog outputs. Signals on these outputs are typically the left and right channels of a stereo
audio signal.
If the FPLD is handling these values in a bit-parallel manner, then the FPLD must contain a set of
shift registers which convert the serial input stream into 20-bit values and another set which
converts 20-bit values into a serial output stream. This is shown in the left-half of Figure 11.
The gating of these shift registers onto the serial input and output pins is synchronized with the
same left/right channel select signal used by the codec chip.
In addition to the shift registers, the FPLD needs circuitry to read and write them and to indicate
when they are full and empty. Since the codec ADCs and DACs generate and consume data at a
set sample rate, it is also necessary to build circuitry which detects overflow and underflow of the
FPLD shift registers if they are not read or written in time.
Figure 11: Connections between the XStend codec chip and the XS Board FPGA or CPLD.
• a clock generator module which outputs the serial data shift clock and the left/right channel
select signals;
03/19/99 Revision 1.0

• a channel module which contains the shift registers, buffers, read/write control, and
• a top-level module which combines the clock generator module with two channel modules to
form a complete codec interface circuit.
The VHDL code for the clock generator module is detailed in Listing 23. The inputs and outputs
of the clock generator as defined in the entity declaration are as follows:
codec.
the FPLD.
bit_cntr: These outputs indicate the current bit being transmitted and received in the serial data
streams.
subcycle_cntr: The duration of each serial data bit is divided into four phases and these outputs
indicate the current phase.
gen_clock: This process increments the sequencing counter and toggles the left/right channel
selector when the count reaches the duration for which a channel is active. The codec chip
requires that the channel duration be either 128, 192, or 256 master clock periods in length.
Thus, the total time to handle both channels is 256, 384, or 512 clock periods. This sets the
sampling rate. So using a channel duration of 128 with a 12 MHz clock gives a sampling rate
of 46.875 KHz that is sufficient for audio.
selector have already been discussed. The serial data shift clock is one-quarter of the master
clock. So transmitting or receiving a 20-bit value will require 4 × 20 = 80 clock periods, and
this will fit within the shortest possible channel duration.
Line 48: The position of the current data bit in the serial stream for a channel is output here.
Since each bit has a duration of four clock periods, the position of the bit in the stream is just
the sequence counter with the two least-significant bits removed.
Line 49: The position within a bit is output on this line. This is given by the two least-significant
bits of the sequence counter.
03/19/99 Revision 1.0

Listing 23: VHDL code for the codec clock generator module.
002- USE IEEE.std_logic_1164.ALL;
005-
007- GENERIC
008- (
009- CHANNEL_DURATION: positive := 128 -- must be 128
010- );
011- PORT
012- (
014- clk: IN std_logic; -- clock input
015- reset: IN std_logic; -- synchronous active-high reset
017- mclk: OUT std_logic; -- master clock output to codec
018- sclk: OUT std_logic; -- serial data clock to codec
019- lrck: OUT std_logic; -- left/right codec channel select
020- bit_cntr: OUT std_logic_vector(5 DOWNTO 0);
021- subcycle_cntr: OUT std_logic_vector(1 DOWNTO 0)
022- );
023- END clkgen;
024-
026- SIGNAL lrck_int: std_logic;
027- SIGNAL seq: std_logic_vector(7 DOWNTO 0);
028- BEGIN
029- gen_clock:
031- BEGIN
032- IF (clk'event AND clk='1') THEN
033- IF(reset=YES) THEN -- synchronous reset
034- seq <= (OTHERS=>'0');
035- lrck_int <= LEFT; -- start with left channel of codec
036- ELSIF(seq=CHANNEL_DURATION-1) THEN
037- seq <= (OTHERS=>'0'); -- reset sequencer every channel period
038- lrck_int <= NOT(lrck_int); -- toggle channel sel every period
039- ELSE
040- seq <= seq+1;
041- lrck_int <= lrck_int;
042- END IF;
043- END IF;
044- END PROCESS;
047- sclk <= seq(1); -- serial data shift clock is 1/4 of the master clock
048- bit_cntr <= seq(7 DOWNTO 2);
049- subcycle_cntr <= seq(1 DOWNTO 0);
03/19/99 Revision 1.0

The VHDL code for the channel module is shown in Listing 24. The inputs and outputs of the
clock generator as defined in the entity declaration are as follows:
chan_on: A high level on this input activates the channel. This input is usually controlled by the
left/right channel selector.
chan_sel: A high level on this input enables the interface that lets the shift registers be read and
written. (Note that despite its name, this input is not controlled by the left/right channel
selector.)
rd: A high level on this input outputs the value stored in the shift register connected to the ADC.
wr: A high level on this input writes a new value into the shift register connected to the DAC.
adc_out: The bits stored in the ADC shift register are read out in parallel through these outputs..
adc_out_rdy: This output goes high after all the bits have been shifted from the codec into the
ADC shift register.
dac_in_rdy: This output goes high after all the bits in the DAC shift register have been shifted
over to the codec.
dac_underrun: This output goes high if the DAC shift register starts shifting data over to the
codec before it has been written through the parallel inputs.
sdin: The serial data stream for the codec DAC is shifted out through this output. (Note that
this output takes its name from the pin it is connected to on the codec chip; it is not an input.)
sdout: The serial data stream from the codec ADC is shifted in through this input. (Note that
this input takes its name from the pin it is connected to on the codec chip; it is not an output.)
rcv_adc: This process receives serial data from the ADC in the codec. The ADC shift register is
cleared upon reset and a flag is set which indicates the shift register does not contain all the
bits from the ADC. Once the reset is removed and the channel is active, bits are shifted into
03/19/99 Revision 1.0

the register during the third subcycle of each bit period (the subcycles are numbered 0, 1, 2
and 3). Accepting data on the third subcycle gives the serial data bit plenty of time to
stabilize. Bits 1,2,..., up to the width of the ADC data value are pushed into the shift register.
Then the shifting stops. The shift register is marked as ‘not full’ as soon as a single bit is
shifted in so that the value will not be inadvertently read. The shift register status changes to
full as soon as the last bit enters the shift register.
Line 66: The contents of the shift register are output in a parallel format on this line. These
outputs are not latched and will change as bits are shifted into the register.
Line 69: A flag is maintained that indicates whether the contents of the ADC shift register have
been read. The flag is set when the ADC register for the channel is full and it is selected for a
read operation. The flag will stay set after the read operation is complete. Reading the
register does not empty it. The shift register is no longer full only when the first bit of the
next sample is shifted into it. This will reset the read flag.
read_adc: This process updates the flag that indicates whether the ADC shift register has been
read.
Lines 84—85: A status output is asserted when the data in the ADC shift register is ready for
reading. Reads are permitted when the register is full and has not yet been read. This output
is cleared as soon as a read occurs or new data is shifted into the register.
detect_adc_overrun: This process monitors the ADC shift register and flags an error condition
if the register begins accepting bits from the current sample period but the data from the
previous period has not yet been read.
tx_dac: This process transmits serial data to the DAC in the codec. The DAC shift register is
cleared upon reset and a flag is set which indicates the shift register contains no bits for the
DAC. After the reset is removed, the register can be loaded in parallel if the channel is
selected for a write operation. If no write operation is in process but the channel is active,
then data is shifted out to the codec on the third subcycle. (This gives the data some hold
time so the codec chip can clock it in reliably.) During the first bit period, a flag is set which
indicates the register is no longer empty and a serial transmission is in process. Then bits
1,2,..., up to the width of the DAC data value are shifted out. As the last bit is output, the
flag is set to show the shift register is now empty.
Line 123: The DAC serial data input of the codec chip is driven by the most-significant bit of the
DAC shift register.
Line 126: A flag is maintained that indicates whether the DAC shift register has been written.
The flag is set when the DAC register for the channel is empty and it is selected for a write
operation. The flag will stay set after the write operation is complete. Writing the register
does not fill it. The shift register is full only when the first bit of the next sample period is
shifted out of it. This will reset the write flag.
03/19/99 Revision 1.0

write_dac: This process updates the flag that indicates whether the DAC shift register has been
written.
Lines 141—142: A status output is asserted when the DAC shift register is ready to be written
with new input data. Writes are permitted when the register is empty and has not yet been
written. This output is cleared as soon as a write occurs or when data bits start shifting out
of the register.
detect_dac_underrun: This process monitors the DAC shift register and flags an error condition
if the register starts shifting out data but has not yet been written with a new data value for
the current sample period.
Listing 24: VHDL code for the codec channel module.

005-
007- GENERIC
008- (
009- DAC_WIDTH: positive := 20;
010- ADC_WIDTH: positive := 20
011- );
012- PORT
013- (
017- chan_on: IN std_logic;
018- bit_cntr: IN std_logic_vector(5 DOWNTO 0);
019- subcycle_cntr: IN std_logic_vector(1 DOWNTO 0);
020- chan_sel: IN std_logic; -- select left/right channel for read/write
021- rd: IN std_logic; -- read from the codec ADC
022- wr: IN std_logic; -- write to the codec DAC
023- adc_out: OUT std_logic_vector(ADC_WIDTH-1 DOWNTO 0); -- ADC output
024- dac_in: IN std_logic_vector(DAC_WIDTH-1 DOWNTO 0); -- DAC input
025- adc_out_rdy: OUT std_logic; -- ADC output is ready to be read
026- adc_overrun: OUT std_logic; -- ADC overwritten before being read
027- dac_in_rdy: OUT std_logic; -- DAC input is ready to be written
028- dac_underrun: OUT std_logic; -- input to DAC did not arrive in time
030- sdin: OUT std_logic; -- serial output to codec DAC
031- sdout: IN std_logic -- serial input from codec ADC
032- );
033- END channel;
034-
036- SIGNAL dac_shfreg: std_logic_vector(DAC_WIDTH-1 DOWNTO 0); -- DAC shf rg
037- SIGNAL dac_empty: std_logic; -- DAC shift register is empty
038- SIGNAL dac_wr: std_logic; -- the DAC channel has been written
039- SIGNAL dac_wr_nxt: std_logic; -- the DAC channel has been written
040- SIGNAL dac_in_rdy_int: std_logic; -- internal version of dac_in_rdy
041- SIGNAL adc_shfreg: std_logic_vector(ADC_WIDTH-1 DOWNTO 0); -- ADC shf rg
042- SIGNAL adc_full: std_logic; -- ADC shift register is full
03/19/99 Revision 1.0

043- SIGNAL adc_rd: std_logic; -- the ADC channel has been read
044- SIGNAL adc_rd_nxt: std_logic; -- the ADC channel has been read
045- SIGNAL adc_out_rdy_int: std_logic; -- internal version adc_out_rdy
046- BEGIN
048- rcv_adc:
050- BEGIN
051- IF(clk'event AND (clk=YES)) THEN
054- adc_full <= NO;
055- ELSIF((chan_on=YES) AND (subcycle_cntr=2)) THEN
056- IF(bit_cntr<ADC_WIDTH-1) THEN
058- adc_shfreg <= adc_shfreg(ADC_WIDTH-2 DOWNTO 0) & sdout;
059- ELSIF(bit_cntr=ADC_WIDTH-1) THEN
060- adc_full <= YES;
062- END IF;
063- END IF;
064- END IF;
065- END PROCESS;
067-
069- adc_rd_nxt <= YES WHEN (adc_full=YES AND chan_sel=YES AND rd=YES) OR
070- (adc_full=YES AND adc_rd=YES)
071- ELSE NO;
072- read_adc:
074- BEGIN
075- IF(clk'event AND clk='1') THEN
076- IF(reset=YES) THEN
077- adc_rd <= NO;
078- ELSE
080- END IF;
081- END IF;
082- END PROCESS;
083- -- ADC data is ready if register is full and hasn't been read yet
084- adc_out_rdy_int <= YES WHEN adc_full=YES AND adc_rd=NO ELSE NO;
086-
090- BEGIN
093- adc_overrun <= NO;
094- ELSIF(bit_cntr=1 AND chan_on=YES AND adc_out_rdy_int=YES) THEN
095- adc_overrun <= YES;
096- END IF;
097- END IF;
098- END PROCESS;
099-
101- tx_dac:
03/19/99 Revision 1.0

103- BEGIN
107- dac_empty <= YES;
108- ELSIF(chan_sel=YES AND wr=YES) THEN
110- ELSIF(chan_on=YES AND subcycle_cntr=2) THEN
111- IF(bit_cntr<DAC_WIDTH-1) THEN
112- dac_empty <= NO;
113- dac_shfreg <= dac_shfreg(DAC_WIDTH-2 DOWNTO 0) & '0';
114- ELSIF(bit_cntr=DAC_WIDTH-1) THEN
117- END IF;
118- END IF;
119- END IF;
120- END PROCESS;
121-
123- sdin <= dac_shfreg(DAC_WIDTH-1) WHEN chan_on=YES ELSE '0';
124-
126- dac_wr_nxt <= YES WHEN (dac_empty=YES AND chan_sel=YES AND wr=YES) OR
127- (dac_empty=YES AND dac_wr=YES)
128- ELSE NO;
129- write_dac:
131- BEGIN
134- dac_wr <= NO;
135- ELSE
137- END IF;
138- END IF;
139- END PROCESS;
140- -- DAC is ready if register is empty and hasn't been written yet
141- dac_in_rdy_int <= YES WHEN dac_empty=YES AND dac_wr=NO ELSE NO;
143-
147- BEGIN
150- dac_underrun <= NO;
151- ELSIF(bit_cntr=1 AND chan_on=YES AND dac_in_rdy_int=YES) THEN
152- dac_underrun <= YES;
153- END IF;
154- END IF;
155- END PROCESS;
03/19/99 Revision 1.0

The VHDL code for the top-level module that combines the clock generator module with two
channel modules is detailed in Listing 25. The inputs and outputs of the top-level module as
rd: A high level on this input outputs the value stored in the selected shift register connected to
the ADC.
wr: A high level on this input writes a new value into the selected shift register connected to the
DAC.
ldac_in, rdac_in: The DAC shift registers are loaded in parallel with bits passed through these
inputs.
ladc_out_rdy, rdac_out_rdy: These outputs go high after all the bits have been shifted from the
codec into the left or right ADC shift register, respectively.
adc_overrun: This output goes high if new serial data is shifted into either the left or right ADC
shift register before the old contents have been read out through the parallel outputs.
ldac_in_rdy, rdac_in_rdy: These outputs go high after all the bits in the left or right DAC shift
register have been shifted over to the codec, respectively.
dac_underrun: This output goes high if either the left or right DAC shift register starts shifting
data over to the codec before it has been written through the parallel inputs.
codec.
Within the main body of the top-level module architecture section, the following modules are
instantiated:
03/19/99 Revision 1.0

u0: One clock generator module is instantiated. It receives the 12 MHz clock as an input and
generates the master clock, left/right clock, and serial shift clock for the codec. It also
outputs the position of the current bit in the serial stream and the current cycle within each bit
period.
Lines 73—75: The input signals to the codec on the XStend V1.3 Board pass through inverters.
Therefore, the clock signals are inverted on these lines to remove the effect of the inverters.
u_left: The module which handles the left channel of the codec is instantiated. This module is
activated during one half of the left/right clock period. It is selected for reading or writing by
the left/right selection input.
u_right: The module which handles the right channel of the codec is instantiated. This module is
activated during the other half of the left/right clock period. It is selected for reading and
writing by the opposite polarity of the left/right selection input.
Lines 133—134: The overrun and underrun error indicators for the total codec interface are
formed by the logical-OR of the associated error outputs of the left and right channel
modules. Thus an error is reported if either channel reports an error.
Line 138: The serial data stream that is transmitted to the codec chip is selected from the output
data stream of the currently-active channel module. The data stream input to the codec on
the XStend V1.3 Board passes through an inverter. Therefore, the data stream is inverted on
this line to remove the effect of the inverter.
03/19/99 Revision 1.0

Listing 25: VHDL code for the top-level codec interface module.
005-
007- GENERIC
008- (
010- ADC_WIDTH: positive := 20;
012- );
013- PORT
014- (
018- lrsel: IN std_logic; -- select left/right channel for read/write
021- ladc_out: OUT std_logic_vector(ADC_WIDTH-1 DOWNTO 0); -- left ADC
022- radc_out: OUT std_logic_vector(ADC_WIDTH-1 DOWNTO 0); -- right ADC
023- ldac_in: IN std_logic_vector(DAC_WIDTH-1 DOWNTO 0); -- left DAC
024- rdac_in: IN std_logic_vector(DAC_WIDTH-1 DOWNTO 0); -- right DAC
025- ladc_out_rdy: OUT std_logic; -- left ADC output is ready to be read
026- radc_out_rdy: OUT std_logic; -- right ADC output is ready to be read
028- ldac_in_rdy: OUT std_logic; -- left DAC input is ready to be written
029- rdac_in_rdy: OUT std_logic; --right DAC input is ready to be written
030- dac_underrun: OUT std_logic; -- DAC did not receive data in time
037- );
039-
041- SIGNAL mclk_int: std_logic; -- internal codec master clock
042- SIGNAL lrck_int: std_logic; -- internal left/right codec channel select
043- SIGNAL sclk_int: std_logic; -- internal codec data shift clock
044- SIGNAL bit_cntr: std_logic_vector(5 DOWNTO 0);
045- SIGNAL subcycle_cntr: std_logic_vector(1 DOWNTO 0);
046- SIGNAL lsdin: std_logic;
047- SIGNAL rsdin: std_logic;
048- SIGNAL ladc_overrun: std_logic;
049- SIGNAL radc_overrun: std_logic;
050- SIGNAL ldac_underrun: std_logic;
051- SIGNAL rdac_underrun: std_logic;
052- SIGNAL lchan_sel: std_logic;
053- SIGNAL rchan_sel: std_logic;
054- SIGNAL lchan_on: std_logic;
055- SIGNAL rchan_on: std_logic;
056- BEGIN
057-
03/19/99 Revision 1.0

058- u0: clkgen

059- GENERIC MAP
060- (
061- CHANNEL_DURATION=>CHANNEL_DURATION
062- )
063- PORT MAP
064- (
065- clk=>clk,
066- reset=>reset,
067- mclk=>mclk_int,
068- sclk=>sclk_int,
072- );
073- lrck <= NOT(lrck_int); -- invert because of inverter in XStend V1.3
074- mclk <= NOT(mclk_int);
075- sclk <= NOT(sclk_int);
076-
077- lchan_sel <= YES WHEN lrsel=LEFT ELSE NO;
078- lchan_on <= YES WHEN lrck_int=LEFT ELSE NO;
080- GENERIC MAP
081- (
082- DAC_WIDTH=>DAC_WIDTH,
083- ADC_WIDTH=>ADC_WIDTH
084- )
085- PORT MAP
086- (
087- clk=>clk,
088- reset=>reset,
093- rd=>rd,
094- wr=>wr,
101- sdin=>lsdin,
102- sdout=>sdout
103- );
104-
105- rchan_sel <= YES WHEN lrsel=RIGHT ELSE NO;
106- rchan_on <= YES WHEN lrck_int=RIGHT ELSE NO;
108- GENERIC MAP
109- (
112- )
113- PORT MAP
114- (
115- clk=>clk,
116- reset=>reset,
03/19/99 Revision 1.0

121- rd=>rd,
122- wr=>wr,
129- sdin=>rsdin,
130- sdout=>sdout
131- );
132-
133- dac_underrun <= YES WHEN ldac_underrun=YES OR rdac_underrun=YES ELSE NO;
134- adc_overrun <= YES WHEN ladc_overrun=YES OR radc_overrun=YES ELSE NO;
135-
137- -- codec DAC depending on which channel is being loaded
138- sdin <= NOT(lsdin) WHEN lrck_int=LEFT ELSE NOT(rsdin);
139-
The interfaces to these three modules are placed into the package shown in Listing 26. (The I/O
declarations in the COMPONENT constructs have been removed for the sake of brevity.) The
declarations for the constants used in these modules are also included in the package.
Listing 26 : VHDL code for the codec package.

001- LIBRARY IEEE;
004-
013-
015- GENERIC
016- (
017- ...
018- );
019- PORT
020- (
021- ...
022- );
023- END COMPONENT;
024-
026- GENERIC
027- (
028- ...
03/19/99 Revision 1.0

029- );
030- PORT
031- (
032- ...
033- );
034- END COMPONENT;
035-
037- GENERIC
038- (
039- ...
040- );
041- PORT
042- (
043- ...
044- );
045- END COMPONENT;
046- END PACKAGE;
03/19/99 Revision 1.0

Once the codec interface module is completed and packaged, we can use it in an application.
The simplest use is to have the FPLD accept the left and right stereo inputs from the codec
ADCs and loop these back to the codec DACs so they can output the stereo signals.
The VHDL code for the loopback application is detailed in Listing 27. The inputs and outputs
of the loopback design are as follows:
reset: A high level on this input synchronously resets the codec interface module. The reset
input is driven from the parallel port of the PC.
the codec interface.
codec.
application:
u0: This is the instantiation of the codec interface module. Note that the ADC output buses of
this module are connected back to the DAC input buses on lines 43—46.
loop: This process controls the reading of each ADC and the writing of the value back to the
associated DAC. For example, if the output of the left channel ADC is ready to be read and
the left channel DAC is ready to be written, then the left channel is selected and the read and
write control lines are asserted. This reads the data from the ADC shift register and writes it
into the DAC shift register during a single clock cycle. Then the ADC and DAC registers
will no longer be ready for reading or writing so the read and write signals will be deasserted.
03/19/99 Revision 1.0

Listing 27: VHDL code for a design that uses the codec interface module to do loopback.
004-
006- PORT
007- (
016- );
017- END loopback;
018-
024- BEGIN
026- GENERIC MAP
027- (
028- adc_width=>20,
029- dac_width=>20
030- )
031- PORT MAP
032- (
033- clk=>clk,
034- reset=>rst,
035- mclk=>mclk,
036- sclk=>sclk,
037- lrck=>lrck,
038- sdout=>sdout,
039- sdin=>sdin,
040- lrsel=>lrsel,
041- rd=>rd,
042- wr=>wr,
053- );
054-
056- BEGIN
03/19/99 Revision 1.0


065- ELSE
069- END IF;
070- END PROCESS;
008- net s<0> loc=p25;
009- net s<1> loc=p26;
008- net s<0> loc = p21
009- net s<1> loc = p23
03/19/99 Revision 1.0

are as follows:
• Synthesize the VHDL code in the LOOP40\LOOPBACK.VHD for an XC4005XL FPGA.
position.
XSLOAD LOOP40.BIT.
are as follows:
• Synthesize the VHDL code in the LOOP95\LOOP.VHD for an XC95108 CPLD.
position.
XSLOAD LOOP95.BIT.
03/19/99 Revision 1.0

5 XStend V1.3 Schematics

The detailed schematics for the XStend Board are on the following pages.
03/19/99 Revision 1.0

xstnd1_3.sch-1 - Mon Feb 8 15:50:00 1999
xstnd1_3.sch-2 - Mon Feb 8 15:50:02 1999
xstnd1_3.sch-3 - Mon Feb 8 15:50:04 1999
xstnd1_3.sch-4 - Mon Feb 8 15:50:05 1999
xstnd1_3.sch-5 - Mon Feb 8 15:50:07 1999
2608 Sweetgum Drive
Apex NC 27502
Toll-free: 800-549-9377
FAX: 919-387-1302
XStend Board V1.3.2 Manual
How to install and use

your new XStend Board


Table of Contents
Getting Help!........................................................................................................3
Packing List .........................................................................................................3
XStend Board Features ......................................................................................4
XS40/XS95 Board Mounting Area ..............................................................5
LEDs .............................................................................................................6
Switches........................................................................................................8
VGA Interface ...............................................................................................9
PS/2 Keyboard Interface............................................................................10
RAMs ..........................................................................................................11
Stereo Codec..............................................................................................12
XILINX Xchecker Interface ........................................................................13
Prototyping Area.........................................................................................14
Daughterboard Connector .........................................................................15
Introduction ........................................................................................................21
Displaying Switch Settings on the XStend Board LEDs.................................21
Displaying Graphics from RAM Through the VGA Interface .........................26
VGA Color Signals .....................................................................................26
VGA Signal Timing.....................................................................................27
VGA Signal Generator Algorithm ..............................................................28
VGA Signal Generator in VHDL ................................................................30
Reading Keyboard Scan Codes Through the PS/2 Interface........................38
Inputting and Outputting Stereo Signals Through the Codec ........................43

Chapter
1
Preliminaries
Getting Help!
If you can't get the XStend Board hardware to work, send an e-mail message
describing your problem to help@xess.com or submit a problem report at
http://www.xess.com/reqhelp.html. Our web site also has
answers to frequently-asked-questions,
example designs for the XS Boards,
application notes,
a place to sign-up for our email forum where you can post questions to other XS
Board users.
If you can't get your XILINX Foundation software tools installed properly, send an e-
at http://support.xilinx.com.
Packing List
an XStend Board;
an XSTOOLs CDROM with software utilities and documentation for using the XStend
Board.
Chapter
2
XStend Overview
The XS40 and XS95 Boards offer a flexible, low-cost method of prototyping FPGA and
CPLD designs. However, their small physical size limits the amount of support circuitry
they can hold. The XStend Board removes this limitation by providing additional support
circuitry that the XS40 and XS95 Boards can access through their breadboard interfaces.
The XStend Board contains resources that extend the range of applications of the XS
Boards into three areas:
The pushbuttons, DIP switches, LEDs, and prototyping area are useful for basic lab
experiments. These features in combination with the XS Boards replicate the
functionality of the older HW/UW FPGABOARD.
The VGA monitor interface, PS/2 keyboard/mouse interface, and static RAM let the
XS Boards be used in video and computing experiments.
The stereo codec and dual-channel analog input/output circuitry are useful for
processing of audio signals in combination with DSP circuits synthesized with
XILINX's CORE generation software.
XStend Board Features
mounting sockets for both an XS40 and an XS95 Board;
additional bargraph LED and LED digits;
pushbutton and DIP switches;
an interface to VGA monitors;
an interface to a PS/2-style keyboard or mouse;
an additional 64 Kbytes of static RAM (optional);
a stereo codec with left/right input and output channels.
an interface to the XILINX Xchecker cable;
a 2.75"×3.5" prototyping area with selectable 3.3V or 5V supply;
4
a 42×2 header connector for add-on daughterboards.
These resources are shown in the simplified view of the XStend Board (Figure 1). Each of
these resources will be described below.
• Figure 1: XStend Board layout.
XS40/XS95 Board Mounting Area
sockets. These sockets mate with the breadboard interface pins of the XS Boards to give
5
them access to all the resources of the XStend Board. To use an XS40 Board with the
XStend Board, insert it into the right-most columns of the socket strips. When using an
XS95 Board, you should insert it into the left-most columns of the sockets. There are
markings on the XStend Board to indicate the appropriate column for each type of XS
Board.
circuitry will supply VCC and GND to the XStend Board through the mounting sockets.
XS40 Boards with 3.3V FPGAs will supply both 3.3V and 5V to the XStend Board, while
XS40 Boards with 5V FPGAs and XS95 Boards will supply only 5V.
External voltage supplies can also be used with the XStend Board. A 5V power supply
can be connected to header J12 and a 3.3V supply can be attached to header J14 as
shown in Figure 2. These supplies will power the attached XS Board as well as the
XStend electronics.
• Figure 2: Connection of external power supplies to the XStend Board.
Warning: Do not attach external voltage supplies while also supplying power to the
XStend Board with an XS Board. !!!
Warning: Never place shunts on either J12 or J14 or you will short the power
supplies to ground and damage the XStend Board and the attached XS Board.. !!!
LEDs
The XStend Board provides a bargraph LED with eight LEDs (D1—D8) and two more
LED displays (U1 and U2) for use by an XS Board. All of these LEDs are active-low
meaning that an LED segment will glow when a logic-low is applied to it.
The LEDs are enabled and disabled by setting the shunts on the 2-pin jumpers as
described in Table 1.
6
• Table 1: Jumper settings for XStend LEDs.
Jumper Setting
J8 Removing the shunt on this jumper disconnects the power from bargraph LEDs D1—D8. Placing the shunt on the
jumper enables the bargraph LEDs.
J4 Removing the shunt on this jumper disconnects the power from left LED digit U1. Placing the shunt on the jumper
enables the LED digit.
J7 Removing the shunt on this jumper disconnects the power from right LED digit U2. Placing the shunt on the jumper
enables the LED digit.
J13 A shunt placed on this jumper will enable the LEDs when you are using the XStend Board with an XS95 Board. This
shunt must be removed if you are using an XS40 Board with the XStend Board!!
Listing 1 and Listing 2 show the connections from the XS40 and XS95 Boards to the
LEDs on the XStend Board expressed as UCF constraints (for the UCF syntax and usage
tips, check out http://www.xilinx.com/techdocs/2449.htm).
• Listing 1: Connections between the XStend LEDs and the XS40.

NET LSB<0> LOC=P3;
NET LSB<1> LOC=P4;
NET LSB<2> LOC=P5;
NET LSB<3> LOC=P78;
NET LSB<4> LOC=P79;
NET LSB<5> LOC=P82;
NET LSB<6> LOC=P83;
NET LDPB LOC=P84;
#
NET RSB<0> LOC=P59;
NET RSB<1> LOC=P57;
NET RSB<2> LOC=P51;
NET RSB<3> LOC=P56;
NET RSB<4> LOC=P50;
NET RSB<5> LOC=P58;
NET RSB<6> LOC=P60;
NET RDPB LOC=P28;
#
NET DB<1> LOC=P41;
NET DB<2> LOC=P40;
NET DB<3> LOC=P39;
NET DB<4> LOC=P38;
NET DB<5> LOC=P35;
NET DB<6> LOC=P81;
NET DB<7> LOC=P80;
NET DB<8> LOC=P10;
7
• Listing 2: Connections between the XStend LEDs and the XS95.

NET LSB<0> LOC=P1;
NET LSB<1> LOC=P2;
NET LSB<2> LOC=P3;
NET LSB<3> LOC=P75;
NET LSB<4> LOC=P79;
NET LSB<5> LOC=P82;
NET LSB<6> LOC=P83;
NET LDPB LOC=P84;
#
NET RSB<0> LOC=P58;
NET RSB<1> LOC=P56;
NET RSB<2> LOC=P54;
NET RSB<3> LOC=P55;
NET RSB<4> LOC=P53;
NET RSB<5> LOC=P57;
NET RSB<6> LOC=P61;
NET RDPB LOC=P34;
#
NET DB<1> LOC=P44;
NET DB<2> LOC=P43;
NET DB<3> LOC=P41;
NET DB<4> LOC=P40;
NET DB<5> LOC=P39;
NET DB<6> LOC=P37;
NET DB<7> LOC=P36;
NET DB<8> LOC=P35;
Switches
The XStend has a bank of eight DIP switches and two pushbuttons (labeled SPARE and
RESET) that are accessible from an XS Board. (There is a third pushbutton labeled
PROGRAM, which is used to initiate the programming of the XS40 Board. It is not
intended to be a general-purpose input.)
When closed or ON, each DIP switch pulls the connected pin of the XS Board to ground.
When the DIP switch is open or OFF, the pin is pulled high through a 10KΩ resistor.
When not being used, the DIP switches should be left in the open or OFF
configuration so the pins of the XS Board are not tied to ground and can freely !!!
move between logic low and high levels.
When pressed, each pushbutton pulls the connected pin of the XS Board to ground.
Otherwise, the pin is pulled high through a 10 KΩ resistor.
switches on the XStend Board expressed as UCF constraints.
8
• Listing 3: Connections between the XStend DIP and pushbutton switches and the XS40.

#
NET SPAREB LOC=P67;
NET RESETB LOC=P37;
• Listing 4: Connections between the XStend DIP and pushbutton switches and the XS95.

#
NET SPAREB LOC=P67;
NET RESETB LOC=P10;
VGA Interface
The XStend Board provides an XS Board with an interface to a VGA monitor through
connector J5. (Version 1.2 and higher of the XS Boards already have their own VGA
interfaces, so the XStend circuitry is redundant for them.) The XS Board can drive the
active-low horizontal and vertical sync signals that control the width and height of the video
frame. The XS Board also has access to two bits each of red, green, and blue color
2 2 2
signals so it can generate pixels in any of 2 ×2 ×2 =64 different colors.
VGA interface of the XStend Board. (These pin assignments are identical to the pin
assignments for the XS Boards, which have their own VGA interfaces.)
9
• Listing 5: Connections between the XStend VGA interface and the XS40.
# VGA CONNECTIONS
NET VSYNCB LOC=P67;
NET HSYNCB LOC=P19;
NET RED<1> LOC=P18;
NET RED<0> LOC=P23;
• Listing 6: Connections between the XStend VGA interface and the XS95.
# VGA CONNECTIONS
NET VSYNCB LOC=P24;
NET HSYNCB LOC=P15;
NET RED<1> LOC=P14;
NET RED<0> LOC=P18;
PS/2 Keyboard Interface
The XStend Board provides an XS Board with a PS/2-style interface (mini-DIN connector
J6) to either a keyboard or a mouse. The XS Board receives two signals from the PS/2
interface: a clock signal and a serial data stream that is synchronized with the falling edges
on the clock signal.
PS/2 interface of the XStend Board (expressed as UCF constraints):
• Listing 7: Connections between the XStend PS/2 interface and the XS40.

NET KB_CLK LOC=P68;
• Listing 8: Connections between the XStend PS/2 interface and the XS95.

NET KB_CLK LOC=P26;
10
RAMs
The XStend Board adds an additional 64 KBytes of RAM to the 32 KBytes already on the
XS Board. The XStend RAM connects to the same pins as the XS Board RAM for the
address bus, data bus, write-enable, and output-enable. The chip-selects of the XStend
Board RAMs are connected to different pins so all the RAMs can be individually selected.
Listing 9 and Listing 10 show the connections from the XS40 and XS95 Boards to their
own RAMs and the RAMs of the XStend Board (expressed as UCF constraints):
• Listing 9: Connections between the XStend RAMs and the XS40.

NET D<1> LOC=P40;
NET D<2> LOC=P39;
NET D<3> LOC=P38;
NET D<4> LOC=P35;
NET D<5> LOC=P81;
NET D<6> LOC=P80;
NET D<7> LOC=P10;
NET A<1> LOC=P4;
NET A<2> LOC=P5;
NET A<3> LOC=P78;
NET A<4> LOC=P79;
NET A<5> LOC=P82;
NET A<6> LOC=P83;
NET A<7> LOC=P84;
NET A<9> LOC=P57;
NET A<10> LOC=P51;
NET A<11> LOC=P56;
NET A<12> LOC=P50;
NET A<13> LOC=P58;
NET A<14> LOC=P60;
11
• Listing 10: Connections between the XStend RAMs and the XS95.

NET D<1> LOC=P43;
NET D<2> LOC=P41;
NET D<3> LOC=P40;
NET D<4> LOC=P39;
NET D<5> LOC=P37;
NET D<6> LOC=P36;
NET D<7> LOC=P35;
NET A<1> LOC=P79;
NET A<2> LOC=P82;
NET A<3> LOC=P84;
NET A<4> LOC=P1;
NET A<5> LOC=P3;
NET A<6> LOC=P83;
NET A<7> LOC=P2;
NET A<9> LOC=P56;
NET A<10> LOC=P54;
NET A<11> LOC=P55;
NET A<12> LOC=P53;
NET A<13> LOC=P57;
NET A<14> LOC=P61;
Stereo Codec
The XStend Board has a stereo codec that accepts two analog input channels from jack
J9, digitizes the analog values, and sends the digital values to the XS Board as a serial bit
stream. The codec also accepts a serial bit stream from the XS Board and converts it into
two analog output signals, which exit the XStend Board through jack J10.
The codec is configured by placing shunts on the jumpers as indicated in Table 2.
• Table 2: Jumper settings for XStend codec.
Jumper Setting
J11 Placing a shunt on this jumper disables the codec by holding it in the reset state. No shunt should be placed
on this jumper when the codec is being used.
J17 Removing this shunt prevents the codec’s serial data output from reaching the XS Board. A shunt should be
placed on this jumper when the codec is being used.
Listing 11 and Listing 12 show the connections from the XS40 Board to the codec
interface on the XStend Board (expressed as UCF constraints):
12
• Listing 11: Connections between the XStend stereo codec and the XS40 Board.

• Listing 12: Connections between the XStend stereo codec and the XS95 Board.

The analog stereo input and output signals enter and exit the XStend Board through the
1/8” jacks J9 and J10, respectively. The output of an audio CD player can be input
through J9 and a set of small stereo headphones can be connected to J10 for listening to
the processed output.
The digitized data output from the codec passes through jumper J17 on its way to the XS
Board inserted in the XStend Board. A shunt should be placed on J17 when the codec is
being used. Because the serial data output of the codec is not tristatable and because it
shares the input to the XS Board with other resources on the XStend Board, the shunt on
J17 should be removed when the codec is not being used.
XILINX Xchecker Interface
An XS40 Board inserted in the XStend Board can be configured and tested using a
XILINX Xchecker cable attached to header J19. When using the Xchecker cable, you
must not connect the cable between the XS Board and the parallel port of the PC. In
addition, when using the Xchecker cable with an XStend/XS40 combination, you must
make the following adjustments to the XS40 Board:
Remove the shunts from jumpers J4, J6, J10 and J11 of the XS40 Board;
Remove the serial EPROM from socket U7.
The connections between the Xchecker cable and the XS40 Board is listed in Table 3.
13
• Table 3: Connections between the XStend Board Xchecker interface and the XS40 Board.
Xchecker Pin XS40 Pin

1 – VCC (+5V) 2
2 – RT 32
3 – GND 52
4 – RD 30
6 – TRIG 7
7 – CCLK 73
9 – DONE 53
10 – TDI 15
11 – DIN 71
12 – TCK 16
13 – PROGRAM 55
14 – TMS 17
15 – INIT 41
16 – CLKI 13
17 – RST 8
18 – CLKO 9
Prototyping Area

buses run on the bottom side. The VCC and GND buses have connection holes in which
a small wire can be soldered to make a connection to a nearby component through-hole.
• Figure 3: Top-side view of the network of VCC and GND buses around the component through-holes
in the XStend Board prototyping area.
prototyping area carry either 5V or 3.3V (see Figure 6). Of course, the jumper selection
will have no effect unless you have both these voltages supplied to the XStend Board
either by the XS Board or by connecting external power supplies.
14
• Figure 4: Shunt placement for setting the VCC bus voltage..
Connections from the XS Board to the prototyping area are made through connector J3.
The arrangement of pins on this connector exactly matches the arrangement of pins on
the XS40 Board. For example, the pin at the bottom-left of J3 on the XStend Board
corresponds to pin 21 at the bottom-left of the XS40 Board.
The XS95 Board has a completely different pin arrangement than the XS40. Therefore,
each pin on J3 is explicitly labeled with the corresponding pin number on the XS95 Board.
For example, the pin at the bottom-left of J3 on the XStend Board is connected to pin 68
near the top-left of the XS95 Board.
Daughterboard Connector
connector J18. This 42×2 connector brings all the I/O and VCC/GND from the XS40 or
XS95 Board to the daughterboard.
15
Chapter
3
Programmer's
Models
The interconnections of the XStend Board resources and an XS40 or XS95 Board are
shown in Figure 5 and Figure 6, respectively. These figures remove much of the
extraneous detail of the actual schematics, so we refer to them as programmer’s models.
Items within the shaded area in each figure correspond to circuitry housed on the XS
Board. The remaining items are XStend Board resources.
example, the codec, DIP switch, and microcontroller port P1 are all connected to the same
set of pins on the FPGA or CPLD. So any design has to ensure that only one of these
resources is outputting data at any particular time. (Hence the need in some designs to
place the DIP switches in the OPEN position, or remove the shunt through which the
codec SDOUT drives serial data, or keep the microcontroller in the reset state.)
respectively, in a tabular format, which makes it easier to see which resources share
common connections.
• Figure 5: Programmer's model of the XS40/XStend Board combination.
17
• Figure 6: Programmer's model of the XS95/XStend Board combination.
18
• Table 4: Connections between the XS40 Board and the XStend Board resources.
Stereo Codec
Push-buttons
Power/ GND
BOARD Pin
PC Parallel
(J1,J3,J18)
DIP Switch
UW-FPGA
Oscillator
XS40 Pin
Interface
Interface
8051 uC
RAMs
LEDs
PS/2
VGA
Port
Function
15 JTAG TDI; DIN
16 JTAG TCK; CCLK
17 JTAG TMS
36 RST uC reset
66 DIPSW7 LRCK P1.6 PC_S5 DIP switch; codec left-right channel switch; uC I/O port; PC P27
69 DIPSW8 KB_DATA P3.1 (TX PC_S6 DIP switch; PS/2 keyboard serial data; uC I/O port; PC par P28
70 DIPSW6 SDIN P1.5 PC_S3 DIP switch; codec serial input data; uC I/O port; PC paralle P26
71 JTAG TDI; DIN
72 JTAG TDO; DOUT
73 JTAG TCK; CCLK
77 DIPSW5 SCLK P1.4 PC_S4 DIP switch; codec serial I/O clock; uC I/O port; PC parallel P25
• 84 LDPB A7 Left LED decimal-point; RAM address line P37
19
• Table 5: Connections between the XS95 Board and the XStend Board resources.
Stereo Codec
Push-buttons
Power/ GND
BOARD Pin
PC Parallel
DIP Switch
XS95 Pins
UW-FPGA
Oscillator
Interface
Interface
8051 Uc
RAMs
LEDs
PS/2
VGA
Port
(J2)
Function
28 JTAG TDI; DIN
29 JTAG TMS
30 JTAG TCK; CCLK
45 RST uC reset
59 JTAG TDO; DOUT
66 DIPSW7 LRCK P1.6 PC_S5 DIP switch; codec left-right channel select; uC I/O port; PC P27
70 DIPSW8 KB_DATA P3.1 (TX PC_S6 DIP switch; PS/2 keyboard serial data; uC I/O port; PC par P28
71 DIPSW6 SDIN P1.5 PC_S3 DIP switch; codec serial input data; uC I/O port; PC paralle P26
72 DIPSW5 SCLK P1.4 PC_S4 DIP switch; codec serial clock; uC I/O port; PC parallel por P25
24,67 SPAREBDP VSYNCB P1.7 Pushbutton; XS Board LED decimal-point; VGA horiz. sync P18
20
Chapter
4
Example Designs
Introduction
This chapter discusses some design examples that you can build using the Xstend Board
coupled with an XS40 or XS95 Board. You can find links to the source code for these
designs at http://www.xess.com/ho03000.html.
Displaying Switch Settings on the XStend Board LEDs
This example creates a circuit that displays the settings of the DIP switches on the LEDs
and LED digits of the XStend and XS Boards. The particular set of LEDs, which is
activated, is selected by the SPARE and RESET pushbuttons. The VHDL code for this
example is shown in Listing 13.
The steps for compiling and testing the design using an XS40 combined with an XStend
Synthesize the VHDL code in the SWTCH40\SWITCHES.VHD file for an XC4005XL

FPGA.
Compile the synthesized netlist using the SWTCH40.UCF constraint file (Listing 14).
Mount an XS40 Board in the XStend Board and attach the downloading cable from
the XS40 to the PC parallel port. Apply 9VDC though jack J9 of the XS40. Place
shunts on jumpers J4, J7, and J8 of the XStend Board to enable the LED displays.
Remove the shunt on jumper J17 to keep the XStend codec serial output from
interfering with the DIP switch logic levels.
Download the SWTCH40.BIT file into the XS40/XStend combination with the
command: XSLOAD SWTCH40.BIT.
Set the DIP switches and press the SPARE and RESET pushbuttons. Observe the
results on the LEDs.
The steps for compiling and testing the design using an XS95 combined with an
XStend Board are as follows:
Synthesize the VHDL code in the SWTCH95\SWITCHES.VHD file for an XC95108

CPLD.
Compile the synthesized netlist using the SWTCH95.UCF constraint file (Listing 15).
Generate an SVF file for the design.
Mount an XS95 Board in the XStend Board and attach the downloading cable from
the XS95 to the PC parallel port. Apply 9VDC though jack J9 of the XS95. Place
shunts on jumpers J4, J7, and J8 of the XStend Board to enable the LED displays.
Remove the shunt on jumper J17 to keep the XStend codec serial output from
interfering with the DIP switch logic levels.
Download the SWTCH95.SVF file into the XS95/XStend combination with the
command: XSLOAD SWTCH95.SVF.
Set the DIP switches and press the SPARE and RESET pushbuttons. Observe the
results on the LEDs.
• Listing 13: VHDL code for using the XStend LEDs and switches.
001- LIBRARY IEEE;

003-
005- PORT
006- (
010-
015-
018- );
019- END switches;
020-
022- BEGIN
023- -- this prevents accidental activation of the RAMs or uC
026-
032-
038-
22
044-
• Listing 14: XS40 UCF file for the LED/switch example.

002- net s<1> loc=p26;
003- net s<2> loc=p24;
004- net s<3> loc=p20;
005- net s<4> loc=p23;
006- net s<5> loc=p18;
007- net s<6> loc=p19;
037- net db<2> loc=p40;
038- net db<3> loc=p39;
039- net db<4> loc=p38;
040- net db<5> loc=p35;
041- net db<6> loc=p81;
042- net db<7> loc=p80;
043- net db<8> loc=p10;
23
24
• Listing 15: XS95 UCF file for the LED/switch example.

002- net s<1> loc=p23;
003- net s<2> loc=p19;
004- net s<3> loc=p17;
005- net s<4> loc=p18;
006- net s<5> loc=p14;
007- net s<6> loc=p15;
037- net db<2> loc=p43;
038- net db<3> loc=p41;
039- net db<4> loc=p40;
040- net db<5> loc=p39;
041- net db<6> loc=p37;
042- net db<7> loc=p36;
043- net db<8> loc=p35;
25
Displaying Graphics from RAM Through the VGA Interface
This section discusses the timing for the signals that drive a VGA monitor and describes a
VHDL module that will let you drive a monitor with a picture stored in RAM.
VGA Color Signals
There are three signals -- red, green, and blue -- that send color information to a VGA
monitor. These three signals each drive an electron gun that emits electrons which paint
one primary color at a point on the monitor screen. Analog levels between 0 (completely
dark) and 0.7 V (maximum brightness) on these control lines tell the monitor what
intensities of these three primary colors to combine to make the color of a dot (or pixel) on
the monitor’s screen.
Each analog color input can be set to one of four levels by two digital outputs using a
simple two-bit digital-to-analog converter (see Figure 7). The four possible levels on each
analog input are combined by the monitor to create a pixel with one of 4 × 4 × 4 = 64
different colors. So the six digital control lines let us select from a palette of 64 colors.
26
• Figure 7: Digital-to-analog interface to a VGA monitor.
VGA Signal Timing
A single dot of color on a video monitor doesn’t impart much information. A horizontal line
of pixels carries a bit more information. But a frame composed of multiple lines can
present an image on the monitor screen. A frame of VGA video typically has 480 lines and
each line usually contains 640 pixels. In order to paint a frame, there are deflection circuits
in the monitor that move the electrons emitted from the guns both left-to-right and top-to-
bottom across the screen. These deflection circuits require two synchronization signals in
order to start and stop the deflection circuits at the right times so that a line of pixels is
painted across the monitor and the lines stack up from the top to the bottom to form an
image. The timing for the VGA synchronization signals is shown in Figure 8.
Negative pulses on the horizontal sync signal mark the start and end of a line and ensure
that the monitor displays the pixels between the left and right edges of the visible screen
area. The actual pixels are sent to the monitor within a 25.17 µs window. The horizontal
sync signal drops low a minimum of 0.94 µs after the last pixel and stays low for 3.77 µs.
A new line of pixels can begin a minimum of 1.89 µs after the horizontal sync pulse ends.
So a single line occupies 25.17 µs of a 31.77 µs interval. The other 6.6 µs of each line is
the horizontal blanking interval during which the screen is dark.
In an analogous fashion, negative pulses on a vertical sync signal mark the start and end
of a frame made up of video lines and ensure that the monitor displays the lines between
the top and bottom edges of the visible monitor screen. The lines are sent to the monitor
27
within a 15.25 ms window. The vertical sync signal drops low a minimum of 0.45 ms after
the last line and stays low for 64 µs. The first line of the next frame can begin a minimum
of 1.02 ms after the vertical sync pulse ends. So a single frame occupies 15.25 ms of a
16.784 ms interval. The other 1.534 ms of the frame interval is the vertical blanking
interval during which the screen is dark.
• Figure 8: VGA signal timing.
VGA Signal Generator Algorithm
Now we have to figure out a process that will send pixels to the monitor with the correct
timing and framing. We can store a picture in the RAM of the XS Board. Then we can
retrieve the data from the RAM, format it into lines of pixels, and send the lines to the
monitor with the appropriate pulses on the horizontal and vertical sync pulses.
The pseudocode for a single frame of this process is shown in Listing 16. The
pseudocode has two outer loops: one, which displays the L lines of visible pixels, and
another, which inserts the V, blank lines and the vertical sync pulse. Within the first loop,
there are two more loops: one, which sends the P pixels of each video line to the monitor,
and another, which inserts the H, blank pixels and the horizontal sync pulse.
28
Within the pixel display loop, there are statements to get the next byte from the RAM.
Each byte contains four two-bit pixels. A small loop iteratively extracts each pixel to be
displayed from the lower two bits of the byte. Then the byte is shifted by two bits so the
next pixel will be in the right position during the next iteration of the loop. Since it has only
two bits, each pixel can store one of four colors. The mapping from the two-bit pixel value
to the actual values required by the monitor electronics is done by the COLOR_MAP()
routine.
• Listing 16: VGA signal generation pseudocode.

for line_cnt=1 to L
data = RAM(address)
for d=1 to 4
pixel = data & 00000011
data = data>>2
d = d + 1
color = BLANK
hsync = 0
else
hsync = 1
color = BLANK
vsync = 0
else
vsync = 1
address = 0
29
Figure 9 shows how to pipeline certain operations to account for delays in accessing data
from the RAM. The pipeline has three stages:
Stage 1: The circuit uses the horizontal and vertical counters to compute the address
where the next pixel is found in RAM. The counters are also used to determine the
firing of the sync pulses and whether the video should be blanked. The pixel data
from the RAM, blanking signal, and sync pulses are latched at the end of this stage so
they can be used in the next stage.
Stage 2: The circuit uses the pixel data and the blanking signal to determine the binary
color outputs. These outputs are latched at the end of this stage.
Stage 3: The binary color outputs are applied to the DAC, which sets the intensity levels
for the monitor’s color guns. The actual pixel is painted on the screen during this
stage.
• Figure 9: Pipelining of VGA signal generation tasks.
VGA Signal Generator in VHDL
The pseudocode and pipeline timing in the last section will help us to understand the
VHDL code for a VGA signal generator shown in Listing 17. The inputs and outputs of
the circuit as defined in the entity declaration are as follows:
maximum rate at which pixels can be sent to the monitor. The time interval within
each line for transmitting viewable pixels is 25.17 µs, so this VGA generator circuit can
only put a maximum of 25.17 ms × 12 MHz = 302 pixels on each line. For purposes
of storing images in the RAM, it is convenient to reduce this to 256 pixels per line and
blank the remaining 46 pixels. Half of these blank pixels are placed before the 256
viewable pixels and half are placed after them on a line. This centers the viewable
pixels between the left and right edges of the monitor screen.
30
hsyncb, vsyncb: The outputs for the horizontal and vertical sync pulses are declared.
The hsyncb output is declared as a buffer because it will also be referenced within the
architecture section as a clock for the vertical line counter.
rgb: The outputs that control the red, green, and blue color guns of the monitor are
declared here. Each gun is controlled by two bits, so there are four possible
intensities for each color. Thus, this circuit can produce 4 × 4 × 4 = 64 different colors.
address, data: These lines declare the outputs for driving the address lines of the RAM
and the inputs for receiving the data from the RAM.
ceb, oeb, web: These are the declarations for the outputs which drive the chip-select,
output-enable, and write-enable control lines of the RAM.
hcnt, vcnt: The counters that store the current horizontal position within a line of pixels
and the vertical position of the line on the screen are declared on these lines. We will
call these the horizontal or pixel counter, and the vertical or line counter, respectively.
The line period is 31.77 µs that is 381 clock cycles, so the pixel counter needs at least
nine bits of resolution. Each frame is composed of 528 video lines (only 480 are
visible, the other 48 are blanked), so a ten bit counter is needed for the line counter.
pixrg: This is the declaration for the eight-bit register that stores the four pixels received
from the RAM.
blank, pblank: This line declares the video blanking signal and its registered counterpart
that is used in the next pipeline stage.
inc_horiz_pixel_counter: This process describes the operation of the horizontal pixel

counter. The counter is asynchronously set to zero when the reset input is high. The
counter increments on the rising edge of each pixel clock. The range for the horizontal
pixel counter is [0,380]. When the counter reaches 380, it rolls over to zero on the
next cycle. Thus, the counter has a period of 381 pixel clocks. With a pixel clock of
12 MHz, this translates to a period of 31.75 µs.
inc_vert_line_counter: This process describes the operation of the vertical line counter.
increments on the rising edge of the horizontal sync pulse after a line of pixels is
completed. The range for the horizontal pixel counter is [0,527]. When the counter
reaches 527, it rolls over to zero on the next cycle. Thus, the counter has a period of
528 lines. Since the duration of a line of pixels is 31.75 µs, this makes the frame
interval equal to 16.76 ms.
generator. The horizontal sync is set to its inactive high level when the reset is
activated. During normal operations, the horizontal sync output is updated on every
pixel clock. The sync signal goes low on the cycle after the pixel counter reaches 291
and continues until the cycle after the counter reaches 337. This gives a low
31
horizontal sync pulse of (337-291)=46 pixel clocks. With a pixel clock of 12 MHz, this
translates to a low-going horizontal sync pulse of 3.83 µs. The sync pulse starts 292
clocks after the line of pixels begin, which translates to 24.33 µs. This is less than the
26.11 µs we stated before. The difference of 1.78 ms translates to 21 pixel clocks.
This time interval corresponds to the 23 blank pixels that are placed before the 256
viewable pixels (minus two clock cycles for pipelining delays).
generate_vert_sync: This process describes the operation of the vertical sync pulse
generator. The vertical sync is set to its inactive high level when the reset is activated.
During normal operations, the vertical sync output is updated after every line of pixels
is completed. The sync signal goes low on the cycle after the line counter reaches
493 and continues until the cycle after the counter reaches 495. This gives a low
vertical sync pulse of (495-493)= 2 lines. With a line interval of 31.75 µs, this
translates to a low-going vertical sync pulse of 63.5 µs. The vertical sync pulse starts
494 × 31.75 µs = 15.68 ms after the beginning of the first video line.
Line 91: This line describes the computation of the combinatorial blanking signal. The
video is blanked after 256 pixels on a line are displayed, or after 480 lines are
displayed.
pipeline_blank: This process describes the operation of the pipelined video blanking
signal. Within the process, the blanking signal is stored in a register so it can be used
during the next stage of the pipeline when the color is computed.
Lines 104 -- 106: On these lines, the RAM is permanently selected and writing to the
RAM is disabled. This makes the RAM look like a ROM, which stores video data. In
addition, the outputs from the RAM are disabled when the video is blanked since
there is no need for pixels during the blanking intervals. This isn’t really necessary
since no other circuit is trying to access the RAM.
concatenating the lower nine bits of the line counter with bits 7,6,5,4,3 and 2 of the
9
pixel counter. With this arrangement, the line counter stores the address of one of 2
6
= 512 pages. Each page contains 2 = 64 bytes. Each byte contains four pixels, so
each page stores one line of 256 pixels. The pixel counter increments through the
bytes of a page to get the pixels for the current line. (Note that we don’t need to use
bits 1 and 0 of the pixel counter when computing the RAM address since each byte
contains four pixels.) After the line is displayed, the line counter is incremented to
point to the next page.
update_pixel_register: This process describes the operation of the register that holds the
byte of pixel data read from RAM. The register is asynchronously cleared when the
VGA circuit is reset. The register is updated on the rising edge of each pixel clock.
The pixel register is loaded with data from the RAM whenever the lowest two bits of
the pixel counter are both zero. The active pixel is always in the lower two bits of the
register. Each pixel in the RAM data byte is shifted into the active position by right
shifting the register two bits on each rising clock edge.
mapped into the six bits that drive the red, green and blue color guns. The register is
set to zero (which displays as the color black) when the reset input is high. The color
register is clocked on the rising edge of the pixel clock since this is the rate at which
new pixel values arrive. The value clocked into the register is a function of the pixel
32
value and the blanking input. When the pipelined blanking input is low (inactive), the
color displayed on the monitor is red, green, blue, or white depending upon whether
the pixel value is 00, 01, 10, or 11, respectively. When the pipelined blanking input is
high, the color register is loaded with zero (black).
• Listing 17: VHDL code for a VGA generator.
001- LIBRARY IEEE;

004-
006- PORT
007- (
018- );
020-
022- SIGNAL hcnt: STD_LOGIC_VECTOR(8 DOWNTO 0); -- horiz. pixel counter
024- SIGNAL pixrg: STD_LOGIC_VECTOR(7 DOWNTO 0); -- byte register for 4
pix
025- SIGNAL blank: STD_LOGIC;-- video blanking signal
028- BEGIN
029-
032- BEGIN
034- hcnt <= "000000000";
037- hcnt <= hcnt + 1;
038- ELSE
039- hcnt <= "000000000";
040- END IF;
041- END IF;
042- END PROCESS;
043-
33
046- BEGIN
048- vcnt <= "0000000000";
051- vcnt <= vcnt + 1;
052- ELSE
053- vcnt <= "0000000000";
054- END IF;
055- END IF;
056- END PROCESS;
057-
060- BEGIN
062- int_hsyncb <= '1';
066- int_hsyncb <= '0';
067- ELSE
068- int_hsyncb <= '1';
069- END IF;
070- END IF;
072- END PROCESS;
073-
076- BEGIN
077- IF reset='1' THEN -- reset inactivates vertical sync
078- vsyncb <= '1';
083- vsyncb <= '0';
084- ELSE
085- vsyncb <= '1';
086- END IF;
087- END IF;
088- END PROCESS;
089-
095- BEGIN
097- pblank <= '0';
34
100- END IF;
101- END PROCESS;
102-
107-
111- -- the byte at address ^h1234=^b0001,0010,0011,0100 contains the pixels
114-
117- BEGIN
119- pixrg <= "00000000";
130- ELSE
131- pixrg <= "00" & pixrg(7 DOWNTO 2); -- R-shift pixel register
132- END IF;
133- END IF;
134- END PROCESS;
135-
141- BEGIN
143- rgb <= "000000";
144- ELSIF (clk'EVENT AND clk='1') THEN -- update color every clock
148- WHEN "00" => rgb <= "110000"; -- red
149- WHEN "01" => rgb <= "001100"; -- green
150- WHEN "10" => rgb <= "000011"; -- blue
152- END CASE;
35
154- rgb <= "000000"; -- black
155- END IF;
156- END IF;
157- END PROCESS;
158-
• Listing 18: XS40 UCF file for the VGA signal generator.

36
• Listing 19: XS95 UCF file for the VGA signal generator.

The steps for compiling and testing the VGA design using an XS40 combined with an
XStend Board are as follows:
1. Synthesize the VHDL code in the VGA40\VGA.VHD file for an XC4005XL FPGA.
2. Compile the synthesized netlist using the VGA40.UCF constraint file (Listing 18).
3. Mount an XS40 Board in the XStend Board and attach the downloading cable
from the XS40 to the PC parallel port. Apply 9VDC though jack J9 of the XS40.
Place shunts on jumpers J4, J7, and J8 of the XStend Board to enable the LED
displays. Remove the shunt on jumper J17 to keep the XStend codec serial
37
output from interfering with the DIP switch logic levels. Set all the DIP switches to
the OPEN position.
4. Attach a VGA monitor to the DB-HD15 connector (J5).
5. Download the VGA40.BIT file and a video test pattern into the XS40/XStend
combination with the command: XSLOAD TESTPATT.HEX VGA40.BIT.
6. Release the reset to the VGA circuitry with the command: XSPORT 0.
7. Observe the color bars on the monitor screen.
1. Synthesize the VHDL code in the VGA95\VGA.VHD file for an XC95108 CPLD.
2. Compile the synthesized netlist using the VGA95.UCF constraint file (Listing 19).
3. Generate an SVF file for the design.
Place shunts on jumpers J4, J7, and J8 of the XStend Board to enable the LED
displays. Remove the shunt on jumper J17 to keep the XStend codec serial
output from interfering. Set all the DIP switches to the OPEN position.
5. Attach a VGA monitor to the DB-HD15 connector (J5).
6. Download the VGA95.SVF file and a video test pattern into the XS95/XStend
combination with the command: XSLOAD TESTPATT.HEX VGA95.SVF.
7. Release the reset to the VGA circuitry with the command: XSPORT 0.
8. Observe the color bars on the monitor screen.
Reading Keyboard Scan Codes Through the PS/2 Interface
This example creates a circuit that accepts scan codes from a keyboard attached to the
PS/2 interface of the XStend Board. The binary pattern of the scan code is displayed on
the bargraph LEDs. In addition, if a scan code for one of the keys '0'—'9' arrives, then the
numeral will be displayed on the right LED display of the XStend Board.
The format of the scan code transmissions from the keyboard are shown in Figure 10.
The keyboard electronics drive the clock and data lines. The start of a scan code
transmission is indicated by a low level on the data line on the falling edge of the clock.
The eight bits of the scan code follow (starting with the least-significant bit) on successive
falling clock edges. These are followed by an odd-parity bit and then a high-level stop bit.
When the clock line goes high after the stop bit, the receiver (in this case, the FPGA or
CPLD on the XS Board inserted in the XStend Board) can pull the clock line low to inhibit
any further transmissions. After the clock line is released and it returns to a high level, the
38
keyboard can send another scan code. If the receiver never pulls the clock line low, then
the keyboard will send scan codes whenever a key is pressed.
• Figure 10: Keyboard data transmission waveforms.
The VHDL code for this example is shown in . The inputs and outputs of the circuit as
Lines 22 & 23: The microcontroller reset pin and the RAM output-enable pin are driven
high so these chips cannot interfere while receiving data from the keyboard.
Lines 25 & 26: The keyboard clock passes through an input buffer and then a global clock
buffer before it reaches the rest of the circuitry. (These buffers are declared on lines
18 and 19, respectively.) The global clock buffer distributes the clock signal with
minimal skew in the XS40 Board FPGA. These statements are not used with the
CPLD in the XS95 Board.
gather_scancode: On every falling edge of kb_clk, this process shifts the data bit on the
kb_data input into the most-significant bit of a 10-bit shift register. After 11 clock
cycles, the lower 8 bits of the register will contain the scan code, the upper 2 bits will
store the stop and parity bits, and the start bit will have been shifted through the entire
register and discarded.
bargraph. Since the bargraph segments are active-low, a segment will light for every
‘1’ bit in the shift register. The LED segment drivers are not registered so there will be
some flickering as the shift register contents change.
39
Lines 40-51: If the scan code in the shift register matches the codes for the digits 0-9,
then the right LED digit segments will be activated to display the corresponding digit.
If the scan code does not match one of these codes, the letter ‘E’ is displayed.
1. Synthesize the VHDL code in the KEYBRD40\KEYBRD.VHD for an XC4005XL

FPGA.
2. Compile the synthesized netlist using the KEYBRD40.UCF constraint file (Listing
21).
Place shunts on jumpers J4, J7, and J8 to enable the LEDs. Remove the shunt
on jumper J17 to keep the XStend codec from interfering. Set all the DIP
4. Attach a keyboard to the PS/2 connector of the XStend Board.
5. Download the KEYBRD40.BIT file into the XS40/XStend combination with the
command: XSLOAD KEYBRD40.BIT.
6. Press keys on the keyboard and observe the results on the LED displays.
1. Synthesize the VHDL code in the KEYBRD95\KEYBRD.VHD for an XC95108

CPLD.
2. Compile the synthesized netlist using the KEYBRD95.UCF constraint file (Listing
22).
Place shunts on jumpers J4, J7, and J8 to enable the LEDs. Remove the shunt
on jumper J17 to keep the XStend codec from interfering. Set all the DIP
5. Download the KEYBRD95.SVF file into the XS95/XStend combination with the
command: XSLOAD KEYBRD95.SVF.
6. Press keys on the keyboard and observe the results on the LED displays.
40
• Listing 20: VHDL code for receiving keyboard scan codes from the PS/2 interface.
001- LIBRARY IEEE;

003-
005- PORT
006- (
009- kb_data: IN STD_LOGIC;-- serial data from the keyboard
013- );
014- END kbd_read;
015-
021- BEGIN
024-
027-
032- BEGIN
035- END IF;
036- END PROCESS;
037-
038- db <= NOT(scancode(7 DOWNTO 0)); -- show scancode on the bargraph
039-
41
051- "0010010"; -- E
• Listing 21: XS40 UCF file for the PS/2 keyboard interface.

012- net db<1> loc=p41;
013- net db<2> loc=p40;
014- net db<3> loc=p39;
015- net db<4> loc=p38;
016- net db<5> loc=p35;
017- net db<6> loc=p81;
018- net db<7> loc=p80;
019- net db<8> loc=p10;
• Listing 22: XS95 UCF file for the PS/2 keyboard interface.

012- net db<1> loc=p44;
013- net db<2> loc=p43;
014- net db<3> loc=p41;
015- net db<4> loc=p40;
016- net db<5> loc=p39;
017- net db<6> loc=p37;
018- net db<7> loc=p36;
019- net db<8> loc=p35;
42
Inputting and Outputting Stereo Signals Through the Codec
The stereo codec on the XStend Board is capable of digitizing two analog signals to 20
bits of resolution while simultaneously generating two analog signals from 20-bit values. A
high-level view of the codec chip is shown on the right-half of Figure 11. Two analog
inputs (which are typically the left and right channels of a stereo audio signal) enter the
codec and are digitized into two 20-bit values by analog-to-digital converters (ADCs).
These values are loaded into shift registers, which are shifted out of a single pin of the
codec under control of a shift clock and a left/right channel selector control input. At the
same time, 20-bit values are alternately shifted into two shift registers in the codec, which
feed digital-to-analog converters (DACs) that drive two analog outputs. Signals on these
outputs are typically the left and right channels of a stereo audio signal.
If the FPLD is handling these values in a bit-parallel manner, then the FPLD must contain
a set of shift registers which convert the serial input stream into 20-bit values and another
set which converts 20-bit values into a serial output stream. This is shown in the left-half
of Figure 11. The gating of these shift registers onto the serial input and output pins is
synchronized with the same left/right channel select signal used by the codec chip.
In addition to the shift registers, the FPLD needs circuitry to read and write them and to
indicate when they are full and empty. Since the codec ADCs and DACs generate and
consume data at a set sample rate, it is also necessary to build circuitry which detects
overflow and underflow of the FPLD shift registers if they are not read or written in time.
• Figure 11: Connections between the XStend codec chip and the XS Board FPGA or CPLD.
a clock generator module which outputs the serial data shift clock and the left/right
channel select signals;
43
a channel module which contains the shift registers, buffers, read/write control, and
a top-level module, which combines the clock generator module with two channel
modules to form a complete codec, interface circuit.
The VHDL code for the clock generator module is detailed in Listing 23. The inputs and
outputs of the clock generator as defined in the entity declaration are as follows:
clk: This is the main clock input, which is typically the 12 MHz clock from the XS Board.
sclk: This output is the clock for synchronizing serial data transfers between the FPLD
and the codec.
lrck: This output controls the activation of the left and right channel circuitry in the codec
and the FPLD.
bit_cntr: These outputs indicate the current bit being transmitted and received in the serial
data streams.
subcycle_cntr: The duration of each serial data bit is divided into four phases and these
outputs indicate the current phase.
gen_clock: This process increments the sequencing counter and toggles the left/right
channel selector when the count reaches the duration for which a channel is active.
The codec chip requires that the channel duration be either 128, 192, or 256 master
clock periods in length. Thus, the total time to handle both channels is 256, 384, or
512 clock periods. This sets the sampling rate. So using a channel duration of 128
with a 12 MHz clock gives a sampling rate of 46.875 KHz that is sufficient for audio.
selector have already been discussed. The serial data shift clock is one-quarter of the
master clock. So transmitting or receiving a 20-bit value will require 4 × 20 = 80 clock
periods, and this will fit within the shortest possible channel duration.
Line 48: The position of the current data bit in the serial stream for a channel is output
here. Since each bit has a duration of four clock periods, the position of the bit in the
stream is just the sequence counter with the two least-significant bits removed.
Line 49: The position within a bit is output on this line. This is given by the two least-
significant bits of the sequence counter.
44
• Listing 23: VHDL code for the codec clock generator module.

005-
007- GENERIC
008- (
010- );
011- PORT
012- (
020- bit_cntr: OUT std_logic_vector(5 DOWNTO 0);
021- subcycle_cntr: OUT std_logic_vector(1 DOWNTO 0)
022- );
023- END clkgen;
024-
026- SIGNAL lrck_int: std_logic;
027- SIGNAL seq: std_logic_vector(7 DOWNTO 0);
028- BEGIN
029- gen_clock:
031- BEGIN
032- IF (clk'event AND clk='1') THEN
033- IF(reset=YES) THEN -- synchronous reset
034- seq <= (OTHERS=>'0');
035- lrck_int <= LEFT; -- start with left channel of codec
036- ELSIF(seq=CHANNEL_DURATION-1) THEN
037- seq <= (OTHERS=>'0'); -- reset sequencer every channel period
038- lrck_int <= NOT(lrck_int); -- toggle channel sel every period
039- ELSE
040- seq <= seq+1;
041- lrck_int <= lrck_int;
042- END IF;
043- END IF;
044- END PROCESS;
047- sclk <= seq(1); -- serial data shift clock = 1/4 master clock
048- bit_cntr <= seq(7 DOWNTO 2);
45
049- subcycle_cntr <= seq(1 DOWNTO 0);
The VHDL code for the channel module is shown in Listing 24. The inputs and outputs of
the clock generator as defined in the entity declaration are as follows:
chan_on: A high level on this input activates the channel. This input is usually controlled
by the left/right channel selector.
chan_sel: A high level on this input enables the interface that lets the shift registers be
read and written. (Note that despite its name, this input is not controlled by the
left/right channel selector.)
rd: A high level on this input outputs the value stored in the shift register connected to the
ADC.
wr: A high level on this input writes a new value into the shift register connected to the
DAC.
adc_out: The bits stored in the ADC shift register are read out in parallel through these
outputs..
adc_out_rdy: This output goes high after all the bits have been shifted from the codec
into the ADC shift register.
dac_in_rdy: This output goes high after all the bits in the DAC shift register have been
shifted over to the codec.
dac_underrun: This output goes high if the DAC shift register starts shifting data over to
the codec before it has been written through the parallel inputs.
sdin: The serial data stream for the codec DAC is shifted out through this output. (Note
that this output takes its name from the pin it is connected to on the codec chip; it is
not an input.)
sdout: The serial data stream from the codec ADC is shifted in through this input. (Note
that this input takes its name from the pin it is connected to on the codec chip; it is not
an output.)
46
rcv_adc: This process receives serial data from the ADC in the codec. The ADC shift
register is cleared upon reset and a flag is set which indicates the shift register does
not contain all the bits from the ADC. Once the reset is removed and the channel is
active, bits are shifted into the register during the third subcycle of each bit period (the
subcycles are numbered 0, 1, 2 and 3). Accepting data on the third subcycle gives
the serial data bit plenty of time to stabilize. Bits 1,2,..., up to the width of the ADC
data value are pushed into the shift register. Then the shifting stops. The shift
register is marked as ‘not full’ as soon as a single bit is shifted in so that the value will
not be inadvertently read. The shift register status changes to full as soon as the last
bit enters the shift register.
Line 66: The contents of the shift register are output in a parallel format on this line.
These outputs are not latched and will change as bits are shifted into the register.
Line 69: A flag is maintained that indicates whether the contents of the ADC shift register
have been read. The flag is set when the ADC register for the channel is full and it is
selected for a read operation. The flag will stay set after the read operation is
complete. Reading the register does not empty it. The shift register is no longer full
only when the first bit of the next sample is shifted into it. This will reset the read flag.
read_adc: This process updates the flag that indicates whether the ADC shift register has
been read.
Lines 84—85: A status output is asserted when the data in the ADC shift register is ready
for reading. Reads are permitted when the register is full and has not yet been read.
This output is cleared as soon as a read occurs or new data is shifted into the register.
detect_adc_overrun: This process monitors the ADC shift register and flags an error
condition if the register begins accepting bits from the current sample period but the
data from the previous period has not yet been read.
tx_dac: This process transmits serial data to the DAC in the codec. The DAC shift
register is cleared upon reset and a flag is set which indicates the shift register
contains no bits for the DAC. After the reset is removed, the register can be loaded in
parallel if the channel is selected for a write operation. If no write operation is in
process but the channel is active, then data is shifted out to the codec on the third
subcycle. (This gives the data some hold time so the codec chip can clock it in
reliably.) During the first bit period, a flag is set which indicates the register is no
longer empty and a serial transmission is in process. Then bits 1,2,..., up to the width
of the DAC data value are shifted out. As the last bit is output, the flag is set to show
the shift register is now empty.
Line 123: The DAC serial data input of the codec chip is driven by the most-significant bit
of the DAC shift register.
Line 126: A flag is maintained that indicates whether the DAC shift register has been
written. The flag is set when the DAC register for the channel is empty and it is
selected for a write operation. The flag will stay set after the write operation is
complete. Writing the register does not fill it. The shift register is full only when the
first bit of the next sample period is shifted out of it. This will reset the write flag.
write_dac: This process updates the flag that indicates whether the DAC shift register has
been written.
47
Lines 141—142: A status output is asserted when the DAC shift register is ready to be
written with new input data. Writes are permitted when the register is empty and has
not yet been written. This output is cleared as soon as a write occurs or when data
bits start shifting out of the register.
detect_dac_underrun: This process monitors the DAC shift register and flags an error
condition if the register starts shifting out data but has not yet been written with a new
data value for the current sample period.
• Listing 24: VHDL code for the codec channel module.

005-
007- GENERIC
008- (
010- ADC_WIDTH: positive := 20
011- );
012- PORT
013- (
017- chan_on: IN std_logic;
018- bit_cntr: IN std_logic_vector(5 DOWNTO 0);
019- subcycle_cntr: IN std_logic_vector(1 DOWNTO 0);
020- chan_sel: IN std_logic; -- select L/R channel for read/write
023- adc_out: OUT std_logic_vector(ADC_WIDTH-1 DOWNTO 0); -- ADC output
024- dac_in: IN std_logic_vector(DAC_WIDTH-1 DOWNTO 0); -- DAC input
025- adc_out_rdy: OUT std_logic; -- ADC output is ready to be read
027- dac_in_rdy: OUT std_logic; -- DAC input is ready to be written
028- dac_underrun: OUT std_logic; -- input to DAC arrived late
032- );
033- END channel;
034-
036- SIGNAL dac_shfreg: std_logic_vector(DAC_WIDTH-1 DOWNTO 0);
037- SIGNAL dac_empty: std_logic; -- DAC shift register is empty
038- SIGNAL dac_wr: std_logic; -- the DAC channel has been written
039- SIGNAL dac_wr_nxt: std_logic; -- the DAC channel has been written
040- SIGNAL dac_in_rdy_int: std_logic; -- internal version of dac_in_rdy
041- SIGNAL adc_shfreg: std_logic_vector(ADC_WIDTH-1 DOWNTO 0);
042- SIGNAL adc_full: std_logic; -- ADC shift register is full
48
043- SIGNAL adc_rd: std_logic; -- the ADC channel has been read
044- SIGNAL adc_rd_nxt: std_logic; -- the ADC channel has been read
045- SIGNAL adc_out_rdy_int: std_logic; -- internal version adc_out_rdy
046- BEGIN
048- rcv_adc:
050- BEGIN
051- IF(clk'event AND (clk=YES)) THEN
055- ELSIF((chan_on=YES) AND (subcycle_cntr=2)) THEN
056- IF(bit_cntr<ADC_WIDTH-1) THEN
059- ELSIF(bit_cntr=ADC_WIDTH-1) THEN
060- adc_full <= YES;
062- END IF;
063- END IF;
064- END IF;
065- END PROCESS;
067-
069- adc_rd_nxt <= YES WHEN (adc_full=YES AND chan_sel=YES AND rd=YES) OR
070- (adc_full=YES AND adc_rd=YES)
071- ELSE NO;
072- read_adc:
074- BEGIN
077- adc_rd <= NO;
078- ELSE
080- END IF;
081- END IF;
082- END PROCESS;
083- -- ADC data is ready if register is full and hasn't been read yet
084- adc_out_rdy_int <= YES WHEN adc_full=YES AND adc_rd=NO ELSE NO;
086-
090- BEGIN
093- adc_overrun <= NO;
094- ELSIF(bit_cntr=1 AND chan_on=YES AND adc_out_rdy_int=YES) THEN
095- adc_overrun <= YES;
096- END IF;
49
097- END IF;
098- END PROCESS;
099-
101- tx_dac:
103- BEGIN
108- ELSIF(chan_sel=YES AND wr=YES) THEN
110- ELSIF(chan_on=YES AND subcycle_cntr=2) THEN
111- IF(bit_cntr<DAC_WIDTH-1) THEN
112- dac_empty <= NO;
114- ELSIF(bit_cntr=DAC_WIDTH-1) THEN
117- END IF;
118- END IF;
119- END IF;
120- END PROCESS;
121-
123- sdin <= dac_shfreg(DAC_WIDTH-1) WHEN chan_on=YES ELSE '0';
124-
126- dac_wr_nxt <= YES WHEN (dac_empty=YES AND chan_sel=YES AND wr=YES) OR
127- (dac_empty=YES AND dac_wr=YES)
128- ELSE NO;
129- write_dac:
131- BEGIN
134- dac_wr <= NO;
135- ELSE
137- END IF;
138- END IF;
139- END PROCESS;
140- -- DAC is ready if register is empty and hasn't been written yet
141- dac_in_rdy_int <= YES WHEN dac_empty=YES AND dac_wr=NO ELSE NO;
143-
147- BEGIN
150- dac_underrun <= NO;
50
151- ELSIF(bit_cntr=1 AND chan_on=YES AND dac_in_rdy_int=YES) THEN
152- dac_underrun <= YES;
153- END IF;
154- END IF;
155- END PROCESS;
The VHDL code for the top-level module that combines the clock generator module with
two channel modules is detailed in Listing 25. The inputs and outputs of the top-level
module as defined in the entity declaration are as follows:
rd: A high level on this input outputs the value stored in the selected shift register
connected to the ADC.
wr: A high level on this input writes a new value into the selected shift register connected
to the DAC.
ldac_in, rdac_in: The DAC shift registers are loaded in parallel with bits passed through
these inputs.
ladc_out_rdy, rdac_out_rdy: These outputs go high after all the bits have been shifted
from the codec into the left or right ADC shift register, respectively.
adc_overrun: This output goes high if new serial data is shifted into either the left or right
ADC shift register before the old contents have been read out through the parallel
outputs.
ldac_in_rdy, rdac_in_rdy: These outputs go high after all the bits in the left or right DAC
shift register have been shifted over to the codec, respectively.
dac_underrun: This output goes high if either the left or right DAC shift register starts
shifting data over to the codec before it has been written through the parallel inputs.
and the codec.
51
Within the main body of the top-level module architecture section, the following modules
are instantiated:
u0: One clock generator module is instantiated. It receives the 12 MHz clock as an input
and generates the master clock, left/right clock, and serial shift clock for the codec. It
also outputs the position of the current bit in the serial stream and the current cycle
within each bit period.
Lines 73—75: The input signals to the codec on the XStend V1.3 Board pass through
inverters. Therefore, the clock signals are inverted on these lines to remove the effect
of the inverters.
u_left: The module, which handles the left channel of the codec, is instantiated. This
module is activated during one half of the left/right clock period. It is selected for
reading or writing by the left/right selection input.
u_right: The module, which handles the right channel of the codec, is instantiated. This
module is activated during the other half of the left/right clock period. It is selected for
reading and writing by the opposite polarity of the left/right selection input.
Lines 133—134: The overrun and underrun error indicators for the total codec interface
are formed by the logical-OR of the associated error outputs of the left and right
channel modules. Thus an error is reported if either channel reports an error.
Line 138: The serial data stream that is transmitted to the codec chip is selected from the
output data stream of the currently-active channel module. The data stream input to
the codec on the XStend V1.3 Board passes through an inverter. Therefore, the data
stream is inverted on this line to remove the effect of the inverter.
• Listing 25: VHDL code for the top-level codec interface module.

005-
007- GENERIC
008- (
010- ADC_WIDTH: positive := 20;
012- );
013- PORT
014- (
018- lrsel: IN std_logic; -- select L/R channel for read/write
021- ladc_out: OUT std_logic_vector(ADC_WIDTH-1 DOWNTO 0); -- L ADC
022- radc_out: OUT std_logic_vector(ADC_WIDTH-1 DOWNTO 0); -- R ADC
52
023- ldac_in: IN std_logic_vector(DAC_WIDTH-1 DOWNTO 0); -- left DAC
024- rdac_in: IN std_logic_vector(DAC_WIDTH-1 DOWNTO 0); -- right DAC
025- ladc_out_rdy: OUT std_logic; -- left ADC output ready to read
026- radc_out_rdy: OUT std_logic; -- right ADC output ready to read
027- adc_overrun: OUT std_logic; -- ADC overwritten before read
028- ldac_in_rdy: OUT std_logic; -- left DAC in ready to be written
029- rdac_in_rdy: OUT std_logic; --right DAC in ready to be written
030- dac_underrun: OUT std_logic; -- DAC did not receive data in time
037- );
039-
041- SIGNAL mclk_int: std_logic; -- internal codec master clock
042- SIGNAL lrck_int: std_logic; -- internal L/R codec channel select
043- SIGNAL sclk_int: std_logic; -- internal codec data shift clock
044- SIGNAL bit_cntr: std_logic_vector(5 DOWNTO 0);
045- SIGNAL subcycle_cntr: std_logic_vector(1 DOWNTO 0);
046- SIGNAL lsdin: std_logic;
047- SIGNAL rsdin: std_logic;
048- SIGNAL ladc_overrun: std_logic;
049- SIGNAL radc_overrun: std_logic;
050- SIGNAL ldac_underrun: std_logic;
051- SIGNAL rdac_underrun: std_logic;
052- SIGNAL lchan_sel: std_logic;
053- SIGNAL rchan_sel: std_logic;
054- SIGNAL lchan_on: std_logic;
055- SIGNAL rchan_on: std_logic;
056- BEGIN
057-
058- u0: clkgen
059- GENERIC MAP
060- (
061- CHANNEL_DURATION=>CHANNEL_DURATION
062- )
063- PORT MAP
064- (
065- clk=>clk,
066- reset=>reset,
067- mclk=>mclk_int,
068- sclk=>sclk_int,
072- );
073- lrck <= NOT(lrck_int); -- invert for inverter in XStend V1.3
074- mclk <= NOT(mclk_int);
075- sclk <= NOT(sclk_int);
076-
53
077- lchan_sel <= YES WHEN lrsel=LEFT ELSE NO;
078- lchan_on <= YES WHEN lrck_int=LEFT ELSE NO;
080- GENERIC MAP
081- (
084- )
085- PORT MAP
086- (
087- clk=>clk,
088- reset=>reset,
093- rd=>rd,
094- wr=>wr,
101- sdin=>lsdin,
102- sdout=>sdout
103- );
104-
105- rchan_sel <= YES WHEN lrsel=RIGHT ELSE NO;
106- rchan_on <= YES WHEN lrck_int=RIGHT ELSE NO;
108- GENERIC MAP
109- (
112- )
113- PORT MAP
114- (
115- clk=>clk,
116- reset=>reset,
121- rd=>rd,
122- wr=>wr,
129- sdin=>rsdin,
130- sdout=>sdout
54
131- );
132-
133- dac_underrun <= YES WHEN ldac_underrun=YES OR rdac_underrun=YES
134- ELSE NO;
135- adc_overrun <= YES WHEN ladc_overrun=YES OR radc_overrun=YES
136- ELSE NO;
137-
139- -- codec DAC depending on which channel is being loaded
140- sdin <= NOT(lsdin) WHEN lrck_int=LEFT ELSE NOT(rsdin);
141-
The interfaces to these three modules are placed into the package shown in Listing 26.
(The I/O declarations in the COMPONENT constructs have been removed for the sake of
brevity.) The declarations for the constants used in these modules are also included in the
package.
• Listing 26 : VHDL code for the codec package.
001- LIBRARY IEEE;

004-
013-
015- GENERIC
016- (
017- ...
018- );
019- PORT
020- (
021- ...
022- );
023- END COMPONENT;
024-
026- GENERIC
027- (
028- ...
029- );
030- PORT
031- (
032- ...
033- );
55
034- END COMPONENT;
035-
037- GENERIC
038- (
039- ...
040- );
041- PORT
042- (
043- ...
044- );
045- END COMPONENT;
046- END PACKAGE;
Once the codec interface module is completed and packaged, we can use it in an
application. The simplest use is to have the FPLD accept the left and right stereo inputs
from the codec ADCs and loop these back to the codec DACs so they can output the
stereo signals.
The VHDL code for the loopback application is detailed in Listing 27. The inputs and
outputs of the loopback design are as follows:
reset: A high level on this input synchronously resets the codec interface module. The
reset input is driven from the parallel port of the PC.
lrck: This output controls the activation of the left and right channel circuitry in the codec
and the codec interface.
and the codec.
application:
u0: This is the instantiation of the codec interface module. Note that the ADC output
buses of this module are connected back to the DAC input buses on lines 43—46.
loop: This process controls the reading of each ADC and the writing of the value back to
the associated DAC. For example, if the output of the left channel ADC is ready to be
read and the left channel DAC is ready to be written, then the left channel is selected
and the read and write control lines are asserted. This reads the data from the ADC
shift register and writes it into the DAC shift register during a single clock cycle. Then
the ADC and DAC registers will no longer be ready for reading or writing so the read
and write signals will be deasserted.
56
• Listing 27: VHDL code for a design that uses the codec interface module to do loopback.

004-
006- PORT
007- (
016- );
017- END loopback;
018-
024- BEGIN
026- GENERIC MAP
027- (
028- adc_width=>20,
029- dac_width=>20
030- )
031- PORT MAP
032- (
033- clk=>clk,
034- reset=>rst,
035- mclk=>mclk,
036- sclk=>sclk,
037- lrck=>lrck,
038- sdout=>sdout,
039- sdin=>sdin,
040- lrsel=>lrsel,
041- rd=>rd,
042- wr=>wr,
57
053- );
054-
056- BEGIN
065- ELSE
069- END IF;
070- END PROCESS;
• Listing 28: XS40 UCF file for the stereo signal loopback application.

008- net s<0> loc=p25;
009- net s<1> loc=p26;
• Listing 29: XS95 UCF file for the stereo signal loopback application.

008- net s<0> loc = p21
009- net s<1> loc = p23
1. Synthesize the VHDL code in the LOOP40\LOOPBACK.VHD for an XC4005XL

FPGA.
2. Compile the synthesized netlist using the LOOP40.UCF constraint file (Listing
28).
58
Remove the shunts from jumpers J4, J7, and J8 to disable the LEDs. Place a
shunt on jumper J17 so the codec serial output data stream can reach the FPLD.
Set all the DIP switches to the OPEN position.
4. Connect a stereo audio source (such as a CD player) to jack J9. Then plug a set
of stereo mini-headphones into jack J10.
5. Download the LOOP40.BIT file into the XS40/XStend combination with the
command: XSLOAD LOOP40.BIT.
6. Release the reset on the loopback circuit with the command XSPORT 0.
7. Start the CD player and listen to the result with the headphones.
1. Synthesize the VHDL code in the LOOP95\LOOP.VHD for an XC95108 CPLD.
2. Compile the synthesized netlist using the LOOP95.UCF constraint file (Listing
29).
Remove the shunts from jumpers J4, J7, and J8 to disable the LEDs. Place a
shunt on jumper J17 so the codec serial output data stream can reach the FPLD.
Set all the DIP switches to the OPEN position.
5. Connect a stereo audio source (such as a CD player) to jack J9. Then plug a set
of stereo mini-headphones into jack J10.
6. Download the LOOP95.BIT file into the XS95/XStend combination with the
command: XSLOAD LOOP95.BIT.
7. Release the reset on the loopback circuit with the command XSPORT 0.
8. Start the CD player and listen to the result with the headphones.
59
Appendix
A
XStend Schematics
xst1_3_2.sch-1 - Mon Nov 6 17:09:31 2000
xst1_3_2.sch-2 - Mon Nov 6 17:09:32 2000
xst1_3_2.sch-3 - Mon Nov 6 17:09:33 2000
xst1_3_2.sch-4 - Mon Nov 6 17:09:34 2000
xst1_3_2.sch-5 - Mon Nov 6 17:09:35 2000
El archivo http://www.dacya.ucm.es/mendias/143/docs/xstv20.pdf es un documento seguro que se ha incrustado en este
XSV Virtex Prototyping Board
XSV The XSV Board brings you the power of the XILINX Virtex FPGA embedded in a
framework for processing video and audio signals. The XSV Board accepts Virtex
FPGAs from 50K to 800K gates in size. The XSV can accept PAL, SECAM, or NTSC
● XCV50-XCV800
video with up to 9-bits of resolution on the red, green, and blue channels and can output
Virtex FPGA
video images through a 110 MHz, 24-bit RAMDAC. The XSV can also process stereo
● XC95108 CPLD
audio signals with up to 20 bits of resolution and a bandwidth of 50 KHz. Two
● Two 512K x 16
independent banks of 512K x 16 SRAM are provided for local buffering of signals and
SRAM banks
data.
● PAL/SECAM/NTSC
video decoder
● 110 MHz RAMDAC The XSV Board has a variety of interfaces for communicating with the outside world:
● 10/100 Ethernet PHY parallel and serial ports, Xchecker cable, USB port, PS/2 mouse and keyboard port, and
● 16 Mbit Flash RAM 10/100 Ethernet PHY layer interface. There are also two independent expansion ports,
● 100 MHz each with 38 general purpose I/O pins connected directly to the FPGA.
programmable
oscillator You configure the XSV Board through a PC parallel port, serial port, or from a bitstream
● Two expansion stored in the 16 Mbit Flash RAM. The Flash RAM can also store data for use by the
connectors each with FPGA after configuration is complete.
38 general-purpose
I/O
● Four pushbuttons
● DIP switch
● Two LED digits
● LED bargraph
● 20-bit stereo codec
● stereo in/out ports
● VGA monitor port
● mouse/keyboard PS/2
port
● USB port (host or
hub)
● Parallel/serial port
connectors
● ATX power input or
9 VDC power jack
2608 Sweetgum Drive
Apex NC 27502
Toll-free: 800-549-9377
FAX: 919-387-1302
;69%RDUG90DQXDO
How to install and use

your new XSV Board
XSV BOARD V1.0 MANUAL RELEASE DATE: 3/1/2000

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state.
XSV BOARD V1.0 MANUAL RELEASE DATE: 3/1/2000

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Limited Warranty...................................................................................... 1
Preliminaries................................................................................................... 4
Getting Help!............................................................................................ 4
Packing List ............................................................................................. 4
XSV Overview ................................................................................................ 5
XSV Board Features................................................................................ 5
Installation ...................................................................................................... 8
Installing the XSVTOOLs Software.......................................................... 8
Unpacking the Board ............................................................................... 8
Configuring the Jumpers.......................................................................... 8
Applying Power........................................................................................ 8
Connecting to a PC.................................................................................. 9
Testing the XSV Board ............................................................................ 9
Setting the Oscillator Frequency.............................................................. 9
Programming the Interface .................................................................... 10
Downloading Virtex Configuration Bitstreams........................................ 11
Downloading Virtex Configuration Bitstreams to Flash .......................... 12
XSV Circuitry ................................................................................................ 13
Programmable logic: XCV50-XCV800 Virtex FPGA and XC95108 CPLD13
100 MHz programmable oscillator......................................................... 13
16 Mbit Flash RAM ................................................................................ 14
SRAM Banks ......................................................................................... 16
Video Decoder....................................................................................... 17
RAMDAC and VGA Monitor Interface ................................................... 18
Stereo Codec......................................................................................... 20
Ethernet PHY......................................................................................... 20
Expansion Headers ............................................................................... 23
Pushbuttons and Eight-Position DIP Switch .......................................... 25
Digit and Bargraph LEDs....................................................................... 27
PS/2 Port ............................................................................................... 28
USB Port................................................................................................ 29
Parallel Port ........................................................................................... 30
Serial Port .............................................................................................. 31
Xchecker Cable ..................................................................................... 32
Power Connectors ................................................................................. 32
XSV Pin Connections................................................................................... 33
XSV Schematics........................................................................................... 34

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If you follow the instructions in this manual and you encounter problems, here are some
places to get help:
If you can't get the XSV Board hardware to work, send an e-mail message describing
your problem to bugs@xess.com or check our web site at http://www.xess.com.
If you can't get your XILINX software tools installed properly, send an e-mail message
http://support.xilinx.com.
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an XSV Board;
a 6-foot, 25-wire cable with a male DB25 connector at each end;
a 3.5" floppy diskette with XSV documentation and utilities;
a CDROM with XS Board documentation and utilities.
XSV BOARD V1.0 MANUAL 3/1/2000

;692YHUYLHZ
The XSV Board brings you the power of the XILINX Virtex FPGA embedded in a
framework for processing video and audio signals. The XSV Board has a single Virtex
FPGA from 50K to 800K gates in size. The XSV can digitize PAL, SECAM, or NTSC
video with up to 9-bits of resolution on the red, green, and blue channels and can output
video images through a 110 MHz, 24-bit RAMDAC. The XSV can also process stereo
audio signals with up to 20 bits of resolution and a bandwidth of 50 KHz. Two
independent banks of 512K x 16 SRAM are provided for local buffering of signals and
data.
The XSV Board has a variety of interfaces for communicating with the outside world:
parallel and serial ports, Xchecker cable, a USB port, PS/2 mouse and keyboard port, and
10/100 Ethernet PHY layer interface. There are also two independent expansion ports,
each with 38 general-purpose I/O pins connected directly to the Virtex FPGA.
You can configure the XSV Board through a PC parallel port, serial port, Xchecker cable
or from a bitstream stored in the 16 Mbit Flash RAM. The Flash RAM can also store data
for use by the FPGA after configuration is complete.
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The XSV Board includes the following resources:
Programmable logic chips:
XILINX Virtex FPGA: Virtex FPGAs from 57 Kgates (XCV50) up to 888 Kgates
(XCV800) in a 240-pin PQFP or HQFP package are compatible with the XSV
Board. The Virtex FPGA is the main repository of programmable logic on the
XSV Board.
XILINX XC95108 CPLD: The CPLD is used to manage the configuration of the
Virtex FPGA via the parallel port, serial port, or Flash RAM. The CPLD also
controls the configuration of the Ethernet PHY chip.
Programmable oscillator that provides a clock signal to the FPGA and CPLD derived
form a 100 MHz base frequency.
16 Mbit Flash RAM that can store multiple configurations or general-purpose data for
the FPGA.
Two independent 512K x 16 SRAM banks used by the FPGA for general-purpose
data storage.

Video decoder that accepts NTSC/PAL/SECAM signals through an RCA jack or S-
video connector and outputs the digitized signal to the FPGA.
RAMDAC with a 256-entry, 24-bit colormap that is used by the FPGA to output video
to a VGA monitor.
Stereo codec that lets the FPGA digitize and generate 0-50 KHz audio signals with up
to 20 bits of resolution.
10BASE-T/100BASE-TX Ethernet PHY that allows the FPGA to access a LAN at up

to 100 Mbps.
Two expansion headers interface the FPGA to external circuitry through 76 general-
purpose I/Os.
Four pushbuttons and one eight-position DIP switch provide general-purpose inputs to
the FPGA and CPLD.
Two LED digits and one LED bargraph let the FPGA and CPLD display status
information.
Mouse/keyboard PS/2 port gives the FPGA access to common PC input devices.
Single USB port provides the FPGA with a serial I/O channel with bandwidths of 1.5 to
12 Mbps.
Parallel/serial port interfaces let the CPLD send and receive data in a parallel or serial
format similar to a PC.
Xchecker cable interface allows downloading and readback of the FPGA

configuration.
ATX power connector or 9 VDC power jack lets the XSV Board receive power from a
standard ATX power supply or a 9 VDC power supply.
The location of these resources are indicated in the simplified view of the XSV Board
shown below. Each of these resources will be described in the following section.

9 VDC Parallel Port Serial RCA S-Video
Jack Port Jack Jack
DIP S w.
ATX Pow er
Connector
Xchecker
X C 9 5 1 08
CPLD 16 M bit Flash
E xpansion Connector
E xpansion Connector
512K x 8 512K x 8
SRA M Virtex FPG A SRA M
(XCV 50-800)
512K x 8 512K x 8
SRA M SRA M
Pushbuttons
Ether
Phy RAM
DAC
Stereo Stereo USB PS /2 RJ45 VG A

Input O utput Port Port Port O utput

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Run the setup.exe file on the XSVTOOLs CDROM. This will install the utilities and
configuration files for testing and programming your XSV Board.
If you are running Windows NT™, then you must also install the parallel port driver using
the port95nt.exe installation script on the CDROM.
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You should place the XSV Board on a non-conducting surface.
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1. Place a shunt on jumper J23.
2. Place a shunt on pins 2 and 3 of jumper J31.
3. Place a shunt on pins 2 and 3 of J22.
4. Place a shunt on pins 1 and 2 of J36.
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You can supply the XSV Board with power in two ways:
1. Recommended! Attach an ATX PC power supply to connector J11. Remove any

shunts on jumpers J13 and J14. Place a shunt on pins 1 and 2 of jumper J32.
2. Attach a 9 VDC power supply with a 2.1mm, center-positive plug to jack J12. The
power supply must be able to source at least 1.5 A. Place shunts on jumpers J13 and
J14. Place a shunt on pins 1 and 2 of jumper J32.
LED D2 will glow when the power is on.

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One DB25 connector on the 6-foot cable should be attached to connector J10 on the XSV
Board and the other end should plug into the parallel port connector of a PC.
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GXSTEST runs your XSV Board through a simple diagnostic routine to validate the
operation of the hardware. You start GXSTEST by clicking on the icon placed
on the desktop during the XSVTOOLs installation. This brings up the screen shown
below.
port pulldown list. GXSTEST starts with parallel port LPT1 as the default, but you can also
After selecting the parallel port, you select the type of XSV Board you are testing from the
associated pulldown list. Then click on the TEST button to start the testing procedure.
GXSTEST will program the CPLD on the XSV Board and then use it to program the Virtex
FPGA witha test circuit. Status messages will be printed at the bottom of the GXSTEST
window as the testing proceeds. At the end of the test, you will receive a message
informing you whether your XSV Board passed the test or not.
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The XSV Board has a programmable oscillator which provides a clock signal to the FPGA
and CPLD. The oscillator has an internal 100 MHZ frequency source that is scaled by a
divisor between 1 and 2052 to generate the clock signal for the rest of the XSV Board.
The divisor is stored in non-volatile memory in the oscillator chip so it will be restored each
time power is applied to the XSV Board.
The divisor is set with the GXSSETCLK software utility. You start GXSSETCLK by clicking
on the icon placed on the desktop during the XSVTOOLs installation. This
brings up the screen shown below.

Your next step is to select the parallel port that your XSV Board is connected to from the
port pulldown list. GXSSETCLK starts with parallel port LPT1 as the default, but you can
also select LPT2 or LPT3 depending upon the configuration of your PC. After selecting
the parallel port, you select "XSV" from the pulldown list of XS Board types.
Next you must enter a divisor between 1 and 2052 into the text box. Once programmed,
the oscillator will output a clock signal generated by dividing its 100 MHz master frequency
by the divisor. The divisor is stored in non-volatile storage in the oscillator chip so you only
need to use GXSSETCLK when you want to change the frequency.
The external clock checkbox is inactive for the XSV Board because no external clock is
connected to the programmable oscillator chip.
Clicking on the SET button will start the oscillator programming procedure. Status
messages will be printed at the bottom of the GXSSETCLK window as the programming
proceeds. You will also receive instructions on how to set the shunts on the XSV Board
jumpers to place the oscillator into its programming mode. At the end of the programming,
you will receive a message informing you that your XSV Board clock has been set.
Note that GXSSETCLK reprograms the CPLD on the XSV Board in order to access the
programmable oscillator. So you will need to reprogram the CPLD with a parallel port
interface circuit if you want to program the FPGA. (See the next section for details on
this.)
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The Virtex FPGA is the main repository of programmable logic on the XSV Board. The
CPLD manages the configuration of the FPGA via the parallel port or from the Flash
memory. Therefore, the CPLD must be configured so that it implements the necessary
interface. The CPLD stores its configuration in its internal non-volatile memory so the
interface is restored each time power is applied to the XSV Board (unless the interface
circuit is erased).
The CPLD is enabled for configuration by placing a shunt on jumper J23. The CPLD is
configured with an interface by using the GXSLOAD software utility. You start GXSLOAD
by clicking on the icon placed on the desktop during the XSVTOOLs installation.
This brings up the screen shown below.

Your next step is to select the parallel port that your XSV Board is connected to as shown
below. GXSLOAD starts with parallel port LPT1 as the default, but you can also select
LPT2 or LPT3 depending upon the configuration of your PC.
After setting the parallel port, you can download an .SVF file to the CPLD on the XSV
Board simply by dragging it to the GXSLOAD window. To program the CPLD with the
parallel port interface, drag the dwnldpar.svf file from the XSTOOLS\BIN directory. Once
you release the mouse left-button and drop the file, GXSLOAD will begin sending it to the
XSV Board through the parallel port connection. During the process, GXSLOAD will
display the name of the file currently being downloaded.
Once the CPLD is programmed with the parallel port interface circuit, you can remove the
shunt from jumper J23 to prevent accidental reprogramming of the CPLD.
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Once the CPLD is programmed with the downloading interface circuit, you can download
bitstreams into the Virtex FPGA using the GXSLOAD utility. Make sure there is a shunt
across pins 2 and 3 of jumper J31. Then drag-and-drop into the GXSLOAD window a
.BIT configuration bitstream for the type of Virtex FPGA on your XSV Board. The
bitstream will pass through the parallel port and CPLD and then into the FPGA. (During
the download process, you will notice a "fluttering" of the bottom segment of the left LED
digit.)
Once the downloading is finished, the .BIT file name is added to the Recent Files window
and the Reload button is enabled. You can download the file to the XSV Board again just
by clicking on the Reload button.
Your XSV Board is now configured with the circuit in your .BIT file.

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You can also store a bitstream for the FPGA in the 16 Mb Flash RAM on the XSV Board.
Once again, make sure there is a shunt across pins 2 and 3 of jumper J31. Also make
sure that all the DIP switches are in the OFF position. Then just drag-and-drop a .EXO file
containing the bitstream to the GXSLOAD window. GXSLOAD will configure the CPLD
with a circuit that lets it program the Flash RAM. Then GXSLOAD uses the CPLD to
program the Flash with the contents of the .EXO file. Finally, the CPLD is configured with
a circuit that loads the FPGA when power is applied.
Now the Virtex FPGA will be loaded with the circuit you stored in the Flash whenever
power is applied to the XSV Board. You will have to reprogram the CPLD with the
dwnldpar.svf file if you want to reconfigure the FPGA with a .BIT file using the parallel port.
The .EXO file is generated using the Programmer tool in Foundation. The configuration
data should start at address 0 and extend upward to higher addresses.

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This section describes the various sections of the XSV Board and shows how the I/O of
the FPGA and CPLD are connected to the rest of the circuitry. The schematics which
follow are less detailed so as to simplify the descriptions. Please refer to the complete
schematics at the end of this document if you need more details.
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The XSV Board contains two programmable logic chips:
A XILINX Virtex FPGA in a 240-pin QFP package. Virtex FPGAs from 57 Kgates
(XCV50) up to 888 Kgates (XCV800) are compatible with the XSV Board. The Virtex
FPGA is the main repository of programmable logic on the XSV Board.
A XILINX XC95108 CPLD that is used to manage the configuration of the Virtex
FPGA via the parallel port, serial port, or Flash RAM. The CPLD also controls the
configuration of the Ethernet PHY chip.
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A Dallas DS1075 programmable oscillator
(http://www.dalsemi.com/DocControl/PDFs/1075.pdf) provides a clock signal to both the
FPGA and the CPLD. The DS1075 has a maximum frequency of 100 MHz that is divided
to provide frequencies of 100 MHz, 50 MHz, 33.3 MHz, 25 MHz, ..., 48.7 KHz. The clock
signal is connected to dedicated clock inputs of both the CPLD and FPGA as follows:
'6 9LUWH[ ;&

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CLK 89 22
To set the divisor value, the DS1075 must be placed in its programming mode. This is
done by pulling the clock output to Vcc on power-up with a shunt across pins 1 and 2 of
jumper J22. Then programming commands to set the divisor can be sent to the DS1075
by either the CPLD or FPGA. The divisor is stored in EEPROM in the DS1075 so it will be
restored whenever power is applied to the XSV Board. The shunt on jumper J22 must be
across pins 2 and 3 to make the oscillator output a clock signal upon power-up.
To get a precise frequency value or to sync the XSV circuitry with an external system, you
can insert an external clock signal through pin 1 of connector J27 and place a shunt
across pins 2 and 3 of jumper J36. This external clock replaces the output from the
DS1075 oscillator.

J2 2
2
1 3
100 M H z
Prog. O sc.
1
J3 6
DS1075
2
3
22 89 1
External
J2 7 C lock
XC95108 Virte x
CPLD FPGA
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An Intel 28F016S5 Flash RAM
(http://developer.intel.com/design/flcomp/datashts/290597.htm) with 16 Mbits of storage
(2M × 8) is connected to both the Virtex FPGA and XC95108 CPLD as follows:
re se t
ce
oe
XC95108 we
rd y
1 6 M b it
CPLD 8 F lash R A M
d 0 -7
a 0 -2 0
21
Virte x
FPGA
The CPLD and FPGA both have access to the Flash RAM. Typically, the CPLD will
program the Flash with data passed through the parallel or serial port. If the data is an
FPGA configuration bitstream then the CPLD can be configured to program the FPGA
with the Flash bitstream whenever the XSV Board is powered up. After power-up, the
FPGA can read and/or write the Flash. (Of course, the CPLD and FPGA have to be
programmed such that they do not conflict if both are trying to access the Flash.) The
Flash can be disabled by raising the /CE pin to Vcc in which case the I/O lines connected
to the Flash can be used for general-purpose communication between the FPGA and the
CPLD.
The pins of the FPGA and CPLD connected to the Flash RAM are listed below:

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/RESET N/A 3
/CE 170 46
/OE 173 42
/WE 131 43
RDY 171 41
D0 177 32
D1 167 33
D2 163 34
D3 156 35
D4 145 36
D5 138 37
D6 134 39
D7 124 40
A0 132 16
A1 133 17
A2 139 18
A3 141 19
A4 144 20
A5 147 23
A6 152 24
A7 154 25
A8 157 27
A9 160 28
A10 162 29
A11 169 30
A12 168 49
A13 161 50
A14 159 52
A15 155 53
A16 153 54
A17 149 55
A18 146 56
A19 142 58
A20 140 59

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The FPGA has access to two independent banks of SRAM as shown below: Each SRAM
bank is organized as 512K × 16 bits. Each bank is made from two AS7C4096 SRAMs
(ftp://ftp14.ba.best.com/pub/pai/FTP_site/pdf/sram.pdf/as7c34096.pdf). The FPGA pins
connected to the SRAM banks are shown in the accompanying table.
8 8
d 0 - 7
d 0 - 7
4 M b it ce
oe
ce
oe
4 M b it
SR AM we we SR AM
a 0 - 1 8
19 19 a 0 - 1 8
Virte x
FPGA
a 0 - 1 8
a 0 - 1 8
4 M b it ce
oe
ce 4 M b it
oe
SR AM we we SR AM
8 8
d 0 - 7
d 0 - 7
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/CE 186 109
/OE 228 95
/WE 201 68
D0 202 70
D1 203 71
D2 205 72
D3 206 73
D4 207 74
D5 208 78
D6 209 79
D7 215 80
D8 216 81
D9 217 82
D10 218 84
D11 220 85
D12 221 86
D13 222 87
D14 223 93
D15 224 94

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A0 200 67
A1 199 66
A2 195 65
A3 194 64
A4 193 63
A5 192 57
A6 191 56
A7 189 55
A8 188 54
A9 187 53
A10 238 108
A11 237 107
A12 236 103
A13 235 102
A14 234 101
A15 232 100
A16 231 99
A17 230 97
A18 229 96
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The XSV Board can digitize NTSC, SECAM, and PAL video signals using the SAA7113
video decoder (http://www-us.semiconductors.philips.com/pip/SAA7113H). The digitized
video arrives at the FPGA over the VPO bus. The arrival of video data is synchronized
with the rising edge of the LLC (line-locked clock) from the video decoder. The FPGA
2
programs the video options of the SAA7113 using the I C bus (SCL and SDA).
8
vpo 0 - 7
lu m a S -V id eo
rts0 a i11 C o nn ecto r
S A A 7 11 3 a i12 c hrom a (J8)
Virte x rts1
FPGA
rtco Vide o
llc a i21
scl D e co d er a i22 c vbs
R C A Ja ck
sda (J9)
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RTS0 111
RTS1 110

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RTCO 113
VPO0 116
VPO1 117
VPO2 118
VPO3 125
VPO4 126
VPO5 127
VPO6 128
VPO7 130
SCL 114
SDA 115
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The FPGA can generate a video signal for display on a VGA monitor either directly or
using a BT481A RAMDAC
(http://www.erc.msstate.edu/~reese/EE4993/data_sheets/btl481a_c.pdf) depending upon
the arrangement of the shunts on jumpers J5, J6, and J7.
vsyn c
h sync
p 5
p 4
p 3
p 2
p
p
1
0
r 0
r 1
g 0
g 1
b 0
b 1
VGA
C o nn ecto r
(J4)
8
p 0 - 7
J5 re d
b lan k re d
p ixelclk
Virte x B T 4 8 1A g ree n
J6 g ree n
rd
FPGA wr RAM DAC
rs J7 b lue
0 - 2
b lue
d
8 0 - 7
When the FPGA is directly generating VGA signals, the lower six bits of the P bus provide
two-bits of red, green, and blue color information to a simple resistor-ladder DAC. The
outputs of the DAC are sent to a VGA monitor along with the horizontal and vertical sync
pulses (/HSYNC, /VSYNC) from the FPGA.
When the RAMDAC generates the VGA color signals, then the FPGA uses the full eight-
bit P bus to pass the index of the color for the current pixel. The index is used to lookup
the 24-bit color value (eight bits for the red, green, and blue components) stored in the

256-entry colormap of the RAMDAC chip. The transfers over the P bus are synchronized
with the PIXELCLK generated by the FPGA. The FPGA lowers the /BLANK signal when
the pixels fall outside the desired visible area of the monitor screen.
The colormap of the RAMDAC is initialized by the FPGA using the D bus along with the
RS, /WR, and /RD signals. The 24-bit colormap entries are passed in groups of three
bytes over the eight-bit D bus synchronized by the /WR signal. The register-select signals
(RS0, RS1, RS2) select the staging register for writing the colormap. The contents of the
staging register are written into the colormap after the last byte of color information arrives
over the D bus, and then the internal colormap address is incremented to point to the next
entry.
The shunt placement to enable the FPGA to generate VGA signals directly or through the
RAMDAC is shown below.
J7 J6 J5 J7 J6 J5
Direct VG A RAM DAC
Shunt Setting Shunt Setting
The pin assignments for the connection of the FPGA to the VGA signal generation circuitry
are shown below. Note that the FPGA shares some connections between the RAMDAC
and the chip which interfaces to the Ethernet (LXT970A). The RAMDAC pins are used to
load the colormap and should not be active except during system initialization. The other
connections are used for Ethernet data transmission and reception and are usually only
active after system initialization.
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PIXELCLK 52
/HSYNC /HSYNC 48
/VSYNC /VSYNC 49
/BLANK 50
RED0 P0 70
RED1 P1 71
GREEN0 P2 72
GREEN1 P3 73
BLUE0 P4 74
BLUE1 P5 78
P6 79
P7 80
/RD 47
/WR 46
RS0 31 TXD4
RS1 28 RX_ER
RS2 26 RX_DV
D0 42 TXD0

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D1 41 TXD1
D2 40 TXD2
D3 39 TXD3
D4 38 RXD0
D5 36 RXD1
D6 35 RXD2
D7 34 RXD3
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The XSV Board has an AK4520A stereo codec
(http://www.akm.com/ProductPages/ak4520a.html) that accepts two analog input
channels from jack J1, digitizes the analog values, and sends the digital values to the
FPGA as a serial bit stream. The codec also accepts a serial bit stream from the XS
Board and converts it into two analog output signals, which exit the XSV Board through
jack J2. The serial bit streams are synchronized with a clock from the FPGA that enters
the codec on SCLK signal. The FPGA uses the LRCK signal to select the left or right
channel as the source/destination of the serial data. The master clock from the FPGA
m clk in S tere o Ja ck
le ft
lrck in (J1)
Virte x sclk
A K 4 52 0 A r ig h t
FPGA sdin
Codec o ut le f t S tere o Ja ck
Am p
o ut (J2)
sdo ut rig h t
(MCLK) synchronizes all the internal operations of the codec.
The FPGA pins which connect to the codec are as follows:
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MCLK 3
LRCK 4
SCLK 5
SDIN 6
SDOUT 7
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The XSV Board interfaces to an Ethernet LAN at 10 or 100 Mbps. The LXT970A Ethernet
PHY chip (http://128.11.21.45/scripts/mardev/product/lxt970.asp ) connects to both the

FPGA and the CPLD. The FPGA acts as a MAC (media access controller) and manages
the transfer of data packets to and from the PHY chip, while the CPLD controls the
configuration pins that determine the operational mode of the PHY chip.
tx_e rr
tx_clk
tx_e n
4
txd 0 - 4
rx_e r
tp op
tra n sfo rm e r
rx_clk
Virte x rx_d v
tp on R J45
4 C o nn ecto r
FPGA rxd 0 - 4
tp ip (J3)
col
crs tp in
trste
fd s/m dint
L X T 9 70 A
m dio E th e rne t
m dc PH Y
4 mf 0 -4
2 cfg 0 - 1
m dd is
fd e
re se t
X C 95 1 0 8 p w rdw n
C P LD le d s
le d r
le d t
le d l
le d c
The FPGA enables the transmitter with TX_EN and sends bits on TXD4-0 in sync with the
transmit clock (TX_CLK) generated by the PHY chip. The PHY chip is alerted to
transmission errors that occur in the MAC when the TX_ERR signal is asserted. The
FPGA also receives an indication when valid data has been received (RX_DV) and the
data (RXD0-4) in sync with the receiver clock (RX_CLK) from the PHY chip. Any reception
errors are indicated to the FPGA via the RX_ER signal. The CRS signal indicates when
the receiver is non-idle. The COL signal is asserted when data collides on the Ethernet.
The FPGA can disable the interface to the PHY chip by asserting the tristate control
(TRSTE). Otherwise, the FPGA passes management information to and from the PHY
chip over the serial data line (MDIO) in sync with a clock (MDC). the FPGA can be alerted
to changes in PHY chip status by the FDS/MDINT interrupt line.
The CPLD sets the static values on pins which control the configuration of the PHY chip.
Pins MF0-4 set the modes for auto-negotiation, repeating, symbol transmission,
scrambling, etc. Likewise, the configurations signals (CFG0-1) select the 10 Mbps or 100
Mbps operating speed of the PHY chip. MDDIS enables/disables the management
information interface. FDE selects either full-duplex or half-duplex communication mode.
The reset (/RESET) and power-down (PWRDWN) signals do exactly what they say.

The CPLD also gets receives the status outputs from the PHY chip that normally drive
LEDs. The outputs are active-low and indicate when 100 Mbps operation is selected
(/LEDS), the receiver is active (/LEDR), the transmitter is active (/LEDT), the link is active
(/LEDL), and a collision is detected (/LEDC). The CPLD can relay these signals to the
LEDs on the XSV Board if you wish to display the Ethernet status.
The connections of the PHY chip to the FPGA and CPLD are listed below. Note that the
FPGA shares some connections between the PHY chip and the RAMDAC. The
RAMDAC pins are used to load the colormap and should not be active except during
system initialization. The PHY connections are used for data transmission and reception
and are usually only active after system initialization.
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COL 23
CRS 21
TRSTE 24
TX_CLK 210
TX_EN 25
TX_ER 27
TXD0 42 D0
TXD1 41 D1
TXD2 40 D2
TXD3 39 D3
TXD4 31 RS0
RX_CLK 213
RX_DV 26 RS2
RX_ER 28 RS1
RXD0 38 D4
RXD1 36 D5
RXD2 35 D6
RXD3 34 D7
RXD4 33
FDS/MDINT 18
MDC 19
MDIO 20
MDDIS 94
MF0 91
MF1 90
MF2 89
MF3 87
MF4 86
CFG0 93
CFG1 2
FDE 92
/RESET 3

/LEDS 1
/LEDR 95
/LEDT 96
/LEDL 97
/LEDC 99
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The XSV Board has two 50-pin headers (J25 and J26) which connect the FPGA to
external systems. The arrangement of the headers is shown below:
J2 6
1
50
49
Virte x
FPGA
U18
49
50
1
2
J2 5
The connections between the FPGA and the expansion headers are listed below. The
FPGA pins which connect to the left and right expansion headers are also connected to
the left and right banks of SRAM, respectively. The SRAM bank chip-enable should be
raised to disable the SRAMs on that side if the associated expansion header is being used
for external I/O.
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1 186 109 /CE
2 187 53 A9
3 +5V
4 188 54 A8
5 189 55 A7
6 191 56 A6
7 GND
8 192 57 A5
9 193 63 A4
10 194 64 A3
11 +5
12 195 65 A2
13 199 66 A1
14 200 67 A0
15 GND
16 201 68 /WE
17 202 70 D0
18 203 71 D1
19 +5
20 205 72 D2
21 206 73 D3
22 207 74 D4
23 GND
24 208 78 D5
25 209 79 D6
26 215 80 D7
27 +3.3
28 216 81 D8
29 217 82 D9
30 218 84 D10
31 GND
32 220 85 D11
33 221 86 D12
34 222 87 D13
35 +3.3
36 223 93 D14
37 224 94 D15
38 228 95 /OE
39 GND
40 229 96 A18
41 230 97 A17
42 231 99 A16
43 +3.3
44 232 100 A15

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45 234 101 A14
46 235 102 A13
47 GND
48 236 103 A12
49 237 107 A11
50 238 108 A10
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The XSV Board has a bank of eight DIP switches and four pushbuttons that are
accessible from the FPGA. The CPLD is also connected to the DIP switches and one of
the pushbuttons. When pressed, each pushbutton pulls the connected pin of the FPGA
and CPLD to ground. Otherwise, the pin is pulled high through a resistor. Likewise, each
DIP switch pulls the connected pin of the FPGA or CPLD to ground when it is closed or
ON. When the DIP switch is open or OFF, the pin is pulled high through a resistor.
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External
C lock
D IP
S w itch
(S W 6 )
SW 4
SW 3
SW 2
SW 1
X C 95 1 0 8 Virte x
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The table below lists the connections from the FPGA and CPLD to the switches. The DIP
switches also share the same pins as the uppermost eight bits of the Flash RAM address
bus. If the Flash RAM is programmed with several FPGA bitstreams, then the DIP switch
can be used to select a particular bitstreams which will be loaded into the FPGA by the
CPLD on power-up.
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SW1 174
SW2 175
SW3 176
SW4 185 7
DIPSW1 161 50 A13
DIPSW2 159 52 A14
DIPSW3 155 53 A15
DIPSW4 153 54 A16
DIPSW5 149 55 A17
DIPSW6 146 56 A18
DIPSW7 142 58 A19

DIPSW8 140 59 A20
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The XSV Board has a 10-segment bargraph LED and two more 7-segment LED digits for
use by the FPGA and CPLD. All of these LEDs are active-high meaning that an LED
segment will glow when a logic-high is applied to it.
The table below lists the connections from the FPGA and CPLD to the LEDs. The LEDs
also share the same pins as the uppermost eight bits of the Flash RAM address bus. If
the Flash RAM is programmed with several FPGA bitstreams, then the DIP switch can be
used to select a particular bitstreams which will be loaded into the FPGA by the CPLD.

S6
S5 S4
S2 S3 S1
S0

S6
S5 S4
S2 S3 S1
S0
7 7 10 7 7 10
XC95108 Virte x
CPLD FPGA
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SL0 177 32 D0
SL1 167 33 D1
SL2 163 34 D2
Left Digit
SL3 156 35 D3
SL4 145 36 D4
SL5 138 37 D5
SL6 134 39 D6

SR0 124 40 D7
SR1 132 16 A0
Right Digit
SR2 133 17 A1
SR3 139 18 A2
SR4 141 19 A3
SR5 144 20 A4
SR6 147 23 A5
B0 152 24 A6
B1 154 25 A7
B2 157 27 A8
B3 160 28 A9
Bargraph
B4 162 29 A10
B5 169 30 A11
B6 168 49 A12
B7 173 42 /OE
B8 131 43 /WE
B9 171 41 RDY
36 3RUW
The XSV Board provides a PS/2-style interface (mini-DIN connector J20) to either a
keyboard or a mouse. The FPGA receives two signals from the PS/2 interface: a clock
signal and a serial data stream that is synchronized with the falling edges on the clock
signal.
clk P S /2
Virte x C o nn ecto r
d ata
FPGA (J20 )
The following table shows the connections from the FPGA to the PS/2 interface.
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CLK 13
DATA 17

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The XSV Board has a USB interface (J35) that can be connected to a variety of high-
speed or low-speed USB peripherals. The FPGA interfaces to the two differential data
signals from the USB port through a PDIUSBP11A USB interface chip (http://www-
us.semiconductors.philips.com/pip/PDIUSBP11A_2).
J1 6
J1 8
P D IU S B P 11A lo w
1 3
h igh V
/O E c c
VPO spe ed 2 spe ed

D- USB
V M O /F S E O D-
Virte x RCV D+ C o nn ecto r
VP D+
FPGA VM
(J35 )
SUSPND
SPEED
MODE
J3 7 J3 4 J3 3
3 1
h igh 2 lo w
spe ed spe ed J1 9
The USB port is set to high (12 Mbps) or low speed (1.5 Mbps) by shunts on jumpers J18
and J37. A 15K load can be placed on the D+ and D- USB signals by placing shunts
across jumpers J33 and J34. If the USB peripheral connected to the port needs to draw
power from the XSV Board, then a shunt should be placed on jumper J16.
The connections of the FPGA to the USB interface chip are listed below. Note that the
FPGA shares some of its pins between the USB interface, the PS/2 interface and one
pushbutton switch.
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/OE 12
VPO 13 PS/2 CLK
VMO/FSEO 17 PS/2 DATA
RCV 11
VP 10
VM 9
SUSPND 176 SW3

3DUDOOHO 3RUW
The CPLD handles the interface to the parallel port. The seventeen active lines of the
parallel port connect to general-purpose I/O pins on the CPLD.
Four of the parallel port lines also connect to the JTAG pins through which the CPLD is
programmed. The TCK signal clocks configuration data in through the TDI pin while the
TMS signal steers the actions of the programming state machine. The TDO pin outputs
information back through the parallel port. Removing the shunt from jumper J23 isolates
the TCK pin from the parallel port so the CPLD will not be inadvertently reprogrammed
during routine parallel port operations. The series resistor prevents the TDO output from
interfering with the general-purpose I/O pin during routine parallel port operations.
The CPLD can be programmed to act as an interface between the FPGA and the parallel
port (the dwnldpar.svf file is an example of such an interface). Schmitt-trigger inverters
can be inserted into the d0, d1, and c1 signal lines by placing shunts on pins 2 and 3 of
jumpers J29, J30, and J31, respectively. Along with the parallel port interface circuitry in
the CPLD, these inverters make the XSV Board compatible with the GXSPORT and
GXSLOAD software utilities. If your application requires direct access to these signal
lines, then you can move the shunts on one or more of these jumpers to pins 1 and 2. But
GXSLOAD will no longer work if you remove the inverter from the c1 signal line.
3
J2 9 d 0
2
1
3
J3 0 d 1
2
1
d 2
d 3
d 4
d 5 P a ralle l P ort
d 6
C o nn ecto r
d
s
7
3
(J10 )
s 4
s 5
s 6
XC95108 s 7
c 0
CPLD 3
J3 1 c 1
2
1
c 2
c 3
td i J2 3
tm s
tck
td o
The table below lists the connections from the parallel port to the general-purpose I/O pins
of the CPLD:
3DUDOOHO ;&
3RUW 3LQ &3/' 3LQ

1 (C0) 79
2 (D0) 77
3 (D1) 74
4 (D2) 72
5 (D3) 70
6 (D4) 68
7 (D5) 67
8 (D6) 66
9 (D7) 65
10 (S6) 64
11 (S7) 63
12 (S5) 61
13 (S4) 60
14 (C1) 78
15 (S3) 76
16 (C2) 73
17 (C3) 71
6HULDO 3RUW
The CPLD handles the interface to the serial port. The four active lines of the serial port
connect to general-purpose I/O pins on the CPLD as follows.
6HULDO 3RUW ;&

3LQ &3/' 3LQ
RTS 82
TD 81
CTS 85
RD 80
M AX232A
rd
cts S e ria l P ort

X C 95 1 0 8 C o nn ecto r
C P LD td (J28 )
rts
le vel
shifte rs

;FKHFNHU &DEOH
Header J21 provides an interface between the FPGA and an Xchecker cable. The
Xchecker cable can be used to perform configuration and readback operations on the
FPGA. To prevent interference with the Xchecker cable, the CPLD should be erased or
the pins in the table below should be tristated when the CPLD is active. The shunt should
also be removed from jumper J36 to disconnect the DS1075 and any external clocks from
the clock input by the Xchecker cable (CLKI).
;FKHFNHU 3LQ 9LUWH[ )3*$ 3LQ &3/' 3LQ

1 – VCC (+5V) N/A N/A
2 – RT 132 16
3 – GND N/A N/A
4 – RD 133 17
6 – TRIG 139 18
7 – CCLK 179 12
9 – DONE 120 10
10 – TDI 167 33
11 – DIN 177 32
12 – TCK 239 4
13 – PROGRAM 122 11
14 – TMS 156 35
15 – INIT 123 9
16 – CLKI 89 22
17 – RST 144 20
18 – CLKO 141 19
3RZHU &RQQHFWRUV
A standard ATX PC power supply can be connected to the XSV Board through connector
J11. The connector is keyed so power cannot be applied with the wrong polarity. The
shunts should be removed from jumpers J13 and J14 to prevent the 9 VDC converter
circuitry from interfering with the ATX power supply. We recommend using the ATX
power supply due to its stability and power capacity.
The XSV Board can also be powered from a 9 VDC power supply through jack J12. The
power supply must have a 2.1mm, center-positive plug. Two voltage regulators will
generate the 5V and 3.3V voltages for the other XSV Board components. Shunts should
be placed on jumpers J13 and J14 to connect the outputs from the voltage regulators to
the rest of the XSV Board. We do not recommend the 9 VDC power input for general use!
The 2.5V for the Virtex FPGA core logic can be generated on the XSV Board or supplied
from an external source. Placing a shunt across pins 1 and 2 of jumper J32 will use the
on-board regulator to generate the 2.5V from the 5V supply. You can inject 2.5V from an
external source by attaching the positive terminal to pin 2 of jumper J32 and ground to pin
3.

$
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&RQQHFWLRQV
The following tables list the pin numbers of the Virtex FPGA and the XC95108 CPLD
along with the pin names of the other chips that they connect to. These connections
correspond with the pin assignments in the user-constraint files VIRTEX.UCF and
CPLD.UCF.

Connections Between the Virtex FPGA and the Other XSV Board Components
XC95108 Flash Video Parallel Serial Prog.
Virtex FPGA CPLD LEDs Switches RAM Ethernet Decoder RAMDAC Codec RAM PS/2 USB Port Port Osc. Xchecker
1 GND
2 TMS 35 S3 (left) D3 TMS
3 MCLK
4 LRCK
5 SCLK
6 SDIN
7 SDOUT
8 GND
9 VM
10 VP
11 RCV
12 /OE
13 CLK VPO
14 GND
15 VCCO
16 VCCINT
17 DATA VMO
18 FDS/MDINT
19 MDC
20 MDIO
21 CRS
22 GND
23 COL
24 TRSTE
25 TxEN
26 RxDV RS2
27 TxERR
28 RxERR RS1
29 GND
30 VCCO
31 TxD4 RS0
32 VCCINT
33 RxD4
34 RxD3 D7
35 RxD2 D6
36 RxD1 D5
37 GND
38 RxD0 D4
39 TxD3 D3
40 TxD2 D2
41 TxD1 D1
42 TxD0 D0
43 VCCINT
44 VCCO
45 GND
46 /WR
47 /RD
48 /HSYNC
49 /VSYNC
50 /BLANK
51 GND
52 PIXELCLK
53 A9 (right)
54 A8 (right)
55 A7 (right)
56 A6 (right)
57 A5 (right)
58 M1 14
59 GND
60 M0 13
61 VCCO
62 M2 15
63 A4 (right)
64 A3 (right)
65 A2 (right)
66 A1 (right)
67 A0 (right)
68 /WE (right)
69 GND
70 P0 D0 (right)
71 P1 D1 (right)
72 P2 D2 (right)
73 P3 D3 (right)
74 P4 D4 (right)
75 GND
76 VCCO
77 VCCINT
78 P5 D5 (right)
79 P6 D6 (right)
80 P7 D7 (right)
81 D8 (right)
82 D9 (right)
83 GND
84 D10 (right)
85 D11 (right)
86 D12 (right)
87 D13 (right)
88 VCCINT
89 PGCK 22 CLK CLKI
90 VCCO
91 GND
92 PGCK LLCK
93 D14 (right)
94 D15 (right)
95 /OE (right)
96 A18 (right)
97 A17 (right)
98 GND
99 A16 (right)
100 A15 (right)
101 A14 (right)
102 A13 (right)
103 A12 (right)
104 VCCINT
105 VCCO
106 GND
107 A11 (right)
108 A10 (right)
109 /CE (right)
110 RTS1
111 RTS0
112 GND
113 RTC0
114 SCL
115 SDA
116 VPO0
117 VPO1
118 VPO2
119 GND
120 DONE 10 DONE
121 VCCO
122 /PROG 11 /PROGRAM
123 /INIT 9 /INIT
124 D7 40 S0 (right) D7
125 VPO3
126 VPO4
127 VPO5
128 VPO6
129 GND
130 VPO7
131 43 BAR8 /WE
132 16 S1 (right) A0 RT
133 17 S2 (right) A1 RD
134 D6 39 S6 (left) D6
135 GND
136 VCCO
137 VCCINT
138 D5 37 S5 (left) D5
139 18 S3 (right) A2 TRIG
140 59 DIPSW8 A20
141 19 S4 (right) A3 CLKO
142 58 DIPSW7 A19
143 GND RST
144 20 S5 (right) A4
145 D4 36 S4 (left) D4
146 56 DIPSW6 A18
147 23 S6 (right) A5
148 VCCINT
149 55 DIPSW5 A17
150 VCCO
151 GND
152 24 BAR0 A6
153 54 DIPSW4 A16
154 25 BAR1 A7
155 53 DIPSW3 A15
156 D3 35 S3 (left) D3 TMS
157 27 BAR2 A8
158 GND
159 52 DIPSW2 A14
160 28 BAR3 A9
161 50 DIPSW1 A13
162 29 BAR4 A10
163 D2 34 S2 (left) D2 TDO
164 VCCINT
165 VCCO
166 GND
167 D1 33 S1 (left) D1 TDI
168 49 BAR6 A12
169 30 BAR5 A11
170 46 /CE
171 41 BAR9 RDY
172 GND
173 42 BAR7 /OE
174 SW1
175 SW2
176 SW3 SUSPND
177 D0/DIN 32 S0 (left) D0 DIN
178 BUSY/DOUT 6
179 CCLK 12 CCLK
180 VCCO
181 TDO 34 S2 (left) D2 TDO
182 GND
183 TDI 33 S1 (left) D1 TDI
184 /CS 8
185 /WR 7 SW4
186 /CE (left)
187 A9 (left)
188 A8 (left)
189 A7 (left)
190 GND
191 A6 (left)
192 A5 (left)
193 A4 (left)
194 A3 (left)
195 A2 (left)
196 GND
197 VCCO
198 VCCINT
199 A1 (left)
200 A0 (left)
201 /WE (left)
202 D0 (left)
203 D1 (left)
204 GND
205 D2 (left)
206 D3 (left)
207 D4 (left)
208 D5 (left)
209 D6 (left)
210 PGCK TxCLK
211 GND
212 VCCO
213 PGCK RxCLK
214 VCCINT
215 D7 (left)
216 D8 (left)
217 D9 (left)
218 D10 (left)
219 GND
220 D11 (left)
221 D12 (left)
222 D13 (left)
223 D14 (left)
224 D15 (left)
225 VCCINT
226 VCCO
227 GND
228 /OE (left)
229 A18 (left)
230 A17 (left)
231 A16 (left)
232 A15 (left)
233 GND
234 A14 (left)
235 A13 (left)
236 A12 (left)
237 A11 (left)
238 A10 (left)
239 TCK 4 TCK
240 VCCO
Connections Between the XC95108 CPLD and the Other XSV Board Components
Virtex Flash Video Parallel Serial Prog.
XC95108 CPLD FPGA LEDs Switches RAM Ethernet Decoder RAMDAC Codec RAM PS/2 USB Port Port Osc. Xchecker
1 /LEDS
2 CFG1
3 /RESET /RESET CE
4 239 TCK
5 VCCINT
6 178
7 185 SW4
8 184
9 123 /INIT
10 120 DONE
11 122 /PROGRAM
12 179 CCLK
13 60
14 58
15 62
16 132 S1 (right) A0 RT
17 133 S2 (right) A1 RD
18 139 S3 (right) A2 TRIG
19 141 S4 (right) A3 CLKO
20 144 S5 (right) A4
21 GND
22 PGCK 89 CLK CLKI
23 PGCK 147 S6 (right) A5
24 152 BAR0 A6
25 154 BAR1 A7
26 VCCO
27 PGCK 157 BAR2 A8
28 160 BAR3 A9
29 162 BAR4 A10
30 169 BAR5 A11
31 GND
32 177 S0 (left) D0 DIN
33 167 S1 (left) D1 TDI
34 163 S2 (left) D2 TDO
35 156 S3 (left) D3 TMS
36 145 S4 (left) D4
37 138 S5 (left) D5
38 VCCO
39 134 S6 (left) D6
40 124 S0 (right) D7
41 171 BAR9 RDY
42 173 BAR7 /OE
43 131 BAR8 /WE
44 GND
45 TDI C3
46 170 /CE
47 TMS C2
48 TCK C1
49 168 BAR6 A12
50 161 DIPSW1 A13
51 VCCO
52 159 DIPSW2 A14
53 155 DIPSW3 A15
54 153 DIPSW4 A16
55 149 DIPSW5 A17
56 146 DIPSW6 A18
57 VCCINT
58 142 DIPSW7 A19
59 140 DIPSW8 A20
60 S4
61 S5
62 GND
63 S7
64 S6
65 D7
66 D6
67 D5
68 D4
69 GND
70 D3
71 C3
72 D2
73 C2
74 D1
75 GND
76 S3
77 D0
78 C1
79 C0
80 RxD
81 TxD
82 RTS
83 TDO
84 GND
85 CTS
86 MF4
87 MF3
88 VCCO
89 MF2
90 MF1
91 MF0
92 FDE
93 CFG0
94 MDDIS
95 /LEDR
96 /LEDT
97 /LEDL
98 VCCINT
99 /LEDC
100 GND
%
;696FKHPDWLFV
The following pages show the detailed schematics for the XSV Board.

XSTE5 CSoC Board
XSTE5 The XSTE5 CSoC Board is perfect for experimenting with hardware/software
codesigns based on the Triscend TE505 Configurable System on a Chip (CSoC).
The TE505 CSoC combines an 8032 microcontroller core with 512 cells of
● Triscend TE505 CSoC
configurable system logic (CSL). You customize the CSL with a variety of soft
● 128 KByte SRAM
modules that act as peripherals for the 8032 while it executes your application
● 128 KByte Flash
code. The Triscend FastChip software helps you integrate 8032 application code
● 100 MHz programmable
from a variety of third-party development tools with Triscend's library of soft
oscillator
modules. Or you can build your own modules using Orcad or other tools which
● Parallel port
output an EDIF netlist.
● mouse/keyboard PS/2
port
● VGA monitor port
● 7-segment LED
● 8 position DIP switch
● 84-pin breadboard
interface
● 5V/3.3V regulators
● 9V DC power supply
The XSTE5 Board provides additional circuitry that speeds your development
process. Just connect the XSTE5 Board to the parallel port of a PC and you can
download your application code and soft modules to the TE505 CSoC directly from
the FastChip environment. Or you can store your design in the 128 KByte Flash
so it starts running whenever power is applied to the board. An additional 128
KBytes of SRAM is provided for running larger applications or for general-purpose
data storage. The programmable 100 MHz oscillator lets you select just the right
speed that balances your design's performance against its power consumption.
The FastChip software provides extensive in-circuit debugging features through

the cable attached to the XSTE5 Board. In addition, the 8-position DIP switch and
7-segment LED on the board let you input control signals directly to the TE505 and
observe the results for diagnostic purposes. Or connect a keyboard or mouse to
the PS/2 port for more extensive input capabilities, while graphical output can be
displayed on a monitor attached to the VGA port.
The TE505 CSoC will be used in a wide variety of systems and applications. The
XSTE5 Board makes it easy to connect to external systems through an 84-pin
breadboard interface that gives you access to all the general-purpose I/O of the
CSoC. The TE505 operates at 3.3V but is 5V-tolerant so you can connect it to a
wide variety of chips. The on-board regulators of the XSTE5 Board generate all
the voltages you need from a single 9V DC power input.
El archivo http://www.dacya.ucm.es/mendias/143/docs/xste5v10.pdf es un documento seguro que se ha incrustado en este
APS-V240 VIRTEX PC104 FPGA
DEVELOPMENT BOARD & KITS
Available with FPGA Devlopment Software and boilerplates
Powered By:
APS-V240-REVB_DATASHEET 02-1-2000_____ _________________________________ __1
Applications:
Dimensions: v Embedded Programmable Logic Board
3.8 x 3.6 x .6" (PC104 Stackable !) v Algorithm Testing
v Rapid Development Module
v Reconfigurable Processor
Features: v Custom DSP processing
ü 240 pin QFP FPGA
ü 3.3v IO/TTL compliant operation (3.3v on board reg.) The APS-V240 board can be ordered with the following
ü 2.5v core VIRTEX XCV50 to XCV800 or (2.5v reg.) FPGAs:
ü 256K x 18 ZBT SRAM OPTION
ü 1 9572XL CPLD in JTAG chain Virtex System Block Ram
ü XILINX 1800 series JTAG chained in circuit FPGA Gates Bytes
programmable EPROM's means FPGA configuration XCV50 57,906 4,096
is non-volatile. Eproms programmed right on board XCV100 108,904 5,120
using low cost Parallel Cable or JTAG port cable.
XCV150 164,674 6,144
ü Xchecker/JTAG Cable Port
XCV200 236,666 7,168
ü Real Time Programmable Direct Digital Synthesized
Clock module option (.5-30 MHz) (to 120Mhz w PLL) XCV300 322,970 8,192
ü On board Phase Lock Loop clock multiplier chip. XCV400 468,252 10,240
ü PC104 DMA / IRQ / IORW / MEMRW XCV600 661,111 12,288
ü 3 Oscillator Sockets XCV800 888,439 14,336
ü Up to 888,439 system gates (XCV800)
ü 166 available IO pins (-45 Sram, -50 ISA) Options:
ü Configured from Bus, Eprom, JTAG Cable Ø Real time programmable Direct Digital Synthesis
ü On Board 2 channel RS232 transceiver Clock (.5-30 MHz)
ü Wall transformer option ( to 120MHz using provided PLL chip )
ü ISA carrier board option Ø 256Kby 18 ZBT SRAM
ü RS-232 Transceiver and Com port connector with Ø PC104 to ISA Carrier Board
VHDL UART example included. Ø In-circuit programmable JTAG FPGA eprom
ü Stackable PC104 (ISA) format Ø 2.4 Amp Wall transformer
____________________________________________________________________________________________________________1
© Associated Professional Systems (APS) URL: http://www.associatedpro.com
3003 Latrobe Court Abingdon, MD 21009 USA email: X240@associatedpro.com
Voice: 410.569.5897 Fax: 888.709.8707
Powered By:
PRICING AND OPTIONS:
PRODUCT Price
APS-V240-XCV50 $575.00
APS-V240-XCV100 $630.00
APS-V240-XCV150 $670.00
APS-V240-XCV200 $710.00
APS-V240-XCV300 $790.00
APS-V240-XCV400 $900.00
APS-V240-XCV600 $1100.00
APS-V240-XCV800 $1400.00
OPTION: Direct Digital Synthesis Clock $99.00
(.5-30 MHz)
OPTION: 256Kby 18 ZBT SRAM Option $ 80.00
OPTION: PC104 to ISA Carrier Board $150.00
OPTION: 2.4 Amp Wall transformer $40.00
FPGA Required Cost

Prom(s)
XCV50 U14-Xc1801 $50.00
U16- NI
XCV100 U14-Xc1801 $50.00
U16-NI
XCV150 U14- NI $55.00
U16-Xc1802
XCV200 U14-NI $55.00
U16-1802
XCV300 U14-NI $55.00
U16-1802
XCV400 U14-NI $55.00
U16-1802
XCV600 U14-NI $60.00
U16-1804
XCV800 U14-1801 $60.00
U16-1804
____________________________________________________________________________________________________________2
Voice: 410.569.5897 Fax: 888.709.8707
Powered By:
note: CPLD ON BACK OF BOARD
____________________________________________________________________________________________________________3
Voice: 410.569.5897 Fax: 888.709.8707
Powered By:
Application Examples: Many different Examples are provided to allow the user to easily
step through and verify the programming and operation of the APS-V240 board. Two basic
modes are supported in the provided examples, although there can be many others modes
and variations of modes. The two basic modes provided in the examples are Stand-Alone,
and PC-104 ISA mode. Five basic examples are provided:
Real Time Programing CPLD image FPGA PROM

APPLICATION EXAMPLE Control Mode Mode Configuration
file
Stand-Alone LED None CPLD-JTAG CPLD_m1.JED v240_LED.mcs
(use to verify downloads) PROM-JTAG
FPGA-PROM
Stand-Alone Serial Port TX Rs232 TX only CPLD-JTAG CPLD_M1.JED Serial.mcs
PROM-JTAG
FPGA-PROM
Stand-Alone Serial TX/RX RS232 CPLD-JTAG CPLD_M1.JED VCOMSER.mcs
PROM-JTAG
FPGA-PROM
PC-104/ISA LED Blink ISA CPLD-JTAG CPLD_ISA.JED V_ISALED.mcs
PROM-NA
FPGA-ISA BUS
PC-104/ISA ZBT SRAM TEST ISA CPLD-JTAG CPLD_ISA.JED VISA_RAM.mcs
PROM-NA
FPGA-ISA BUS
____________________________________________________________________________________________________________4
Voice: 410.569.5897 Fax: 888.709.8707
Powered By:
Description:The APS-V240 card is a PC104

module with a large FPGA, optional 256K by 18 POS1 POS2 POS3 POS4 ADDR
ZBT SRAM, three oscillator sockets, on board MSB LSB
XC1800 series JTAG chained eproms, XC95144 ON ON ON ON 300h
CPLD, on board programmable Direct Digital ON ON ON OFF 310h
Synthsized (DDS) clock. Phase Lock Loop Clock ON ON OFF ON 320h
Multiplier chip .The board can use any of XILINX's ON ON OFF OFF 330h
VIRTEX FPGAs in the 240 pin QFP format. The ON OFF ON ON 340h
board gets its power from the ISA BUS or can use ON OFF ON OFF 350h
an off board transformer or power supply. The ON OFF OFF ON 360h
board is ideal for PC104 applications as well as ON OFF OFF OFF 370h
being an ideal platform for development and FPGA OFF ON ON ON 380h
code design. The board's small size makes it great OFF ON ON OFF 390h
for embedded designs where a powerful OFF ON OFF ON 3A0h
programmable logic device is required. User's can
OFF ON OFF OFF 3B0h
leverage off of the large number of PC104
OFF OFF ON ON 3C0h
controller and peripheral board options available for
the PC104 family. An ISA board carrier can be OFF OFF ON OFF 3D0h
purchased to allow the 104 card to be placed in a OFF OFF OFF ON 3E0h
standard PC chassis slot if desired. OFF OFF OFF OFF 3F0h
JP6 ISA FPGA CONFIGURATION PORT ADDRESS

PC104 FORMAT: The APS-V240 FPGA board SETTINGS
is in the PC-104 form factor. This form factor is the
PC ISA platform extended into an embedded The address used to strap the FPGA's download
format. Because we used this standard, the board address cannot be used by the FPGA's
can easily mate with tons of existing controller implemented core. Doing so could cause the FPGA
boards and peripheral boards. Since the PC104 to be reset or reprogrammed. The general idea is to
platform is just a reformatted ISA BUS, standard use the configuration address seting as the base IO
tools such as Microsoft C/C++ can be used to address and add additional addresses in the FPGA
develop control applications. APS also sells an ISA CODE as you require additional addresses.
optional PC ISA ADAPTER BOARD which allows Keep in mind that the Address straps do not get
the module to be used directly on a standard PC. ported to FPGA, so only the CPLD can read them.
Modules can be stacked and combined to facilitate
greater FPGA horsepower. The Test FPGA can access up to two interrupts.
(IRQA, and IRQB). The following table shows the
The APS-V240 FPGA board uses the CPLD to setup for IRQA
perform the decode of FPGA configuration over the
PC104/ISA BUS. The FPGA is downloaded using JP3 SETTING IRQA SELECTED
one IO address. The following table shows the JP4-1 to JP4-2 IRQ5
Addresses which the CPLD_ISA .JED image
JP4-3 to JP4-2 IRQ6
shipped with the board allows the V240
OFF No IRQ
configuration port to be mapped to:
JP5 SETTING IRQB SELECTED

JP6-1 to JP6-2 IRQ7
JP6-3 to JP6-2 IRQ10
OFF No IRQ
The APS-V240 can also use a DMA channel both

the DMA request and DMA Acknowledge must be
____________________________________________________________________________________________________________5
Voice: 410.569.5897 Fax: 888.709.8707
Powered By:
set. DMA request is set on JP2, while the The board can get power from the PC104 bus(5v),
acknowledge is set on JP4. or via a standalone wall transformer power
supply(5v).
JP2 SETTING DRQ SELECTED J5 is the JTAG port connector. The V240 can chain
JP3-1 to JP3-2 DRQ5 all the programmable devices , or can allow
JP3-3 to JP3-2 DRQ6 connection to each device separatly. The TMS and
OFF No DRQ TCLK lines are common to all devices. Be sure to
have the correct configuration option enabled when
compiling the FPGA. Set the configuration clock to
JTAG when configuring the FPGA clock directly,
and to CCLK when using the EPROM. When using
JP4 SETTING DACK SELECTED the EPROM it is not necessary to chain in the
FPGA, since the FPGA can boot right from the
JP5-1 to JP5-2 DACK5
newly configured EPROM.
JP5-3 to JP5-2 DACK6
OFF No DACK JTAG Port J5:
J5 Pin
The APS-V240 can use an on board serial EPROM
1 GND
as well as being downloaded from the PC104 BUS
2 CPLD_TDI
or XCHECKER CABLE. JP7 sets the DOWNLOAD
MODE. BE AWARE THAT THE CPLD CAN ALSO 3 CPLD_TDO
DRIVE THE MODE PINS. IT IS NOT 4 FPGA_TDO
RECCOMENDED TO USE THE JUMPERS TO 5 JTAG_TMS
SET THE FPGA MODE. RATHER USE THE CPLD 6 3.3V
TO SET THE MODE. 7 PROM_TDI
8 FPGA_TDI
JP7 SETTING MODE SELECTED 9 PROM_TDO
M0 M1 M2 10 JTAG_TCLK
0FF 0FF 0FF
ON OFF OFF
OFF ON OFF Oscillator and Clock Options: The APS-V240 has
several on board oscillator and clock options
ON ON OFF
available for use. The ISA BUS provides an 8.33
OFF OFF ON
MHz clock which is sent into the FPGA on pin 162.
ON OFF ON There are also internal FPGA oscillators which can
OFF ON ON be used and instantiated in your designs. For more
ON ON ON precise clocks, two oscillator sockets (U19, and
U20) are on board the V240 board which allow for
standard oscillators to be installed. The output pins
Four LEDs are available for utility use and for are connected to the primary global clock inputs.
FPGA status. JP2 can be strapped as follows: The oscillator socket runs on 5 Volts. The output of
U19 also goes to the CPLD Clock. The output of
LED JP1 Pos FPGA Purpose U20 goes to the same pin as the output of the DDS
Pin # module if installed. U20 and the DDS module
1 7-8 118 Utility should not be installed at the same time.
2 5-6 117 Utility
3 3-4 116 Utility DDS OPTION MODULE:
4 1-2 na FPGA DONE
FROM cpld The APS-DDS-1 module is a compact 24 pin
PIN 56 (standard 0.6 inch wide through hole)
programmable clock oscillator module based on the
____________________________________________________________________________________________________________6
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AD9850 Direct Digital Synthesizer. The APS-DDS

module also contains an on board oscillator, high
speed comparator, an on board LPF. In the
standard configuration, the oscillator is 100 Mhz,
and the LPF is at 42 Mhz. The output range with
this standard configuration is .5Mhz to 32 Mhz in
less than one hertz increments. All the
programming bits of the 9850 are available on the
module, although only the serial programming
mode is supported on the V240. There are a total of
40 programming bits. A 32 bit frequency word (4
bytes) and a fifth byte consisting of a 5 bit phase
word 2 control bits and a power down bit. (see the
APS-DDS1 data sheet for more details)
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IO CONNECTIONS: Besides the PC104

connectors, the APS-V240 has four 50 pin IO
connectors J1 through J4. The following tables
outline those six connectors:
J1 Pin # FPGA Pin Function J1 Pin # FPGA Pin Function

Number Number
1 100 IO 2 5V 5V
3 101 IO 4 3.3V 3.3V
5 102 IO 6 2.5V 2.5V
7 103 IO 8 GND GND
9 107 IO 10 GND GND
11 108 IO 12 GND GND
J1 IO Connectors (ODD PINS) J1 IO Connectors (EVEN PINS)
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J2 pin # FPGA Pin Function J2 Pin # FPGA Pin Function

Number Number
1 65 IO 2 5V 5V
3 66 IO 4 3.3V 3.3V
5 67 IO 6 2.5V 2.5V
7 68 IO 8 GND GND
9 70 IO 10 GND GND
11 71 IO 12 GND GND
13 72 IO 14 GND GND
15 73 IO 16 GND GND
17 74 IO 18 GND GND
19 78 IO 20 GND GND
21 79 IO 22 GND GND
23 80 IO 24 GND GND
25 81 IO 26 GND GND
27 82 IO 28 GND GND
29 84 IO 30 GND GND
31 85 IO 32 GND GND
33 86 IO 34 GND GND
35 87 IO 36 GND GND
37 92 IO 38 GND GND
39 93 IO 40 GND GND
41 94 IO 42 GND GND
43 95 IO 44 GND GND
45 96 IO 46 GND GND
47 97 IO 48 GND GND
49 99 IO 50 GND GND
____________________________________________________________________________________________________________9
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Number Number
1 157 IO 26 RS232_R1OUT RS232_R1OUT
2 5V 5V 27 89 FPGAGCLK1
3 155 IO 28 RS232_R2OUT RS232_R2OUT
4 3.3V 3.3V 29 185 IO AND SELECT
5 154 IO MAP WRITE
6 2.5V 2.5V 30 RS232_T1OUT RS232_T1OUT
7 153 IO 31 184 IO AND SELECT
MAP CHIP
8 GND GND SELECT LINE
9 152 IO 32 RS232_T2OUT RS232_T2OUT
10 CPLD Pin 28 CPLD_TDI 33 177 IO AND SELECT
11 149 IO MAP DO
12 PROM TDO PROM TDO 34 GND GND
14 JTAG_TMS JTAG_TMS MAP D1
16 JTAG_TCK JTAG_TCK 37 163 IO AND SELECT
MAP D2
17 144 IO
38 GND GND
18 RS232_TIN RS232_TIN
39 156 IO AND SELECT
19 142 IO MAP D3
20 RS232_T2IN RS232_T2IN 40 GND GND
22 RS232_R1IN RS232_R1IN MAP D4
23 (cpld pin 64) Cpld_spare1 42 GND GND
24 RS232_R2IN RS232_R2IN 43 138 IO AND SELECT
25 (cpld pin 2) Cpld_Spare2 MAP D5
44 GND GND
J3 IO Connectors (1-25) 45 134 IO AND SELECT
MAP D6
46 GND GND
MAP D7
48 GND GND
MAP BUSY
50 GND GND
J3 IO Connectors (25-50)
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J4 is connected to the ZBT SRAM pins. If the

SRAM is not installed these pins can also be used
for additional IO pins.

Number Number
1 223 SRAM A9 2 5V 5V
3 224 SRAM A8 4 3.3V 3.3V
5 208 SRAM LD 6 2.5V 2.5V
7 207 SRAM OE 8 GND GND
9 206 SRAMRW 10 209 SRAMA17
11 205 SRAMCLK 12 188 SRAMDP0
13 203 SRAMBWS0 14 187 SRAMDQ7
15 202 SRAMBWS1 16 186 SRAMDQ6
17 170 SRAMCE2 18 160 SRAMDQ5
19 228 SRAMA7 20 159 SRAMDQ4
21 229 SRAMA6 22 215 SRAMA16
23 189 SRAMDQ8 24 216 SRAMA15
25 191 SRAMDQ9 26 217 SRAMA14
27 192 SRAMDQ10 28 218 SRAMA13
29 193 SRAMDQ11 30 220 SRAMA12
31 194 SRAMDQ12 32 221 SRAMA11
33 195 SRAMDQ13 34 222 SRAMA10
35 199 SRAMDQ14 36 235 SRAMA0
37 200 SRAMDQ15 38 236 SRAMA1
39 201 SRAMDQ16 40 234 SRAMA2
41 171 SRAMDQ0 42 232 SRAMA3
43 173 SRAMDQ1 44 231 SRAMA4
45 174 SRAMDQ2 46 230 SRAMA5
47 175 SRAMDQ3 48 237 SRAMmode
49 174 SRAM ZZ 50 nc
____________________________________________________________________________________________________________ 11
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The PC104 Connectors and associated

connections are shown:
J7(Row A) FPGA Pin Function J8(Row B) FPGA Pin Function

Number Number
1 - 1 - GND
2 10 D7 2 -
3 9 D6 3 - 5V
4 7 D5 4 -
5 6 D4 5 -
6 5 D3 6 -
7 4 D2 7 -
8 3 D1 8 -
9 238 D0 9 -
10 - - 10 -
11 23 AEN 11 53 *MEMW
12 - - 12 54 *MEMR
13 - - 13 52 *IOW
14 - - 14 50 *IOR
15 - - 15 -
16 24 A15 16 -
17 25 A14 17 -
18 26 A13 18 -
19 27 A12 19 -
20 28 A11 20 162 SYSCLK
21 31 A10 21 46 IRQ7
22 33 A9 22 57 IRQ6
23 34 A8 23 57 IRQ5
24 35 A7 24 -
25 36 A6 25 -
26 38 A5 26 -
27 39 A4 27 48 TC
28 40 A3 28 49 BALE
29 41 A2 29 - 5V
30 42 A1 30 -
31 47 A0 31 - GND
32 - GND 32 - GND
J7 PC104 ROW A J8 PC104 ROW B
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J9(Row C) FPGA Pin Function

Number ZBT SRAM: The V240 board can be ordered
0 - GND with an optional 256K by 16 ZBT SRAM.
1 -
2 - Development Software: The APS-V240 is
3 - also available with the best selling XILINX
4 - Foundation Software Packages which include
5 - schematic capture, HDL (Verilog, VHDL) and
6 - internet enabled router and project manager. The
7 - software also comes with HDL simulator demos
8 - and an HDL tutorial for new HDL users.
9 -
10 -
11 11 D8
12 12 D9
13 13 D10
14 17 D11
15 18 D12
16 19 D13
17 20 D14
18 21 D15
19 - -
J9 PC104 ROW C
J10(Row D) FPGA Pin Function

Number
0 -
1 56 *MEMCS16
2 55 *IOCS16
3 46 IRQ10
4 --
5 -
6 -
7 -
8 -
9 -
10 63 DACK5
11 64 DRQ5
12 63 DACK6
13 64 DRQ6
14 - -
15 - -
16 - 5V
17 - -
18 - GND
19 - GND
J10 PC104 ROW D
____________________________________________________________________________________________________________ 13
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____________________________________________________________________________________________________________ 14
Voice: 410.569.5897 Fax: 888.709.8707
A B C D E
APS
Associated Professional Systems
4 3003 Latrobe Court Abingdon, Maryland 21009 4
Voice: 410.569.5897 Fax 888.709.8707 Email aps@apsfpga.com

Website: http://www.associatedpro.com
TABLE OF CONTENTS
PAGE DESCRIPTION
1 COVER PAGE (this page)

2 CPLD PAGE XC9572XL
3 FPGA Page (XILINX VIRTEX 240 pin Quad Flat Pack)
4 EPROM PAGE (XILINX 18xx ISP JTAG PROGRAMMABLE)
5 PC104 ISA Connectors
3 6 Clock Circuits (pericom P16C918 PLL, ASP-DDS, EPSON SG-531P Oscillators 3
7 POWER (MIC29150-3.3BU and MIC39150-2.5BU Regulators, Power Connectors)
8 RS232 Transceiver (MAXIM 3223)
9 SRAM (MICRON MT55L256L18P ZBT SRAM)
10 CONNECTORS-J1, J2, J3, J4(50pin) DRQ/DACK, IRQ, LED, JTAG
INSTRUCTIONS
INSTRUCT # DESCRIPTION
1 ORCAD Release 9 was used for this Schematic

2 All bypass caps should be as close to VCC pins as possible
3 All components should have silkscreen refs (U2, C12, R11, JP2, etc)
4 If possible please include APS logo shown above on silk screen, or use a Times Roman BOLD italic font.
2 2
5 If SILKCREEN Labels are called out on schematics please try to place them on board
6 Place silkscreen "1" to mark pin one on all multi pin components
7 Unless otherwise specified all Rs are 805 and C sizes are 1206's
1 1
Title
APS-V240 PC104 XILINX FPGA DEVELOPMENT BOARD
Size Document Number Rev

A APS-V240 A
Date: Tuesday, October 12, 1999 Sheet 1 of 10

A B C D E
A B C D E
PROM1_RESET_OUT
TO CLOCK PAGE PLL PLL_OE
PLL_SEL1
PLL_SEL0
CPLD_TDO
4 3.3VOLTS 4
DONE_LED
DDS_WCLK
TO CLOCK PAGE DDS DDS_FQUD
DDS_RESET
DDS_DATA
D7
TO/FROM PC104 ISA BUS D6 3.3VOLTS
D5
CPLD_SPARE1
R8 10K
R9 27K
R10 10K JP6
3.3VOLTS
R11 27K 1 2
R12 10K 3 4
3.3VOLTS 5 6
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
U21 R13 27K 7 8
R14 10K ADDRESS
GND
TDO
VCCIO
FB2_8
FB2_6
FB2_5
FB2_2
FB2_4
FB2_3
FB4_6
FB4_17
FB4_15
FB4_12
FB4_10
FB4_14
FB2_9 GSR
3.3VOLTS
3 3
D0 1 48 DIN
FB2_10 FB4_11
CPLD_SPARE2 2 47
FB2_11 gts2 FB4_4 CCLK
3 46 DONE
3.3VOLTS VCCINT FB4_3
D2 4 45 INIT
FB2_12 FB4_8
PROM2_RESET_OUT 5 44 PROG
FB2_14 gts1 FB4_5
D4 6 43
FB2_15 FB4_2
A0 7 42
TO/FROM PC104 ISA BUS FB2_17 XC9572XL CPLD FB3_16
A1 8 41
FB1_2 GND
A2 9 40
FB1_5 FB3_12
A3 10 39
FB1_6 FB3_10
A4 11 38 AEN
FB1_8 FB3_17
A5 12 37 3.3VOLTS
FB1_3 VCCINT
13 36 D1
A6 FB1_4 FB3_15
14 35 D3
GND FB3_14
IOW 15 34 OSC_OE_2
FB1_9 gclk1 FB3_6
IOR 16 33 OSC_OE_1
FB1_11 gclk2 FB3_11
FB1_14 gclk3
FB1_10
FB1_15
FB1_17
FB1_12
VCCIO
FB3_2
FB3_5
FB3_8
FB3_9
FB3_3
FB3_4
GND
2 2
TMS
TCK
TDI
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
M0
PROM_CLK
JTAG_TCK TO JTAG PORT
JTAG_TMS
3.3VOLTS
CPLD_TDI
M1
3.3VOLTS
C7 C8 C9 C10 C11 C12 C13 C14
M2 TO AND FROM EEPROMS
.01uf .01uf .01uf .01uf .01uf .01uf .01uf .01uf
PROM_DATA
CPLD BYPASS PROM_OE
PROM_CE
CAPS
A9
A8
A7
CPLD_CLK
1 1
Title
APS-V240 VIRTEX PC104 FPGA BOARD

B APS-V1 A

A B C D E
A B C D E
3.3VOLTS
FPGAGCLK3
FPGAGCLK2
C17 C18 C19 C20 C21 C22 C23 C24
3.3VOLTS
FPGAP184
FPGAP185
SramBWS0
SramDQ15
SramDQ13
SramDQ11
SramDQ14
SramDQ12
SramDQ10
SramBWS1
SramDP0
FPGA_TDO
FPGA_TDI
SramDQ9
SramDQ8
SramDQ7
SramDQ6
SramMODE
3.3VOLT S
2.5VOLT S
2.5VOLT S
2.5VOLT S
JTAG_TCK
3.3VOLTS
3.3VOLTS
SramA12
SramA13
SramA16
SramA10
SramA11
SramA14
SramA15
SramA17
SramDQ16
Sram/OE
SramCLK
SramRW
SramA0
SramA5
SramA7
SramA1
SramA2
SramA3
SramA4
SramA6
SramA8
SramLD
SramA9
FPGA BYPASS
CAPS
D0
4 4
2.5VOLTS
240
239
238
237
236
235
234
233
232
231
230
229
228
227
226
225
224
223
222
221
220
219
218
217
216
215
214
213
212
211
210
209
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
C25 C26 C27 C28 C29 C30 C31 C32
GND
GND
GND
GND
GND
GND
GND
GND
CS
TDO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
TCK
VCCO
VCCO
VCCO
VCCO
VCCINT
VCCINT
VCCINT
TDI
GCLK3
GCLK2
VREFB0
VREFB0
VREFB0
VREFB0
VREFB0
VREFB0
VREFB0
VREFB1
VREFB1
VREFB1
VREFB1
VREFB1
VREFB1
VREFB1
WRITE
1 180 FPGA BYPASS

GND VCCO 3.3VOLTS
JTAG_TMS 2 179 CCLK
CAPS
TMS CCLK
3 178 FPGAP178
D1 IO BUSY/DOUT
4 177 DIN
D2 IO D0/DIN
5 176
D3 VREFB7 IO SramDQ3
6 175
D4 IO VREFB2 SramDQ2
7 174
D5 IO IO SramZZ
8 173
GND IO SramDQ1
9 172
D6 VREFB9 GND
10 171
D7 IO VREFB2 SramDQ0
11 170 SramCE2
D8 VREFB7 IO
12 169 RS232_T1IN
D9 VREFB7 VREFB2
13 168 RS232_T2IN
D10 IO VREFB2
14 167 FPGAP167
GND D1
3.3VOLTS 15 166
VCCO GND
2.5VOLTS 16 165 3.3VOLTS
VCCINT VCCO
17 164 2.5VOLTS
D11 IO VCCINT
3 18 163 FPGAP163 3
D12 IO D2
19 162
D13 VREFB7 IO SYSCLK
D14 20 161 PLL_IN
IO VREFB2
D15 21 160
IO IO SramDQ5
22 159
AEN GND U22 IO SramDQ4
23 158
A15 VREFB7 GND
24 157 RS232_R1OUT
A14 IO XILINX VIRTEX 240 QFP FPGA VREFB2
25 156 FPGAP156
A13 IO D3
26 155 RS232_R2OUT
A12 VREFB7 IO
27 154 FPGAP154
A11 IO VREFB2
28 153 FPGAP153
IO IO
29 152 FPGAP152
GND IO
3.3VOLTS 30 151
A10 VCCO GND
31 150 3.3VOLTS
IO VCCO
2.5VOLTS 32 149 FPGAP149
A9 VCCINT IO
33 148 2.5VOLTS
A8 VREFB6 VCCINT
34 147 FPGAP147
A7 IO VREFB3
35 146 FPGAP146
IO IO
36 145 FPGAP145
A6 IO D4
37 144 FPGAP144
GND VREFB3
38 143
A5 IO GND
39 142 FPGAP142
A4 IO IO
40 141 FPGAP141
A3 VREFB6 IO
41 140 FPGAP140
A2 IO VREFB3
2 42 139 FPGAP139 2
A1 IO IO
2.5VOLTS 43 138 FPGAP138
VCCINT D5
3.3VOLTS 44 137 2.5VOLTS
VCCO VCCINT
45 136 3.3VOLTS
GND VCCO
46 135
IRQ_B IO GND
47 134 FPGAP134
A0 VREFB6 D6
48 133 FPGAP133
TC VREFB6 VREFB3
49 132 FPGAP132
BALE IO VREFB3
50 131 FPGAP131
IOR VREFB6 IO
51 130 FPGAP130
GND VREFB3
52 129
IOW IO GND
53 128 FPGAP128
MEMW IO IO
54 127 FPGAP127
MEMR VREFB6 IO
55 126 FPGAP126
IOCS16 IO VREFB3
56 125 FPGAP125
MEMCS16 IO IO
57 124 FPGAP124
R20 IRQ_A IO D7
58 123 INIT
M1 INIT
59 122 PROG
R21 GND PROGRAM
60 121 3.3VOLTS
3.3VOLTS M0 VCCO
3.3VOLTS
VREFB5
VREFB5
VREFB6
VREFB5
VREFB5
VREFB5
VREFB4
VREFB4
VREFB4
VREFB4
VREFB4
VREFB4
VCCINT
VCCINT
VCCINT
4.7K
VREFB
VREFB
GCLK1
GCLK0
VCCO
VCCO
VCCO
VCCO
DONE
GND
GND
GND
GND
GND
GND
GND
GND
3.3VOLTS 4.7K
M2
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
M0
1 R22 1
M1
JP7 DONE
4.7K
1 2
3.3VOLT S
3.3VOLT S
3.3VOLT S
2.5VOLTS
2.5VOLTS
2.5VOLTS
3.3VOLTS
FPGAP100
FPGAP102
FPGAP107
FPGAP109
FPGAP110
FPGAP114
FPGAP115
FPGAP117
FPGAP101
FPGAP103
FPGAP108
FPGAP111
FPGAP113
FPGAP116
FPGAP118
FPGAP66
FPGAP68
FPGAP71
FPGAP73
FPGAP74
FPGAP78
FPGAP79
FPGAP81
FPGAP84
FPGAP86
FPGAP93
FPGAP94
FPGAP96
FPGAP99
Silkscreen
FPGAGCLK1
FPGAP65
FPGAP67
FPGAP70
FPGAP72
FPGAP80
FPGAP82
FPGAP85
FPGAP87
FPGAP92
FPGAP95
FPGAP97
DRQ
3 4
Label JP7 5 6 Title
"FPGA MODE" FPGA MODE STRAP APS-V240 VIRTEX PC104 FPGA BOARD

M2 DACK B APS-V1 1B

A B C D E
A B C D E
PROM1_RESET_OUT
EEPROMs
JTAG_TCK
PROM_TDI
JTAG_TMS
4 4
PROM_TDO
3.3VOLTS
C15
.01uf
20
19
U14
3
2
1
D2
D0
VCC
CLK
VCCO
PLACE RESISTOR
4 18 R15 WHEN 1801 NOT
TDI VCC 0
5 17 INSTALLED
R17 TMS TDO
6 16
R16 TCK D1
7 15 XC1804TDO
0 0 D4 D3
8 14
RESET/OE D5
XC1804TDO
GND
CEO
/CE
D6
D7
3 3
10
11
12
13
9
XC1801PC20
For XCV50,XCV100,XCV150 install U14,

R14 DO NOT INSTALL U16, R15, R16,
3.3VOLTS
FOR XCV200,300,400,600 INSTALL

U16 R15, DO NOT INSTALL R16, R18 3.3VOLTS
R17, U14 4.7K
U16 R19
44
43
42
41
40
39
38
37
36
35
34
FOR XCV800 INSTALL U14 U12 4.7K

R16, DO NOT INSTALL R17,
NC
NC
NC
NC
GND
D2
D0
VCC
VCC
CLK
VCCO
R15 1 33
NC NC
2 32
NC NC
3 31 XC1804TDO
TDI TD0
4 30 PROM_DATA
XCV50 U14=1801 U16-NI XCV100 nc NC
5 29 PROM_CLK
TMS D1
U14=1801 U16=NI XCV150 U14=1801 6 28 PROM_CE
GND GND
U16=NI XCV200 U14=NI U16=1802 7 27 PROM_OE
TCK D3
XCV300 U16=NI U14=1802 XCV400 8 26
VCCO VCC0
2 9 25 2
D4 D5
RESET/OE
U14=NI U16=1804 XCV600 U14=NI

10 24 PROM2_RESET_OUT
U16=1804 XCV800 U14=1801 NC NC
11 23
NC NC
VCCO
U16=1804
GND
CEO
VCC
/CE
NC
NC
NC
D6
D7
xc1804vq44 R24 R25 R26

12
13
14
15
16
17
18
19
20
21
22
10K 10K 10K
3.3VOLTS
1 C16 1
.01uf
Title

B APS-V1 1B

A B C D E
A B C D E
J6 J7
0
0
1 0
D7 IOCHCHK* na
2 1
4
D6 SD7 0V 4
3 2
D5 SD6 RESETDRV
4 3
D4 SD5 +5V 5v
5 4
D3 SD4 IRQ9
6 5
D2 SD3 -5V
7 6
D1 SD2 DRQ2 J9
8 7
D0 SD1 -12V J8
9 8
SD0 ENDXFER*
10 9 0 0
AEN IOCHRDY +12V 0V 0V
11 10 1 1 MEMCS16
AEN KEY SBHE* MEMCS16*
12 11 MEMW 2 2 IOCS16
SA19 SMEMW* LA23 IOCS16*
13 12 MEMR 3 3 IRQ10
SA18 SMEMR* LA22 IRQ10
14 13 IOW 4 4
SA17 IOW* LA21 IRQ11
15 14 IOR 5 5
A15 SA16 IOR* LA20 IRQ12
16 15 6 6
A14 SA15 DACK3* LA19 IRQ15
17 16 7 7
A13 SA14 DRQ3 LA18 IRQ14
18 17 8 8
A12 SA13 DACK1* LA17 DACK0*
19 18 9 9
A11 SA12 DRQ1 MEMR* DRQ0
3 20 19 10 10 DACK5
3
A10 SA11 REFRESH/KEY D8 MEMW* DACK5*
21 20 SYSCLK 11 11 DRQ5
A9 SA10 SYSCLK D9 SD8 DRQ5
22 21 IRQ7 12 12 DACK6
A8 SA9 IRQ7 D10 SD9 DACK6*
23 22 IRQ6 13 13 DRQ6
A7 SA8 IRQ6 D11 SD10 DRQ6
24 23 IRQ5 14 14
A6 SA7 IRQ5 D12 SD11 DACK7*
25 24 15 15
A5 SA6 IRQ4 D13 SD12 DRQ7
26 25 16 16
A4 SA5 IRQ3 D14 SD13 +5V 5v
27 26 17 17
A3 SA4 DACK2* D15 SD14 MASTER
28 27 TC 18 18
A2 SA3 TC SD15 0V
29 28 BALE 19 19
A1 SA2 BALE KEY 0V
30 29
A0 SA1 +5V 5v
31 30
SA0 OSC PC104_RC PC104_RD
32 31
0V 0V
32
0V
PC104_RA PC104_RB
2 2
LONG CONNECTOR
1 1
Title

A APS-V1 A

A B C D E
A B C D E
C1
U17 .01uf
1 8 FROM CPLD
PLL_OE OE VCC 3.3VOLTS
2 7 PLL_SEL1
X1 SEL1
3 6 PLL_SEL0
FROM CPLD X2 SEL0
4 5
4 GND CLKOUT FPGAGCLK0 4
R1 0 C2
PERICOM P16C918 CLOCK PHASE LOCK LOOP 0
MULTIPLIER
PLL_IN
TO FPGA
FPGAGCLK3
5VOLTS
14
19
U18
AVDD
DVCC
3 1 3
D0
2
D1
3
D2 TO FPGA
4 15
D3 QOUT
5 18 FPGAGCLK1
D4 QOUTB
6
D5
7
D6 APS-DDS-1
DDS_DATA 8
D7
DDS_RESET 9
RESET SINE
16 OSCILLATOR SOCKETS TO CPLD GCK3
DDS_FQUD 12 CPLD_CLK
FQUD
DDS_WCLK 17
WCLK U19
FROM CPLD 13 1 8
NC OSC_OE_1 OE VDD 5v
R2
0 TO FPGA
DGND
DGND
DGND
DGND
DGND
AGND
4 5
GND OUT FPGAGCLK2
11
2 OSC SG-531P
2
5v
10
21
22
23
24
20
SHORT (8PIN) THROUGH HOLE SOCKET
DIRECT DIGITAL U20 C4 C5

SYNTHESIS OSC_OE_2 1
OE VDD
8
5v
.01uf .01uf
MODULE R3
0 TO FPGA
4 5 FPGAGCLK1
GND OUT
SG-531P
use dds or this osc socket
1 1
Title

A APS-V1 A

A B C D E
A B C D E
TO263 PACKAGE
4 4
MIC29150-3.3V REGULATOR
5v
1 3 3.3VOLTS
VIN 3.3VOUT
C33
GND
10uf
U23
2
C34
10uf
3 3
TO263 PACKAGE
MIC29150-2.5V REGULATOR
5v
1 3 2.5VOLTS
VIN 2.5VOUT
C35
GND 10uf
U24
2
C36
10uf
2 2
SILK SCREEN LABEL Keep GND and GND Power tie in
J10 "5V DC"

DC POWER 3.5 mm
PLACE JP8 POWER HEADER WHICH -- IS
A RIGHT ANGLE 2 PIN HEADER- RIGHT
NEXT TO THE J10 POWER CONNECTOR
5v 5VOLTS
J10
5v JP8
1
1 5v 2
1
2 3 1
DC POWER
Title
POWER HEADER APS-V240 VIRTEX PC104 FPGA BOARD

A APS-V1 1B

A B C D E
A B C D E
3.3VOLTS
4 4
+ C37
.01uF
19
U25
+ C38 2
VCC
.1uf C1+
4 3
C1- V+
5 7 + C39
C2+ V- 0.1uf
6
+ C40 C2- C41
+
0.1uf
0.1uf
3
RS232_T1IN 13 17 RS232_T1OUT
3
T1in T1Out
TO FPGA 12 8
RS232_T2IN T2in T2Out RS232_T2OUT
RS232_R1OUT 15 16 RS232_R1IN
R1out R1in
TO FPGA 10 9
RS232_R2OUT R2out R2in RS232_R2IN
1 11
/en InvalidOut
GND
14 20 3.3VOLTS
forceon forceoff
max3223
18
2 2
1 1
Title

A APS-V1 <RevCode>

A B C D E
A B C D E
3.3VOLTS
C42 C43 C44 C45

SRAM DNU is Do Not .01uf .01uf .01uf .01uf
use. Data sheet says SRAM Bypass
to not connect or to Caps
4 ground these pins. 4
SramDNU
R23
SramDQ2
0
3.3VOLTS
3.3VOLTS
3.3VOLTS
3.3VOLTS
3.3VOLTS
3.3VOLTS
SramA17
SramDP0
SramDQ5
SramDQ4
SramDQ1
SramDQ0
SramZZ
SramDQ7
SramDQ6
SramDQ3
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS
VSS
VSS
VSS
VSS
A17
DP0
VDD
VDD
NC
NC
NC
NC
NC
NC
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
ZZ
SramA9 81 50 SramA16
A9 A16
SramA8 82 49 SramA15
A8 A15
3 83 48 SramA14
3
NC A14
84 47 SramA13
NC A13
SramLD 85 46 SramA12
ADV/*LD A12
Sram/OE 86 45 SramA11
/OE A11
87 44 SramA10
/CEN U26 A10
SramRW 88 43 SramDNU
R/W DNU
SramCLK 89 42 SramDNU
CLK MT55L256L18P DNU
90 41 3.3VOLTS
VSS VDD
91 40
3.3VOLTS VDD VSS
92 39 SramDNU
/CE2 DNU
SramBWS0 93 38 SramDNU
/BWS0 DNU
SramBWS1 94 37 SramA0
/BWS1 A0
95 36 SramA1
NC A1
96 35 SramA2
NC A2
SramCE2 97 34 SramA3
CE2 A3
98 33 SramA4
/CE1 A4
SramA7 99 32 SramA5
A7 A5
SramA6 100 31 SramMODE
2 A6 MODE 2
VDDQ
VDDQ
VDDQ
VDDQ
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
VDD
VDD
VDD
DQ8
DQ9
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
3
4
5
6
7
8
9
3.3VOLTS
3.3VOLTS
3.3VOLTS
3.3VOLTS
3.3VOLTS
3.3VOLTS
3.3VOLTS
SramDQ10
SramDQ11
SramDQ14
SramDQ15
SramDQ16
SramDQ12
SramDQ13
SramDQ8
SramDQ9
1 1
Title

A APS-V1 1B

A B C D E
A B C D E
SRAM FPGA LINES

TOP OF CARD RIGHT SIDE OF CARD LEFT SIDE OF CARD
INSIDE
J3 J1 J2 J4
FPGAP157 1 2 5v 1 2 5v 1 2 5v SramA9 1 2 5v
1 2 FPGAP100 1 2 FPGAP65 1 2 1 2
FPGAP155 3 4 3.3VOLTS 3 4 3.3VOLTS 3 4 3.3VOLTS SramA8 3 4 3.3VOLTS
3 4 FPGAP101 3 4 FPGAP66 3 4 3 4
FPGAP154 5 6 2.5VOLTS 5 6 2.5VOLTS 5 6 2.5VOLTS SramLD 5 6 2.5VOLTS
5 6 FPGAP102 5 6 FPGAP67 5 6 5 6
FPGAP153 7 8 7 8 7 8 Sram/OE 7 8
7 8 FPGAP103 7 8 FPGAP68 7 8 7 8
FPGAP152 9 10 CPLD_TDI FPGAP107 9 10 9 10 SramRW 9 10
4 9 10 9 10 FPGAP70 9 10 9 10 SramA17 4
FPGAP149 11 12 PROM_TDO FPGAP108 11 12 11 12 SramCLK 11 12
11 12 11 12 FPGAP71 11 12 11 12 SramDP0
FPGAP147 13 14 FPGAP109 13 14 13 14 SramBWS0 13 14
13 14 JTAG_TMS 13 14 FPGAP72 13 14 13 14 SramDQ7
FPGAP146 15 16 JTAG_TCK FPGAP110 15 16 15 16 SramBWS1 15 16
15 16 15 16 FPGAP73 15 16 15 16 SramDQ6
FPGAP144 17 18 RS232_T1IN FPGAP111 17 18 17 18 SramCE2 17 18
17 18 17 18 FPGAP74 17 18 17 18 SramDQ5
FPGAP142 19 20 RS232_T2IN 19 20 19 20 SramA7 19 20
19 20 FPGAP113 19 20 FPGAP78 19 20 19 20 SramDQ4
FPGAP141 21 22 RS232_R1IN 21 22 21 22 SramA6 21 22 SramA16
21 22 FPGAP114 21 22 FPGAP79 21 22 21 22
23 24 23 24 23 24 23 24
Select Map CPLD_SPARE1 25
23 24
26
RS232_R2IN FPGAP115
25
23 24
26
FPGAP80
25
23 24
26
SramDQ8
25
23 24
26
SramA15
CPLD_SPARE2 25 26 RS232_R1OUT FPGAP116 25 26 FPGAP81 25 26 SramDQ9 25 26 SramA14
Lines FPGAGCLK1 27 28 RS232_R2OUT 27 28 27 28 27 28 SramA13
27 28 FPGAP117 27 28 FPGAP82 27 28 SramDQ10 27 28
29 30 29 30 29 30 29 30
SM Wr FPGAP185 31
29 30
32
RS232_T1OUT FPGAP118
31
29 30
32
FPGAP84
31
29 30
32
SramDQ11
31
29 30
32
SramA12
SM CS FPGAP184 33
31 32
34
RS232_T2OUT FPGAP125
33
31 32
34 FPGAP85 33
31 32
34 SramDQ12 33
31 32
34
SramA11
SM D0 FPGAP177 35
33 34
36
FPGAP126
35
33 34
36
FPGAP86
35
33 34
36
SramDQ13
35
33 34
36
SramA10
SM D1 FPGAP167 37
35 36
38
FPGAP127
37
35 36
38
FPGAP87
37
35 36
38
SramDQ14
37
35 36
38
SramA0
SM D2 FPGAP163 39
37 38
40
FPGAP128
39
37 38
40
FPGAP92
39
37 38
40
SramDQ15
39
37 38
40
SramA1
SM D3 FPGAP156 41
39 40
42
FPGAP130
41
39 40
42
FPGAP93
41
39 40
42
SramDQ16
41
39 40
42
SramA2
SM D4 FPGAP145 43
41 42
44 FPGAP131 43
41 42
44 FPGAP94 43
41 42
44 SramDQ0 43
41 42
44
SramA3
SM D5 FPGAP138 45
43 44
46
FPGAP132
45
43 44
46
FPGAP95
45
43 44
46
SramDQ1
45
43 44
46
SramA4
SM D6 FPGAP134 47
45 46
48
FPGAP133
47
45 46
48
FPGAP96
47
45 46
48
SramDQ2
47
45 46
48
SramA5
SM D7 FPGAP124 47 48 FPGAP139 47 48 FPGAP97 47 48 SramDQ3 47 48 SramMODE
49 50 FPGAP140 49 50 49 50 49 50
BUSY FPGAP178 49 50 49 50 FPGAP99 49 50 SramZZ 49 50
3
50PIN_CONN 50PIN_CONN 50PIN_CONN 50PIN_CONN 3
IRQ Silkscreen Label

Silkscreen Label LED HEADER
JP2"LEDs"
Rs232 Serial D9 Ribbon Connector
JP3 JP3 IRQ5 "IRQ JP1

1 DONE_LED 1 2
J11
2 IRQ_A
IRQ6
A" FPGAP116 3 4
1 2 3 FPGAP117 5 6
RS232_R1IN 3 4 RS232_T2OUT FPGAP118 7 8
RS232_T1OUT 5 6 RS232_R2IN
INT A LEDs
7 8
9 10 Silkscreen Label D1 D2 D3 D4
CON10A
JP5IRQ7 LED LED LED LED
JP5
1 "IRQ
2 IRQ_B
2
3 IRQ10 B" 2
R4 R5 R6 R7
INT B 150 150 150 150
JP2 Silkscreen Label

JP2 DRQ5 "DRQ"
JTAG PORT Silkscreen Label 1
2 DRQ
J5 3 DRQ6
J5
"JTAG"
1 10 JTAG_TCK
DRQ
Silkscreen Label
CPLD_TDI 2 9 PROM_TDO
JP4
JP4
CPLD_TDO 3 8 FPGA_TDI
1 FPGA_TDO 4 7 PROM_TDI 1 DACK5 "DACK" 1
JTAG_TMS 5 6 3.3VOLTS 2 DACK
3 DACK6
JTAG CONNECTOR
DACK
Title

B APS-V1 A

A B C D E
Teclado numérico
Componentes: La placa dispone de un teclado matricial numérico 4x4 con una fila
adicional de 4 pulsadores dispuestos como cursores.
● Keypad 4x4
● 4 pulsadores
Conectores:
(izq. a der. según la foto)
● alimentación
● tierra
● código de retorno (4 bits)
● código de scan (5 bits)
● AND del código de scan
1 2 3 4
D D
8
Vcc JP1
C0 C1 C2 C3 1
2
Vcc 1
R0 3
4
2
1
R1 5
6
3
R2 7
C
8
4
R3 9
10
PAD1
11
KEYPAD_16
C 12 C
HEADER 12
8
AR1 S1
10K
U1A S2 S3
1 C4
3
2
U1C S4
74F08 9
8 nINT
10
U1B 74F08
4
6
5
B B
74F08
U1D
12
A
11
Y
13
B
7
GND
74F08
14
VCC
Vcc C1
100nF
Title
A Keypad Board A
Size Number Revision

A4
Date: 15-Jan-2002 Sheet of
File: C:\Documents and Settings\Administrador\Escritorio\UCM.ddb
Drawn By:
1 2 3 4
Banco de displays 7-segmentos
Componentes: La placa dispone de 8 displays 7 segmentos multiplexados (con las

líneas de datos comunes). Tanto el código de selección de display
● 2 bancos de displays 7 como el código 7 segmentos utilizan lógica directa.
segmentos de cátodo
común
Conectores:
● selección (3 bits)
● código 7-segs (dp, g..a)
● tierra
● alimentación
1 2 3 4
D D
DISP2 DISP1
7SEG_4DISP Catodo Común RP2 7SEG_4DISP Catodo Común RP1
a 1 1 16 A a 1 1 16 A
b 2 2 15 B b 2 2 15 B
a a a a a a a a
c 3 3 14 C c 3 3 14 C
f b f b f b f b d 4 4 13 D f b f b f b f b d 4 4 13 D
g g g g g g g g
e 5 5 12 E e 5 5 12 E
e c e c e c e c 6 6 11 F e c e c e c e c 6 6 11 F
C d d d d f d d d d f C
7 7 10 G 7 7 10 G
dp dp dp dp g dp dp dp dp g
dp 8 8 9 DP dp 8 8 9 DP
4 3 2 1 4 3 2 1
470 470
JP1
9
9
12
11
10
12
11
10
Vdd HEADER 13
1
2
A
3
B
4
C
5
D
6
10
11
12
13
14
15
E
7
9
7
U1 F
8
G
9
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Vdd C1 DP
10
8 16 D0
GND VCC 11
D1
12
G2A
G2B
100nF D2
G1
B 13 B
A
C
B
74F138
5
4
6
3
2
1
Vdd
Title
A Placa de 7 segmentos A

A4
1.0
Drawn By:
1 2 3 4
Matriz de leds
Componentes: La placa forma una matriz 40x7 de leds multiplexada (lógica directa
para filas e inversa para columnas), accesible en serie a través de 2
registros de desplazamiento de 40 y 7 bits.
● 8 matrices 5x7de leds con
filas en cátodo común y
columnas en ánodo común La placa puede encadenarse en vertical u horizontal con otras
similares, para formar matrices de leds de mayores dimensiones.
Conectores:
● tierra
● alimentación
● entrada serie columnas
● reloj columnas
● entrada serie filas
● reloj filas
● salida serie columnas
● salida serie filas
1 2 3 4 5 6 7 8
D D
Vcc
U7
DISP0 DISP1 DISP2 DISP3 DISP4 DISP5 DISP6 DISP7 10 9
Vcc GND
DOT_MATRIX_DISP DOT_MATRIX_DISP DOT_MATRIX_DISP DOT_MATRIX_DISP DOT_MATRIX_DISP DOT_MATRIX_DISP DOT_MATRIX_DISP DOT_MATRIX_DISP 11 8
ROW0 1 ROW0 1 ROW0 1 ROW0 1 ROW0 1 ROW0 1 ROW0 1 ROW0 1 ROW0 12 7
C ROW5 5 ROW5 5 ROW5 5 ROW5 5 ROW5 5 ROW5 5 ROW5 5 ROW5 5 ROW5 17 2 C
ULN2803
4
3
7
9
4
3
7
9
4
3
7
9
4
3
7
9
4
3
7
9
4
3
7
9
4
3
7
9
4
3
7
9
12
12
12
12
12
12
12
12
15
9
7
6
5
4
3
2
1
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
16
15
14
13
12
11
10
9
9
U6
QH1
QH
QG
QE
QD
QA
QF
QC
QB
RP1 RP2 RP3 RP4 RP5 SN74LS594
100 100 100 100 100
SRCLR
SRCK
RCLR
RCK
SER
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
15
15
15
15
15
9
7
6
5
4
3
2
1
9
7
6
5
4
3
2
1
9
7
6
5
4
3
2
1
9
7
6
5
4
3
2
1
9
7
6
5
4
3
2
1
14
11
10
12
13
U1 U2 U3 U4 U5
QH1
QH1
QH1
QH1
QH1
QH
QG
QE
QD
QA
QH
QG
QE
QD
QA
QH
QG
QE
QD
QA
QH
QG
QE
QD
QA
QH
QG
QE
QD
QA
QF
QC
QB
QF
QC
QB
QF
QC
QB
QF
QC
QB
QF
QC
QB
SN74LS594 SN74LS594 SN74LS594 SN74LS594 SN74LS594
SRCLR
SRCLR
SRCLR
SRCLR
SRCLR
SRCK
SRCK
SRCK
SRCK
SRCK
RCLR
RCLR
RCLR
RCLR
RCLR
B B
RCK
RCK
RCK
RCK
RCK
SER
SER
SER
SER
SER
Vcc
J1
1
14
11
10
12
13
14
11
10
12
13
14
11
10
12
13
14
11
10
12
13
14
11
10
12
13
2
COL_Serial_IN
3
COL_Clk
4
ROW_Serial_IN
5
ROW_Clk
6
Reset
7
COL_Serial_OUT
8
ROW_Serial_OUT
9
CON9
A A
Title
8 Dot Matrix Display 5x7
A3
2.0
Drawn By:
1 2 3 4 5 6 7 8
The Concise LCD Data Sheet. http://www.senet.com.au/~cpeacock
Instruction RS RW D7 D6 D5 D4 D3 D2 D1 D0 Description Clocks

NOP 0 0 0 0 0 0 0 0 0 0 No Operation 0
Clear Display 0 0 0 0 0 0 0 0 0 1 Clears display & sets address counter to zero. 165
Cursor Home 0 0 0 0 0 0 0 0 1 0 Sets address counter to zero, returns shifted 3
display to original position.
DDRAM contents remains unchanged.
Entry Mode Set 0 0 0 0 0 0 0 1 I/D S Sets cursor move direction, and specifies 3
automatic shift.
Display Control 0 0 0 0 0 0 1 D C B Turns display (D), cursor on/off (C) or cursor 3
blinking(B).
Cursor/display shift 0 0 0 0 0 1 S/C R/L 0 0 Moves cursor and shift display. DDRAM contents 3
remains unchanged.
Function Set 0 0 0 0 1 DL N M G 0 Sets interface data width(DL), number of display 3
lines (N,M) and voltage generator control (G).
Set CGRAM Addr 0 0 0 1 Character Generator RAM Sets CGRAM Address 3
Set DDRAM Addr 0 0 1 Display Data RAM Address Sets DDRAM Address 3
Busy Flag & Addr 0 1 BF Address Counter Reads Busy Flag & Address Counter 0
Read Data 1 0 Read Data Reads data from CGRAM or DDRAM 3
Write Data 1 1 Write Data Writes data from CGRAM or DDRAM 3
Write Cycle
RS
tas tah
R/W
tw
tf
Enable
tr tds th
Data Valid Data
tc
(2)
Parameter Symbol Min (1) Typ (1) Max (1) Unit
Enable Cycle Time tc 500 - - ns
Enable Pulse Width tw 230 - - ns
(High)
Enable Rise/Fall Time tr,tf - - 20 ns
Address Setup Time tas 40 - - ns
Address Hold Time tah 10 - - ns Pin No Name I/O Description
Data Setup Time 80 - ns 1 Vss Power GND
tds
2 Vdd Power +5v
Data Hold Time th 10 - - ns 3 Vo Analog Contrast Control
4 RS Input Register Select
Note 1 The above specifications are a indication only. Timing will vary from manufacturer 5 R/W Input Read/Write
to manufacturer. 6 E Input Enable (Strobe)
7 D0 I/O Data LSB
8 D1 I/O Data
Note 2 A 2 line by 16 Character LCD Module is Pictured. Data will work on most 1 line x 9 D2 I/O Data
16 character, 1 line x 20 character, 2 line x 16 character, 2 line x 20 character, 4 lines x 10 D3 I/O Data
20 character, 2 lines x 40 character etc. modules compatible with the HD44780 LCD 11 D4 I/O Data
Module. 12 D5 I/O Data
13 D6 I/O Data
14 D7 I/O Data MSB
1 2 3 4
D D
J1
CON14
10
11
12
13
14
1
2
3
4
5
6
7
8
9
R1
10K 330
POT1
C C
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
LED A
LED K
Vdriver
RS
D0
D1
D2
D3
D4
D5
D6
D7
GND
RW
Vcc
E
LCD
B B
LCD_16X2
LCD1
Title
A LCD A

A4
1.1
Date: 10-Apr-2002 Sheet of
File: D:\Mis Documentos\_Trabajo\Electronica\UCM.ddb
Drawn By:
1 2 3 4
Banco de interruptores, pulsadores y leds
Componentes: La placa dispone de 8 columnas formadas por un interruptor y un

pulsador con terminales comunes (lógica inversa) conectados a un
● 8 pulsadores led bicolor configurable (rojo/verde, rojo/apagado, verde/apagado).
● 8 interruptores
● 8 leds bicolor La placa puede usarse como placa de salida (si todos los
interruptores están en OFF) o como placa de entrada (siendo los leds
testigos del valor enviado por los interruptores).
Conectores:
● tierra
● alimentación
● columnas 1-8
1 2 3 4 5 6
LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED0

D LED_BICOLOR LED_BICOLOR LED_BICOLOR LED_BICOLOR LED_BICOLOR LED_BICOLOR LED_BICOLOR LED_BICOLOR D
K
G
R
R
1
3
R31 R30 R29 R28 R27 R26 R25 R24 R23 R22 R21 R20 R19 R18 R17 R16
470 470 470 470 470 470 470 470 470 470 470 470 470 470 470 470
U1B U1D U1F U2B U2D U2F U3B U3D

3 4 9 8 13 12 3 4 9 8 13 12 3 4 9 8
74F14 74F14 74F14
74F14 74F14 74F14 74F14 74F14
10
10
Vcc Vcc Vcc
2
6
74F14 U1C U1E 74F14 U2C U2E 74F14 U3C
VCC
VCC
VCC
GND
GND
GND
A Y
A Y
A Y
U1A C8 74F14 74F14 U2A C9 74F14 74F14 U3A C10 74F14
1
5
14
11
14
11
14
C C
JP1
1
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4
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6
7
8
9
10
Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc
HEADER 10
R15 R14 R13 R12 R11 R10 R9 R8

10K 10K 10K 10K 10K 10K 10K 10K
B B
C7 C6 C5 C4 C3 C2 C1 C0
R7 R6 R5 R4 R3 R2 R1 R0
P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
A A
Title
8 Digital Inputs
B
1.0
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1 2 3 4
D D
U?
C R1 C
VCC BUZZER
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CON3
R2
SPEAKER1
SPEAKER
B B
Title
A Sound A

A4
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¡ Semiconductor
¡ Semiconductor MSM80C154S/83C154S
MSM80C154S/83C154S
CMOS 8-bit Microcontroller
GENERAL DESCRIPTION
The MSM80C154S/MSM83C154S, designed for the high speed version of the existing
MSM80C154/MSM83C154, is a higher performance 8-bit microcontroller providing low-power
consumption.
The MSM80C154S/MSM83C154S covers the functions and operating range of the existing
MSM80C154/83C154/80C51F/80C31F.
The MSM80C154S is identical to the MSM83C154S except it does not contain the internal
program memory (ROM).
FEATURES
• Operating range
Operating frequency : 0 to 3 MHz (Vcc=2.2 to 6.0 V)
0 to 12 MHz (Vcc=3.0 to 6.0 V)
0 to 24 MHz (Vcc=4.5 to 6.0 V)
Operating voltage : 2.2 to 6.0 V
Operating temperature : –40 to +85°C (Operation at +125°C conforms to
the other specification.)
• Fully static circuit
• Upward compatible with the MSM80C51F/80C31F
• On-chip program memory : 16K words x 8 bits ROM (MSM83C154S only)
• On-chip data memory : 256 words x 8 bits RAM
• External program memory address space : 64K bytes ROM (Max)
• External data memory address space : 64K bytes RAM
• I/O ports : 4 ports x 8 bits
(Port 1, 2, 3, impedance programmable) : 32
• 16-bit timer/counters : 3
• Multifunctional serial port : I/O Expansion mode
: UART mode (featuring error detection)
• 6-source 2-priority level
Interrupt and multi-level
Interrupt available by programming IP and IE registers
• Memory-mapped special function registers
• Bit addressable data memory and SFRs
• Minimum instruction cycle : 500 ns @ 24 MHz operation
• Standby functions : Power-down mode (oscillator stop)
Activated by software or hardware; providing
ports with floating or active status
The software power-down stet mode is termi-
nated by interrupt signal enabling execution from
the interrupted address.
259
MSM80C154S/83C154S ¡ Semiconductor
• Package options
40-pin plastic DIP (DIP40-P-600-2.54) : (Product name: MSM80C154SRS/
MSM83C154S-xxxRS)
44-pin plastic QFP (QFP44-P-910-0.80-2K) : (Product name: MSM80C154SGS-2K/
MSM83C154S-xxxGS-2K)
44-pin QFJ (QFJ44-P-S650-1.27) : (Product name: MSM80C154SJS/
MSM83C154S-xxxJS)
44-pin TQFP (TQFP44-P-1010-0.80-K) : (Product name: MSM80C154STS-K/
MSM83C154S-xxxTS-K)
xxx: indicates the code number
260
¡ Semiconductor
BLOCK DIAGRAM (MSM83C154S)
P2.0
PORT 2
P2.7 DPH CONTROL SIGNAL R/W SIGNAL
ADDRESS DECODER
P0.0 ROM SPECIAL
FUNCTION
PORT 0
DPL PLA REGISTER

PCHL PCLL ADDRESS
16K WORDS x 8BITS DECODER
P0.7
XTAL1 PCH PCL SP IR AIR

SENSE AMP
PCON
XTAL2
OSC and TIMING
C-ROM
ALE
PSEN
IOCON
EA
RESET
RAM
P1.0 256 WORDS RAMDP
PORT 1
TIMER/ RCAP2L RCAP2H x 8BITS PSW BR

ALU
COUNTER 2
P1.7
MSM80C154S/83C154S
P3.0
PORT 3
TH1 TL1 TH0 TL0 TMOD TCON IE IP SBUF(T) SBUF(R) SCON

P3.7 INTERRUPT
TIMER/COUNTER 0 & 1 SERIAL IO
261
PIN CONFIGURATION (TOP VIEW)
P1.0/T2 1 40 VCC
P1.1/T2EX 2 39 P0.0
P1.2 3 38 P0.1
P1.3 4 37 P0.2
P1.4 5 36 P0.3
P1.5 6 35 P0.4
P1.6 7 34 P0.5
P1.7 8 33 P0.6
RESET 9 32 P0.7
P3.0/RXD 10 31 EA
P3.1/TXD 11 30 ALE
P3.3/INT1 13 28 P2.7
P3.4/T0 14 27 P2.6
P3.5/T1/HPDI 15 26 P2.5
P3.6/WR 16 25 P2.4
P3.7/RD 17 24 P2.3
XTAL2 18 23 P2.2
XTAL1 19 22 P2.1
VSS 20 21 P2.0
40-Pin Plastic DIP
262
PIN CONFIGURATION (Continued)

44 P1.4
43 P1.3
42 P1.2
41 P1.1
40 P1.0
37 P0.0
36 P0.1
35 P0.2
34 P0.3
38 VCC
39 NC
P1.5 1 33 P0.4
P1.6 2 32 P0.5
P1.7 3 31 P0.6
RESET 4 30 P0.7
P3.0/RXD 5 29 EA
NC 6 28 NC
P3.1/TXD 7 27 ALE
P3.2/INT0 8 26 PSEN
P3.3/INT1 9 25 P2.7
P3.4/T0 10 24 P2.6
P3.5/T1/HPDI 11 23 P2.5
P3.6/WR 12
P3.7/RD 13
XTAL2 14
XTAL1 15
VSS 16
VSS 17
P2.0 18
P2.1 19
P2.2 20
P2.3 21
P2.4 22
NC : No-connection pin
44-Pin Plastic QFP
263
44 P1.4
43 P1.3
42 P1.2
41 P1.1
40 P1.0
39 NC
38 VCC
37 P0.0
36 P0.1
35 P0.2
34 P0.3
P1.5 1 33 P0.4
P1.6 2 32 P0.5
P1.7 3 31 P0.6
RESET 4 30 P0.7
P3.0/RXD 5 29 EA
NC 6 28 NC
P3.1/TXD 7 27 ALE
P3.2/INT0 8 26 PSEN
P3.3/INT1 9 25 P2.7
P3.4/T0 10 24 P2.6
P3.5/T1/HPDI 11 23 P2.5
P3.6/WR 12
P3.7/RD 13
XTAL2 14
XTAL1 15
VSS 16
VSS 17
P2.0 18
P2.1 19
P2.2 20
P2.3 21
P2.4 22
44-Pin Plastic TQFP
264
PIN CONFIGURATION (Continued)

, 32 PSEN
39 P0.4
38 P0.5
37 P0.6
36 P0.7
31 P2.7
30 P2.6
29 P2.5
33 ALE
34 NC
35 EA
P0.3 40 28 P2.4
P0.2 41 27 P2.3
P0.1 42 26 P2.2
P0.0 43 25 P2.1
VCC 44 24 P2.0
NC 1 23 NC
P1.0/T2 2 22 VSS
P1.1/T2EX 3 21 XTAL1
P1.2 4 20 XTAL2
P1.3 5 19 P3.7/RD
P1.4 6 18 P3.6/WR
RESET 10
P3.0/RXD 11
NC 12
P3.1/TXD 13
P3.2/INT0 14
P3.3/INT1 15
P3.4/T0 16
P3.5/T1/HPDI 17
P1.5 7
P1.6 8
P1.7 9
44-Pin Plastic QFJ
265
PIN DESCRIPTIONS
Symbol Descriptipn
P0.0 to P0.7 Bidirectional I/O ports. They are also the data/address bus (input/output of data and output of
lower 8-bit address when external memory is accessed).
They are open-drain outputs when used as I/O ports, but 3-state outputs when used as data/address
bus.
P1.0 to P1.7 P1.0 to P1.7 are quasi-bidirectional I/O ports. They are pulled up internally when used as input
ports. Two of them have the following secondary functions:
•P1.0 (T2) : used as external clock input pins for the timer/counter 2.
•P1.1 (T2EX) : used as trigger input for the timer/counter 2 to be reloaded or captured;
causing the timer/counter 2 interrupt.
P2.0 to P2.7 P2.0 to P2.7 are quasi-bidirectional I/O ports. They also output the higher 8-bit address when
an external memory is accessed. They are pulled up internally when used as input ports.
P3.0 to P3.7 P3.0 to P3.7 are quasi-bidirectional I/O ports. They are pulled up internally when used as input
ports. They also have the following secondary functions:
•P3.0 (RXD)
Serial data input/output in the I/O expansion mode and serial data input in the UART mode when
the serial port is used.
•3.1 (TXD)
Synchronous clock output in the I/O expansion mode and serial data output in the UART mode
when the serial port is used.
•3.2 (INT0)
Used as input pin for the external interrupt 0, and as count-up control pin for the timer/counter 0.
•3.3 (INT1)
Used as input pin for the external interrupt 1, and as count-up control pin for the timer/counter 1.
•3.4 (T0)
Used as external clock input pin for the timer/counter 0.
•3.5 (T1)
Used as external clock input pin for the timer/counter 1 and power-down-mode control input pin.
•3.6 (WR)
Output of the write-strobe signal when data is written into external data memory.
•3.7 (RD)
Output of the read-strobe signal when data is read from external data memory.
ALE Address latch enable output for latching the lower 8-bit address during external memory access.
Two ALE pulses are activated per machine cycle except during external data memory access at
which time one ALE pulse is skipped.
PSEN Program store enable output which enables the external memory output to the bus during external
program memory access. Two PSEN pulses are activated per machine cycle except during
external data memory access at which two PSEN pulses are skipped.
EA When EA is held at "H" level, the MSM 83C154S executes instructions from internal program
memory at address 0000H to 3FFFH, and executes instructions from external program memory
above address 3FFFH.
When EA is held at "L" level, the MSM80C154S/MSM83C154S executes instructions from external
program memory for all addresses.
266
PIN Descriptions (Continued)
Symbol Descriptipn
RESET If this pin remains "H" for at least one machine cycle, the MSM80C154S/MSM83C154S is reset.
Since this pin is pulled down internally, a power-on reset is achieved by simply connecting a
capacitor between VCC and this pin.
XTAL1 Oscillator inverter input pin. External clock is input through XTAL1 pin.
XTAL2 Oscillator inverter output pin.
VCC Power supply pin during both normal operation and standby operations.
VSS GND pin.
267
REGISTERS
Diagram of Special Function Registers
REGISTER BIT ADDRESS DIRECT

NAME b7 b6 b5 b4 b3 b2 b1 b0 ADDRESS
IOCON FF FE FD FC FB FA F9 F8 0F8H (248)
B F7 F6 F5 F4 F3 F2 F1 F0 0F0H (240)
ACC E7 E6 E5 E4 E3 E2 E1 E0 0E0H (224)
PSW D7 D6 D5 D4 D3 D2 D1 D0 0D0H (208)
TH2 0CDH (205)
TL2 0CCH (204)
RCAP2H 0CBH (203)
RCAP2L 0CAH (202)
T2CON CF CE CD CC CB CA C9 C8 0C8H (200)
IP BF BE BD BC BB BA B9 B8 0B8H (184)
P3 B7 B6 B5 B4 B3 B2 B1 B0 0B0H (176)
IE AF AE AD AC AB AA A9 A8 0A8H (168)
P2 A7 A6 A5 A4 A3 A2 A1 A0 0A0H (160)
SBUF 99H (153)
SCON 9F 9E 9D 9C 9B 9A 99 98 98H (152)
P1 97 96 95 94 93 92 91 90 90H (144)
TH1 8DH (141)
TH0 8CH (140)
TL1 8BH (139)
TL0 8AH (138)
TMOD 89H (137)
TCON 8F 8E 8D 8C 8B 8A 89 88 88H (136)
PCON 87H (135)
DPH 83H (131)
DPL 82H (130)
SP 81H (129)
P0 87 86 85 84 83 82 81 80 80H (128)
268
Special Function Registers
Timer mode register (TMOD)
MSB LSB
NAME ADDRESS
7 6 5 4 3 2 1 0
TMOD 89H GATE C/T M1 M0 GATE C/T M1 M0
BIT LOCATION FLAG FUNCTION
0 0 8-bit timer/counter with 5-bit prescalar.
0 1 16-bit timer/counter.
1 0 8-bit timer/counter with 8-bit auto reloading.
TMOD.1 M1 1 1 Timer/counter 0 separated into TLO (8-bit) timer/counter
and TH0 (8-bit) timer/counter. TF0 is set by TL0 carry, and
TF1 is set by TH0 carry.

XTAL1•2 divided by 12 clocks is the input applied to timer/counter 0 when
C/T = "0".
The external clock applied to the T0 pin is the input applied to timer/counter 0
when C/T = "1".
TMOD.3 GATE When this bit is "0", the TR0 bit of TCON (timer control register) is used to
control the start and stop of timer/counter 0 counting.
If this bit is "1", timer/counter 0 starts counting when both the TR0 bit of TCON
and INT0 pin input signal are "1", and stops counting when either is changed
to "0".
0 0 8-bit timer/counter with 5-bit prescalar.
1 0 8-bit timer/counter with 8-bit auto reloading.
TMOD.5 M1
1 1 Timer/counter 1 operation stopped.
XTAL1•2 divided by 12 clocks is the input applied to timer/counter 1 when
C/T = "0".
The external clock applied to the T1 pin is the input applied to timer/counter 1
when C/T = "1".
TMOD.7 GATE When this bit is "0", the TR1 bit of TCON is used to control the start and stop of
timer/counter 1 counting.
If this bit is "1", timer/counter 1 starts counting when both the TR1 bit of TCON
and INT1 pin input signal are "1", and stops counting when either is changed
to "0".
269
Power control register (PCON)
MSB LSB
NAME ADDRESS
7 6 5 4 3 2 1 0
PCON 87H SMOD HPD RPD — GF1 GF0 PD IDL
PCON.0 IDL IDLE mode is set when this bit is set to "1". CPU operations are stopped when
IDLE mode is set, but XTAL1•2, timer/counters 0, 1 and 2, the interrupt circuits,
and the serial port remain active. IDLE mode is cancelled when the CPU is reset
or when an interrupt is generated.
PCON.1 PD PD mode is set when this bit is set to "1". CPU operations and XTAL1•2 are
stopped when PD mode is set. PD mode is cancelled when the CPU is reset or
when an interrupt is generated.
PCON.2 GF0 General purpose bit.

PCON.3 GF1 General purpose bit.
PCON.4 — Reserved bit. The output data is "1", if the bit is read.
PCON.5 RPD This bit is used to specify cancellation of CPU power down mode (IDLE or PD) by an
interrupt signal.
Power-down mode cannot be cancelled by an interrupt signal if the interrupt is not
enabled by IE (interrupt enable register) when this bit is "0".
If the interrupt flag is set to "1" by an interrupt request signal when this bit is
"1" (even if interrupt is disabled), the program is executed from the next address
of the power-down-mode setting instruction.
The flag is reset to "0" by software.
PCON.6 HPD The hard power-down setting mode in enabled when this bit is set to "1".
If the level of the power failure detect signal applied to the HPDI pin (pin 3.5)
is changed from "1" to "0" when this bit is "1", XTAL1•2 oscillation is stopped and
the system is put into hard power down mode. HPD mode is cancelled when the
CPU is reset.
PCON.7 SMOD When the timer/counter 1 carry signal is used as a clock in mode 1, 2 or 3 of
the serial port, this bit has the following functions.
The serial port operation clock is reduced by 1/2 when the bit is "0" for delayed
processing. When the bit is "1", the serial port operation clock is normal
for faster processing.
270
Timer control register (TCON)
MSB LSB
NAME ADDRESS
7 6 5 4 3 2 1 0
TCON 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
TCON.0 IT0 External interrupt 0 signal is used in level-detect mode when this bit is "0" and in
trigger detect mode when "1".
The bit is reset automatically when an interrupt is serviced.
The bit can be set and reset by software when IT0 = "1".
TCON.2 IT1 External interrupt 1 signal is used in level detect mode when this bit is "0", and in
trigger detect mode when "1".
The bit can be set and reset by software when IT1 = "1".
Timer/counter 0 starts counting when this bit is "1", and stops counitng when "0".
The bit is set to "1" when a carry signal is generated from timer/counter 0.
The timer/counter 1 starts counting when this bit is "1", and stops counting when "0".
The bit is reset automatically when interrupt is serviced.
The bit is set to "1" when carry signal is generated from timer/counter 1.
271
Serial port control register (SCON)
MSB LSB
NAME ADDRESS
7 6 5 4 3 2 1 0
SCON 98H SM0 SM1 SM2 REN TB8 RB8 TI RI
SCON.0 RI "End of serial port reception" interrupt request flag.
This flag must be reset by software during interrupt service routine.
This flag is set after the eighth bit of data has been received when in mode 0, or
by the STOP bit when in any other mode.
In mode 2 or 3, however, RI is not set if the RB8 data is "0" with SM2 = "1".
RI is set in mode 1 if STOP bit is received when SM2 = "1".
SCON.1 TI "End of serial port tramsmission" interrupt request flag. This flag must be reset
by software during interrupt service routine.
This flag is set after the eighth bit of data has been sent when in mode 0, or after
the last bit of data has been sent when in any other mode.
SCON.2 RB8 The ninth bit of data received in mode 2 or 3 is passed to RB8.
The STOP bit is applied to RB8 if SM2 = "0" when in mode 1.
RB8 can not be used in mode 0.
SCON.3 TB8 The TB8 data is sent as the ninth data bit when in mode 2 or 3.
Any desired data can be set in TB8 by software.
SCON.4 REN Reception enable control bit.
No reception when REN = "0".
Reception enabled when REN = "1".
SCON.5 SM2 If the ninth bit of received data is "0" with SM2 = "1" in mode 2 or 3, the "end of
reception" signal is not set in the RI flag.
The "end of reception" signal set in the RI flag if the STOP bit is not "1" when
SM2 = "1" in mode 1.
SCON.6 SM1 SM0 SM1 MODE

0 0 0 8-bit shift register I/O
SCON.7 SM0 1 0 2 9-bit UART 1/32 XTAL1, 1/64 XTAL1 baud rate
272
Interrupt enable register (IE)
MSB LSB
NAME ADDRESS
7 6 5 4 3 2 1 0
IE 0A8H EA — ET2 ES ET1 EX1 ET0 EX0



IE.4 ES Interrupt control bit for serial port.


IE.6 — Reserved bit. The output data is "1" if the bit is read.
IE.7 EA Overall interrupt control bit.
All interrupts are disabled when bit is "0".
All interrupts are controlled by IE.0 thru IE.5 when bit is "1".
273
Interrupt priority register (IP)
MSB LSB
NAME ADDRESS
7 6 5 4 3 2 1 0
IP 0B8H PCT — PT2 PS PT1 PX1 PT0 PX0
IP.4 PS Interrupt priority bit for serial port.
IP.6 — Reserved bit. The output data is "1" if the bit is read.
IP.7 PCT Priority interrupt circuit control bit.
The priority register contents are valid and priority assigned interrupts can be
processed when this bit is "0". When the bit is "1", the priority interrupt circuit is
stopped, and interrupts can only be controlled by the interrupt enable register (IE).
274
Program status word register (PSW)
MSB LSB
NAME ADDRESS
7 6 5 4 3 2 1 0
PSW 0D0H CY AC F0 RS1 RS0 OV F1 P
PSW.0 P Accumulator (ACC) parity indicator.
This bit is "1" when the "1" bit number in the accumulator is an odd number, and
"0" when an even number.
PSW.2 OV Overflow flag which is set if the carry C6 from bit 6 of the ALU or CY is "1" as a
result of an arithmetic operation. The flag is also set to "1" if the resultant product
of executing multiplication instruction (MUL AB) is greater than 0FFH, but is reset
to "0" if the product is less than or equal to 0FFH.
PSW.3 RS0 RAM register bank switch

RS1 RS0 BANK RAM ADDRESS
0 0 0 00H - 07H
PSW.4 RS1 0 1 1 08H - 0FH
1 0 2 10H - 17H
1 1 3 18H - 1FH
PSW.6 AC Auxiliary carry flag.
This flag is set to "1" if a carry C3 is generated from bit 3 of the ALU as a result of
executing an arithmetic operation instruction.
In all other cases, the flag is reset to "0".
PSW.7 CY Main carry flag.

This flag is set to "1" if a carry C7 is generated from bit 7 of the ALU as result of
executing an arithmetic operation instruction.
If a carry C7 is not generated, the flag is reset to "0".
275
I/O control register (IOCON)
MSB LSB
NAME ADDRESS
7 6 5 4 3 2 1 0
IOCON 0F8H — T32 SERR IZC P3HZ P2HZ P1HZ ALF
IOCON.0 ALF If CPU power down mode (PD, HPD) is activated with this bit set to "1", the
outputs from ports 0, 1, 2, and 3 are switched to floating status.
When this bit is "0", ports 0, 1, 2, and 3 are in output mode.
IOCON.4 IZC The 10 kW pull-up resistor for ports 1, 2, and 3 is switched off when this bit
is "1", leaving only the 100 kW pull-up resistor.
IOCON.5 SERR Serial port reception error flag.
This flag is set to "1" if an overrun or framing error is generated when data is
received at a serial port.
The flag is reset by software.
IOCON.6 T32 Timer/counters 0 and 1 are connected serially to from a 32-bit timer/counter
when this bit is set to "1".
TF1 of TCON is set if a carry is generated in the 32-bit timer/counter.
IOCON.7 — Leave this bit at "0".
276
Timer 2 control register (T2CON)
MSB LSB
NAME ADDRESS
7 6 5 4 3 2 1 0
T2CON 0C8H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
T2CON.0 CP/RL2 Capture mode is set when TCLK + RCLK = "0" and CP/RL2 = "1".
16-bit auto reload mode is set when TCLK + RCLK = "0" and CP/RL2 = "0".
CP/RL2 is ignored when TCLK + RCLK = "1".
T2CON.1 C/T2 Timer/counter 2 count clock designation control bit.

The internal clocks (XTAL1•2 ÷ 12, XTAL1•2 ÷ 2) are used when this bit is "0",
and the external clock applied to the T2 pin is passed to timer/counter 2 when
the bit is "1".
T2CON.2 TR2 Timer/counter 2 counting start and stop control bit.

Timer/counter 2 commences counting when this bit is "1" and stops counting
when "0".
T2CON.3 EXEN2 T2EX timer/counter 2 external control signal control bit.

Input of the T2EX signal is disabled when this bit is "0", and enabled when "1".
T2CON.4 TCLK Serial port transmit circuit drive clock control bit.
Timer/counter 2 is switched to baud rate generator mode when this bit is "1",
and the timer/counter 2 carry signal becomes the serial port transmit clock.
Note, however, that the serial ports can only use the timer/counter 2 carry signal
in serial port modes 1 and 3.
T2CON.5 RCLK Serial port receive circuit drive clock control bit.
Timer/counter 2 is switched to baud rate generator mode when this bit is "1",
and the timer/counter 2 carry signal becomes the serial port transmit clock.
Note, however, that the serial ports can only use the timer/counter 2 carry signal
in serial port modes 1 and 3.
T2CON.6 EXF2 Timer/counter 2 external flag.
This bit is set to "1" when the T2EX timer/counter 2 external control signal level
is changed from "1" to "0" while EXEN2 = "1".
This flag serves as the timer interrupt 2 request signal. If an interrupt is
generated, EXF2 must be reset to "0" by software.
T2CON.7 TF2 Timer/counter 2 carry flag.
This bit is set to "1" by a carry signal when timer/counter 2 is in 16-bit auto
reload mode or in capture mode.
This flag serves as the timer interrupt 2 request signal. If an interrupt is
generated, TF2 must be reset to "0" by software.
277
MEMORY MAPS
Program Area
65535 0FFFFH Timer interrupt 2 start 43 002BH

MSM83C154S EXTERNAL ROM AREA
S I/O interrupt start 35 0023H

MSM80C154S EXTERNAL ROM AREA
Timer interrupt 1 start 27 001BH
External interrupt 1 start 19 0013H

16384 4000H
16383 3FFFH
MSM83C154S INTERNAL ROM AREA
Timer interrupt 0 start 11 000BH
44 002CH
43 002BH External interrupt 0 start 3 0003H
2 0002H
1 0001H
0 7 6 5 4 3 2 1 0 CPU reset start 0 0000H
278
Internal Data Memory and Special Function Register Layout Diagram

HEX
0FF IOCON FFH~F8H 248(0F8H)
B F7H~F0H 240(0F0H)
ACC E7H~E0H 224(0E0H)
PSW D7H~D0H 208(0D0H)
TH2 205(0CDH)
TL2 204(0CCH)
RCAP2H 203(OCBH)
RCAP2L 202(0CAH)
T2CON CFH~C8H 200(0C8H)
SPECIAL FUNCTION REGISTERS

IP BFH~B8H 184(0B8H)
P3 B7H~B0H 176(0B0H)
REGISTER INDIRECT ADDRESSING
IE AFH~A8H 168(0A8H)
P2 A7H~A0H 160(0A0H)
USER DATA RAM
SBUF 153( 99H)
SCON 9FH~98H 152( 98H)
P1 97H~90H 144( 90H)
TH1 141( 8DH)
TH0 140( 8CH)
TL1 139( 8BH)
TL0 138( 8AH)
TMOD 137( 89H)
TCON 8FH~88H 136( 88H)
PCON 135( 87H)
DPH 131( 83H)
DPL 130( 82H)
SP 129( 81H)
80 P0 87H~80H 128( 80H)
7F
USER DATA RAM
30
2F 7F 78
BIT RAM
20 7 0
BIT ADDRESSING
1F R7
BANK3
18 R0
17 R7
BANK2
10 R0
0F R7
BANK1
08 R0
DATA ADDRESSING
07 R7
BANK0
00 R0
279
Diagram of Internal Data Memory (RAM)
0FFH 255
USER DATA RAM
80H 128
7FH 127
USER DATA RAM
30H 48
2FH 7F 7E 7D 7C 7B 7A 79 78 47
2EH 77 76 75 74 73 72 71 70 46
2DH 6F 6E 6D 6C 6B 6A 69 68 45
REGISTER 0, 1, INDIRECT ADDRESSING

2CH 67 66 65 64 63 62 61 60 44
2BH 5F 5E 5D 5C 5B 5A 59 58 43
DATA ADDRESSING
2AH 57 56 55 54 53 52 51 50 42
BIT ADDRESSING
29H 4F 4E 4D 4C 4B 4A 49 48 41
28H 47 46 45 44 43 42 41 40 40
27H 3F 3E 3D 3C 3B 3A 39 38 39
26H 37 36 35 34 33 32 31 30 38
25H 2F 2E 2D 2C 2B 2A 29 28 37
24H 27 26 25 24 23 22 21 20 36
23H 1F 1E 1D 1C 1B 1A 19 18 35
22H 17 16 15 14 13 12 11 10 34
21H 0F 0E 0D 0C 0B 0A 09 08 33
20H 07 06 05 04 03 02 01 00 32
1FH 31
REGISTERS 0-7 DIRIECT ADDRESSING
Bank 3
18H 24
17H 23
Bank 2
10H 16
0FH 15
Bank 1
08H 8
07H 7
Bank 0
00H 0
280
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Condition Rating Unit

Supply voltage VCC Ta=25°C –0.5 to 7 V
Input voltage VI Ta=25°C –0.5 to VCC+0.5 V
Storage temperature TSTG — –55 to +150 °C
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Condition Range Unit

Power supply voltage VCC See below 2.0 to 6.0 V
Memory retension voltage VCC fOSC=0 Hz (Oscillation stop) 2.0 to 6.0 V
Oxcillation frequency fOSC See below 1 to 24 MHz
External clock operating fEXTCLK See below 0 to 24 MHz
frequency
Ambient temperature Ta — –40 to +85 °C
*1 Depends on the specifications for the oscillator or ceramic resonater.
12 1
5
fOSC fEXTCLK (MHz)
4 3
tCY (ms)
2 6
1 12
0.6 20
0.5 24
2 2.2 3 4 5 6
Power Supply Voltage (VCC)
281
Meas-
circuit
Except XTAL1, EA,
and RESET
Input High Voltage VIH1 XTAL1, RESET and EA 0.7 VCC — VCC+0.5 V
Output Low Voltage
VOL IOL=1.6 mA — — 0.45 V
(PORT 1, 2, 3)
Output Low Voltage
VOL1 IOL=3.2 mA — — 0.45 V
(PORT 0, ALE, PSEN)
1
IOH=–60 mA
2.4 — — V
Output High Voltage VCC=5 V±10%
VOH
(PORT 1, 2, 3) IOH=–30 mA 0.75 VCC — — V
IOH=–10 mA 0.9 VCC — — V
IOH=–400 mA
2.4 — — V
Output High Voltage VCC=5 V±10%
VOH1
(PORT 0, ALE, PSEN) IOH=–150 mA 0.75 VCC — — V
IOH=–40 mA 0.9 VCC — — V
Logical 1 Output Current/ IIL / IOH –5 –20 –80 mA
(PORT 1, 2, 3) VO=0.45 V
2
ITL VI=2.0 V — –190 –500 mA
Ta=25°C, f=1 MHz
(except XTAL1)
282
VCC 4V 5V 6V
Freq
1 MHz 2.2 3.1 4.1
3 MHz 3.9 5.2 7.0
12 MHz 12.0 16.0 20.0
16 MHz 16.0 20.0 25.0
20 MHz 19.0 25.0 30.0
VCC 4.5 V 5V 6V
Freq
24 MHz 25.0 29.0 35.0
VCC 4V 5V 6V
Freq
1 MHz 0.8 1.2 1.6
3 MHz 1.2 1.7 2.3
12 MHz 3.1 4.4 5.9
16 MHz 3.8 5.5 7.3
20 MHz 4.5 6.4 8.6
VCC 4.5 V 5V 6V
Freq
24 MHz 6.4 7.4 9.8
283

Meas-
circuit
Except XTAL1, EA,
and RESET
Input High Voltage VIH1 XTAL1, RESET, and EA 0.6 VCC+0.6 — VCC+0.5 V
Output Low Voltage
VOL IOL=10 mA — — 0.1 V
(PORT 1, 2, 3)
Output Low Voltage
VOL1 IOL=20 mA — — 0.1 V
(PORT 0, ALE, PSEN)
1
Output High Voltage
VOH IOH=–5 mA 0.75 VCC — — V
Output High Voltage
(PORT 1, 2, 3)
VOH1 IOH=–20 mA 0.75 VCC — — V
(PORT 0, ALE, PSEN)
Logical 1 Output Current/ IIL / IOH –5 –10 –40 mA
(PORT 1, 2, 3) VO=0.1 V
2
ITL VI=1.9 V — –80 –300 mA
Ta=25°C, f=1 MHz
(except XTAL1)
284
VCC 2.2 V 3.0 V 4.0 V

Freq
1 MHz 0.9 1.4 2.2
3 MHz 1.8 2.4 4.3
12 MHz — 8.0 12.0
16 MHz — — 16.0
VCC 2.2 V 3.0 V 4.0 V

Freq
1 MHz 0.3 0.5 0.8
3 MHz 0.5 0.8 1.2
12 MHz — 2.0 3.1
16 MHz — — 3.8
285
Measuring circuits
1 2
VCC (*2) (*1) VCC
OUTPUT
OUTPUT
VIH
INPUT
INPUT
(*3)
V A IO V A
VIL
VSS VSS
3 4
VCC (*2) VCC

OUTPUT
OUTPUT
VIH VIH
INPUT
INPUT
(*3)
(*3)
V A
VIL VIL
VSS VSS
*1: Repeated for specified input pins.

*2: Repeated for specified output pins.
*3: Input logic for specified status.
286
AC Characteristics
(1) External program memory access AC characteristics

Parameter Symble 1 to 24 MHz Unit
Min. Max.
XTAL1, XTAL 2 Oscillation Cycle tCLCL 41.7 1000 ns
Address Setup Time
Address Hold Time
tLLPL — 4tCLCL-100 ns
From ALE Falling Edge to PSEN
tLLPL 1tCLCL-30 — ns
Falling Edge
PSEN Signal Width tPLPH 3tCLCL-35 — ns
tPLIV — 3tCLCL-45 ns
(from PSEN Falling Edge)
Instruction Data Hold Time
tPXIX 0 — ns
(from PSEN Rising Edge)
Bus Floating Time after Instruction
tPXIZ — 1tCLCL-20 ns
Data Read (from PSEN Rising Edge)
tAVIV — 5tCLCL-105 ns
Bus Floating Time(PSEN Rising
tAZPL 0 — ns
Edge from Address float)
Address Output Time from PSEN
tPXAV 1tCLCL-20 — ns
Rising Edge
287
(2) External program memory read cycle
tLHLL
ALE
tAVLL tLLPL tPLPH

tLLIV
tPLIV
PSEN
tPXAV
tPXIZ
tLLAX tAZPL tPXIX
PORT0 A0 to A7 INSTR A0 to A7
IN
tAVIV
PORT2 A8 to A15 A8 to A15 A8 to A15
288
(3) External data memory access AC characteristics

Parameter Symbol 1 to 24 MHz Unit
Min. Max.
XTAL1, XTAL2 Oscillator Cycle tCLCL 41.7 1000 ns
Address Setup Time
Address Hold Time
RD Signal Width tRLRL 6tCLCL-100 — ns
WR Signal Width tWLWH 6tCLCL-100 — ns
RAM Data Read Time
tRLDV — 5tCLCL-105 ns
(from RD Signal Falling Edge)
RAM Data Read Hold Time
tRHDX 0 — ns
Data Bus Floating Time
tRHDZ — 2tCLCL-70 ns
RAM Data Read Time
tLLDV — 8tCLCL-100 ns
(from ALE Signal Falling Edge)
RAM Data Read Time
tAVDV — 9tCLCL-105 ns
RD/WR Output Time from ALE 3tCLCL-40
tLLWL 3tCLCL+40 ns
Falling Edge *2 3tCLCL-100
RD/WR Output Time from Address
tAVWL 4tCLCL-70 — ns
Output
WR Output Time from Data Output tQVWX 1tCLCL-40 — ns
Time from Data to WR Rising Edge tQVWH 7tCLCL-105 — ns
Data Hold Time
tWHQX 2tCLCL-50 — ns
(from WR Rising Edge)
Time from to Address Float RD
tRLAZ 0 — ns
Output
Time from RD/WR Rising Edge to 1tCLCL+40
tWHLH 1tCLCL-30 ns
ALE Rising Edge *2 1tCLCL+100
*2 For 2.2£VCC<4 V
289
(4) External data memory read cycle
tLHLL tWHLH
ALE
PSEN
tLLDV
tLLWL tRLRH
RD
tRHDZ
tAVLL tLLAX tRLDV tRHDX
tAZRL
PORT 0 INSTR A0 to A7 A0 to A7 DATA IN A0 to A7
IN PCL Rr or DPL PCL
tAVWL
tAVDV
PORT 2 PCH A8 to A15 PCH P2.0 to P2.7 DATA or A8 to A15 DPH A8 to A15 PCH
(5) External data memory write cycle
tLHLL tWHLH
ALE
PSEN
tLLWL tWLWH
WR
tLLAX
tAVLL tQVWH
tWHQX
tQVWX
PORT 0 INSTR A0 to A7 A0 to A7
DATA (ACC) A0 to A7
IN PCL Rr or DPL PCL
tAVWL
A8 to A15 A8 to A15 PCH P2.0 to P2.7 DATA or A8 to A15 DPH A8 to A15 PCH
PORT 2 PCH
290
(6) Serial port (I/O Extension Mode) AC characteristics
(VCC=2.2 to 6.0V, VSS=0V, Ta=–40°C to +85°C)

Parameter Symbol Min. Max. Unit
Serial Port Clock Cycle Time tXLXL 12tCLCL — ns
Output Data Setup to Clock Rising Edge tQVXH 10tCLCL-133 — ns
Output Data Hold After Clock Rising Edge tXHQX 2tCLCL-75 — ns
Input Data Hold After Clock Rising Edge tXHDX 0 — ns
Clock Rising Edge to Input Data Valid tXHDV — 10tCLCL-133 ns
291
292
MSM80C154S/83C154S
MACHINE
CYCLE
ALE
tXLXL
SHIFT
CLOCK
tQVXH tXHQX
OUTPUT
DATA
tXHDX
¡ Semiconductor
tXHDV
INPUT VALID VALID VALID VALID VALID VALID VALID VALID

DATA
(7) AC Characteristics Measuring Conditions
1.Input/output signal
VOH VOH
VIH VIH
TEST POINT
VIL VIL
VOL VOL
* The input signals in AC test mode are either VOH (logic "1") or VOL (logic "0") input signals
where logic "1" corresponds to a CPU output signal waveform measuring point in excess of
VIH, and logic "0" to a point below VIL.
2.Floating
Floating
VOH VOH
VIH VIH
VIL VIL
VOL VOL
* The port 0 floating interval is measured from the time the port 0 pin voltage drops below VIH
after sinking to GND at 2.4 mA when switching to floating status from a "1" output, and from
the time the port 0 pin voltage exceeds VIL after connecting to a 400 mA source when switching
to floating status from a "0" output.
(8) XTAL1 external clock input waveform conditions
Parameter Symbol Min. Max. Unit

External Clock Freq. 1/tCLCL 0 24 MHz
Clock Pulse width 1 tCHCx 15 — ns
Clock Pulse width 2 tCLCX 15 — ns
Rise Time tCLCH — 5 ns
Fall Time tCHCL — 5 ns
External Clock Drive Waveform
0.7 VCC
EXTERNAL
OSCILLATOR 0.2 VCC - 0.1
tCHCL tCLCH
SIGNAL tCHCX tCLCX
tCLCL
293
294
CYCLE M1 M1 M2 M1
STEP S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
Basic timing
1
XTAL 1
Timing Diagram
0
1
ALE
0
MSM80C154S/83C154S
1
PSEN
0
1
RD/WR
0
DPL&Rr
1
PORT-0 PCL PCL PCL ACC & RAM PCL PCL PCL
0
1
,,
PORT-2 PCH PCH PCH PCH DPH & PORT DATA PCH PCH PCH
,,
,,
,,
,,
,,
,,
DATA STABLE DATA STABLE
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
1
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
CPU¨PORT
,,
,,
,,
,,
,,
,,
0
,,
,,
,,
,,
,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
,,
1
,,
,,
,,
,,
,,
,,
,,
,,
,,
PORT OLD DATA
,,
,,
PORT¨CPU
,,
,,
,,
PORT NEW DATA
,
,
,,
,,
,,
,,
,,
0
Instruction decoding Instruction decoding Instruction decoding
Instruction execution Instruction execution Instruction execution

PC+1 PC+1 PC+1 PC+1 PC+1
TM+1 TM+1 TM+1 TM+1
External data memory instruction

Port output/input execution Port output/input
instruction execution instruction execution
¡ Semiconductor
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R
XC4000E and XC4000X Series Field
Programmable Gate Arrays
May 14, 1999 (Version 1.6) 0 0* Product Specification
XC4000E and XC4000X Series Low-Voltage Versions Available

Features • Low-Voltage Devices Function at 3.0 - 3.6 Volts
Note: Information in this data sheet covers the XC4000E, • XC4000XL: High Performance Low-Voltage Versions of
XC4000EX, and XC4000XL families. A separate data sheet XC4000EX devices
covers the XC4000XLA and XC4000XV families. Electrical
Specifications and package/pin information are covered in Additional XC4000X Series Features
separate sections for each family to make the information • Highest Performance — 3.3 V XC4000XL
easier to access, review, and print. For access to these sec- • Highest Capacity — Over 180,000 Usable Gates
tions, see the Xilinx WEBLINX web site at • 5 V tolerant I/Os on XC4000XL
http://www.xilinx.com/partinfo/databook.htm#xc4000. • 0.35 µm SRAM process for XC4000XL
• Additional Routing Over XC4000E
• System featured Field-Programmable Gate Arrays - almost twice the routing capacity for high-density
- Select-RAMTM memory: on-chip ultra-fast RAM with designs
- synchronous write option • Buffered Interconnect for Maximum Speed Blocks
- dual-port RAM option • Improved VersaRingTM I/O Interconnect for Better Fixed
- Fully PCI compliant (speed grades -2 and faster) Pinout Flexibility 6
- Abundant flip-flops • 12 mA Sink Current Per XC4000X Output
- Flexible function generators • Flexible New High-Speed Clock Network
- Dedicated high-speed carry logic - Eight additional Early Buffers for shorter clock delays
- Wide edge decoders on each edge - Virtually unlimited number of clock signals
- Hierarchy of interconnect lines • Optional Multiplexer or 2-input Function Generator on
- Internal 3-state bus capability Device Outputs
- Eight global low-skew clock or signal distribution • Four Additional Address Bits in Master Parallel
networks Configuration Mode
• System Performance beyond 80 MHz • XC4000XV Family offers the highest density with
• Flexible Array Architecture 0.25 µm 2.5 V technology
• Low Power Segmented Routing Architecture
• Systems-Oriented Features Introduction
- IEEE 1149.1-compatible boundary scan logic
support XC4000 Series high-performance, high-capacity Field Pro-
- Individually programmable output slew rate grammable Gate Arrays (FPGAs) provide the benefits of
- Programmable input pull-up or pull-down resistors custom CMOS VLSI, while avoiding the initial cost, long
- 12 mA sink current per XC4000E output development cycle, and inherent risk of a conventional
• Configured by Loading Binary File masked gate array.
- Unlimited re-programmability The result of thirteen years of FPGA design experience and
• Read Back Capability feedback from thousands of customers, these FPGAs com-
- Program verification bine architectural versatility, on-chip Select-RAM memory
- Internal node observability with edge-triggered and dual-port modes, increased
• Backward Compatible with XC4000 Devices speed, abundant routing resources, and new, sophisticated
• Development System runs on most common computer software to achieve fully automated implementation of
platforms complex, high-density, high-performance designs.
- Interfaces to popular design environments
The XC4000E and XC4000X Series currently have 20
- Fully automatic mapping, placement and routing
members, as shown in Table 1.
- Interactive design editor for design optimization
May 14, 1999 (Version 1.6) 6-5

R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Table 1: XC4000E and XC4000X Series Field Programmable Gate Arrays
Max Logic Max. RAM Typical Number

Logic Gates Bits Gate Range CLB Total of Max.
Device Cells (No RAM) (No Logic) (Logic and RAM)* Matrix CLBs Flip-Flops User I/O
XC4002XL 152 1,600 2,048 1,000 - 3,000 8x8 64 256 64
XC4003E 238 3,000 3,200 2,000 - 5,000 10 x 10 100 360 80
XC4005E/XL 466 5,000 6,272 3,000 - 9,000 14 x 14 196 616 112
XC4006E 608 6,000 8,192 4,000 - 12,000 16 x 16 256 768 128
XC4008E 770 8,000 10,368 6,000 - 15,000 18 x 18 324 936 144
XC4010E/XL 950 10,000 12,800 7,000 - 20,000 20 x 20 400 1,120 160
XC4013E/XL 1368 13,000 18,432 10,000 - 30,000 24 x 24 576 1,536 192
XC4020E/XL 1862 20,000 25,088 13,000 - 40,000 28 x 28 784 2,016 224
XC4025E 2432 25,000 32,768 15,000 - 45,000 32 x 32 1,024 2,560 256
XC4028EX/XL 2432 28,000 32,768 18,000 - 50,000 32 x 32 1,024 2,560 256
XC4036EX/XL 3078 36,000 41,472 22,000 - 65,000 36 x 36 1,296 3,168 288
XC4044XL 3800 44,000 51,200 27,000 - 80,000 40 x 40 1,600 3,840 320
XC4052XL 4598 52,000 61,952 33,000 - 100,000 44 x 44 1,936 4,576 352
XC4062XL 5472 62,000 73,728 40,000 - 130,000 48 x 48 2,304 5,376 384
XC4085XL 7448 85,000 100,352 55,000 - 180,000 56 x 56 3,136 7,168 448
* Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
Note: All functionality in low-voltage families is the same as where hardware is changed dynamically, or where hard-
in the corresponding 5-Volt family, except where numerical ware must be adapted to different user applications.
references are made to timing or power. FPGAs are ideal for shortening design and development
cycles, and also offer a cost-effective solution for produc-
Description tion rates well beyond 5,000 systems per month. For lowest
XC4000 Series devices are implemented with a regular, high-volume unit cost, a design can first be implemented in
flexible, programmable architecture of Configurable Logic the XC4000E or XC4000X, then migrated to one of Xilinx’
Blocks (CLBs), interconnected by a powerful hierarchy of compatible HardWire mask-programmed devices.
versatile routing resources, and surrounded by a perimeter
of programmable Input/Output Blocks (IOBs). They have
Taking Advantage of Re-configuration
generous routing resources to accommodate the most FPGA devices can be re-configured to change logic func-
complex interconnect patterns. tion while resident in the system. This capability gives the
The devices are customized by loading configuration data system designer a new degree of freedom not available
into internal memory cells. The FPGA can either actively with any other type of logic.
read its configuration data from an external serial or Hardware can be changed as easily as software. Design
byte-parallel PROM (master modes), or the configuration updates or modifications are easy, and can be made to
data can be written into the FPGA from an external device products already in the field. An FPGA can even be re-con-
(slave and peripheral modes). figured dynamically to perform different functions at differ-
XC4000 Series FPGAs are supported by powerful and ent times.
sophisticated software, covering every aspect of design Re-configurable logic can be used to implement system
from schematic or behavioral entry, floor planning, simula- self-diagnostics, create systems capable of being re-con-
tion, automatic block placement and routing of intercon- figured for different environments or operations, or imple-
nects, to the creation, downloading, and readback of the ment multi-purpose hardware for a given application. As an
configuration bit stream. added benefit, using re-configurable FPGA devices simpli-
Because Xilinx FPGAs can be reprogrammed an unlimited fies hardware design and debugging and shortens product
number of times, they can be used in innovative designs time-to-market.
6-6 May 14, 1999 (Version 1.6)

R
XC4000E and XC4000X Series much as 50% from XC4000 values. See “Fast Carry Logic”
on page 18 for more information.
Compared to the XC4000
For readers already familiar with the XC4000 family of Xil- Select-RAM Memory: Edge-Triggered, Synchro-
inx Field Programmable Gate Arrays, the major new fea- nous RAM Modes
tures in the XC4000 Series devices are listed in this The RAM in any CLB can be configured for synchronous,
section. The biggest advantages of XC4000E and edge-triggered, write operation. The read operation is not
XC4000X devices are significantly increased system affected by this change to an edge-triggered write.
speed, greater capacity, and new architectural features,
particularly Select-RAM memory. The XC4000X devices Dual-Port RAM
also offer many new routing features, including special A separate option converts the 16x2 RAM in any CLB into a
high-speed clock buffers that can be used to capture input 16x1 dual-port RAM with simultaneous Read/Write.
data with minimal delay.
The function generators in each CLB can be configured as
Any XC4000E device is pinout- and bitstream-compatible either level-sensitive (asynchronous) single-port RAM,
with the corresponding XC4000 device. An existing edge-triggered (synchronous) single-port RAM, edge-trig-
XC4000 bitstream can be used to program an XC4000E gered (synchronous) dual-port RAM, or as combinatorial
device. However, since the XC4000E includes many new logic.
features, an XC4000E bitstream cannot be loaded into an
XC4000 device. Configurable RAM Content
XC4000X Series devices are not bitstream-compatible with The RAM content can now be loaded at configuration time,
equivalent array size devices in the XC4000 or XC4000E so that the RAM starts up with user-defined data.
families. However, equivalent array size devices, such as
the XC4025, XC4025E, XC4028EX, and XC4028XL, are H Function Generator
6
pinout-compatible. In current XC4000 Series devices, the H function generator
is more versatile than in the original XC4000. Its inputs can
Improvements in XC4000E and XC4000X come not only from the F and G function generators but
also from up to three of the four control input lines. The H
Increased System Speed
function generator can thus be totally or partially indepen-
XC4000E and XC4000X devices can run at synchronous dent of the other two function generators, increasing the
system clock rates of up to 80 MHz, and internal perfor- maximum capacity of the device.
mance can exceed 150 MHz. This increase in performance
over the previous families stems from improvements in both IOB Clock Enable
device processing and system architecture. XC4000 The two flip-flops in each IOB have a common clock enable
Series devices use a sub-micron multi-layer metal process. input, which through configuration can be activated individ-
In addition, many architectural improvements have been ually for the input or output flip-flop or both. This clock
made, as described below. enable operates exactly like the EC pin on the XC4000
The XC4000XL family is a high performance 3.3V family CLB. This new feature makes the IOBs more versatile, and
based on 0.35µ SRAM technology and supports system avoids the need for clock gating.
speeds to 80 MHz.
Output Drivers
PCI Compliance The output pull-up structure defaults to a TTL-like
XC4000 Series -2 and faster speed grades are fully PCI totem-pole. This driver is an n-channel pull-up transistor,
compliant. XC4000E and XC4000X devices can be used to pulling to a voltage one transistor threshold below Vcc, just
implement a one-chip PCI solution. like the XC4000 family outputs. Alternatively, XC4000
Series devices can be globally configured with CMOS out-
Carry Logic puts, with p-channel pull-up transistors pulling to Vcc. Also,
The speed of the carry logic chain has increased dramati- the configurable pull-up resistor in the XC4000 Series is a
cally. Some parameters, such as the delay on the carry p-channel transistor that pulls to Vcc, whereas in the origi-
chain through a single CLB (TBYP), have improved by as nal XC4000 family it is an n-channel transistor that pulls to
a voltage one transistor threshold below Vcc.
May 14, 1999 (Version 1.6) 6-7

R
Input Thresholds Additional Improvements in XC4000X Only

The input thresholds of 5V devices can be globally config- Increased Routing
ured for either TTL (1.2 V threshold) or CMOS (2.5 V
threshold), just like XC2000 and XC3000 inputs. The two New interconnect in the XC4000X includes twenty-two
global adjustments of input threshold and output level are additional vertical lines in each column of CLBs and twelve
independent of each other. The XC4000XL family has an new horizontal lines in each row of CLBs. The twelve “Quad
input threshold of 1.6V, compatible with both 3.3V CMOS Lines” in each CLB row and column include optional repow-
and TTL levels. ering buffers for maximum speed. Additional high-perfor-
mance routing near the IOBs enhances pin flexibility.
Global Signal Access to Logic
Faster Input and Output
There is additional access from global clocks to the F and
G function generator inputs. A fast, dedicated early clock sourced by global clock buffers
is available for the IOBs. To ensure synchronization with the
Configuration Pin Pull-Up Resistors regular global clocks, a Fast Capture latch driven by the
During configuration, these pins have weak pull-up resis- early clock is available. The input data can be initially
tors. For the most popular configuration mode, Slave loaded into the Fast Capture latch with the early clock, then
Serial, the mode pins can thus be left unconnected. The transferred to the input flip-flop or latch with the low-skew
three mode inputs can be individually configured with or global clock. A programmable delay on the input can be
without weak pull-up or pull-down resistors. A pull-down used to avoid hold-time requirements. See “IOB Input Sig-
resistor value of 4.7 kΩ is recommended. nals” on page 20 for more information.
The three mode inputs can be individually configured with Latch Capability in CLBs
or without weak pull-up or pull-down resistors after configu-
Storage elements in the XC4000X CLB can be configured
ration.
as either flip-flops or latches. This capability makes the
The PROGRAM input pin has a permanent weak pull-up. FPGA highly synthesis-compatible.
Soft Start-up IOB Output MUX From Output Clock

Like the XC3000A, XC4000 Series devices have “Soft A multiplexer in the IOB allows the output clock to select
Start-up.” When the configuration process is finished and either the output data or the IOB clock enable as the output
the device starts up, the first activation of the outputs is to the pad. Thus, two different data signals can share a sin-
automatically slew-rate limited. This feature avoids poten- gle output pad, effectively doubling the number of device
tial ground bounce when all outputs are turned on simulta- outputs without requiring a larger, more expensive pack-
neously. Immediately after start-up, the slew rate of the age. This multiplexer can also be configured as an
individual outputs is, as in the XC4000 family, determined AND-gate to implement a very fast pin-to-pin path. See
by the individual configuration option. “IOB Output Signals” on page 23 for more information.
XC4000 and XC4000A Compatibility Additional Address Bits

Existing XC4000 bitstreams can be used to configure an Larger devices require more bits of configuration data. A
XC4000E device. XC4000A bitstreams must be recompiled daisy chain of several large XC4000X devices may require
for use with the XC4000E due to improved routing a PROM that cannot be addressed by the eighteen address
resources, although the devices are pin-for-pin compatible. bits supported in the XC4000E. The XC4000X Series
therefore extends the addressing in Master Parallel config-
uration mode to 22 bits.
6-8 May 14, 1999 (Version 1.6)

R
Detailed Functional Description Each CLB contains two storage elements that can be used
to store the function generator outputs. However, the stor-
XC4000 Series devices achieve high speed through age elements and function generators can also be used
advanced semiconductor technology and improved archi- independently. These storage elements can be configured
tecture. The XC4000E and XC4000X support system clock as flip-flops in both XC4000E and XC4000X devices; in the
rates of up to 80 MHz and internal performance in excess XC4000X they can optionally be configured as latches. DIN
of 150 MHz. Compared to older Xilinx FPGA families, can be used as a direct input to either of the two storage
XC4000 Series devices are more powerful. They offer elements. H1 can drive the other through the H function
on-chip edge-triggered and dual-port RAM, clock enables generator. Function generator outputs can also drive two
on I/O flip-flops, and wide-input decoders. They are more outputs independent of the storage element outputs. This
versatile in many applications, especially those involving versatility increases logic capacity and simplifies routing.
RAM. Design cycles are faster due to a combination of
increased routing resources and more sophisticated soft- Thirteen CLB inputs and four CLB outputs provide access
ware. to the function generators and storage elements. These
inputs and outputs connect to the programmable intercon-
Basic Building Blocks nect resources outside the block.
Xilinx user-programmable gate arrays include two major Function Generators
configurable elements: configurable logic blocks (CLBs)
Four independent inputs are provided to each of two func-
and input/output blocks (IOBs).
tion generators (F1 - F4 and G1 - G4). These function gen-
• CLBs provide the functional elements for constructing erators, with outputs labeled F’ and G’, are each capable of
the user’s logic. implementing any arbitrarily defined Boolean function of
• IOBs provide the interface between the package pins four inputs. The function generators are implemented as
and internal signal lines. memory look-up tables. The propagation delay is therefore
independent of the function implemented. 6
Three other types of circuits are also available:
• 3-State buffers (TBUFs) driving horizontal longlines are A third function generator, labeled H’, can implement any
associated with each CLB. Boolean function of its three inputs. Two of these inputs can
• Wide edge decoders are available around the periphery optionally be the F’ and G’ functional generator outputs.
of each device. Alternatively, one or both of these inputs can come from
• An on-chip oscillator is provided. outside the CLB (H2, H0). The third input must come from
outside the block (H1).
Programmable interconnect resources provide routing
paths to connect the inputs and outputs of these config- Signals from the function generators can exit the CLB on
urable elements to the appropriate networks. two outputs. F’ or H’ can be connected to the X output. G’ or
H’ can be connected to the Y output.
The functionality of each circuit block is customized during
configuration by programming internal static memory cells. A CLB can be used to implement any of the following func-
The values stored in these memory cells determine the tions:
logic functions and interconnections implemented in the • any function of up to four variables, plus any second
FPGA. Each of these available circuits is described in this function of up to four unrelated variables, plus any third
section. function of up to three unrelated variables1
• any single function of five variables
Configurable Logic Blocks (CLBs) • any function of four variables together with some
Configurable Logic Blocks implement most of the logic in functions of six variables
an FPGA. The principal CLB elements are shown in • some functions of up to nine variables.
Figure 1. Two 4-input function generators (F and G) offer
Implementing wide functions in a single block reduces both
unrestricted versatility. Most combinatorial logic functions
the number of blocks required and the delay in the signal
need four or fewer inputs. However, a third function gener-
path, achieving both increased capacity and speed.
ator (H) is provided. The H function generator has three
inputs. Either zero, one, or two of these inputs can be the The versatility of the CLB function generators significantly
outputs of F and G; the other input(s) are from outside the improves system speed. In addition, the design-software
CLB. The CLB can, therefore, implement certain functions tools can deal with each function generator independently.
of up to nine variables, like parity check or expand- This flexibility improves cell usage.
able-identity comparison of two sets of four inputs.
1. When three separate functions are generated, one of the function outputs must be captured in a flip-flop internal to the CLB. Only two
unregistered function generator outputs are available from the CLB.
May 14, 1999 (Version 1.6) 6-9

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4
C1 • • • C4
H1 D IN /H 2 SR/H 0 EC
G4 S/R Bypass
CONTROL
DIN YQ
G3 LOGIC SD
F' D
FUNCTION G' Q
G'
OF
H'
G2 G1-G4
G1
LOGIC
EC
FUNCTION RD
G'
OF H' H'
F', G', 1
AND Y
H1
F4 Bypass
S/R
CONTROL
DIN XQ
F3 LOGIC SD
F'
FUNCTION F' D Q
G'
OF
H'
F2 F1-F4
F1
EC
RD
K
(CLOCK) 1
H'
X
F'
Multiplexer Controlled
by Configuration Program
X6692
Figure 1: Simplified Block Diagram of XC4000 Series CLB (RAM and Carry Logic functions not shown)
Flip-Flops Clock Enable

The CLB can pass the combinatorial output(s) to the inter- The clock enable signal (EC) is active High. The EC pin is
connect network, but can also store the combinatorial shared by both storage elements. If left unconnected for
results or other incoming data in one or two flip-flops, and either, the clock enable for that storage element defaults to
connect their outputs to the interconnect network as well. the active state. EC is not invertible within the CLB.
The two edge-triggered D-type flip-flops have common
clock (K) and clock enable (EC) inputs. Either or both clock Table 2: CLB Storage Element Functionality
inputs can also be permanently enabled. Storage element (active rising edge is shown)
functionality is described in Table 2.
Mode K EC SR D Q
Latches (XC4000X only) Power-Up or
X X X X SR
GSR
The CLB storage elements can also be configured as
latches. The two latches have common clock (K) and clock X X 1 X SR
enable (EC) inputs. Storage element functionality is Flip-Flop __/ 1* 0* D D
described in Table 2. 0 X 0* X Q
1 1* 0* X Q
Clock Input Latch
0 1* 0* D D
Each flip-flop can be triggered on either the rising or falling Both X 0 0* X Q
clock edge. The clock pin is shared by both storage ele- Legend:
ments. However, the clock is individually invertible for each X Don’t care
storage element. Any inverter placed on the clock input is __/ Rising edge
automatically absorbed into the CLB. SR Set or Reset value. Reset is default.
0* Input is Low or unconnected (default value)
1* Input is High or unconnected (default value)
6-10 May 14, 1999 (Version 1.6)

R
Set/Reset Two fast feed-through paths are available, as shown in

Figure 1. A two-to-one multiplexer on each of the XQ and
An asynchronous storage element input (SR) can be con-
YQ outputs selects between a storage element output and
figured as either set or reset. This configuration option
any of the control inputs. This bypass is sometimes used by
determines the state in which each flip-flop becomes oper-
the automated router to repower internal signals.
ational after configuration. It also determines the effect of a
Global Set/Reset pulse during normal operation, and the Control Signals
effect of a pulse on the SR pin of the CLB. All three
set/reset functions for any single flip-flop are controlled by Multiplexers in the CLB map the four control inputs (C1 - C4
the same configuration data bit. in Figure 1) into the four internal control signals (H1,
DIN/H2, SR/H0, and EC). Any of these inputs can drive any
The set/reset state can be independently specified for each of the four internal control signals.
flip-flop. This input can also be independently disabled for
either flip-flop. When the logic function is enabled, the four inputs are:
The set/reset state is specified by using the INIT attribute, • EC — Enable Clock
or by placing the appropriate set or reset flip-flop library • SR/H0 — Asynchronous Set/Reset or H function
symbol. generator Input 0
• DIN/H2 — Direct In or H function generator Input 2
SR is active High. It is not invertible within the CLB. • H1 — H function generator Input 1.
Global Set/Reset When the memory function is enabled, the four inputs are:
A separate Global Set/Reset line (not shown in Figure 1) • EC — Enable Clock
sets or clears each storage element during power-up, • WE — Write Enable
re-configuration, or when a dedicated Reset net is driven • D0 — Data Input to F and/or G function generator
active. This global net (GSR) does not compete with other • D1 — Data input to G function generator (16x1 and
16x2 modes) or 5th Address bit (32x1 mode).
6
routing resources; it uses a dedicated distribution network.
Each flip-flop is configured as either globally set or reset in Using FPGA Flip-Flops and Latches
the same way that the local set/reset (SR) is specified.
Therefore, if a flip-flop is set by SR, it is also set by GSR. The abundance of flip-flops in the XC4000 Series invites
Similarly, a reset flip-flop is reset by both SR and GSR. pipelined designs. This is a powerful way of increasing per-
formance by breaking the function into smaller subfunc-
STARTUP
tions and executing them in parallel, passing on the results
through pipeline flip-flops. This method should be seriously
PAD GSR Q2 considered wherever throughput is more important than
GTS Q3 latency.
IBUF
Q1Q4
To include a CLB flip-flop, place the appropriate library
CLK DONEIN
symbol. For example, FDCE is a D-type flip-flop with clock
X5260 enable and asynchronous clear. The corresponding latch
Figure 2: Schematic Symbols for Global Set/Reset symbol (for the XC4000X only) is called LDCE.
In XC4000 Series devices, the flip flops can be used as reg-
GSR can be driven from any user-programmable pin as a isters or shift registers without blocking the function gener-
global reset input. To use this global net, place an input pad ators from performing a different, perhaps unrelated task.
and input buffer in the schematic or HDL code, driving the This ability increases the functional capacity of the devices.
GSR pin of the STARTUP symbol. (See Figure 2.) A spe- The CLB setup time is specified between the function gen-
cific pin location can be assigned to this input using a LOC erator inputs and the clock input K. Therefore, the specified
attribute or property, just as with any other user-program- CLB flip-flop setup time includes the delay through the
mable pad. An inverter can optionally be inserted after the function generator.
input buffer to invert the sense of the Global Set/Reset sig-
nal. Using Function Generators as RAM
Alternatively, GSR can be driven from any internal node. Optional modes for each CLB make the memory look-up
tables in the F’ and G’ function generators usable as an
Data Inputs and Outputs array of Read/Write memory cells. Available modes are
The source of a storage element data input is programma- level-sensitive (similar to the XC4000/A/H families),
ble. It is driven by any of the functions F’, G’, and H’, or by edge-triggered, and dual-port edge-triggered. Depending
the Direct In (DIN) block input. The flip-flops or latches drive on the selected mode, a single CLB can be configured as
the XQ and YQ CLB outputs. either a 16x2, 32x1, or 16x1 bit array.
May 14, 1999 (Version 1.6) 6-11

R
Supported CLB memory configurations and timing modes The selected timing mode applies to both function genera-
for single- and dual-port modes are shown in Table 3. tors within a CLB when both are configured as RAM.
XC4000 Series devices are the first programmable logic The number of read ports is also programmable:
devices with edge-triggered (synchronous) and dual-port
• Single Port: each function generator has a common
RAM accessible to the user. Edge-triggered RAM simpli-
read and write port
fies system timing. Dual-port RAM doubles the effective
• Dual Port: both function generators are configured
throughput of FIFO applications. These features can be
together as a single 16x1 dual-port RAM with one write
individually programmed in any XC4000 Series CLB.
port and two read ports. Simultaneous read and write
Advantages of On-Chip and Edge-Triggered RAM operations to the same or different addresses are
supported.
The on-chip RAM is extremely fast. The read access time is
the same as the logic delay. The write access time is RAM configuration options are selected by placing the
slightly slower. Both access times are much faster than appropriate library symbol.
any off-chip solution, because they avoid I/O delays.
Choosing a RAM Configuration Mode
Edge-triggered RAM, also called synchronous RAM, is a
The appropriate choice of RAM mode for a given design
feature never before available in a Field Programmable
should be based on timing and resource requirements,
Gate Array. The simplicity of designing with edge-triggered
desired functionality, and the simplicity of the design pro-
RAM, and the markedly higher achievable performance,
cess. Recommended usage is shown in Table 4.
add up to a significant improvement over existing devices
with on-chip RAM. The difference between level-sensitive, edge-triggered,
and dual-port RAM is only in the write operation. Read
Three application notes are available from Xilinx that dis-
operation and timing is identical for all modes of operation.
cuss edge-triggered RAM: “XC4000E Edge-Triggered and
Dual-Port RAM Capability,” “Implementing FIFOs in
XC4000E RAM,” and “Synchronous and Asynchronous Table 4: RAM Mode Selection
FIFO Designs.” All three application notes apply to both Dual-Port
XC4000E and XC4000X RAM. Level-Sens Edge-Trigg Edge-Trigg
itive ered ered
Table 3: Supported RAM Modes Use for New
No Yes Yes
Designs?
16 16 32 Edge- Level-
x x x Triggered Sensitive Size (16x1,
1/2 CLB 1/2 CLB 1 CLB
1 2 1 Timing Timing Registered)
Single-Port √ √ √ √ √ Simultaneous
No No Yes
Read/Write
Dual-Port √ √
Relative 2X (4X
X 2X
Performance effective)
RAM Configuration Options
The function generators in any CLB can be configured as RAM Inputs and Outputs
RAM arrays in the following sizes:
The F1-F4 and G1-G4 inputs to the function generators act
• Two 16x1 RAMs: two data inputs and two data outputs as address lines, selecting a particular memory cell in each
with identical or, if preferred, different addressing for look-up table.
each RAM
• One 32x1 RAM: one data input and one data output. The functionality of the CLB control signals changes when
the function generators are configured as RAM. The
One F or G function generator can be configured as a 16x1 DIN/H2, H1, and SR/H0 lines become the two data inputs
RAM while the other function generators are used to imple- (D0, D1) and the Write Enable (WE) input for the 16x2
ment any function of up to 5 inputs. memory. When the 32x1 configuration is selected, D1 acts
Additionally, the XC4000 Series RAM may have either of as the fifth address bit and D0 is the data input.
two timing modes: The contents of the memory cell(s) being addressed are
• Edge-Triggered (Synchronous): data written by the available at the F’ and G’ function-generator outputs. They
designated edge of the CLB clock. WE acts as a true can exit the CLB through its X and Y outputs, or can be cap-
clock enable. tured in the CLB flip-flop(s).
• Level-Sensitive (Asynchronous): an external WE signal Configuring the CLB function generators as Read/Write
acts as the write strobe. memory does not affect the functionality of the other por-
6-12 May 14, 1999 (Version 1.6)

R
tions of the CLB, with the exception of the redefinition of the nals. An internal write pulse is generated that performs the
control signals. In 16x2 and 16x1 modes, the H’ function write. See Figure 4 and Figure 5 for block diagrams of a
generator can be used to implement Boolean functions of CLB configured as 16x2 and 32x1 edge-triggered, sin-
F’, G’, and D1, and the D flip-flops can latch the F’, G’, H’, or gle-port RAM.
D0 signals. The relationships between CLB pins and RAM inputs and
Single-Port Edge-Triggered Mode outputs for single-port, edge-triggered mode are shown in
Table 5.
Edge-triggered (synchronous) RAM simplifies timing
requirements. XC4000 Series edge-triggered RAM timing The Write Clock input (WCLK) can be configured as active
operates like writing to a data register. Data and address on either the rising edge (default) or the falling edge. It uses
are presented. The register is enabled for writing by a logic the same CLB pin (K) used to clock the CLB flip-flops, but it
High on the write enable input, WE. Then a rising or falling can be independently inverted. Consequently, the RAM
clock edge loads the data into the register, as shown in output can optionally be registered within the same CLB
Figure 3. either by the same clock edge as the RAM, or by the oppo-
site edge of this clock. The sense of WCLK applies to both
TWPS function generators in the CLB when both are configured
WCLK (K) as RAM.
TWSS TWHS The WE pin is active-High and is not invertible within the
CLB.
WE
Note: The pulse following the active edge of WCLK (TWPS
TDSS TDHS in Figure 3) must be less than one millisecond wide. For
most applications, this requirement is not overly restrictive;
DATA IN however, it must not be forgotten. Stopping WCLK at this 6
point in the write cycle could result in excessive current and
TASS TAHS
even damage to the larger devices if many CLBs are con-
ADDRESS
figured as edge-triggered RAM.
Table 5: Single-Port Edge-Triggered RAM Signals
TILO TILO
TWOS RAM Signal CLB Pin Function
D D0 or D1 (16x2, Data In
DATA OUT OLD NEW 16x1), D0 (32x1)
X6461
A[3:0] F1-F4 or G1-G4 Address
Figure 3: Edge-Triggered RAM Write Timing A[4] D1 (32x1) Address
WE WE Write Enable
Complex timing relationships between address, data, and WCLK K Clock
write enable signals are not required, and the external write SPO F’ or G’ Single Port Out
enable pulse becomes a simple clock enable. The active (Data Out) (Data Out)
edge of WCLK latches the address, input data, and WE sig-
May 14, 1999 (Version 1.6) 6-13

R
4
C1 • • • C4
WE D1 D0 EC
DIN
WRITE 16-LATCH
DECODER ARRAY MUX G'
4 4
G1 • • • G4
1 of 16
LATCH
ENABLE
READ
WRITE PULSE ADDRESS
DIN
WRITE 16-LATCH
DECODER ARRAY MUX F'
4 4
F1 • • • F4
1 of 16
LATCH
ENABLE
K
(CLOCK) READ
WRITE PULSE ADDRESS
X6752
Figure 4: 16x2 (or 16x1) Edge-Triggered Single-Port RAM
4
C1 • • • C4
EC
WE D1/A4 D0 EC
DIN
WRITE 16-LATCH
G1 • • • G4 4 4
F1 • • • F4 1 of 16
LATCH
ENABLE
READ
WRITE PULSE ADDRESS
H'
DIN
WRITE 16-LATCH
4 4
1 of 16
LATCH
ENABLE
K
(CLOCK) READ
WRITE PULSE ADDRESS
X6754
Figure 5: 32x1 Edge-Triggered Single-Port RAM (F and G addresses are identical)
6-14 May 14, 1999 (Version 1.6)

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Dual-Port Edge-Triggered Mode Table 6: Dual-Port Edge-Triggered RAM Signals

In dual-port mode, both the F and G function generators RAM Signal CLB Pin Function
are used to create a single 16x1 RAM array with one write D D0 Data In
port and two read ports. The resulting RAM array can be A[3:0] F1-F4 Read Address for F,
read and written simultaneously at two independent Write Address for F and G
addresses. Simultaneous read and write operations at the DPRA[3:0] G1-G4 Read Address for G
same address are also supported. WE WE Write Enable
WCLK K Clock
Dual-port mode always has edge-triggered write timing, as
SPO F’ Single Port Out
shown in Figure 3.
(addressed by A[3:0])
Figure 6 shows a simple model of an XC4000 Series CLB DPO G’ Dual Port Out
configured as dual-port RAM. One address port, labeled (addressed by DPRA[3:0])
A[3:0], supplies both the read and write address for the F
function generator. This function generator behaves the Note: The pulse following the active edge of WCLK (TWPS
in Figure 3) must be less than one millisecond wide. For
same as a 16x1 single-port edge-triggered RAM array. The
most applications, this requirement is not overly restrictive;
RAM output, Single Port Out (SPO), appears at the F func-
however, it must not be forgotten. Stopping WCLK at this
tion generator output. SPO, therefore, reflects the data at
address A[3:0]. point in the write cycle could result in excessive current and
even damage to the larger devices if many CLBs are con-
The other address port, labeled DPRA[3:0] for Dual Port figured as edge-triggered RAM.
Read Address, supplies the read address for the G function
generator. The write address for the G function generator, Single-Port Level-Sensitive Timing Mode
however, comes from the address A[3:0]. The output from Note: Edge-triggered mode is recommended for all new
this 16x1 RAM array, Dual Port Out (DPO), appears at the designs. Level-sensitive mode, also called asynchronous
G function generator output. DPO, therefore, reflects the 6
mode, is still supported for XC4000 Series backward-com-
data at address DPRA[3:0]. patibility with the XC4000 family.
Therefore, by using A[3:0] for the write address and Level-sensitive RAM timing is simple in concept but can be
DPRA[3:0] for the read address, and reading only the DPO complicated in execution. Data and address signals are
output, a FIFO that can read and write simultaneously is presented, then a positive pulse on the write enable pin
easily generated. Simultaneous access doubles the effec- (WE) performs a write into the RAM at the designated
tive throughput of the FIFO. address. As indicated by the “level-sensitive” label, this
The relationships between CLB pins and RAM inputs and RAM acts like a latch. During the WE High pulse, changing
outputs for dual-port, edge-triggered mode are shown in the data lines results in new data written to the old address.
Table 6. See Figure 7 on page 16 for a block diagram of a Changing the address lines while WE is High results in spu-
CLB configured in this mode. rious data written to the new address—and possibly at
other addresses as well, as the address lines inevitably do
not all change simultaneously.
RAM16X1D Primitive
DPO (Dual Port Out)
The user must generate a carefully timed WE signal. The
WE WE
D D D Q Registered DPO
delay on the WE signal and the address lines must be care-
DPRA[3:0] AR[3:0] fully verified to ensure that WE does not become active
AW[3:0] until after the address lines have settled, and that WE goes
inactive before the address lines change again. The data
G Function Generator
must be stable before and after the falling edge of WE.
SPO (Single Port Out)
WE In practical terms, WE is usually generated by a 2X clock. If

D D Q Registered SPO a 2X clock is not available, the falling edge of the system
A[3:0] AR[3:0]
clock can be used. However, there are inherent risks in this
AW[3:0]
approach, since the WE pulse must be guaranteed inactive
F Function Generator
before the next rising edge of the system clock. Several
WCLK
older application notes are available from Xilinx that dis-
cuss the design of level-sensitive RAMs. These application
X6755
notes include XAPP031, “Using the XC4000 RAM Capabil-
Figure 6: XC4000 Series Dual-Port RAM, Simple ity,” and XAPP042, “High-Speed RAM Design in XC4000.”
Model However, the edge-triggered RAM available in the XC4000
Series is superior to level-sensitive RAM for almost every
application.
May 14, 1999 (Version 1.6) 6-15

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4
C1 • • • C4
WE D1 D0 EC
DIN
WRITE 16-LATCH
4
1 of 16
LATCH
ENABLE
READ
4 WRITE PULSE ADDRESS
G1 • • • G4
DIN
WRITE 16-LATCH
4 4
F1 • • • F4 1 of 16
LATCH
ENABLE
K
READ
(CLOCK) WRITE PULSE ADDRESS
X6748
Figure 7: 16x1 Edge-Triggered Dual-Port RAM
Figure 8 shows the write timing for level-sensitive, sin- attached to the RAM or ROM symbol, as described in the
gle-port RAM. schematic library guide. If not defined, all RAM contents
The relationships between CLB pins and RAM inputs and are initialized to all zeros, by default.
outputs for single-port level-sensitive mode are shown in RAM initialization occurs only during configuration. The
Table 7. RAM content is not affected by Global Set/Reset.
Figure 9 and Figure 10 show block diagrams of a CLB con- Table 7: Single-Port Level-Sensitive RAM Signals
figured as 16x2 and 32x1 level-sensitive, single-port RAM.
RAM Signal CLB Pin Function
Initializing RAM at Configuration D D0 or D1 Data In
A[3:0] F1-F4 or G1-G4 Address
Both RAM and ROM implementations of the XC4000 WE WE Write Enable
Series devices are initialized during configuration. The ini- O F’ or G’ Data Out
tial contents are defined via an INIT attribute or property
T WC
ADDRESS
TAS T WP T AH
WRITE ENABLE
T DS T DH
DATA IN REQUIRED
X6462
Figure 8: Level-Sensitive RAM Write Timing
6-16 May 14, 1999 (Version 1.6)

R
4
C1 • • • C4
WE D1 D0 EC
DIN
Enable
WRITE 16-LATCH
4
G1 • • • G4
1 of 16
4
READ ADDRESS
DIN
Enable
WRITE 16-LATCH
4
F1 • • • F4
1 of 16
4
X6746 READ ADDRESS
6
Figure 9: 16x2 (or 16x1) Level-Sensitive Single-Port RAM
4
C1 • • • C4
WE D1/A4 D0 EC
DIN
Enable
WRITE 16-LATCH
G1 • • • G4 4
F 1 • • • F4 1 of 16
4
READ ADDRESS
H'
DIN
Enable
WRITE 16-LATCH
4
1 of 16
4
READ ADDRESS X6749
Figure 10: 32x1 Level-Sensitive Single-Port RAM (F and G addresses are identical)
May 14, 1999 (Version 1.6) 6-17

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Fast Carry Logic XC4000.” This discussion also applies to XC4000E

devices, and to XC4000X devices when the minor logic
Each CLB F and G function generator contains dedicated
changes are taken into account.
arithmetic logic for the fast generation of carry and borrow
signals. This extra output is passed on to the function gen- The fast carry logic can be accessed by placing special
erator in the adjacent CLB. The carry chain is independent library symbols, or by using Xilinx Relationally Placed Mac-
of normal routing resources. ros (RPMs) that already include these symbols.
Dedicated fast carry logic greatly increases the efficiency
and performance of adders, subtractors, accumulators, CLB CLB CLB CLB
comparators and counters. It also opens the door to many
new applications involving arithmetic operation, where the
previous generations of FPGAs were not fast enough or too
inefficient. High-speed address offset calculations in micro-
processor or graphics systems, and high-speed addition in CLB CLB CLB CLB
digital signal processing are two typical applications.
The two 4-input function generators can be configured as a
2-bit adder with built-in hidden carry that can be expanded
to any length. This dedicated carry circuitry is so fast and
CLB CLB CLB CLB
efficient that conventional speed-up methods like carry
generate/propagate are meaningless even at the 16-bit
level, and of marginal benefit at the 32-bit level.
This fast carry logic is one of the more significant features
of the XC4000 Series, speeding up arithmetic and counting CLB CLB CLB CLB
into the 70 MHz range.
The carry chain in XC4000E devices can run either up or X6687
down. At the top and bottom of the columns where there
Figure 11: Available XC4000E Carry Propagation
are no CLBs above or below, the carry is propagated to the
Paths
right. (See Figure 11.) In order to improve speed in the
high-capacity XC4000X devices, which can potentially
have very long carry chains, the carry chain travels upward
only, as shown in Figure 12. Additionally, standard intercon-
nect can be used to route a carry signal in the downward CLB CLB CLB CLB
direction.
Figure 13 on page 19 shows an XC4000E CLB with dedi-
cated fast carry logic. The carry logic in the XC4000X is
similar, except that COUT exits at the top only, and the sig-
CLB CLB CLB CLB
nal CINDOWN does not exist. As shown in Figure 13, the
carry logic shares operand and control inputs with the func-
tion generators. The carry outputs connect to the function
generators, where they are combined with the operands to
form the sums. CLB CLB CLB CLB
Figure 14 on page 20 shows the details of the carry logic
for the XC4000E. This diagram shows the contents of the
box labeled “CARRY LOGIC” in Figure 13. The XC4000X
carry logic is very similar, but a multiplexer on the
CLB CLB CLB CLB
pass-through carry chain has been eliminated to reduce
delay. Additionally, in the XC4000X the multiplexer on the
G4 path has a memory-programmable 0 input, which per-
X6610
mits G4 to directly connect to COUT. G4 thus becomes an
additional high-speed initialization path for carry-in. Figure 12: Available XC4000X Carry Propagation
Paths (dotted lines use general interconnect)
The dedicated carry logic is discussed in detail in Xilinx
document XAPP 013: “Using the Dedicated Carry Logic in
6-18 May 14, 1999 (Version 1.6)

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C OUT C IN DOWN D IN
CARRY
LOGIC
Y
G H
CARRY
G4
G3
G
G2 DIN
H S/R
G D Q YQ
F
G1
EC
COUT0
6
H1 H
DIN
F H S/R
CARRY G D Q XQ
F
EC
F4
F3
F
F2
H
F1
X
F
CIN UP C OUT K S/R EC
X6699
Figure 13: Fast Carry Logic in XC4000E CLB (shaded area not present in XC4000X)
May 14, 1999 (Version 1.6) 6-19

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C OUT
M
G1
M
1
0 1 G2
I 0
G4
G3
C OUT0
TO
M FUNCTION
GENERATORS
F2
M
1
0 1
F1
M 0
F4
M 0 1
M 3
F3 1 M
M 0
M 1 0
C IN UP
X2000
C IN DOWN
Figure 14: Detail of XC4000E Dedicated Carry Logic
Input/Output Blocks (IOBs) The choice is made by placing the appropriate library sym-
bol. For example, IFD is the basic input flip-flop (rising edge
User-configurable input/output blocks (IOBs) provide the triggered), and ILD is the basic input latch (transpar-
interface between external package pins and the internal ent-High). Variations with inverted clocks are available, and
logic. Each IOB controls one package pin and can be con- some combinations of latches and flip-flops can be imple-
figured for input, output, or bidirectional signals.
mented in a single IOB, as described in the XACT Libraries
Figure 15 shows a simplified block diagram of the Guide.
XC4000E IOB. A more complete diagram which includes
The XC4000E inputs can be globally configured for either
the boundary scan logic of the XC4000E IOB can be found
TTL (1.2V) or 5.0 volt CMOS thresholds, using an option in
in Figure 40 on page 43, in the “Boundary Scan” section. the bitstream generation software. There is a slight input
The XC4000X IOB contains some special features not hysteresis of about 300mV. The XC4000E output levels are
included in the XC4000E IOB. These features are high- also configurable; the two global adjustments of input
lighted in a simplified block diagram found in Figure 16, and threshold and output level are independent.
discussed throughout this section. When XC4000X special
Inputs on the XC4000XL are TTL compatible and 3.3V
features are discussed, they are clearly identified in the
CMOS compatible. Outputs on the XC4000XL are pulled to
text. Any feature not so identified is present in both the 3.3V positive supply.
XC4000E and XC4000X devices.
The inputs of XC4000 Series 5-Volt devices can be driven
IOB Input Signals by the outputs of any 3.3-Volt device, if the 5-Volt inputs are
Two paths, labeled I1 and I2 in Figure 15 and Figure 16, in TTL mode.
bring input signals into the array. Inputs also connect to an Supported sources for XC4000 Series device inputs are
input register that can be programmed as either an shown in Table 8.
edge-triggered flip-flop or a level-sensitive latch.
6-20 May 14, 1999 (Version 1.6)

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Slew Rate Passive

Pull-Up/
Control Pull-Down
T
Flip-Flop
D Q
Out Output
CE Buffer
Pad
Output
Clock
I1
Flip- Input
Flop/ Buffer
Latch
I2
Q D
Delay
Clock
Enable CE
Input
Clock
X6704
6
Figure 15: Simplified Block Diagram of XC4000E IOB
Passive
Slew Rate Pull-Up/
Control Pull-Down
T
Output MUX
0
1
Flip-Flop
Out D Q
Output
CE Buffer
Pad
Output Clock Input

Buffer
I1
Flip-Flop/
Latch
I2 Delay Delay
Q D
Q D
Latch
Clock Enable CE Fast G
Capture
Latch
Input Clock
X5984
Figure 16: Simplified Block Diagram of XC4000X IOB (shaded areas indicate differences from XC4000E)
May 14, 1999 (Version 1.6) 6-21

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Table 8: Supported Sources for XC4000 Series Device Optional Delay Guarantees Zero Hold Time
Inputs The data input to the register can optionally be delayed by
XC4000E/EX XC4000XL several nanoseconds. With the delay enabled, the setup
Series Inputs Series Inputs time of the input flip-flop is increased so that normal clock
Source 5 V, 5 V, 3.3 V routing does not result in a positive hold-time requirement.
TTL CMOS CMOS A positive hold time requirement can lead to unreliable,
temperature- or processing-dependent operation.
Any device, Vcc = 3.3 V,
√ √ The input flip-flop setup time is defined between the data
CMOS outputs
Unreli measured at the device I/O pin and the clock input at the
XC4000 Series, Vcc = 5 V,
√ -able √ IOB (not at the clock pin). Any routing delay from the device
TTL outputs
Data clock pin to the clock input of the IOB must, therefore, be
Any device, Vcc = 5 V,
√ √ subtracted from this setup time to arrive at the real setup
TTL outputs (Voh ≤ 3.7 V)
time requirement relative to the device pins. A short speci-
Any device, Vcc = 5 V,
√ √ √ fied setup time might, therefore, result in a negative setup
CMOS outputs time at the device pins, i.e., a positive hold-time require-
XC4000XL 5-Volt Tolerant I/Os ment.
The I/Os on the XC4000XL are fully 5-volt tolerant even When a delay is inserted on the data line, more clock delay
though the VCC is 3.3 volts. This allows 5 V signals to can be tolerated without causing a positive hold-time
directly connect to the XC4000XL inputs without damage, requirement. Sufficient delay eliminates the possibility of a
as shown in Table 8. In addition, the 3.3 volt VCC can be data hold-time requirement at the external pin. The maxi-
applied before or after 5 volt signals are applied to the I/Os. mum delay is therefore inserted as the default.
This makes the XC4000XL immune to power supply The XC4000E IOB has a one-tap delay element: either the
sequencing problems. delay is inserted (default), or it is not. The delay guarantees
a zero hold time with respect to clocks routed through any
Registered Inputs
of the XC4000E global clock buffers. (See “Global Nets and
The I1 and I2 signals that exit the block can each carry Buffers (XC4000E only)” on page 35 for a description of the
either the direct or registered input signal. global clock buffers in the XC4000E.) For a shorter input
The input and output storage elements in each IOB have a register setup time, with non-zero hold, attach a NODELAY
common clock enable input, which, through configuration, attribute or property to the flip-flop.
can be activated individually for the input or output flip-flop, The XC4000X IOB has a two-tap delay element, with
or both. This clock enable operates exactly like the EC pin choices of a full delay, a partial delay, or no delay. The
on the XC4000 Series CLB. It cannot be inverted within the attributes or properties used to select the desired delay are
IOB. shown in Table 10. The choices are no added attribute,
The storage element behavior is shown in Table 9. MEDDELAY, and NODELAY. The default setting, with no
added attribute, ensures no hold time with respect to any of
Table 9: Input Register Functionality the XC4000X clock buffers, including the Global Low-Skew
(active rising edge is shown) buffers. MEDDELAY ensures no hold time with respect to
Clock the Global Early buffers. Inputs with NODELAY may have a
Mode Clock D Q positive hold time with respect to all clock buffers. For a
Enable
description of each of these buffers, see “Global Nets and
Power-Up or X X X SR
Buffers (XC4000X only)” on page 37.
GSR
Flip-Flop __/ 1* D D Table 10: XC4000X IOB Input Delay Element
0 X X Q Value When to Use
Latch 1 1* X Q full delay Zero Hold with respect to Global
0 1* D D (default, no Low-Skew Buffer, Global Early Buffer
Both X 0 X Q attribute added)
Legend: MEDDELAY Zero Hold with respect to Global Early
X Don’t care Buffer
__/ Rising edge
SR Set or Reset value. Reset is default. NODELAY Short Setup, positive Hold time
1* Input is High or unconnected (default value)
6-22 May 14, 1999 (Version 1.6)

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Additional Input Latch for Fast Capture (XC4000X only) the desired delay based on the discussion in the previous
The XC4000X IOB has an additional optional latch on the subsection.
input. This latch, as shown in Figure 16, is clocked by the IOB Output Signals
output clock — the clock used for the output flip-flop —
rather than the input clock. Therefore, two different clocks Output signals can be optionally inverted within the IOB,
can be used to clock the two input storage elements. This and can pass directly to the pad or be stored in an
additional latch allows the very fast capture of input data, edge-triggered flip-flop. The functionality of this flip-flop is
which is then synchronized to the internal clock by the IOB shown in Table 11.
flip-flop or latch. An active-High 3-state signal can be used to place the out-
To use this Fast Capture technique, drive the output clock put buffer in a high-impedance state, implementing 3-state
pin (the Fast Capture latching signal) from the output of one outputs or bidirectional I/O. Under configuration control, the
of the Global Early buffers supplied in the XC4000X. The output (OUT) and output 3-state (T) signals can be
second storage element should be clocked by a Global inverted. The polarity of these signals is independently con-
Low-Skew buffer, to synchronize the incoming data to the figured for each IOB.
internal logic. (See Figure 17.) These special buffers are The 4-mA maximum output current specification of many
described in “Global Nets and Buffers (XC4000X only)” on FPGAs often forces the user to add external buffers, which
page 37. are especially cumbersome on bidirectional I/O lines. The
The Fast Capture latch (FCL) is designed primarily for use XC4000E and XC4000EX/XL devices solve many of these
with a Global Early buffer. For Fast Capture, a single clock problems by providing a guaranteed output sink current of
signal is routed through both a Global Early buffer and a 12 mA. Two adjacent outputs can be interconnected exter-
Global Low-Skew buffer. (The two buffers share an input nally to sink up to 24 mA. The XC4000E and XC4000EX/XL
pad.) The Fast Capture latch is clocked by the Global Early FPGAs can thus directly drive buses on a printed circuit
buffer, and the standard IOB flip-flop or latch is clocked by board. 6
the Global Low-Skew buffer. This mode is the safest way to By default, the output pull-up structure is configured as a
use the Fast Capture latch, because the clock buffers on TTL-like totem-pole. The High driver is an n-channel pull-up
both storage elements are driven by the same pad. There is transistor, pulling to a voltage one transistor threshold
no external skew between clock pads to create potential below Vcc. Alternatively, the outputs can be globally config-
problems. ured as CMOS drivers, with p-channel pull-up transistors
To place the Fast Capture latch in a design, use one of the pulling to Vcc. This option, applied using the bitstream gen-
special library symbols, ILFFX or ILFLX. ILFFX is a trans- eration software, applies to all outputs on the device. It is
parent-Low Fast Capture latch followed by an active-High not individually programmable. In the XC4000XL, all out-
input flip-flop. ILFLX is a transparent-Low Fast Capture puts are pulled to the positive supply rail.
latch followed by a transparent-High input latch. Any of the
clock inputs can be inverted before driving the library ele- Table 11: Output Flip-Flop Functionality (active rising
ment, and the inverter is absorbed into the IOB. If a single edge is shown)
BUFG output is used to drive both clock inputs, the soft-
Clock
ware automatically runs the clock through both a Global
Mode Clock Enable T D Q
Low-Skew buffer and a Global Early buffer, and clocks the
Fast Capture latch appropriately. Power-Up X X 0* X SR
or GSR
Figure 16 on page 21 also shows a two-tap delay on the
X 0 0* X Q
input. By default, if the Fast Capture latch is used, the Xilinx
software assumes a Global Early buffer is driving the clock, Flip-Flop __/ 1* 0* D D
and selects MEDDELAY to ensure a zero hold time. Select X X 1 X Z
0 X 0* X Q
ILFFX Legend:
X Don’t care
IPAD D Q to internal __/ Rising edge
logic SR Set or Reset value. Reset is default.
GF 1* Input is High or unconnected (default value)
BUFGE Z 3-state
CE
C
IPAD
BUFGLS
X9013
Figure 17: Examples Using XC4000X FCL
May 14, 1999 (Version 1.6) 6-23

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Any XC4000 Series 5-Volt device with its outputs config- Power/Ground pin pairs are connected to special Power
ured in TTL mode can drive the inputs of any typical and Ground planes within the packages, to reduce ground
3.3-Volt device. (For a detailed discussion of how to inter- bounce. Therefore, the maximum total capacitive load is
face between 5 V and 3.3 V devices, see the 3V Products 300 pF between each external Power/Ground pin pair.
section of The Programmable Logic Data Book.) Maximum loading may vary for the low-voltage devices.
Supported destinations for XC4000 Series device outputs For slew-rate limited outputs this total is two times larger for
are shown in Table 12. each device type: 400 pF for XC4000E devices and 600 pF
An output can be configured as open-drain (open-collector) for XC4000X devices. This maximum capacitive load
by placing an OBUFT symbol in a schematic or HDL code, should not be exceeded, as it can result in ground bounce
then tying the 3-state pin (T) to the output signal, and the of greater than 1.5 V amplitude and more than 5 ns dura-
input pin (I) to Ground. (See Figure 18.) tion. This level of ground bounce may cause undesired
transient behavior on an output, or in the internal logic. This
Table 12: Supported Destinations for XC4000 Series restriction is common to all high-speed digital ICs, and is
Outputs not particular to Xilinx or the XC4000 Series.
XC4000 Series XC4000 Series devices have a feature called “Soft
Outputs Start-up,” designed to reduce ground bounce when all out-
Destination 3.3 V, 5 V, 5 V, puts are turned on simultaneously at the end of configura-
CMOS TTL CMOS tion. When the configuration process is finished and the
Any typical device, Vcc = 3.3 V, √ √ some1 device starts up, the first activation of the outputs is auto-
CMOS-threshold inputs matically slew-rate limited. Immediately following the initial
activation of the I/O, the slew rate of the individual outputs
Any device, Vcc = 5 V, √ √ √
is determined by the individual configuration option for each
TTL-threshold inputs
IOB.
Any device, Vcc = 5 V, Unreliable √
CMOS-threshold inputs Data Global Three-State
1. Only if destination device has 5-V tolerant inputs A separate Global 3-State line (not shown in Figure 15 or
Figure 16) forces all FPGA outputs to the high-impedance
state, unless boundary scan is enabled and is executing an
EXTEST instruction. This global net (GTS) does not com-
OPAD pete with other routing resources; it uses a dedicated distri-
OBUFT bution network.
X6702
Figure 18: Open-Drain Output GTS can be driven from any user-programmable pin as a
global 3-state input. To use this global net, place an input
Output Slew Rate pad and input buffer in the schematic or HDL code, driving
the GTS pin of the STARTUP symbol. A specific pin loca-
The slew rate of each output buffer is, by default, reduced, tion can be assigned to this input using a LOC attribute or
to minimize power bus transients when switching non-criti- property, just as with any other user-programmable pad. An
cal signals. For critical signals, attach a FAST attribute or inverter can optionally be inserted after the input buffer to
property to the output buffer or flip-flop. invert the sense of the Global 3-State signal. Using GTS is
For XC4000E devices, maximum total capacitive load for similar to GSR. See Figure 2 on page 11 for details.
simultaneous fast mode switching in the same direction is Alternatively, GTS can be driven from any internal node.
200 pF for all package pins between each Power/Ground
pin pair. For XC4000X devices, additional internal
6-24 May 14, 1999 (Version 1.6)

R
Output Multiplexer/2-Input Function Generator Other IOB Options

(XC4000X only)
There are a number of other programmable options in the
As shown in Figure 16 on page 21, the output path in the XC4000 Series IOB.
XC4000X IOB contains an additional multiplexer not avail-
able in the XC4000E IOB. The multiplexer can also be con- Pull-up and Pull-down Resistors
figured as a 2-input function generator, implementing a Programmable pull-up and pull-down resistors are useful
pass-gate, AND-gate, OR-gate, or XOR-gate, with 0, 1, or 2 for tying unused pins to Vcc or Ground to minimize power
inverted inputs. The logic used to implement these func- consumption and reduce noise sensitivity. The configurable
tions is shown in the upper gray area of Figure 16. pull-up resistor is a p-channel transistor that pulls to Vcc.
When configured as a multiplexer, this feature allows two The configurable pull-down resistor is an n-channel transis-
output signals to time-share the same output pad; effec- tor that pulls to Ground.
tively doubling the number of device outputs without requir- The value of these resistors is 50 kΩ − 100 kΩ. This high
ing a larger, more expensive package. value makes them unsuitable as wired-AND pull-up resis-
When the MUX is configured as a 2-input function generators.
tor, logic can be implemented within the IOB itself. Com- The pull-up resistors for most user-programmable IOBs are
bined with a Global Early buffer, this arrangement allows active during the configuration process. See Table 22 on
very high-speed gating of a single signal. For example, a page 58 for a list of pins with pull-ups active before and dur-
wide decoder can be implemented in CLBs, and its output ing configuration.
gated with a Read or Write Strobe Driven by a BUFGE
After configuration, voltage levels of unused pads, bonded
buffer, as shown in Figure 19. The critical-path pin-to-pin
or un-bonded, must be valid logic levels, to reduce noise
delay of this circuit is less than 6 nanoseconds.
sensitivity and avoid excess current. Therefore, by default,
As shown in Figure 16, the IOB input pins Out, Output unused pads are configured with the internal pull-up resis-
Clock, and Clock Enable have different delays and different 6
tor active. Alternatively, they can be individually configured
flexibilities regarding polarity. Additionally, Output Clock with the pull-down resistor, or as a driven output, or to be
sources are more limited than the other inputs. Therefore, driven by an external source. To activate the internal
the Xilinx software does not move logic into the IOB func- pull-up, attach the PULLUP library component to the net
tion generators unless explicitly directed to do so. attached to the pad. To activate the internal pull-down,
The user can specify that the IOB function generator be attach the PULLDOWN library component to the net
used, by placing special library symbols beginning with the attached to the pad.
letter “O.” For example, a 2-input AND-gate in the IOB func-
Independent Clocks
tion generator is called OAND2. Use the symbol input pin
labelled “F” for the signal on the critical path. This signal is Separate clock signals are provided for the input and output
placed on the OK pin — the IOB input with the shortest flip-flops. The clock can be independently inverted for each
delay to the function generator. Two examples are shown in flip-flop within the IOB, generating either falling-edge or ris-
Figure 20. ing-edge triggered flip-flops. The clock inputs for each IOB
are independent, except that in the XC4000X, the Fast
Capture latch shares an IOB input with the output clock pin.
IPAD
BUFGE Early Clock for IOBs (XC4000X only)
F Special early clocks are available for IOBs. These clocks
OPAD
from
FAST are sourced by the same sources as the Global Low-Skew
internal OAND2
logic buffers, but are separately buffered. They have fewer loads
and therefore less delay. The early clock can drive either
X9019
the IOB output clock or the IOB input clock, or both. The
Figure 19: Fast Pin-to-Pin Path in XC4000X early clock allows fast capture of input data, and fast
clock-to-output on output data. The Global Early buffers
that drive these clocks are described in “Global Nets and
OMUX2 Buffers (XC4000X only)” on page 37.
F D0
O
D1 Global Set/Reset
OAND2 S0 As with the CLB registers, the Global Set/Reset signal
X6598
X6599 (GSR) can be used to set or clear the input and output reg-
Figure 20: AND & MUX Symbols in XC4000X IOB isters, depending on the value of the INIT attribute or prop-
erty. The two flip-flops can be individually configured to set
May 14, 1999 (Version 1.6) 6-25

R
or clear on reset and after configuration. Other than the glo- Standard 3-State Buffer
bal GSR net, no user-controlled set/reset signal is available All three pins are used. Place the library element BUFT.
to the I/O flip-flops. The choice of set or clear applies to Connect the input to the I pin and the output to the O pin.
both the initial state of the flip-flop and the response to the The T pin is an active-High 3-state (i.e. an active-Low
Global Set/Reset pulse. See “Global Set/Reset” on enable). Tie the T pin to Ground to implement a standard
page 11 for a description of how to use GSR. buffer.
JTAG Support Wired-AND with Input on the I Pin
Embedded logic attached to the IOBs contains test struc- The buffer can be used as a Wired-AND. Use the WAND1
tures compatible with IEEE Standard 1149.1 for boundary library symbol, which is essentially an open-drain buffer.
scan testing, permitting easy chip and board-level testing. WAND4, WAND8, and WAND16 are also available. See the
More information is provided in “Boundary Scan” on XACT Libraries Guide for further information.
page 42.
The T pin is internally tied to the I pin. Connect the input to
Three-State Buffers the I pin and the output to the O pin. Connect the outputs of
all the WAND1s together and attach a PULLUP symbol.
A pair of 3-state buffers is associated with each CLB in the
array. (See Figure 27 on page 30.) These 3-state buffers Wired OR-AND
can be used to drive signals onto the nearest horizontal
longlines above and below the CLB. They can therefore be The buffer can be configured as a Wired OR-AND. A High
used to implement multiplexed or bidirectional buses on the level on either input turns off the output. Use the
horizontal longlines, saving logic resources. Programmable WOR2AND library symbol, which is essentially an
pull-up resistors attached to these longlines help to imple- open-drain 2-input OR gate. The two input pins are func-
ment a wide wired-AND function. tionally equivalent. Attach the two inputs to the I0 and I1
pins and tie the output to the O pin. Tie the outputs of all the
The buffer enable is an active-High 3-state (i.e. an WOR2ANDs together and attach a PULLUP symbol.
active-Low enable), as shown in Table 13.
Three-State Buffer Examples
Another 3-state buffer with similar access is located near
each I/O block along the right and left edges of the array. Figure 21 shows how to use the 3-state buffers to imple-
(See Figure 33 on page 34.) ment a wired-AND function. When all the buffer inputs are
High, the pull-up resistor(s) provide the High output.
The horizontal longlines driven by the 3-state buffers have
a weak keeper at each end. This circuit prevents undefined Figure 22 shows how to use the 3-state buffers to imple-
floating levels. However, it is overridden by any driver, even ment a multiplexer. The selection is accomplished by the
a pull-up resistor. buffer 3-state signal.
Special longlines running along the perimeter of the array Pay particular attention to the polarity of the T pin when
can be used to wire-AND signals coming from nearby IOBs using these buffers in a design. Active-High 3-state (T) is
or from internal longlines. These longlines form the wide identical to an active-Low output enable, as shown in
edge decoders discussed in “Wide Edge Decoders” on Table 13.
page 27. Table 13: Three-State Buffer Functionality
Three-State Buffer Modes IN T OUT
The 3-state buffers can be configured in three modes: X 1 Z
• Standard 3-state buffer IN 0 IN
• Wired-AND with input on the I pin
• Wired OR-AND
P
Z=D ●D ● (D +D ) ● (D +D ) U
A B C D E F U
L P
L
D D
C E
D D D D
A B D F
WAND1 WAND1
WOR2AND WOR2AND
X6465
Figure 21: Open-Drain Buffers Implement a Wired-AND Function
6-26 May 14, 1999 (Version 1.6)

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Z = DA • A + D B • B + D C • C + D N • N
~100 kΩ
DA DB DC DN
BUFT BUFT BUFT BUFT
A B C N
X6466
"Weak Keeper"
Figure 22: 3-State Buffers Implement a Multiplexer
Wide Edge Decoders

Dedicated decoder circuitry boosts the performance of LUP symbol. Location attributes or properties such as L
wide decoding functions. When the address or data field is (left edge) or TR (right half of top edge) should also be used
wider than the function generator inputs, FPGAs need to ensure the correct placement of the decoder inputs.
multi-level decoding and are thus slower than PALs.
XC4000 Series CLBs have nine inputs. Any decoder of up INTERCONNECT
to nine inputs is, therefore, compact and fast. However,
there is also a need for much wider decoders, especially for IOB IOB
address decoding in large microprocessor systems. .I1 .I1
An XC4000 Series FPGA has four programmable decoders A C B
located on each edge of the device. The inputs to each

6
decoder are any of the IOB I1 signals on that edge plus one
local interconnect per CLB row or column. Each row or col-
umn of CLBs provides up to three variables or their compli- ( C) .....
ments., as shown in Figure 23. Each decoder generates a (A • B • C) .....
High output (resistor pull-up) when the AND condition of (A • B • C) .....
the selected inputs, or their complements, is true. This is (A • B • C) .....
analogous to a product term in typical PAL devices.
X2627
Each of these wired-AND gates is capable of accepting up
Figure 23: XC4000 Series Edge Decoding Example
to 42 inputs on the XC4005E and 72 on the XC4013E.
There are up to 96 inputs for each decoder on the
XC4028X and 132 on the XC4052X. The decoders may
also be split in two when a larger number of narrower
OSC4
decoders are required, for a maximum of 32 decoders per F8M
device. F500K
F16K
The decoder outputs can drive CLB inputs, so they can be
F490
combined with other logic to form a PAL-like AND/OR struc-
ture. The decoder outputs can also be routed directly to the F15
chip outputs. For fastest speed, the output should be on the X6703
same chip edge as the decoder. Very large PALs can be

Figure 24: XC4000 Series Oscillator Symbol
emulated by ORing the decoder outputs in a CLB. This
decoding feature covers what has long been considered a
weakness of older FPGAs. Users often resorted to external On-Chip Oscillator
PALs for simple but fast decoding functions. Now, the dedi- XC4000 Series devices include an internal oscillator. This
cated decoders in the XC4000 Series device can imple- oscillator is used to clock the power-on time-out, for config-
ment these functions fast and efficiently. uration memory clearing, and as the source of CCLK in
To use the wide edge decoders, place one or more of the Master configuration modes. The oscillator runs at a nomi-
WAND library symbols (WAND1, WAND4, WAND8, nal 8 MHz frequency that varies with process, Vcc, and
WAND16). Attach a DECODE attribute or property to each temperature. The output frequency falls between 4 and 10
WAND symbol. Tie the outputs together and attach a PUL- MHz.
May 14, 1999 (Version 1.6) 6-27

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The oscillator output is optionally available after configura- • Global routing consists of dedicated networks primarily
tion. Any two of four resynchronized taps of a built-in divider designed to distribute clocks throughout the device with
are also available. These taps are at the fourth, ninth, four- minimum delay and skew. Global routing can also be
teenth and nineteenth bits of the divider. Therefore, if the used for other high-fanout signals.
primary oscillator output is running at the nominal 8 MHz, Five interconnect types are distinguished by the relative
the user has access to an 8 MHz clock, plus any two of 500 length of their segments: single-length lines, double-length
kHz, 16kHz, 490Hz and 15Hz (up to 10% lower for low-volt- lines, quad and octal lines (XC4000X only), and longlines.
age devices). These frequencies can vary by as much as In the XC4000X, direct connects allow fast data flow
-50% or +25%. between adjacent CLBs, and between IOBs and CLBs.
These signals can be accessed by placing the OSC4 Extra routing is included in the IOB pad ring. The XC4000X
library element in a schematic or in HDL code (see also includes a ring of octal interconnect lines near the
Figure 24). IOBs to improve pin-swapping and routing to locked pins.
The oscillator is automatically disabled after configuration if XC4000E/X devices include two types of global buffers.
the OSC4 symbol is not used in the design. These global buffers have different properties, and are
intended for different purposes. They are discussed in
Programmable Interconnect detail later in this section.
All internal connections are composed of metal segments
with programmable switching points and switching matrices CLB Routing Connections
to implement the desired routing. A structured, hierarchical A high-level diagram of the routing resources associated
matrix of routing resources is provided to achieve efficient with one CLB is shown in Figure 25. The shaded arrows
automated routing. represent routing present only in XC4000X devices.
The XC4000E and XC4000X share a basic interconnect Table 14 shows how much routing of each type is available
structure. XC4000X devices, however, have additional rout- in XC4000E and XC4000X CLB arrays. Clearly, very large
ing not available in the XC4000E. The extra routing designs, or designs with a great deal of interconnect, will
resources allow high utilization in high-capacity devices. All route more easily in the XC4000X. Smaller XC4000E
XC4000X-specific routing resources are clearly identified designs, typically requiring significantly less interconnect,
throughout this section. Any resources not identified as do not require the additional routing.
XC4000X-specific are present in all XC4000 Series
devices. Figure 27 on page 30 is a detailed diagram of both the
XC4000E and the XC4000X CLB, with associated routing.
This section describes the varied routing resources avail- The shaded square is the programmable switch matrix,
able in XC4000 Series devices. The implementation soft- present in both the XC4000E and the XC4000X. The
ware automatically assigns the appropriate resources L-shaped shaded area is present only in XC4000X devices.
based on the density and timing requirements of the As shown in the figure, the XC4000X block is essentially an
design. XC4000E block with additional routing.
Interconnect Overview CLB inputs and outputs are distributed on all four sides,
providing maximum routing flexibility. In general, the entire
There are several types of interconnect. architecture is symmetrical and regular. It is well suited to
• CLB routing is associated with each row and column of established placement and routing algorithms. Inputs, out-
the CLB array. puts, and function generators can freely swap positions
• IOB routing forms a ring (called a VersaRing) around within a CLB to avoid routing congestion during the place-
the outside of the CLB array. It connects the I/O with the ment and routing operation.
internal logic blocks.
6-28 May 14, 1999 (Version 1.6)

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Quad
Single
Double
Long
Direct
CLB Connect
Long
Quad Long Global Long Double Single Global Carry Direct

Clock Clock Chain Connect
x5994
Figure 25: High-Level Routing Diagram of XC4000 Series CLB (shaded arrows indicate XC4000X only)
6
Table 14: Routing per CLB in XC4000 Series Devices
e
es
e
bl
bl
gl
ou
XC4000E XC4000X
ou
in
D
S
D
Vertical Horizontal Vertical Horizontal
Singles 8 8 8 8
Double
Doubles 4 4 4 4
Quads 0 0 12 12
Singles
Longlines 6 6 10 6
Six Pass Transistors
Direct 0 0 2 2 Per Switch Matrix
Interconnect Point
Connects Double
Globals 4 0 8 0
X6600
Carry Logic 2 0 1 0
Total 24 18 45 32 Figure 26: Programmable Switch Matrix (PSM)
Programmable Switch Matrices Single-Length Lines

The horizontal and vertical single- and double-length lines Single-length lines provide the greatest interconnect flexi-
intersect at a box called a programmable switch matrix bility and offer fast routing between adjacent blocks. There
(PSM). Each switch matrix consists of programmable pass are eight vertical and eight horizontal single-length lines
transistors used to establish connections between the lines associated with each CLB. These lines connect the switch-
(see Figure 26). ing matrices that are located in every row and a column of
CLBs.
For example, a single-length signal entering on the right
side of the switch matrix can be routed to a single-length Single-length lines are connected by way of the program-
line on the top, left, or bottom sides, or any combination mable switch matrices, as shown in Figure 28. Routing
thereof, if multiple branches are required. Similarly, a dou- connectivity is shown in Figure 27.
ble-length signal can be routed to a double-length line on Single-length lines incur a delay whenever they go through
any or all of the other three edges of the programmable a switching matrix. Therefore, they are not suitable for rout-
switch matrix. ing signals for long distances. They are normally used to
conduct signals within a localized area and to provide the
branching for nets with fanout greater than one.
May 14, 1999 (Version 1.6) 6-29

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QUAD
DOUBLE
SINGLE
DOUBLE
LONG
F4 C4 G4
YQ
Y DIRECT
G1
C1
F1
CLB G3
C3 FEEDBACK
F3
K
X
XQ
F2 C2 G2
LONG
LO G LO D D LO G D
LO O O LO IR
Q N N U SI U N BA EC FE
U G BA G BL N BL G
AD L E G E L T ED
LE BA
C
K
Common to XC4000E and XC4000X
XC4000X only
Programmable Switch Matrix
Figure 27: Detail of Programmable Interconnect Associated with XC4000 Series CLB
6-30 May 14, 1999 (Version 1.6)

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CLB CLB CLB
Doubles
CLB CLB CLB
PSM PSM Singles
Doubles
CLB CLB CLB

CLB CLB CLB
PSM PSM
CLB CLB CLB CLB CLB CLB
X6601
Figure 28: Single- and Double-Length Lines, with X9014
Programmable Switch Matrices (PSMs) Figure 29: Quad Lines (XC4000X only)
Double-Length Lines and up to two independent outputs. Only one of the inde-
The double-length lines consist of a grid of metal segments, pendent inputs can be buffered. 6
each twice as long as the single-length lines: they run past The place and route software automatically uses the timing
two CLBs before entering a switch matrix. Double-length requirements of the design to determine whether or not a
lines are grouped in pairs with the switch matrices stag- quad line signal should be buffered. A heavily loaded signal
gered, so that each line goes through a switch matrix at is typically buffered, while a lightly loaded one is not. One
every other row or column of CLBs (see Figure 28). scenario is to alternate buffers and pass transistors. This
There are four vertical and four horizontal double-length allows both vertical and horizontal quad lines to be buffered
lines associated with each CLB. These lines provide faster at alternating buffered switch matrices.
signal routing over intermediate distances, while retaining Due to the buffered switch matrices, quad lines are very
routing flexibility. Double-length lines are connected by way fast. They provide the fastest available method of routing
of the programmable switch matrices. Routing connectivity heavily loaded signals for long distances across the device.
is shown in Figure 27.
Longlines
Quad Lines (XC4000X only)
Longlines form a grid of metal interconnect segments that
XC4000X devices also include twelve vertical and twelve run the entire length or width of the array. Longlines are
horizontal quad lines per CLB row and column. Quad lines intended for high fan-out, time-critical signal nets, or nets
are four times as long as the single-length lines. They are that are distributed over long distances. In XC4000X
interconnected via buffered switch matrices (shown as dia- devices, quad lines are preferred for critical nets, because
monds in Figure 27 on page 30). Quad lines run past four the buffered switch matrices make them faster for high
CLBs before entering a buffered switch matrix. They are fan-out nets.
grouped in fours, with the buffered switch matrices stag-
gered, so that each line goes through a buffered switch Two horizontal longlines per CLB can be driven by 3-state
matrix at every fourth CLB location in that row or column. or open-drain drivers (TBUFs). They can therefore imple-
(See Figure 29.) ment unidirectional or bidirectional buses, wide multiplex-
ers, or wired-AND functions. (See “Three-State Buffers” on
The buffered switch matrixes have four pins, one on each page 26 for more details.)
edge. All of the pins are bidirectional. Any pin can drive any
or all of the other pins. Each horizontal longline driven by TBUFs has either two
(XC4000E) or eight (XC4000X) pull-up resistors. To acti-
Each buffered switch matrix contains one buffer and six vate these resistors, attach a PULLUP symbol to the
pass transistors. It resembles the programmable switch long-line net. The software automatically activates the
matrix shown in Figure 26, with the addition of a program- appropriate number of pull-ups. There is also a weak
mable buffer. There can be up to two independent inputs keeper at each end of these two horizontal longlines. This
May 14, 1999 (Version 1.6) 6-31

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circuit prevents undefined floating levels. However, it is I/O Routing

overridden by any driver, even a pull-up resistor.
XC4000 Series devices have additional routing around the
Each XC4000E longline has a programmable splitter switch IOB ring. This routing is called a VersaRing. The VersaRing
at its center, as does each XC4000X longline driven by facilitates pin-swapping and redesign without affecting
TBUFs. This switch can separate the line into two indepen- board layout. Included are eight double-length lines span-
dent routing channels, each running half the width or height ning two CLBs (four IOBs), and four longlines. Global lines
of the array. and Wide Edge Decoder lines are provided. XC4000X
Each XC4000X longline not driven by TBUFs has a buff- devices also include eight octal lines.
ered programmable splitter switch at the 1/4, 1/2, and 3/4 A high-level diagram of the VersaRing is shown in
points of the array. Due to the buffering, XC4000X longline Figure 31. The shaded arrows represent routing present
performance does not deteriorate with the larger array only in XC4000X devices.
sizes. If the longline is split, the resulting partial longlines
Figure 33 on page 34 is a detailed diagram of the XC4000E
are independent.
and XC4000X VersaRing. The area shown includes two
Routing connectivity of the longlines is shown in Figure 27 IOBs. There are two IOBs per CLB row or column, there-
on page 30. fore this diagram corresponds to the CLB routing diagram
shown in Figure 27 on page 30. The shaded areas repre-
Direct Interconnect (XC4000X only)
sent routing and routing connections present only in
The XC4000X offers two direct, efficient and fast connec- XC4000X devices.
tions between adjacent CLBs. These nets facilitate a data
flow from the left to the right side of the device, or from the Octal I/O Routing (XC4000X only)
top to the bottom, as shown in Figure 30. Signals routed on Between the XC4000X CLB array and the pad ring, eight
the direct interconnect exhibit minimum interconnect prop- interconnect tracks provide for versatility in pin assignment
agation delay and use no general routing resources. and fixed pinout flexibility. (See Figure 32 on page 33.)
The direct interconnect is also present between CLBs and These routing tracks are called octals, because they can be
adjacent IOBs. Each IOB on the left and top device edges broken every eight CLBs (sixteen IOBs) by a programma-
has a direct path to the nearest CLB. Each CLB on the right ble buffer that also functions as a splitter switch. The buffers
and bottom edges of the array has a direct path to the near- are staggered, so each line goes through a buffer at every
est two IOBs, since there are two IOBs for each row or col- eighth CLB location around the device edge.
umn of CLBs.
The octal lines bend around the corners of the device. The
The place and route software uses direct interconnect lines cross at the corners in such a way that the segment
whenever possible, to maximize routing resources and min- most recently buffered before the turn has the farthest dis-
imize interconnect delays. tance to travel before the next buffer, as shown in
Figure 32.
IOB
IOB
IOB
IOB
IOB
IOB
~ ~
~
IOB IOB
CLB CLB CLB
~
IOB IOB
~ ~
~ ~ ~ ~
~ ~ ~ ~
~ ~
~ ~
~
IOB IOB
CLB CLB CLB
~
IOB IOB
IOB
IOB
IOB
IOB
IOB
IOB
X6603
Figure 30: XC4000X Direct Interconnect
6-32 May 14, 1999 (Version 1.6)

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WED
IOB
Quad
WED
Single
Double
INTERCONNECT
Long
Direct
Connect
Long
IOB
WED
6
Direct Edge Double Long Global Octal
Connect Decode Clock
X5995
Figure 31: High-Level Routing Diagram of XC4000 Series VersaRing (Left Edge)
WED = Wide Edge Decoder, IOB = I/O Block (shaded arrows indicate XC4000X only)
IOB IOB
IOB IOB
Segment with nearest buffer

connects to segment with furthest buffer
X9015
Figure 32: XC4000X Octal I/O Routing
May 14, 1999 (Version 1.6) 6-33

R
QUAD
T
O
DOUBLE
C
SINGLE L
B
DOUBLE
LONG
A
R
R
IOB
A
DECODER
I1 I2
IK
OK
T
CE
O
DIRECT
Y
DECODER
IOB
T O
OK CE
DECODER
IK
I1 I2
LONG
G
LO
ED EC
LO
D
N
G OD
D
O
BA
G
E E
O
C
U
TA
L
BL
L
E
Common to XC4000E and XC4000X
XC4000X only
Figure 33: Detail of Programmable Interconnect Associated with XC4000 Series IOB (Left Edge)
6-34 May 14, 1999 (Version 1.6)

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IOB inputs and outputs interface with the octal lines via the Two different types of clock buffers are available in the
single-length interconnect lines. Single-length lines are XC4000E:
also used for communication between the octals and dou-
• Primary Global Buffers (BUFGP)
ble-length lines, quads, and longlines within the CLB array. • Secondary Global Buffers (BUFGS)
Segmentation into buffered octals was found to be optimal Four Primary Global buffers offer the shortest delay and
for distributing signals over long distances around the negligible skew. Four Secondary Global buffers have
device. slightly longer delay and slightly more skew due to poten-
tially heavier loading, but offer greater flexibility when used
Global Nets and Buffers
to drive non-clock CLB inputs.
Both the XC4000E and the XC4000X have dedicated glo-
The Primary Global buffers must be driven by the
bal networks. These networks are designed to distribute
semi-dedicated pads. The Secondary Global buffers can
clocks and other high fanout control signals throughout the
be sourced by either semi-dedicated pads or internal nets.
devices with minimal skew. The global buffers are
described in detail in the following sections. The text Each CLB column has four dedicated vertical Global lines.
descriptions and diagrams are summarized in Table 15. Each of these lines can be accessed by one particular Pri-
The table shows which CLB and IOB clock pins can be mary Global buffer, or by any of the Secondary Global buff-
sourced by which global buffers. ers, as shown in Figure 34. Each corner of the device has
one Primary buffer and one Secondary buffer.
In both XC4000E and XC4000X devices, placement of a
library symbol called BUFG results in the software choos- IOBs along the left and right edges have four vertical global
ing the appropriate clock buffer, based on the timing longlines. Top and bottom IOBs can be clocked from the
requirements of the design. The detailed information in global lines in the adjacent CLB column.
these sections is included only for reference. A global buffer should be specified for all timing-sensitive
Global Nets and Buffers (XC4000E only) global signal distribution. To use a global buffer, place a 6
BUFGP (primary buffer), BUFGS (secondary buffer), or
Four vertical longlines in each CLB column are driven BUFG (either primary or secondary buffer) element in a
exclusively by special global buffers. These longlines are schematic or in HDL code. If desired, attach a LOC
in addition to the vertical longlines used for standard inter- attribute or property to direct placement to the designated
connect. The four global lines can be driven by either of two location. For example, attach a LOC=L attribute or property
types of global buffers. The clock pins of every CLB and to a BUFGS symbol to direct that a buffer be placed in one
IOB can also be sourced from local interconnect. of the two Secondary Global buffers on the left edge of the
device, or a LOC=BL to indicate the Secondary Global
buffer on the bottom edge of the device, on the left.
Table 15: Clock Pin Access
XC4000E XC4000X Local

L&R T&B Inter-
BUFGP BUFGS BUFGLS
BUFGE BUFGE connect
All CLBs in Quadrant √ √ √ √ √ √
All CLBs in Device √ √ √ √
IOBs on Adjacent Vertical √ √ √ √ √ √
Half Edge
IOBs on Adjacent Vertical √ √ √ √ √
Full Edge
IOBs on Adjacent Horizontal √ √
Half Edge (Direct)
IOBs on Adjacent Horizontal √ √ √ √ √ √
Half Edge (through CLB globals)
IOBs on Adjacent Horizontal √ √ √ √
Full Edge (through CLB globals)
L = Left, R = Right, T = Top, B = Bottom
May 14, 1999 (Version 1.6) 6-35

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IOB IOB IOB IOB
locals
locals
locals
locals
BUFGS BUFGP
PGCK1 SGCK4
SGCK1 PGCK4
4
4
BUFGP BUFGS
4
4 locals locals
CLB CLB
IOB IOB
locals locals
X4 Any BUFGS X4 X4 Any BUFGS X4
locals locals
One BUFGP One BUFGP
IOB per Global Line per Global Line IOB
locals CLB CLB locals
BUFGS BUFGP
PGCK2 SGCK3
SGCK2 PGCK3
locals
locals
locals
locals
BUFGP BUFGS
IOB IOB IOB IOB X6604
Figure 34: XC4000E Global Net Distribution
BUFGLS IOB IOB IOB IOB BUFGLS
GCK1 GCK8 GCK7 GCK6
BUFGE BUFGE
locals
locals
locals
locals
BUFGLS BUFGE BUFGE BUFGLS
CLB CLB
X4 BUFGLS 8 X8 X8 8 BUFGLS X8
BUFGLS 8 locals locals 8 BUFGLS
locals locals
4 8
8 8
IOB CLB CLOCKS CLB CLOCKS IOB

IOB IOB
(PER COLUMN) (PER COLUMN)
CLOCKS CLOCKS
locals locals
locals locals
IOB CLB CLOCKS CLB CLOCKS IOB
IOB CLOCKS (PER COLUMN) (PER COLUMN) CLOCKS IOB
8 8
locals 4 8 locals
BUFGLS 8 locals locals 8 BUFGLS
BUFGLS 8 8 BUFGLS
X4 X8 X8 X8
CLB CLB
locals
locals
locals
locals
BUFGLS BUFGE BUFGE BUFGLS
BUFGE BUFGE
GCK2 GCK3 GCK4 GCK5
BUFGLS IOB IOB IOB IOB BUFGLS X9018
Figure 35: XC4000X Global Net Distribution
6-36 May 14, 1999 (Version 1.6)

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Global Nets and Buffers (XC4000X only) Early and Global Low-Skew buffers share a common input;
they cannot be driven by two different signals.
Eight vertical longlines in each CLB column are driven by
special global buffers. These longlines are in addition to the Choosing an XC4000X Clock Buffer
vertical longlines used for standard interconnect. The glo-
The clocking structure of the XC4000X provides a large
bal lines are broken in the center of the array, to allow faster
distribution and to minimize skew across the whole array. variety of features. However, it can be simple to use, with-
Each half-column global line has its own buffered multi- out understanding all the details. The software automati-
plexer, as shown in Figure 35. The top and bottom global cally handles clocks, along with all other routing, when the
lines cannot be connected across the center of the device, appropriate clock buffer is placed in the design. In fact, if a
as this connection might introduce unacceptable skew. The buffer symbol called BUFG is placed, rather than a specific
top and bottom halves of the global lines must be sepa- type of buffer, the software even chooses the buffer most
rately driven — although they can be driven by the same appropriate for the design. The detailed information in this
global buffer. section is provided for those users who want a finer level of
control over their designs.
The eight global lines in each CLB column can be driven by
either of two types of global buffers. They can also be If fine control is desired, use the following summary and
driven by internal logic, because they can be accessed by Table 15 on page 35 to choose an appropriate clock buffer.
single, double, and quad lines at the top, bottom, half, and • The simplest thing to do is to use a Global Low-Skew
quarter points. Consequently, the number of different buffer.
clocks that can be used simultaneously in an XC4000X • If a faster clock path is needed, try a BUFG. The
device is very large. software will first try to use a Global Low-Skew Buffer. If
There are four global lines feeding the IOBs at the left edge timing requirements are not met, a faster buffer will
of the device. IOBs along the right edge have eight global automatically be used.
• If a single quadrant of the chip is sufficient for the 6
lines. There is a single global line along the top and bottom
edges with access to the IOBs. All IOB global lines are bro- clocked logic, and the timing requires a faster clock than
ken at the center. They cannot be connected across the the Global Low-Skew buffer, use a Global Early buffer.
center of the device, as this connection might introduce Global Low-Skew Buffers
unacceptable skew.
Each corner of the XC4000X device has two Global
IOB global lines can be driven from two types of global buff- Low-Skew buffers. Any of the eight Global Low-Skew buff-
ers, or from local interconnect. Alternatively, top and bottom ers can drive any of the eight vertical Global lines in a col-
IOBs can be clocked from the global lines in the adjacent umn of CLBs. In addition, any of the buffers can drive any of
CLB column. the four vertical lines accessing the IOBs on the left edge of
Two different types of clock buffers are available in the the device, and any of the eight vertical lines accessing the
XC4000X: IOBs on the right edge of the device. (See Figure 36 on
page 38.)
• Global Low-Skew Buffers (BUFGLS)
• Global Early Buffers (BUFGE) IOBs at the top and bottom edges of the device are
accessed through the vertical Global lines in the CLB array,
Global Low-Skew Buffers are the standard clock buffers.
as in the XC4000E. Any Global Low-Skew buffer can,
They should be used for most internal clocking, whenever a
therefore, access every IOB and CLB in the device.
large portion of the device must be driven.
The Global Low-Skew buffers can be driven by either
Global Early Buffers are designed to provide a faster clock
semi-dedicated pads or internal logic.
access, but CLB access is limited to one-fourth of the
device. They also facilitate a faster I/O interface. To use a Global Low-Skew buffer, instantiate a BUFGLS
element in a schematic or in HDL code. If desired, attach a
Figure 35 is a conceptual diagram of the global net struc-
LOC attribute or property to direct placement to the desig-
ture in the XC4000X.
nated location. For example, attach a LOC=T attribute or
Global Early buffers and Global Low-Skew buffers share a property to direct that a BUFGLS be placed in one of the
single pad. Therefore, the same IPAD symbol can drive one two Global Low-Skew buffers on the top edge of the device,
buffer of each type, in parallel. This configuration is particu- or a LOC=TR to indicate the Global Low-Skew buffer on the
larly useful when using the Fast Capture latches, as top edge of the device, on the right.
described in “IOB Input Signals” on page 20. Paired Global
May 14, 1999 (Version 1.6) 6-37

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8 7 8 7
IOB IOB IOB IOB
1 6 1 6
I I I I
O CLB CLB O O CLB CLB O
B B B B
I I I I
O CLB CLB O O CLB CLB O
B B B B
2 5 2 5
IOB IOB IOB IOB
3 4 3 4
X6751
X6753
Figure 36: Any BUFGLS (GCK1 - GCK8) Can Figure 37: Left and Right BUFGEs Can Drive Any or
Drive Any or All Clock Inputs on the Device All Clock Inputs in Same Quadrant or Edge (GCK1 is
shown. GCK2, GCK5 and GCK6 are similar.)
Global Early Buffers
The left-side Global Early buffers can each drive two of the
Each corner of the XC4000X device has two Global Early
four vertical lines accessing the IOBs on the entire left edge
buffers. The primary purpose of the Global Early buffers is
of the device. The right-side Global Early buffers can each
to provide an earlier clock access than the potentially
drive two of the eight vertical lines accessing the IOBs on
heavily-loaded Global Low-Skew buffers. A clock source
the entire right edge of the device. (See Figure 37.)
applied to both buffers will result in the Global Early clock
edge occurring several nanoseconds earlier than the Glo- Each left and right Global Early buffer can also drive half of
bal Low-Skew buffer clock edge, due to the lighter loading. the IOBs along either the top or bottom edge of the device,
using a dedicated line that can only be accessed through
Global Early buffers also facilitate the fast capture of device
the Global Early buffers.
inputs, using the Fast Capture latches described in “IOB
Input Signals” on page 20. For Fast Capture, take a single The top and bottom Global Early buffers can drive half of
clock signal, and route it through both a Global Early buffer the IOBs along either the left or right edge of the device, as
and a Global Low-Skew buffer. (The two buffers share an shown in Figure 38. They can only access the top and bot-
input pad.) Use the Global Early buffer to clock the Fast tom IOBs via the CLB global lines.
Capture latch, and the Global Low-Skew buffer to clock the
normal input flip-flop or latch, as shown in Figure 17 on 8 7
page 23. IOB IOB
1 6
The Global Early buffers can also be used to provide a fast
Clock-to-Out on device output pins. However, an early clock I I
in the output flip-flop IOB must be taken into consideration O CLB CLB O
when calculating the internal clock speed for the design. B B
The Global Early buffers at the left and right edges of the
chip have slightly different capabilities than the ones at the
top and bottom. Refer to Figure 37, Figure 38, and I I
Figure 35 on page 36 while reading the following explana- O CLB CLB O
B B
tion.
Each Global Early buffer can access the eight vertical Glo- 2 5
bal lines for all CLBs in the quadrant. Therefore, only IOB IOB
one-fourth of the CLB clock pins can be accessed. This 3 4
X6747
restriction is in large part responsible for the faster speed of
the buffers, relative to the Global Low-Skew buffers. Figure 38: Top and Bottom BUFGEs Can Drive Any
or All Clock Inputs in Same Quadrant (GCK8 is
shown. GCK3, GCK4 and GCK7 are similar.)
6-38 May 14, 1999 (Version 1.6)

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The top and bottom Global Early buffers are about 1 ns

slower clock to out than the left and right Global Early buff- GND
ers.
Ground and
Vcc Ring for
The Global Early buffers can be driven by either semi-ded- I/O Drivers
icated pads or internal logic. They share pads with the Glo-
bal Low-Skew buffers, so a single net can drive both global
buffers, as described above.
To use a Global Early buffer, place a BUFGE element in a Vcc Vcc
schematic or in HDL code. If desired, attach a LOC
attribute or property to direct placement to the designated Logic
location. For example, attach a LOC=T attribute or property Power Grid
to direct that a BUFGE be placed in one of the two Global
Early buffers on the top edge of the device, or a LOC=TR to
indicate the Global Early buffer on the top edge of the
GND
device, on the right. X5422
Figure 39: XC4000 Series Power Distribution

Power Distribution
Power for the FPGA is distributed through a grid to achieve Pin Descriptions
high noise immunity and isolation between logic and I/O.
Inside the FPGA, a dedicated Vcc and Ground ring sur- There are three types of pins in the XC4000 Series
rounding the logic array provides power to the I/O drivers, devices:
as shown in Figure 39. An independent matrix of Vcc and • Permanently dedicated pins
Ground lines supplies the interior logic of the device. • User I/O pins that can have special functions 6
This power distribution grid provides a stable supply and • Unrestricted user-programmable I/O pins.
ground for all internal logic, providing the external package Before and during configuration, all outputs not used for the
power pins are all connected and appropriately de-coupled. configuration process are 3-stated with a 50 kΩ - 100 kΩ
Typically, a 0.1 µF capacitor connected between each Vcc pull-up resistor.
pin and the board’s Ground plane will provide adequate
After configuration, if an IOB is unused it is configured as
de-coupling.
an input with a 50 kΩ - 100 kΩ pull-up resistor.
Output buffers capable of driving/sinking the specified 12
XC4000 Series devices have no dedicated Reset input.
mA loads under specified worst-case conditions may be
Any user I/O can be configured to drive the Global
capable of driving/sinking up to 10 times as much current
Set/Reset net, GSR. See “Global Set/Reset” on page 11
under best case conditions.
for more information on GSR.
Noise can be reduced by minimizing external load capaci-
XC4000 Series devices have no Powerdown control input,
tance and reducing simultaneous output transitions in the
as the XC3000 and XC2000 families do. The
same direction. It may also be beneficial to locate heavily
XC3000/XC2000 Powerdown control also 3-stated all of the
loaded output buffers near the Ground pads. The I/O Block
device
output buffers have a slew-rate limited mode (default) which
I/O pins. For XC4000 Series devices, use the global 3-state
should be used where output rise and fall times are not
net, GTS, instead. This net 3-states all outputs, but does
speed-critical.
not place the device in low-power mode. See “IOB Output
Signals” on page 23 for more information on GTS.
Device pins for XC4000 Series devices are described in
Table 16. Pin functions during configuration for each of the
seven configuration modes are summarized in Table 22 on
page 58, in the “Configuration Timing” section.
May 14, 1999 (Version 1.6) 6-39

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Table 16: Pin Descriptions
I/O I/O
During After
Pin Name Config. Config. Pin Description
Permanently Dedicated Pins
Eight or more (depending on package) connections to the nominal +5 V supply voltage
VCC I I (+3.3 V for low-voltage devices). All must be connected, and each must be decoupled
with a 0.01 - 0.1 µF capacitor to Ground.
Eight or more (depending on package type) connections to Ground. All must be con-
GND I I
nected.
During configuration, Configuration Clock (CCLK) is an output in Master modes or Asyn-
chronous Peripheral mode, but is an input in Slave mode and Synchronous Peripheral
mode. After configuration, CCLK has a weak pull-up resistor and can be selected as the
CCLK I or O I
Readback Clock. There is no CCLK High or Low time restriction on XC4000 Series de-
vices, except during Readback. See “Violating the Maximum High and Low Time Spec-
ification for the Readback Clock” on page 56 for an explanation of this exception.
DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, it
indicates the completion of the configuration process. As an input, a Low level on DONE
DONE I/O O can be configured to delay the global logic initialization and the enabling of outputs.
The optional pull-up resistor is selected as an option in the XACTstep program that cre-
ates the configuration bitstream. The resistor is included by default.
PROGRAM is an active Low input that forces the FPGA to clear its configuration mem-
ory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGA
finishes the current clear cycle and executes another complete clear cycle, before it
PROGRAM I I
goes into a WAIT state and releases INIT.
The PROGRAM pin has a permanent weak pull-up, so it need not be externally pulled
up to Vcc.
User I/O Pins That Can Have Special Functions
During Peripheral mode configuration, this pin indicates when it is appropriate to write
another byte of data into the FPGA. The same status is also available on D7 in Asyn-
RDY/BUSY O I/O chronous Peripheral mode, if a read operation is performed when the device is selected.
After configuration, RDY/BUSY is a user-programmable I/O pin.
RDY/BUSY is pulled High with a high-impedance pull-up prior to INIT going High.
During Master Parallel configuration, each change on the A0-A17 outputs (A0 - A21 for
XC4000X) is preceded by a rising edge on RCLK, a redundant output signal. RCLK is
RCLK O I/O
useful for clocked PROMs. It is rarely used during configuration. After configuration,
RCLK is a user-programmable I/O pin.
As Mode inputs, these pins are sampled after INIT goes High to determine the configu-
ration mode to be used. After configuration, M0 and M2 can be used as inputs, and M1
can be used as a 3-state output. These three pins have no associated input or output
registers.
I (M0), During configuration, these pins have weak pull-up resistors. For the most popular con-
M0, M1, M2 I O (M1), figuration mode, Slave Serial, the mode pins can thus be left unconnected. The three
I (M2) mode inputs can be individually configured with or without weak pull-up or pull-down re-
sistors. A pull-down resistor value of 4.7 kΩ is recommended.
These pins can only be used as inputs or outputs when called out by special schematic
definitions. To use these pins, place the library components MD0, MD1, and MD2 in-
stead of the usual pad symbols. Input or output buffers must still be used.
If boundary scan is used, this pin is the Test Data Output. If boundary scan is not used,
this pin is a 3-state output without a register, after configuration is completed.
TDO O O This pin can be user output only when called out by special schematic definitions. To
use this pin, place the library component TDO instead of the usual pad symbol. An out-
put buffer must still be used.
6-40 May 14, 1999 (Version 1.6)

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Table 16: Pin Descriptions (Continued)
I/O I/O
During After
If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select
inputs respectively. They come directly from the pads, bypassing the IOBs. These pins
can also be used as inputs to the CLB logic after configuration is completed.
I/O
TDI, TCK, If the BSCAN symbol is not placed in the design, all boundary scan functions are inhib-
I or I
TMS ited once configuration is completed, and these pins become user-programmable I/O.
(JTAG)
In this case, they must be called out by special schematic definitions. To use these pins,
place the library components TDI, TCK, and TMS instead of the usual pad symbols. In-
put or output buffers must still be used.
High During Configuration (HDC) is driven High until the I/O go active. It is available as
HDC O I/O a control output indicating that configuration is not yet completed. After configuration,
HDC is a user-programmable I/O pin.
Low During Configuration (LDC) is driven Low until the I/O go active. It is available as a
LDC O I/O control output indicating that configuration is not yet completed. After configuration,
LDC is a user-programmable I/O pin.
Before and during configuration, INIT is a bidirectional signal. A 1 kΩ - 10 kΩ external
pull-up resistor is recommended.
As an active-Low open-drain output, INIT is held Low during the power stabilization and
internal clearing of the configuration memory. As an active-Low input, it can be used
INIT I/O I/O
to hold the FPGA in the internal WAIT state before the start of configuration. Master 6
mode devices stay in a WAIT state an additional 30 to 300 µs after INIT has gone High.
During configuration, a Low on this output indicates that a configuration data error has
occurred. After the I/O go active, INIT is a user-programmable I/O pin.
Four Primary Global inputs each drive a dedicated internal global net with short delay
PGCK1 - and minimal skew. If not used to drive a global buffer, any of these pins is a user-pro-
PGCK4 Weak grammable I/O.
I or I/O
(XC4000E Pull-up The PGCK1-PGCK4 pins drive the four Primary Global Buffers. Any input pad symbol
only) connected directly to the input of a BUFGP symbol is automatically placed on one of
these pins.
Four Secondary Global inputs each drive a dedicated internal global net with short delay
SGCK1 - and minimal skew. These internal global nets can also be driven from internal logic. If
SGCK4 Weak not used to drive a global net, any of these pins is a user-programmable I/O pin.
I or I/O
(XC4000E Pull-up The SGCK1-SGCK4 pins provide the shortest path to the four Secondary Global Buff-
only) ers. Any input pad symbol connected directly to the input of a BUFGS symbol is auto-
matically placed on one of these pins.
Eight inputs can each drive a Global Low-Skew buffer. In addition, each can drive a Glo-
GCK1 - bal Early buffer. Each pair of global buffers can also be driven from internal logic, but
GCK8 Weak must share an input signal. If not used to drive a global buffer, any of these pins is a
I or I/O
(XC4000X Pull-up user-programmable I/O.
only) Any input pad symbol connected directly to the input of a BUFGLS or BUFGE symbol
is automatically placed on one of these pins.
FCLK1 - Four inputs can each drive a Fast Clock (FCLK) buffer which can deliver a clock signal
FCLK4 to any IOB clock input in the octant of the die served by the Fast Clock buffer. Two Fast
(XC4000XLA Weak Clock buffers serve the two IOB octants on the left side of the die and the other two Fast
I or I/O
and Pull-up Clock buffers serve the two IOB octants on the right side of the die. On each side of the
XC4000XV die, one Fast Clock buffer serves the upper octant and the other serves the lower octant.
only) If not used to drive a Fast Clock buffer, any of these pins is a user-programmable I/O.
May 14, 1999 (Version 1.6) 6-41

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Table 16: Pin Descriptions (Continued)
I/O I/O
During After
These four inputs are used in Asynchronous Peripheral mode. The chip is selected
when CS0 is Low and CS1 is High. While the chip is selected, a Low on Write Strobe
(WS) loads the data present on the D0 - D7 inputs into the internal data buffer. A Low
CS0, CS1, on Read Strobe (RS) changes D7 into a status output — High if Ready, Low if Busy —
I I/O
WS, RS and drives D0 - D6 High.
In Express mode, CS1 is used as a serial-enable signal for daisy-chaining.
WS and RS should be mutually exclusive, but if both are Low simultaneously, the Write
Strobe overrides. After configuration, these are user-programmable I/O pins.
During Master Parallel configuration, these 18 output pins address the configuration
A0 - A17 O I/O
EPROM. After configuration, they are user-programmable I/O pins.
A18 - A21 During Master Parallel configuration with an XC4000X master, these 4 output pins add
(XC4003XL to O I/O 4 more bits to address the configuration EPROM. After configuration, they are user-pro-
XC4085XL) grammable I/O pins. (See Master Parallel Configuration section for additional details.)
During Master Parallel and Peripheral configuration, these eight input pins receive con-
D0 - D7 I I/O
figuration data. After configuration, they are user-programmable I/O pins.
During Slave Serial or Master Serial configuration, DIN is the serial configuration data
DIN I I/O input receiving data on the rising edge of CCLK. During Parallel configuration, DIN is
the D0 input. After configuration, DIN is a user-programmable I/O pin.
During configuration in any mode but Express mode, DOUT is the serial configuration
data output that can drive the DIN of daisy-chained slave FPGAs. DOUT data changes
on the falling edge of CCLK, one-and-a-half CCLK periods after it was received at the
DOUT O I/O DIN input.
In Express modefor XC4000E and XC4000X only, DOUT is the status output that can
drive the CS1 of daisy-chained FPGAs, to enable and disable downstream devices.
After configuration, DOUT is a user-programmable I/O pin.
Unrestricted User-Programmable I/O Pins
These pins can be configured to be input and/or output after configuration is completed.
Weak
I/O I/O Before configuration is completed, these pins have an internal high-value pull-up resis-
Pull-up
tor (25 kΩ - 100 kΩ) that defines the logic level as High.
Boundary Scan of how to enable this circuitry are covered later in this sec-
tion.
The ‘bed of nails’ has been the traditional method of testing
electronic assemblies. This approach has become less By exercising these input signals, the user can serially load
appropriate, due to closer pin spacing and more sophisti- commands and data into these devices to control the driv-
cated assembly methods like surface-mount technology ing of their outputs and to examine their inputs. This
and multi-layer boards. The IEEE Boundary Scan Standard method is an improvement over bed-of-nails testing. It
1149.1 was developed to facilitate board-level testing of avoids the need to over-drive device outputs, and it reduces
electronic assemblies. Design and test engineers can the user interface to four pins. An optional fifth pin, a reset
imbed a standard test logic structure in their device to for the control logic, is described in the standard but is not
achieve high fault coverage for I/O and internal logic. This implemented in Xilinx devices.
structure is easily implemented with a four-pin interface on The dedicated on-chip logic implementing the IEEE 1149.1
any boundary scan-compatible IC. IEEE 1149.1-compati- functions includes a 16-state machine, an instruction regis-
ble devices may be serial daisy-chained together, con- ter and a number of data registers. The functional details
nected in parallel, or a combination of the two. can be found in the IEEE 1149.1 specification and are also
The XC4000 Series implements IEEE 1149.1-compatible discussed in the Xilinx application note XAPP 017: “Bound-
BYPASS, PRELOAD/SAMPLE and EXTEST boundary ary Scan in XC4000 Devices.”
scan instructions. When the boundary scan configuration Figure 40 on page 43 shows a simplified block diagram of
option is selected, three normal user I/O pins become ded- the XC4000E Input/Output Block with boundary scan
icated inputs for these functions. Another user output pin implemented. XC4000X boundary scan logic is identical.
becomes the dedicated boundary scan output. The details
6-42 May 14, 1999 (Version 1.6)

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Figure 41 on page 44 is a diagram of the XC4000 Series data register, respectively, and BSCANT.UPD, which is
boundary scan logic. It includes three bits of Data Register always the last bit of the data register. These three bound-
per IOB, the IEEE 1149.1 Test Access Port controller, and ary scan bits are special-purpose Xilinx test signals.
the Instruction Register with decodes. The other standard data register is the single flip-flop
XC4000 Series devices can also be configured through the BYPASS register. It synchronizes data being passed
boundary scan logic. See “Readback” on page 55. through the FPGA to the next downstream boundary scan
device.
Data Registers
The FPGA provides two additional data registers that can
The primary data register is the boundary scan register. For be specified using the BSCAN macro. The FPGA provides
each IOB pin in the FPGA, bonded or not, it includes three two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are
bits for In, Out and 3-State Control. Non-IOB pins have the decodes of two user instructions. For these instructions,
appropriate partial bit population for In or Out only. PRO- two corresponding pins (BSCAN.TDO1 and
GRAM, CCLK and DONE are not included in the boundary BSCAN.TDO2) allow user scan data to be shifted out on
scan register. Each EXTEST CAPTURE-DR state captures TDO. The data register clock (BSCAN.DRCK) is available
all In, Out, and 3-state pins. for control of test logic which the user may wish to imple-
The data register also includes the following non-pin bits: ment with CLBs. The NAND of TCK and RUN-TEST-IDLE
TDO.T, and TDO.O, which are always bits 0 and 1 of the is also provided (BSCAN.IDLE).
EXTEST SLEW PULL PULL

TS INV M RATE DOWN UP
TS/OE
3-State TS
Boundary
TS - capture VCC 6
Scan
TS - update
OUTPUT
INVERT
OUTPUT
M
sd
D Q
Ouput Data O
EC
M INVERT
Ouput Clock OK M PAD

rd OUT
M S/R SEL
O - capture
Clock Enable Boundary Q - capture
Scan
O - update
M
I - capture
Boundary
Scan
Input Data 1 I1
I - update
M M
sd
Q M M
D
EC Input Data 2 I2
DELAY QL
M INVERT
M
FLIP-FLOP/LATCH
Input Clock IK
rd
M S/R
INPUT
GLOBAL
S/R X5792
Figure 40: Block Diagram of XC4000E IOB with Boundary Scan (some details not shown).
XC4000X Boundary Scan Logic is Identical.
May 14, 1999 (Version 1.6) 6-43

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DATA IN
IOB.T 0
1 sd
D Q D Q 1
0
IOB IOB IOB IOB IOB LE
IOB IOB sd
1
D Q D Q
0
IOB IOB
LE
IOB IOB
1
IOB.I
0
IOB IOB
1 sd
IOB IOB D Q D Q
0
LE
IOB IOB
1
0
IOB IOB IOB.Q
BYPASS
REGISTER
IOB.T 0
M TDO
U 1 sd
INSTRUCTION REGISTER D Q D Q 1
TDI
X 0
LE
1 sd
D Q D Q
0
LE
1
IOB.I
0
DATAOUT UPDATE EXTEST

SHIFT/ CLOCK DATA
CAPTURE REGISTER
X9016
Figure 41: XC4000 Series Boundary Scan Logic
Instruction Set BSDL (Boundary Scan Description Language) files for

XC4000 Series devices are available on the Xilinx FTP site.
The XC4000 Series boundary scan instruction set also
includes instructions to configure the device and read back Including Boundary Scan in a Schematic
the configuration data. The instruction set is coded as
shown in Table 17. If boundary scan is only to be used during configuration, no
special schematic elements need be included in the sche-
Bit Sequence matic or HDL code. In this case, the special boundary scan
pins TDI, TMS, TCK and TDO can be used for user func-
The bit sequence within each IOB is: In, Out, 3-State. The tions after configuration.
input-only M0 and M2 mode pins contribute only the In bit
to the boundary scan I/O data register, while the out- To indicate that boundary scan remain enabled after config-
put-only M1 pin contributes all three bits. uration, place the BSCAN library symbol and connect the
TDI, TMS, TCK and TDO pad symbols to the appropriate
The first two bits in the I/O data register are TDO.T and pins, as shown in Figure 43.
TDO.O, which can be used for the capture of internal sig-
nals. The final bit is BSCANT.UPD, which can be used to Even if the boundary scan symbol is used in a schematic,
drive an internal net. These locations are primarily used by the input pins TMS, TCK, and TDI can still be used as
Xilinx for internal testing. inputs to be routed to internal logic. Care must be taken not
to force the chip into an undesired boundary scan state by
From a cavity-up view of the chip (as shown in XDE or inadvertently applying boundary scan input patterns to
Epic), starting in the upper right chip corner, the boundary these pins. The simplest way to prevent this is to keep TMS
scan data-register bits are ordered as shown in Figure 42. High, and then apply whatever signal is desired to TDI and
The device-specific pinout tables for the XC4000 Series TCK.
include the boundary scan locations for each IOB pin.
6-44 May 14, 1999 (Version 1.6)

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Table 17: Boundary Scan Instructions

Optional To User
Instruction I2 Test I/O Data Logic
TDO Source IBUF
I1 I0 Selected Source
0 0 0 EXTEST DR DR BSCAN
TDI TDI TDO TDO
0 0 1 SAMPLE/PR DR Pin/Logic
TMS TMS DRCK
ELOAD
TCK TCK IDLE
0 1 0 USER 1 BSCAN. User Logic To User
TDO1 SEL1 Logic
TDO1 From
User Logic TDO2 SEL2
0 1 1 USER 2 BSCAN. User Logic X2675
TDO2
1 0 0 READBACK Readback Pin/Logic Figure 43: Boundary Scan Schematic Example
Data
1 0 1 CONFIGURE DOUT Disabled
Configuration
1 1 0 Reserved — — Configuration is the process of loading design-specific pro-
1 1 1 BYPASS Bypass — gramming data into one or more FPGAs to define the func-
Register tional operation of the internal blocks and their
interconnections. This is somewhat like loading the com-
mand registers of a programmable peripheral chip. XC4000
Bit 0 ( TDO end) TDO.T Series devices use several hundred bits of configuration
Bit 1 TDO.O
Bit 2
data per CLB and its associated interconnects. Each con-
Top-edge IOBs (Right to Left) figuration bit defines the state of a static memory cell that
controls either a function look-up table bit, a multiplexer
Left-edge IOBs (Top to Bottom) input, or an interconnect pass transistor. The XACTstep 6
MD1.T development system translates the design into a netlist file.
MD1.O It automatically partitions, places and routes the logic and
MD1.I
MD0.I generates the configuration data in PROM format.
MD2.I
Bottom-edge IOBs (Left to Right)

Special Purpose Pins
Three configuration mode pins (M2, M1, M0) are sampled
Right-edge IOBs (Bottom to Top) prior to configuration to determine the configuration mode.
(TDI end) B SCANT.UPD After configuration, these pins can be used as auxiliary
connections. M2 and M0 can be used as inputs, and M1
X6075 can be used as an output. The XACTstep development sys-
tem does not use these resources unless they are explicitly
Figure 42: Boundary Scan Bit Sequence
specified in the design entry. This is done by placing a spe-
cial pad symbol called MD2, MD1, or MD0 instead of the
Avoiding Inadvertent Boundary Scan
input or output pad symbol.
If TMS or TCK is used as user I/O, care must be taken to
In XC4000 Series devices, the mode pins have weak
ensure that at least one of these pins is held constant dur-
pull-up resistors during configuration. With all three mode
ing configuration. In some applications, a situation may
pins High, Slave Serial mode is selected, which is the most
occur where TMS or TCK is driven during configuration.
popular configuration mode. Therefore, for the most com-
This may cause the device to go into boundary scan mode
mon configuration mode, the mode pins can be left uncon-
and disrupt the configuration process.
nected. (Note, however, that the internal pull-up resistor
To prevent activation of boundary scan during configura- value can be as high as 100 kΩ.) After configuration, these
tion, do either of the following: pins can individually have weak pull-up or pull-down resis-
• TMS: Tie High to put the Test Access Port controller tors, as specified in the design. A pull-down resistor value
in a benign RESET state of 4.7 kΩ is recommended.
• TCK: Tie High or Low—don't toggle this clock input. These pins are located in the lower left chip corner and are
For more information regarding boundary scan, refer to the near the readback nets. This location allows convenient
Xilinx Application Note XAPP 017.001, “Boundary Scan in routing if compatibility with the XC2000 and XC3000 family
XC4000E Devices.“ conventions of M0/RT, M1/RD is desired.
May 14, 1999 (Version 1.6) 6-45

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Configuration Modes Additional Address lines in XC4000 devices

XC4000E devices have six configuration modes. XC4000X The XC4000X devices have additional address lines
devices have the same six modes, plus an additional con- (A18-A21) allowing the additional address space required
figuration mode. These modes are selected by a 3-bit input to daisy-chain several large devices.
code applied to the M2, M1, and M0 inputs. There are three The extra address lines are programmable in XC4000EX
self-loading Master modes, two Peripheral modes, and a devices. By default these address lines are not activated. In
Serial Slave mode, which is used primarily for the default mode, the devices are compatible with existing
daisy-chained devices. The coding for mode selection is XC4000 and XC4000E products. If desired, the extra
shown in Table 18. address lines can be used by specifying the address lines
Table 18: Configuration Modes option in bitgen as 22 (bitgen -g AddressLines:22). The
lines (A18-A21) are driven when a master device detects,
Mode M2 M1 M0 CCLK Data via the bitstream, that it should be using all 22 address
Master Serial 0 0 0 output Bit-Serial lines. Because these pins will initially be pulled high by
Slave Serial 1 1 1 input Bit-Serial internal pull-ups, designers using Master Parallel Up mode
Master 1 0 0 output Byte-Wide, should use external pull down resistors on pins A18-A21. If
Parallel Up increment Master Parallel Down mode is used external resistors are
from 00000 not necessary.
Master 1 1 0 output Byte-Wide, All 22 address lines are always active in Master Parallel
Parallel Down decrement modes with XC4000XL devices. The additional address
from 3FFFF lines behave identically to the lower order address lines. If
Peripheral 0 1 1 input Byte-Wide the Address Lines option in bitgen is set to 18, it will be
Synchronous* ignored by the XC4000XL device.
Peripheral 1 0 1 output Byte-Wide The additional address lines (A18-A21) are not available in
Asynchronous the PC84 package.
Reserved 0 1 0 — —
Peripheral Modes
Reserved 0 0 1 — —
* Can be considered byte-wide Slave Parallel The two Peripheral modes accept byte-wide data from a
bus. A RDY/BUSY status is available as a handshake sig-
A detailed description of each configuration mode, with tim- nal. In Asynchronous Peripheral mode, the internal oscilla-
ing information, is included later in this data sheet. During tor generates a CCLK burst signal that serializes the
configuration, some of the I/O pins are used temporarily for byte-wide data. CCLK can also drive slave devices. In the
the configuration process. All pins used during configura- synchronous mode, an externally supplied clock input to
tion are shown in Table 22 on page 58. CCLK serializes the data.
Master Modes Slave Serial Mode
The three Master modes use an internal oscillator to gener- In Slave Serial mode, the FPGA receives serial configura-
ate a Configuration Clock (CCLK) for driving potential slave tion data on the rising edge of CCLK and, after loading its
devices. They also generate address and timing for exter- configuration, passes additional data out, resynchronized
nal PROM(s) containing the configuration data. on the next falling edge of CCLK.
Master Parallel (Up or Down) modes generate the CCLK Multiple slave devices with identical configurations can be
signal and PROM addresses and receive byte parallel data. wired with parallel DIN inputs. In this way, multiple devices
The data is internally serialized into the FPGA data-frame can be configured simultaneously.
format. The up and down selection generates starting
addresses at either zero or 3FFFF (3FFFFF when 22 Serial Daisy Chain
address lines are used), for compatibility with different Multiple devices with different configurations can be con-
microprocessor addressing conventions. The Master Serial nected together in a “daisy chain,” and a single combined
mode generates CCLK and receives the configuration data bitstream used to configure the chain of slave devices.
in serial form from a Xilinx serial-configuration PROM.
To configure a daisy chain of devices, wire the CCLK pins
CCLK speed is selectable as either 1 MHz (default) or 8 of all devices in parallel, as shown in Figure 51 on page
MHz. Configuration always starts at the default slow fre- 60. Connect the DOUT of each device to the DIN of the
quency, then can switch to the higher frequency during the next. The lead or master FPGA and following slaves each
first frame. Frequency tolerance is -50% to +25%. passes resynchronized configuration data coming from a
single source. The header data, including the length count,
6-46 May 14, 1999 (Version 1.6)

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is passed through and is captured by each FPGA when it tiated and most boundary scan instructions cannot be
recognizes the 0010 preamble. Following the length-count used.
data, each FPGA outputs a High on DOUT until it has The user has some control over the relative timing of these
received its required number of data frames. events and can, therefore, make sure that they occur at the
After an FPGA has received its configuration data, it proper time and the finish point F is reached. Timing is con-
passes on any additional frame start bits and configuration trolled using options in the bitstream generation software.
data on DOUT. When the total number of configuration
clocks applied after memory initialization equals the value XC3000 Master with an XC4000 Series Slave
of the 24-bit length count, the FPGAs begin the start-up Some designers want to use an inexpensive lead device in
sequence and become operational together. FPGA I/O are peripheral mode and have the more precious I/O pins of the
normally released two CCLK cycles after the last configura- XC4000 Series devices all available for user I/O. Figure 44
tion bit is received. Figure 47 on page 53 shows the provides a solution for that case.
start-up timing for an XC4000 Series device.
This solution requires one CLB, one IOB and pin, and an
The daisy-chained bitstream is not simply a concatenation internal oscillator with a frequency of up to 5 MHz as a
of the individual bitstreams. The PROM file formatter must clock source. The XC3000 master device must be config-
be used to combine the bitstreams for a daisy-chained con- ured with late Internal Reset, which is the default option.
figuration.
One CLB and one IOB in the lead XC3000-family device
Multi-Family Daisy Chain are used to generate the additional CCLK pulse required by
the XC4000 Series devices. When the lead device removes
All Xilinx FPGAs of the XC2000, XC3000, and XC4000 the internal RESET signal, the 2-bit shift register responds
Series use a compatible bitstream format and can, there- to its clock input and generates an active Low output signal
fore, be connected in a daisy chain in an arbitrary for the duration of the subsequent clock period. An external
sequence. There is, however, one limitation. The lead connection between this output and CCLK thus creates the 6
device must belong to the highest family in the chain. If the extra CCLK pulse.
chain contains XC4000 Series devices, the master nor-
mally cannot be an XC2000 or XC3000 device.
The reason for this rule is shown in Figure 47 on page 53.
Since all devices in the chain store the same length count
value and generate or receive one common sequence of
CCLK pulses, they all recognize length-count match on the
same CCLK edge, as indicated on the left edge of OE/T
Output
Figure 47. The master device then generates additional Connected
Reset to CCLK
CCLK pulses until it reaches its finish point F. The different 0 0
families generate or require different numbers of additional 1 0 Active Low Output
1 1 Active High Output
CCLK pulses until they reach F. Not reaching F means that 0 1
0 1
the device does not really finish its configuration, although etc
. .
. . X5223
DONE may have gone High, the outputs became active,
and the internal reset was released. For the XC4000 Series Figure 44: CCLK Generation for XC3000 Master
device, not reaching F means that readback cannot be ini- Driving an XC4000 Series Slave
May 14, 1999 (Version 1.6) 6-47

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Setting CCLK Frequency Data Stream Format

For Master modes, CCLK can be generated in either of two The data stream (“bitstream”) format is identical for all con-
frequencies. In the default slow mode, the frequency figuration modes.
ranges from 0.5 MHz to 1.25 MHz for XC4000E and The data stream formats are shown in Table 19. Bit-serial
XC4000EX devices and from 0.6 MHz to 1.8 MHz for data is read from left to right, and byte-parallel data is effec-
XC4000XL devices. In fast CCLK mode, the frequency tively assembled from this serial bitstream, with the first bit
ranges from 4 MHz to 10 MHz for XC4000EX devices and in each byte assigned to D0.
from 5 MHz to 15 MHz for XC4000XL devices. The fre-
quency is selected by an option when running the bitstream The configuration data stream begins with a string of eight
generation software. If an XC4000 Series Master is driving ones, a preamble code, followed by a 24-bit length count
an XC3000- or XC2000-family slave, slow CCLK mode and a separator field of ones. This header is followed by the
must be used. In addition, an XC4000XL device driving a actual configuration data in frames. The length and number
XC4000E or XC4000EX should use slow mode. Slow mode of frames depends on the device type (see Table 20 and
is the default. Table 21). Each frame begins with a start field and ends
with an error check. A postamble code is required to signal
Table 19: XC4000 Series Data Stream Formats
the end of data for a single device. In all cases, additional
All Other start-up bytes of data are required to provide four clocks for
Data Type the startup sequence at the end of configuration. Long
Modes (D0...)
daisy chains require additional startup bytes to shift the last
Fill Byte 11111111b
data through the chain. All startup bytes are don’t-cares;
Preamble Code 0010b
these bytes are not included in bitstreams created by the
Length Count COUNT(23:0) Xilinx software.
Fill Bits 1111b
A selection of CRC or non-CRC error checking is allowed
Start Field 0b by the bitstream generation software. The non-CRC error
Data Frame DATA(n-1:0) checking tests for a designated end-of-frame field for each
CRC or Constant xxxx (CRC) frame. For CRC error checking, the software calculates a
Field Check or 0110b running CRC and inserts a unique four-bit partial check at
Extend Write Cycle — the end of each frame. The 11-bit CRC check of the last
Postamble 01111111b frame of an FPGA includes the last seven data bits.
Start-Up Bytes xxh Detection of an error results in the suspension of data load-
Legend: ing and the pulling down of the INIT pin. In Master modes,
Not shaded Once per bitstream CCLK and address signals continue to operate externally.
Light Once per data frame The user must detect INIT and initialize a new configuration
by pulsing the PROGRAM pin Low or cycling Vcc.
Dark Once per device
6-48 May 14, 1999 (Version 1.6)

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Table 20: XC4000E Program Data
Device XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E

Max Logic Gates 3,000 5,000 6,000 8,000 10,000 13,000 20,000 25,000
CLBs 100 196 256 324 400 576 784 1,024
(Row x Col.) (10 x 10) (14 x 14) (16 x 16) (18 x 18) (20 x 20) (24 x 24) (28 x 28) (32 x 32)
IOBs 80 112 128 144 160 192 224 256
Flip-Flops 360 616 768 936 1,120 1,536 2,016 2,560
Bits per Frame 126 166 186 206 226 266 306 346
Frames 428 572 644 716 788 932 1,076 1,220
Program Data 53,936 94,960 119,792 147,504 178,096 247,920 329,264 422,128
PROM Size 53,984 95,008 119,840 147,552 178,144 247,968 329,312 422,176
(bits)
Notes: 1. Bits per Frame = (10 x number of rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits
Number of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1
Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits
PROM Size = Program Data + 40 (header) + 8
2. The user can add more “one” bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of
any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra “one”
bits, even for extra leading ones at the beginning of the header.
Table 21: XC4000EX/XL Program Data
Device XC4002XL XC4005 XC4010 XC4013 XC4020 XC4028 XC4036 XC4044 XC4052 XC4062 XC4085
Max Logic 2,000 5,000 10,000 13,000 20,000 28,000 36,000 44,000 52,000 62,000 85,000
6
Gates
CLBs 64 196 400 576 784 1,024 1,296 1,600 1,936 2,304 3,136
(Row x (8 x 8) (14 x 14) (20 x 20) (24 x 24) (28 x 28) (32 x 32) (36 x 36) (40 x 40) (44 x 44) (48 x 48) (56 x 56)
Column)
IOBs 64 112 160 192 224 256 288 320 352 384 448
Flip-Flops 256 616 1,120 1,536 2,016 2,560 3,168 3,840 4,576 5,376 7,168
Bits per 133 205 277 325 373 421 469 517 565 613 709
Frame
Frames 459 741 1,023 1,211 1,399 1,587 1,775 1,963 2,151 2,339 2,715
Program Data 61,052 151,910 283,376 393,580 521,832 668,124 832,480 1,014,876 1,215,320 1,433,804 1,924,940
PROM Size 61,104 151,960 283,424 393,632 521,880 668,172 832,528 1,014,924 1,215,368 1,433,852 1,924,992
(bits)
Notes: 1. Bits per frame = (13 x number of rows) + 9 for the top + 17 for the bottom + 8 + 1 start bit + 4 error check bits.
Frames = (47 x number of columns) + 27 for the left edge + 52 for the right edge + 4.
Program data = (bits per frame x number of frames) + 5 postamble bits.
PROM size = (program data + 40 header bits + 8 start bits) rounded up to the nearest byte.
2. The user can add more “one” bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end
of any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra “one”
bits, even for extra leading “ones” at the beginning of the header.
Cyclic Redundancy Check (CRC) for figuration process with a potentially corrupted bitstream is
Configuration and Readback terminated. The FPGA pulls the INIT pin Low and goes into
a Wait state.
The Cyclic Redundancy Check is a method of error detec-
tion in data transmission applications. Generally, the trans- During Readback, 11 bits of the 16-bit checksum are added
mitting system performs a calculation on the serial to the end of the Readback data stream. The checksum is
bitstream. The result of this calculation is tagged onto the computed using the CRC-16 CCITT polynomial, as shown
data stream as additional check bits. The receiving system in Figure 45. The checksum consists of the 11 most signif-
performs an identical calculation on the bitstream and com- icant bits of the 16-bit code. A change in the checksum indi-
pares the result with the received checksum. cates a change in the Readback bitstream. A comparison
to a previous checksum is meaningful only if the readback
Each data frame of the configuration bitstream has four data is independent of the current device state. CLB out-
error bits at the end, as shown in Table 19. If a frame data puts should not be included (Read Capture option not
error is detected during the loading of the FPGA, the con-
May 14, 1999 (Version 1.6) 6-49

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used), and if RAM is present, the RAM content must be

unchanged.
Statistically, one error out of 2048 might go undetected. VCC No
Boundary Scan >3.5 V
Instructions
Configuration Sequence Available:
Yes
There are four major steps in the XC4000 Series power-up

configuration sequence. Test M0 Generate
PROGRAM
One Time-Out Pulse
of 16 or 64 ms = Low
• Configuration Memory Clear
Yes
• Initialization
• Configuration Keep Clearing
Configuration Memory
• Start-Up
The full process is illustrated in Figure 46. EXTEST*
SAMPLE/PRELOAD Completely Clear
Configuration Memory Clear BYPASS Configuration Memory ~1.3 µs per Frame
CONFIGURE* Once More
(* if PROGRAM = High)
When power is first applied or is reapplied to an FPGA, an
internal circuit forces initialization of the configuration logic.
When Vcc reaches an operational level, and the circuit INIT No
High? if
passes the write and read test of a sample pair of configu- Master
ration bits, a time delay is started. This time delay is nomi- Yes Master Waits 50 to 250 µs
Before Sampling Mode Lines
nally 16 ms, and up to 10% longer in the low-voltage
devices. The delay is four times as long when in Master Sample
Mode Lines
Modes (M0 Low), to allow ample time for all slaves to reach
a stable Vcc. When all INIT pins are tied together, as rec- Master CCLK
Goes Active
ommended, the longest delay takes precedence. There-
LDC Output = L, HDC Output = H

Load One
fore, devices with different time delays can easily be mixed Configuration
and matched in a daisy chain. Data Frame
This delay is applied only on power-up. It is not applied

when re-configuring an FPGA by pulsing the PROGRAM Yes
Frame Pull INIT Low
pin Error and Stop
X2 X15 No
X16
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SAMPLE/PRELOAD Config-
BYPASS uration No
memory
SERIAL DATA IN Full
Yes
Polynomial: X16 + X15 + X2 + 1
Pass
Configuration
Data to DOUT
1 1 1 1 1 0 15 14 13 12 11 10 9 8 7 6 5
START BIT
LAST DATA FRAME CRC – CHECKSUM

CCLK
Count Equals No
Length
X1789
Readback Data Stream Count
Yes
Figure 45: Circuit for Generating CRC-16
Start-Up
Sequence
F
I/O Active
Operational
EXTEST
SAMPLE PRELOAD
BYPASS
USER 1 If Boundary Scan
USER 2 is Selected
CONFIGURE
READBACK
X6076
Figure 46: Power-up Configuration Sequence
6-50 May 14, 1999 (Version 1.6)

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Low. During this time delay, or as long as the PROGRAM rise time is excessive or poorly defined. As long as PRO-
input is asserted, the configuration logic is held in a Config- GRAM is Low, the FPGA keeps clearing its configuration
uration Memory Clear state. The configuration-memory memory. When PROGRAM goes High, the configuration
frames are consecutively initialized, using the internal oscil- memory is cleared one more time, followed by the begin-
lator. ning of configuration, provided the INIT input is not exter-
At the end of each complete pass through the frame nally held Low. Note that a Low on the PROGRAM input
addressing, the power-on time-out delay circuitry and the automatically forces a Low on the INIT output. The XC4000
Series PROGRAM pin has a permanent weak pull-up.
level of the PROGRAM pin are tested. If neither is asserted,
the logic initiates one additional clearing of the configura- Using an open-collector or open-drain driver to hold INIT
tion frames and then tests the INIT input. Low before the beginning of configuration causes the
FPGA to wait after completing the configuration memory
Initialization clear operation. When INIT is no longer held Low exter-
During initialization and configuration, user pins HDC, LDC, nally, the device determines its configuration mode by cap-
INIT and DONE provide status outputs for the system inter- turing its mode pins, and is ready to start the configuration
face. The outputs LDC, INIT and DONE are held Low and process. A master device waits up to an additional 250 µs
HDC is held High starting at the initial application of power. to make sure that any slaves in the optional daisy chain
have seen that INIT is High.
The open drain INIT pin is released after the final initializa-
tion pass through the frame addresses. There is a deliber- Start-Up
ate delay of 50 to 250 µs (up to 10% longer for low-voltage
devices) before a Master-mode device recognizes an inac- Start-up is the transition from the configuration process to
the intended user operation. This transition involves a
tive INIT. Two internal clocks after the INIT pin is recognized
as High, the FPGA samples the three mode lines to deter- change from one clock source to another, and a change
from interfacing parallel or serial configuration data where
mine the configuration mode. The appropriate interface 6
most outputs are 3-stated, to normal operation with I/O pins
lines become active and the configuration preamble and
active in the user-system. Start-up must make sure that the
data can be loaded.Configuration
user-logic ‘wakes up’ gracefully, that the outputs become
The 0010 preamble code indicates that the following 24 bits active without causing contention with the configuration sig-
represent the length count. The length count is the total nals, and that the internal flip-flops are released from the
number of configuration clocks needed to load the com- global Reset or Set at the right time.
plete configuration data. (Four additional configuration
Figure 47 describes start-up timing for the three Xilinx fam-
clocks are required to complete the configuration process,
as discussed below.) After the preamble and the length ilies in detail. The configuration modes can use any of the
count have been passed through to all devices in the daisy four timing sequences.
chain, DOUT is held High to prevent frame start bits from To access the internal start-up signals, place the STARTUP
reaching any daisy-chained devices. library symbol.
A specific configuration bit, early in the first frame of a mas- Start-up Timing
ter device, controls the configuration-clock rate and can
increase it by a factor of eight. Therefore, if a fast configu- Different FPGA families have different start-up sequences.
ration clock is selected by the bitstream, the slower clock The XC2000 family goes through a fixed sequence. DONE
rate is used until this configuration bit is detected. goes High and the internal global Reset is de-activated one
Each frame has a start field followed by the frame-configu- CCLK period after the I/O become active.
ration data bits and a frame error field. If a frame data error The XC3000A family offers some flexibility. DONE can be
is detected, the FPGA halts loading, and signals the error programmed to go High one CCLK period before or after
by pulling the open-drain INIT pin Low. After all configura- the I/O become active. Independent of DONE, the internal
tion frames have been loaded into an FPGA, DOUT again global Reset is de-activated one CCLK period before or
follows the input data so that the remaining data is passed after the I/O become active.
on to the next device.
The XC4000 Series offers additional flexibility. The three
Delaying Configuration After Power-Up events — DONE going High, the internal Set/Reset being
de-activated, and the user I/O going active — can all occur
There are two methods of delaying configuration after in any arbitrary sequence. Each of them can occur one
power-up: put a logic Low on the PROGRAM input, or pull
CCLK period before or after, or simultaneous with, any of
the bidirectional INIT pin Low, using an open-collector the others. This relative timing is selected by means of soft-
(open-drain) driver. (See Figure 46 on page 50.) ware options in the bitstream generation software.
A Low on the PROGRAM input is the more radical
approach, and is recommended when the power-supply
May 14, 1999 (Version 1.6) 6-51

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The default option, and the most practical one, is for DONE received since INIT went High equals the loaded value of
to go High first, disconnecting the configuration data source the length count.
and avoiding any contention when the I/Os become active The next rising clock edge sets a flip-flop Q0, shown in
one clock later. Reset/Set is then released another clock Figure 48. Q0 is the leading bit of a 5-bit shift register. The
period later to make sure that user-operation starts from outputs of this register can be programmed to control three
stable internal conditions. This is the most common events.
sequence, shown with heavy lines in Figure 47, but the
designer can modify it to meet particular requirements. • The release of the open-drain DONE output
• The change of configuration-related pins to the user
Normally, the start-up sequence is controlled by the internal function, activating all IOBs.
device oscillator output (CCLK), which is asynchronous to • The termination of the global Set/Reset initialization of
the system clock. all CLB and IOB storage elements.
XC4000 Series offers another start-up clocking option, The DONE pin can also be wire-ANDed with DONE pins of
UCLK_NOSYNC. The three events described above need other FPGAs or with other external signals, and can then
not be triggered by CCLK. They can, as a configuration be used as input to bit Q3 of the start-up register. This is
option, be triggered by a user clock. This means that the called “Start-up Timing Synchronous to Done In” and is
device can wake up in synchronism with the user system. selected by either CCLK_SYNC or UCLK_SYNC.
When the UCLK_SYNC option is enabled, the user can When DONE is not used as an input, the operation is called
externally hold the open-drain DONE output Low, and thus “Start-up Timing Not Synchronous to DONE In,” and is
stall all further progress in the start-up sequence until selected by either CCLK_NOSYNC or UCLK_NOSYNC.
DONE is released and has gone High. This option can be
used to force synchronization of several FPGAs to a com- As a configuration option, the start-up control register
mon user clock, or to guarantee that all devices are suc- beyond Q0 can be clocked either by subsequent CCLK
cessfully configured before any I/Os go active. pulses or from an on-chip user net called STARTUP.CLK.
These signals can be accessed by placing the STARTUP
If either of these two options is selected, and no user clock library symbol.
is specified in the design or attached to the device, the chip
could reach a point where the configuration of the device is Start-up from CCLK
complete and the Done pin is asserted, but the outputs do
If CCLK is used to drive the start-up, Q0 through Q3 pro-
not become active. The solution is either to recreate the bit-
vide the timing. Heavy lines in Figure 47 show the default
stream specifying the start-up clock as CCLK, or to supply
timing, which is compatible with XC2000 and XC3000
the appropriate user clock.
devices using early DONE and late Reset. The thin lines
Start-up Sequence indicate all other possible timing options.
The Start-up sequence begins when the configuration

memory is full, and the total number of configuration clocks
6-52 May 14, 1999 (Version 1.6)

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Length Count Match

CCLK Period
CCLK
F
DONE
I/O
XC2000
Global Reset
F = Finished, no more
F
configuration clocks needed
DONE Daisy-chain lead device
XC3000 must have latest F
I/O
Heavy lines describe
default timing
Global Reset
F
DONE
C1 C2 C3 C4
XC4000E/X I/O
CCLK_NOSYNC
C2 C3 C4
GSR Active 6
C2 C3 C4
DONE IN
F
DONE
C1, C2 or C3
XC4000E/X I/O
CCLK_SYNC
Di Di+1
GSR Active
Di Di+1
F
DONE
C1 U2 U3 U4
I/O
XC4000E/X
UCLK_NOSYNC U2 U3 U4
GSR Active
U2 U3 U4
DONE IN
F
DONE
C1 U2
I/O
XC4000E/X
UCLK_SYNC Di Di+1 Di+2
GSR Active
Di Di+1 Di+2
Synchronization
Uncertainty UCLK Period
X9024
Figure 47: Start-up Timing
May 14, 1999 (Version 1.6) 6-53

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Start-up from a User Clock (STARTUP.CLK) Release of User I/O After DONE Goes High
When, instead of CCLK, a user-supplied start-up clock is By default, the user I/O are released one CCLK cycle after
selected, Q1 is used to bridge the unknown phase relation- the DONE pin goes High. If CCLK is not clocked after
ship between CCLK and the user clock. This arbitration DONE goes High, the outputs remain in their initial state —
causes an unavoidable one-cycle uncertainty in the timing 3-stated, with a 50 kΩ - 100 kΩ pull-up. The delay from
of the rest of the start-up sequence. DONE High to active user I/O is controlled by an option to
the bitstream generation software.
DONE Goes High to Signal End of Configuration
XC4000 Series devices read the expected length count Release of Global Set/Reset After DONE Goes
from the bitstream and store it in an internal register. The High
length count varies according to the number of devices and By default, Global Set/Reset (GSR) is released two CCLK
the composition of the daisy chain. Each device also counts cycles after the DONE pin goes High. If CCLK is not
the number of CCLKs during configuration. clocked twice after DONE goes High, all flip-flops are held
Two conditions have to be met in order for the DONE pin to in their initial set or reset state. The delay from DONE High
go high: to GSR inactive is controlled by an option to the bitstream
generation software.
• the chip's internal memory must be full, and
• the configuration length count must be met, exactly. Configuration Complete After DONE Goes High
This is important because the counter that determines Three full CCLK cycles are required after the DONE pin
when the length count is met begins with the very first goes High, as shown in Figure 47 on page 53. If CCLK is
CCLK, not the first one after the preamble. not clocked three times after DONE goes High, readback
Therefore, if a stray bit is inserted before the preamble, or cannot be initiated and most boundary scan instructions
the data source is not ready at the time of the first CCLK, cannot be used.
the internal counter that holds the number of CCLKs will be
one ahead of the actual number of data bits read. At the
Configuration Through the Boundary Scan
end of configuration, the configuration memory will be full, Pins
but the number of bits in the internal counter will not match XC4000 Series devices can be configured through the
the expected length count. boundary scan pins. The basic procedure is as follows:
As a consequence, a Master mode device will continue to • Power up the FPGA with INIT held Low (or drive the
send out CCLKs until the internal counter turns over to PROGRAM pin Low for more than 300 ns followed by a
zero, and then reaches the correct length count a second High while holding INIT Low). Holding INIT Low allows
time. This will take several seconds [224 ∗ CCLK period] — enough time to issue the CONFIG command to the
which is sometimes interpreted as the device not configur- FPGA. The pin can be used as I/O after configuration if
ing at all. a resistor is used to hold INIT Low.
If it is not possible to have the data ready at the time of the • Issue the CONFIG command to the TMS input
first CCLK, the problem can be avoided by increasing the • Wait for INIT to go High
number in the length count by the appropriate value. The • Sequence the boundary scan Test Access Port to the
XACT User Guide includes detailed information about man- SHIFT-DR state
ually altering the length count. • Toggle TCK to clock data into TDI pin.
Note that DONE is an open-drain output and does not go The user must account for all TCK clock cycles after INIT
High unless an internal pull-up is activated or an external goes High, as all of these cycles affect the Length Count
pull-up is attached. The internal pull-up is activated as the compare.
default by the bitstream generation software. For more detailed information, refer to the Xilinx application
note XAPP017, “Boundary Scan in XC4000 Devices.” This
application note also applies to XC4000E and XC4000X
devices.
6-54 May 14, 1999 (Version 1.6)

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Q3 Q1/Q4
STARTUP DONE
Q2
IN
* IOBs OPERATIONAL PER CONFIGURATION
* GLOBAL SET/RESET OF
ALL CLB AND IOB FLIP-FLOP
1
0
GSR ENABLE
GSR INVERT
STARTUP.GSR CONTROLLED BY STARTUP SYMBOL
IN THE USER SCHEMATIC (SEE
STARTUP.GTS LIBRARIES GUIDE)
GTS INVERT
GTS ENABLE
0
GLOBAL 3-STATE OF ALL IOBs
1
Q S
* DONE
" FINISHED "

1 1 ENABLES BOUNDARY
0 0 SCAN, READBACK AND
CONTROLS THE OSCILLATOR
Q0 Q1 Q2 Q3 Q4
FULL
LENGTH COUNT
S Q D Q D Q
1
D Q D Q
6
0
K K K * K K
CLEAR MEMORY
CCLK 0
STARTUP.CLK 1
USER NET
M
CONFIGURATION BIT OPTIONS SELECTED BY USER IN "MAKEBITS"
* * X1528
Figure 48: Start-up Logic
Readback BACK library symbol and attach the appropriate pad sym-
bols, as shown in Figure 49.
The user can read back the content of configuration mem-
ory and the level of certain internal nodes without interfer- After Readback has been initiated by a High level on
ing with the normal operation of the device. RDBK.TRIG after configuration, the RDBK.RIP (Read In
Progress) output goes High on the next rising edge of
Readback not only reports the downloaded configuration RDBK.CLK. Subsequent rising edges of this clock shift out
bits, but can also include the present state of the device, Readback data on the RDBK.DATA net.
represented by the content of all flip-flops and latches in
CLBs and IOBs, as well as the content of function genera- Readback data does not include the preamble, but starts
tors used as RAMs. with five dummy bits (all High) followed by the Start bit
(Low) of the first frame. The first two data bits of the first
Note that in XC4000 Series devices, configuration data is frame are always High.
not inverted with respect to configuration as it is in XC2000
and XC3000 families. Each frame ends with four error check bits. They are read
back as High. The last seven bits of the last frame are also
XC4000 Series Readback does not use any dedicated read back as High. An additional Start bit (Low) and an
pins, but uses four internal nets (RDBK.TRIG, RDBK.DATA, 11-bit Cyclic Redundancy Check (CRC) signature follow,
RDBK.RIP and RDBK.CLK) that can be routed to any IOB. before RDBK.RIP returns Low.
To access the internal Readback signals, place the READ-
May 14, 1999 (Version 1.6) 6-55

R
IF UNCONNECTED,
DEFAULT IS CCLK
CLK DATA READ_DATA

MD1
READBACK OBUF
READ_TRIGGER TRIG RIP
MD0
IBUF X1786
Figure 49: Readback Schematic Example
Readback Options
I/O I/O
Readback options are: Read Capture, Read Abort, and
Clock Select. They are set with the bitstream generation PROGRAMMABLE
INTERCONNECT
software.
Read Capture
DATA
TRIG
RIP
When the Read Capture option is selected, the readback
I
rdbk I/O I/O I/O rdclk
data stream includes sampled values of CLB and IOB sig-
nals. The rising edge of RDBK.TRIG latches the inverted
values of the four CLB outputs, the IOB output flip-flops and X1787
the input signals I1 and I2. Note that while the bits describ- Figure 50: READBACK Symbol in Graphical Editor
ing configuration (interconnect, function generators, and
RAM content) are not inverted, the CLB and IOB output sig- Violating the Maximum High and Low Time
nals are inverted. Specification for the Readback Clock
When the Read Capture option is not selected, the values The readback clock has a maximum High and Low time
of the capture bits reflect the configuration data originally specification. In some cases, this specification cannot be
written to those memory locations. met. For example, if a processor is controlling readback, an
If the RAM capability of the CLBs is used, RAM data are interrupt may force it to stop in the middle of a readback.
available in readback, since they directly overwrite the F This necessitates stopping the clock, and thus violating the
and G function-table configuration of the CLB. specification.
RDBK.TRIG is located in the lower-left corner of the device, The specification is mandatory only on clocking data at the
as shown in Figure 50. end of a frame prior to the next start bit. The transfer mech-
anism will load the data to a shift register during the last six
Read Abort clock cycles of the frame, prior to the start bit of the follow-
ing frame. This loading process is dynamic, and is the
When the Read Abort option is selected, a High-to-Low
source of the maximum High and Low time requirements.
transition on RDBK.TRIG terminates the readback opera-
tion and prepares the logic to accept another trigger. Therefore, the specification only applies to the six clock
cycles prior to and including any start bit, including the
After an aborted readback, additional clocks (up to one
clocks before the first start bit in the readback data stream.
readback clock per configuration frame) may be required to
At other times, the frame data is already in the register and
re-initialize the control logic. The status of readback is indi-
the register is not dynamic. Thus, it can be shifted out just
cated by the output control net RDBK.RIP. RDBK.RIP is
like a regular shift register.
High whenever a readback is in progress.
The user must precisely calculate the location of the read-
Clock Select back data relative to the frame. The system must keep track
CCLK is the default clock. However, the user can insert of the position within a data frame, and disable interrupts
another clock on RDBK.CLK. Readback control and data before frame boundaries. Frame lengths and data formats
are clocked on rising edges of RDBK.CLK. If readback are listed in Table 19, Table 20 and Table 21.
must be inhibited for security reasons, the readback control
nets are simply not connected. Readback with the XChecker Cable
The XChecker Universal Download/Readback Cable and
RDBK.CLK is located in the lower right chip corner, as Logic Probe uses the readback feature for bitstream verifi-
shown in Figure 50. cation. It can also display selected internal signals on the
PC or workstation screen, functioning as a low-cost in-cir-
cuit emulator.
6-56 May 14, 1999 (Version 1.6)

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XC4000E/EX/XL Program Readback Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements.
The following guidelines reflect worst-case values over the recommended operating conditions.
Finished
Internal Net
rdbk.TRIG
TRCRT TRCRT 2
1 TRTRC 2 1 TRTRC
rdclk.I
4 TRCL TRCH 5
rdbk.RIP
6
TRCRR
rdbk.DATA DUMMY DUMMY VALID VALID
TRCRD
7 X1790
6
E/EX
Description Symbol Min Max Units
rdbk.TRIG rdbk.TRIG setup to initiate and abort Readback 1 TRTRC 200 - ns
rdbk.TRIG hold to initiate and abort Readback 2 TRCRT 50 - ns
rdclk.1 rdbk.DATA delay 7 TRCRD - 250 ns
rdbk.RIP delay 6 TRCRR - 250 ns
High time 5 TRCH 250 500 ns
Low time 4 TRCL 250 500 ns
Note 1: Timing parameters apply to all speed grades.
Note 2: If rdbk.TRIG is High prior to Finished, Finished will trigger the first Readback.
XL
rdbk.TRIG rdbk.TRIG setup to initiate and abort Readback 1 TRTRC 200 - ns
rdbk.TRIG hold to initiate and abort Readback 2 TRCRT 50 - ns
rdclk.1 rdbk.DATA delay 7 TRCRD - 250 ns
rdbk.RIP delay 6 TRCRR - 250 ns
High time 5 TRCH 250 500 ns
Low time 4 TRCL 250 500 ns
Note 1: Timing parameters apply to all speed grades.
Note 2: If rdbk.TRIG is High prior to Finished, Finished will trigger the first Readback.
May 14, 1999 (Version 1.6) 6-57

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Table 22: Pin Functions During Configuration

CONFIGURATION MODE <M2:M1:M0>
SLAVE MASTER SYNCH. ASYNCH. MASTER MASTER
USER
SERIAL SERIAL PERIPHERAL PERIPHERAL PARALLEL DOWN PARALLEL UP
OPERATION
<1:1:1> <0:0:0> <0:1:1> <1:0:1> <1:1:0> <1:0:0>
M2(HIGH) (I) M2(LOW) (I) M2(LOW) (I) M2(HIGH) (I) M2(HIGH) (I) M2(HIGH) (I) (I)
M1(HIGH) (I) M1(LOW) (I) M1(HIGH) (I) M1(LOW) (I) M1(HIGH) (I) M1(LOW) (I) (O)
M0(HIGH) (I) M0(LOW) (I) M0(HIGH) (I) M0(HIGH) (I) M0(LOW) (I) M0(LOW) (I) (I)
HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) I/O
LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) I/O
INIT INIT INIT INIT INIT INIT I/O
DONE DONE DONE DONE DONE DONE DONE
PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM
CCLK (I) CCLK (O) CCLK (I) CCLK (O) CCLK (O) CCLK (O) CCLK (I)
RDY/BUSY (O) RDY/BUSY (O) RCLK (O) RCLK (O) I/O
RS (I) I/O
CS0 (I) I/O
DATA 7 (I) DATA 7 (I) DATA 7 (I) DATA 7 (I) I/O
DIN (I) DIN (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) I/O
DOUT DOUT DOUT DOUT DOUT DOUT SGCK4-GCK5-I/O
TDI TDI TDI TDI TDI TDI TDI-I/O
TCK TCK TCK TCK TCK TCK TCK-I/O
TMS TMS TMS TMS TMS TMS TMS-I/O
TDO TDO TDO TDO TDO TDO TDO-(O)
WS (I) A0 A0 I/O
A1 A1 PGCK4-GCK6-I/O
CS1 A2 A2 I/O
A3 A3 I/O
A4 A4 I/O
A5 A5 I/O
A6 A6 I/O
A7 A7 I/O
A8 A8 I/O
A9 A9 I/O
A10 A10 I/O
A11 A11 I/O
A12 A12 I/O
A13 A13 I/O
A14 A14 I/O
A15 A15 SGCK1-GCK7-I/O
A17 A17 I/O
A18* A18* I/O
A19* A19* I/O
A20* A20* I/O
A21* A21* I/O
ALL OTHERS
6-58 May 14, 1999 (Version 1.6)

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Table 23: Pin Functions During Configuration

CONFIGURATION MODE <M2:M1:M0>
SLAVE MASTER SYNCH. ASYNCH. MASTER MASTER
USER
SERIAL SERIAL PERIPHERAL PERIPHERAL PARALLEL DOWN PARALLEL UP
OPERATION
<1:1:1> <0:0:0> <0:1:1> <1:0:1> <1:1:0> <1:0:0>
M2(HIGH) (I) M2(LOW) (I) M2(LOW) (I) M2(HIGH) (I) M2(HIGH) (I) M2(HIGH) (I) (I)
M1(HIGH) (I) M1(LOW) (I) M1(HIGH) (I) M1(LOW) (I) M1(HIGH) (I) M1(LOW) (I) (O)
M0(HIGH) (I) M0(LOW) (I) M0(HIGH) (I) M0(HIGH) (I) M0(LOW) (I) M0(LOW) (I) (I)
HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) I/O
LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) I/O
INIT INIT INIT INIT INIT INIT I/O
DONE DONE DONE DONE DONE DONE DONE
PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM
CCLK (I) CCLK (O) CCLK (I) CCLK (O) CCLK (O) CCLK (O) CCLK (I)
RDY/BUSY (O) RDY/BUSY (O) RCLK (O) RCLK (O) I/O
RS (I) I/O
CS0 (I) I/O
DATA 1 (I) DATA 1 (I) DATA 1 (I) DATA 1 (I) I/O 6
DIN (I) DIN (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) I/O
DOUT DOUT DOUT DOUT DOUT DOUT SGCK4-GCK5-I/O
TDI TDI TDI TDI TDI TDI TDI-I/O
TCK TCK TCK TCK TCK TCK TCK-I/O
TMS TMS TMS TMS TMS TMS TMS-I/O
TDO TDO TDO TDO TDO TDO TDO-(O)
WS (I) A0 A0 I/O
CS1 A2 A2 I/O
A3 A3 I/O
A4 A4 I/O
A5 A5 I/O
A6 A6 I/O
A7 A7 I/O
A8 A8 I/O
A9 A9 I/O
A10 A10 I/O
A11 A11 I/O
A12 A12 I/O
A13 A13 I/O
A14 A14 I/O
A15 A15 SGCK1-GCK7-I/O
A17 A17 I/O
A18* A18* I/O
A19* A19* I/O
A20* A20* I/O
A21* A21* I/O
ALL OTHERS
* XC4000X only
Notes 1. A shaded table cell represents a 50 kΩ - 100 kΩ pull-up before and during configuration.
2. (I) represents an input; (O) represents an output.
3. INIT is an open-drain output during configuration.
May 14, 1999 (Version 1.6) 6-59

R
Configuration Timing There is an internal delay of 0.5 CCLK periods, which

means that DOUT changes on the falling CCLK edge, and
The seven configuration modes are discussed in detail in the next FPGA in the daisy chain accepts data on the sub-
this section. Timing specifications are included. sequent rising CCLK edge.
Slave Serial Mode Figure 51 shows a full master/slave system. An XC4000
Series device in Slave Serial mode should be connected as
In Slave Serial mode, an external signal drives the CCLK shown in the third device from the left.
input of the FPGA. The serial configuration bitstream must
be available at the DIN input of the lead FPGA a short Slave Serial mode is selected by a <111> on the mode pins
setup time before each rising CCLK edge. (M2, M1, M0). Slave Serial is the default mode if the mode
pins are left unconnected, as they have weak pull-up resis-
The lead FPGA then presents the preamble data—and all tors during configuration.
data that overflows the lead device—on its DOUT pin.
NOTE: NOTE:
M2, M1, M0 can be shorted M2, M1, M0 can be shorted
to Ground if not used as I/O to VCC if not used as I/O
VCC
N/C
4.7 KΩ 4.7 KΩ 4.7 KΩ 4.7 KΩ 4.7 KΩ
4.7 KΩ
M0 M1 M0 M1 M0 M1 PWRDN
M2 N/C M2 M2
DOUT DIN DOUT DIN DOUT
VCC CCLK CCLK

XC4000E/X
MASTER XC1700D +5 V XC4000E/X, XC3100A
4.7 KΩ
SERIAL XC5200 SLAVE
CCLK CLK VPP SLAVE
DIN DATA
PROGRAM LDC CE CEO PROGRAM RESET

DONE INIT RESET/OE DONE INIT D/P INIT
(Low Reset Option Used)
PROGRAM X9025
Figure 51: Master/Slave Serial Mode Circuit Diagram
DIN Bit n Bit n + 1
1 TDCC 2 TCCD 5 TCCL
CCLK
4 TCCH 3 TCCO
DOUT
Bit n - 1 Bit n
(Output)
X5379

DIN setup 1 TDCC 20 ns
DIN hold 2 TCCD 0 ns
DIN to DOUT 3 TCCO 30 ns
CCLK
High time 4 TCCH 45 ns
Low time 5 TCCL 45 ns
Frequency FCC 10 MHz
Note: Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
Figure 52: Slave Serial Mode Programming Switching Characteristics
6-60 May 14, 1999 (Version 1.6)

R
Master Serial Mode For actual timing values please refer to “Configuration
Switching Characteristics” on page 68. Be sure that the
In Master Serial mode, the CCLK output of the lead FPGA serial PROM and slaves are fast enough to support this
drives a Xilinx Serial PROM that feeds the FPGA DIN input. data rate. XC2000, XC3000/A, and XC3100A devices do
Each rising edge of the CCLK output increments the Serial not support the Fast ConfigRate option.
PROM internal address counter. The next data bit is put on
the SPROM data output, connected to the FPGA DIN pin. The SPROM CE input can be driven from either LDC or
The lead FPGA accepts this data on the subsequent rising DONE. Using LDC avoids potential contention on the DIN
CCLK edge. pin, if this pin is configured as user-I/O, but LDC is then
restricted to be a permanently High user output after con-
The lead FPGA then presents the preamble data—and all figuration. Using DONE can also avoid contention on DIN,
data that overflows the lead device—on its DOUT pin. provided the early DONE option is invoked.
There is an internal pipeline delay of 1.5 CCLK periods,
which means that DOUT changes on the falling CCLK Figure 51 on page 60 shows a full master/slave system.
edge, and the next FPGA in the daisy chain accepts data The leftmost device is in Master Serial mode.
on the subsequent rising CCLK edge. Master Serial mode is selected by a <000> on the mode
In the bitstream generation software, the user can specify pins (M2, M1, M0).
Fast ConfigRate, which, starting several bits into the first
frame, increases the CCLK frequency by a factor of eight.
CCLK
(Output)
2 TCKDS
1 TDSCK 6
Serial Data In n n+1 n+2
Serial DOUT n–3 n–2 n–1 n

(Output)
X3223

DIN setup 1 TDSCK 20 ns
CCLK
DIN hold 2 TCKDS 0 ns
Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling PROGRAM
Low until Vcc is valid.
2. Master Serial mode timing is based on testing in slave mode.
Figure 53: Master Serial Mode Programming Switching Characteristics
May 14, 1999 (Version 1.6) 6-61

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Master Parallel Modes Master Parallel Down mode is selected by a <110> on the
mode pins. The EPROM addresses start at 3FFFF and
In the two Master Parallel modes, the lead FPGA directly decrement.
addresses an industry-standard byte-wide EPROM, and
accepts eight data bits just before incrementing or decre- Additional Address lines in XC4000 devices
menting the address outputs.
The XC4000X devices have additional address lines
The eight data bits are serialized in the lead FPGA, which (A18-A21) allowing the additional address space required
then presents the preamble data—and all data that over- to daisy-chain several large devices.
flows the lead device—on its DOUT pin. There is an inter-
The extra address lines are programmable in XC4000EX
nal delay of 1.5 CCLK periods, after the rising CCLK edge
devices. By default these address lines are not activated. In
that accepts a byte of data (and also changes the EPROM
the default mode, the devices are compatible with existing
address) until the falling CCLK edge that makes the LSB
XC4000 and XC4000E products. If desired, the extra
(D0) of this byte appear at DOUT. This means that DOUT
address lines can be used by specifying the address lines
changes on the falling CCLK edge, and the next FPGA in
option in bitgen as 22 (bitgen -g AddressLines:22). The
the daisy chain accepts data on the subsequent rising
lines (A18-A21) are driven when a master device detects,
CCLK edge.
via the bitstream, that it should be using all 22 address
The PROM address pins can be incremented or decre- lines. Because these pins will initially be pulled high by
mented, depending on the mode pin settings. This option internal pull-ups, designers using Master Parallel Up mode
allows the FPGA to share the PROM with a wide variety of should use external pull down resistors on pins A18-A21. If
microprocessors and micro controllers. Some processors Master Parallel Down mode is used external resistors are
must boot from the bottom of memory (all zeros) while oth- not necessary.
ers must boot from the top. The FPGA is flexible and can
All 22 address lines are always active in Master Parallel
load its configuration bitstream from either end of the mem-
modes with XC4000XL devices. The additional address
ory.
lines behave identically to the lower order address lines. If
Master Parallel Up mode is selected by a <100> on the the Address Lines option in bitgen is set to 18, it will be
mode pins (M2, M1, M0). The EPROM addresses start at ignored by the XC4000XL device.
00000 and increment.
The additional address lines (A18-A21) are not available in
the PC84 package.
HIGH TO DIN OF OPTIONAL

or DAISY-CHAINED FPGAS
4.7KΩ N/C
LOW
N/C
M0 M1 M2 TO CCLK OF OPTIONAL
DAISY-CHAINED FPGAS
CCLK
DOUT
NOTE:M0 can be shorted
to Ground if not used A17 ... M0 M1 M2
as I/O.
A16 ... DIN DOUT
VCC
A15 ... EPROM
(8K x 8) CCLK
A14 ...
4.7KΩ (OR LARGER)
USER CONTROL OF HIGHER
INIT A13 ...
ORDER PROM ADDRESS BITS XC4000E/X
CAN BE USED TO SELECT BETWEEN SLAVE
A12 A12
ALTERNATIVE CONFIGURATIONS
A11 A11
PROGRAM
A10 A10
PROGRAM A9 A9
DONE INIT
D7 A8 A8
D6 A7 A7 D7
D5 A6 A6 D6
D4 A5 A5 D5
D3 A4 A4 D4
D2 A3 A3 D3
D1 A2 A2 D2
D0 A1 A1 D1
A0 A0 D0
DONE OE
CE
DATA BUS 8
PROGRAM
X9026
Figure 54: Master Parallel Mode Circuit Diagram
6-62 May 14, 1999 (Version 1.6)

R
A0-A17
(output) Address for Byte n Address for Byte n + 1
1 TRAC
D0-D7
Byte
2 TDRC 3 TRCD
RCLK
(output)
7 CCLKs CCLK
CCLK
(output)
DOUT
(output) D6 D7
Byte n - 1 X6078
Description Symbol Min Max Units 6

Delay to Address valid 1 TRAC 0 200 ns
RCLK Data setup time 2 TDRC 60 ns
Data hold time 3 TRCD 0 ns
Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling PROGRAM
Low until Vcc is valid.
2. The first Data byte is loaded and CCLK starts at the end of the first RCLK active cycle (rising edge).
This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than
500 ns. EPROM data output has no hold-time requirements.
Figure 55: Master Parallel Mode Programming Switching Characteristics
May 14, 1999 (Version 1.6) 6-63

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Synchronous Peripheral Mode The lead FPGA serializes the data and presents the pre-
amble data (and all data that overflows the lead device) on
Synchronous Peripheral mode can also be considered
its DOUT pin. There is an internal delay of 1.5 CCLK peri-
Slave Parallel mode. An external signal drives the CCLK
ods, which means that DOUT changes on the falling CCLK
input(s) of the FPGA(s). The first byte of parallel configura-
edge, and the next FPGA in the daisy chain accepts data
tion data must be available at the Data inputs of the lead on the subsequent rising CCLK edge.
FPGA a short setup time before the rising CCLK edge.
Subsequent data bytes are clocked in on every eighth con- In order to complete the serial shift operation, 10 additional
secutive rising CCLK edge. CCLK rising edges are required after the last data byte has
been loaded, plus one more CCLK cycle for each
The same CCLK edge that accepts data, also causes the daisy-chained device.
RDY/BUSY output to go High for one CCLK period. The pin
name is a misnomer. In Synchronous Peripheral mode it is Synchronous Peripheral mode is selected by a <011> on
really an ACKNOWLEDGE signal. Synchronous operation the mode pins (M2, M1, M0).
does not require this response, but it is a meaningful signal
for test purposes. Note that RDY/BUSY is pulled High with
a high-impedance pullup prior to INIT going High.
NOTE:
M2 can be shorted to Ground
if not used as I/O
N/C 4.7 kΩ N/C
M0 M1 M2 M0 M1 M2
CLOCK CCLK CCLK
OPTIONAL
8 DAISY-CHAINED
DATA BUS D0-7 FPGAs
DOUT DIN DOUT
VCC XC4000E/X XC4000E/X

SYNCHRO- SLAVE
NOUS
4.7 kΩ
PERIPHERAL
CONTROL RDY/BUSY
SIGNALS INIT DONE INIT DONE
4.7 kΩ
PROGRAM PROGRAM PROGRAM
X9027
Figure 56: Synchronous Peripheral Mode Circuit Diagram
6-64 May 14, 1999 (Version 1.6)

R
CCLK
INIT
BYTE BYTE
0 1
BYTE 0 OUT BYTE 1 OUT
DOUT 0 1 2 3 4 5 6 7 0 1
RDY/BUSY
X6096

INIT (High) setup time TIC 5 µs
D0 - D7 setup time TDC 60 ns
6
D0 - D7 hold time TCD 0 ns
CCLK
CCLK High time TCCH 50 ns
CCLK Low time TCCL 60 ns
CCLK Frequency FCC 8 MHz
Notes: 1. Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in the
first data byte on the second rising edge of CCLK after INIT goes High. Subsequent data bytes are clocked in on every
eighth consecutive rising edge of CCLK.
2. The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation does
not require such a response.
3. The pin name RDY/BUSY is a misnomer. In Synchronous Peripheral mode this is really an ACKNOWLEDGE signal.
4. Note that data starts to shift out serially on the DOUT pin 0.5 CCLK periods after it was loaded in parallel. Therefore,
additional CCLK pulses are clearly required after the last byte has been loaded.
Figure 57: Synchronous Peripheral Mode Programming Switching Characteristics
May 14, 1999 (Version 1.6) 6-65

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Asynchronous Peripheral Mode The READY/BUSY handshake can be ignored if the delay
from any one Write to the end of the next Write is guaran-
Write to FPGA teed to be longer than 10 CCLK periods.
Asynchronous Peripheral mode uses the trailing edge of Status Read
the logic AND condition of WS and CS0 being Low and RS
and CS1 being High to accept byte-wide data from a micro- The logic AND condition of the CS0, CS1and RS inputs
processor bus. In the lead FPGA, this data is loaded into a puts the device status on the Data bus.
double-buffered UART-like parallel-to-serial converter and • D7 High indicates Ready
is serially shifted into the internal logic. • D7 Low indicates Busy
The lead FPGA presents the preamble data (and all data • D0 through D6 go unconditionally High
that overflows the lead device) on its DOUT pin. The It is mandatory that the whole start-up sequence be started
RDY/BUSY output from the lead FPGA acts as a hand- and completed by one byte-wide input. Otherwise, the pins
shake signal to the microprocessor. RDY/BUSY goes Low used as Write Strobe or Chip Enable might become active
when a byte has been received, and goes High again when outputs and interfere with the final byte transfer. If this
the byte-wide input buffer has transferred its information transfer does not occur, the start-up sequence is not com-
into the shift register, and the buffer is ready to receive new pleted all the way to the finish (point F in Figure 47 on page
data. A new write may be started immediately, as soon as 53).
the RDY/BUSY output has gone Low, acknowledging
In this case, at worst, the internal reset is not released. At
receipt of the previous data. Write may not be terminated
best, Readback and Boundary Scan are inhibited. The
until RDY/BUSY is High again for one CCLK period. Note
length-count value, as generated by the XACTstep soft-
that RDY/BUSY is pulled High with a high-impedance
pull-up prior to INIT going High. ware, ensures that these problems never occur.
Although RDY/BUSY is brought out as a separate signal,
The length of the BUSY signal depends on the activity in
the UART. If the shift register was empty when the new byte microprocessors can more easily read this information on
was received, the BUSY signal lasts for only two CCLK one of the data lines. For this purpose, D7 represents the
periods. If the shift register was still full when the new byte RDY/BUSY status when RS is Low, WS is High, and the
two chip select lines are both active.
was received, the BUSY signal can be as long as nine
CCLK periods. Asynchronous Peripheral mode is selected by a <101> on
the mode pins (M2, M1, M0).
Note that after the last byte has been entered, only seven of
its bits are shifted out. CCLK remains High with DOUT
equal to bit 6 (the next-to-last bit) of the last byte entered.
N/C
N/C N/C
4.7 kΩ
M0 M1 M2 M0 M1 M2
DATA 8
D0–7 CCLK CCLK
BUS
OPTIONAL
DAISY-CHAINED
FPGAs
DOUT DIN DOUT
VCC ADDRESS CS0
ADDRESS DECODE XC4000E/X
...
BUS LOGIC
ASYNCHRO- XC4000E/X
NOUS SLAVE
4.7 kΩ
PERIPHERAL
4.7 kΩ CS1
RS
WS
CONTROL RDY/BUSY
SIGNALS
INIT INIT
DONE DONE
REPROGRAM
PROGRAM PROGRAM
4.7 kΩ
X9028
Figure 58: Asynchronous Peripheral Mode Circuit Diagram
6-66 May 14, 1999 (Version 1.6)

R
Write to LCA Read Status
WS/CS0 RS, CS0
RS, CS1 WS, CS1

1 TCA
3 TCD 7 4
2 TDC
READY D7
D0-D7
BUSY
CCLK
TWTRB 4
6 TBUSY
RDY/BUSY
DOUT Previous Byte D6 D7 D0 D1 D2
X6097

Effective Write time 1 TCA 100 ns 6
(CS0, WS=Low; RS, CS1=High)
Write
DIN setup time 2 TDC 60 ns
DIN hold time 3 TCD 0 ns
RDY/BUSY delay after end of 4 TWTRB 60 ns
Write or Read
RDY RDY/BUSY active after beginning 7 60 ns
of Read
RDY/BUSY Low output (Note 4) 6 TBUSY 2 9 CCLK
periods
Notes: 1. Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte
processing and the phase of the internal timing generator for CCLK.
3. CCLK and DOUT timing is tested in slave mode.
4. TBUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest
TBUSY occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new word
is loaded into the input register before the second-level buffer has started shifting out data
This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of WS. RDY/BUSY will
go active within 60 ns after the end of WS. A new write may be asserted immediately after RDY/BUSY goes Low, but write
may not be terminated until RDY/BUSY has been High for one CCLK period.
Figure 59: Asynchronous Peripheral Mode Programming Switching Characteristics
May 14, 1999 (Version 1.6) 6-67

R
Configuration Switching Characteristics

Vcc T POR
RE-PROGRAM
>300 ns
PROGRAM
T PI
INIT
T ICCK TCCLK
CCLK OUTPUT or INPUT
<300 ns
M0, M1, M2
VALID DONE RESPONSE
(Required)
X1532
<300 ns
I/O
Master Modes (XC4000E/EX)

M0 = High TPOR 10 40 ms
Power-On Reset M0 = Low TPOR 40 130 ms
Program Latency TPI 30 200 µs per
CLB column
CCLK (output) Delay TICCK 40 250 µs
CCLK (output) Period, slow TCCLK 640 2000 ns
CCLK (output) Period, fast TCCLK 80 250 ns
Master Modes (XC4000XL)

M0 = High TPOR 10 40 ms
Power-On Reset M0 = Low TPOR 40 130 ms
CLB column
CCLK (output) Delay TICCK 40 250 µs
CCLK (output) Period, slow TCCLK 540 1600 ns
CCLK (output) Period, fast TCCLK 67 200 ns
Slave and Peripheral Modes (All)

Power-On Reset TPOR 10 33 ms
CLB column
CCLK (input) Delay (required) TICCK 4 µs
CCLK (input) Period (required) TCCLK 100 ns
6-68 May 14, 1999 (Version 1.6)

R
Product Availability
Table 24, Table 25, and Table 26 show the planned packages and speed grades for XC4000-Series devices. Call your local
sales office for the latest availability information, or see the Xilinx WEBLINX at http://www.xilinx.com for the latest revision of
the specifications.
Table 24: Component Availability Chart for XC4000XL FPGAs

PINS 84 100 100 144 144 160 160 176 176 208 208 240 240 256 299 304 352 411 432 475 559 560
High-Perf.
High-Perf.
High-Perf.
High-Perf.
High-Perf.
High-Perf.
Ceram.
Ceram.
Ceram.
Ceram.
PQFP
VQFP
PQFP
PQFP
PQFP
PLCC
TQFP
TQFP
TQFP
TQFP
Plast.
Plast.
Plast.
Plast.
Plast.
Plast.
Plast.
Plast.
Plast.
Plast.
Plast.
Plast.
BGA
PGA
BGA
PGA
BGA
PGA
PGA
BGA
QFP
QFP
QFP
QFP
TYPE
HQ160
HQ208
HQ240
HQ304
PQ100
VQ100
PQ160
PQ208
PQ240
BG256
PG299
BG352
PG411
BG432
PG475
PG559
BG560
TQ144
TQ176
HT144
HT176
PC84
CODE
-3 CI CI CI
-2 CI CI CI
XC4002XL -1 CI CI CI
-09C C C C
-3 CI CI CI CI CI CI
-2 CI C CI CI CI CI
XC4005XL -1 CI CI CI CI CI CI
-09C C C C C C C
-3 CI CI CI CI CI CI CI
XC4010XL -1 CI CI CI CI CI CI CI
-09C C C C C C C C 6
-09C C C C C C C
-08C C C C C C C
-09C C C C C C C
-09C C C C C C C C
-2 CI CI C CI CI CI CI
-09C C C C C C C C
-08C C C C C C C C
-09C C C C C C C C
-3 CI CI CI CI CI
-2 CI CI CI CI CI
XC4052XL -1 CI CI CI CI CI
-09C C C C C C
-3 CI CI CI CI CI
-2 CI CI CI CI CI
XC4062XL -1 CI CI CI CI CI
-09C C C C C C
-08C C C C C C
-3 CI CI CI
-2 CI CI CI
XC4085XL -1 CI CI CI
-09C C C C
1/29/99
C = Commercial TJ = 0° to +85°C
I= Industrial TJ = -40°C to +100°C
May 14, 1999 (Version 1.6) 6-69

R
Table 25: Component Availability Chart for XC4000E FPGAs

PINS 84 100 100 120 144 156 160 191 208 208 223 225 240 240 299 304
High-Perf.
High-Perf.
High-Perf.
Ceram.
Ceram.
Ceram.
Ceram.
Ceram.
PQFP
VQFP
PQFP
PQFP
PQFP
PLCC
TQFP
Plast.
Plast.
Plast.
Plast.
Plast.
Plast.
Plast.
Plast.
PGA
PGA
PGA
PGA
BGA
PGA
QFP
QFP
QF
TYPE
HQ208
HQ240
HQ304
PQ100
VQ100
PG120
PG156
PQ160
PG191
PQ208
PG223
BG225
PQ240
PG299
TQ144
PC84
CODE
-4 CI CI CI CI
-3 CI CI CI CI
XC4003E -2 CI CI CI CI
-1 C C C C
XC4005E -2 CI CI CI CI CI CI
-1 C C C C C C
-4 CI CI CI CI CI
-3 CI CI CI CI CI
XC4006E -2 CI CI CI CI CI
-1 C C C C C
-4 CI CI CI CI
-3 CI CI CI CI
-1 C C C C
XC4010E -2 CI CI CI CI CI CI
-1 C C C C C C
XC4013E -2 CI CI CI CI CI CI CI
-1 C C C C C C C
-4 CI CI CI
-3 CI CI CI
XC4020E -2 CI CI CI
-1 C C C
-4 CI CI CI CI
-2 C C C C
1/29/99
Table 26: Component Availability Chart for XC4000EX FPGAs

PINS 208 240 299 304 352 411 432
High-Perf. High-Perf. Ceram. High-Perf. Plast. Ceram. Plast.
TYPE
QFP QFP PGA QFP BGA PGA BGA
CODE HQ208 HQ240 PG299 HQ304 BG352 PG411 BG432
-4 CI CI CI CI CI
XC4028EX -3 CI CI CI CI CI
-2 C C C C C
-4 CI CI CI CI CI
XC4036EX -3 CI CI CI CI CI
-2 C C C C C
1/29/99
6-70 May 14, 1999 (Version 1.6)

R
User I/O Per Package

Table 27, Table 28, and Table 29 show the number of user I/Os available in each package for XC4000-Series devices. Call
your local sales office for the latest availability information, or see the Xilinx WEBLINX at http://www.xilinx.com for the latest
revision of the specifications.
Table 27: User I/O Chart for XC4000XL FPGAs

Maximum User Accessible I/O by Package Type
HQ160
HQ208
HQ240
HQ304
PQ100
VQ100
PQ160
PQ208
PQ240
BG256
PG299
BG352
PG411
BG432
PG475
PG559
BG560
TQ144
TQ176
HT144
HT176
PC84
Max
Device I/O
XC4002XL 64 61 64 64
XC4005XL 112 61 77 77 112 112 112
XC4010XL 160 61 77 113 129 145 160 160
XC4013XL 192 113 129 145 160 192 192
XC4020XL 224 113 129 145 160 192 205
XC4028XL 256 129 160 193 205 256 256 256
XC4036XL 288 129 160 193 256 288 288 288
XC4044XL 320 129 160 193 256 289 320 320
XC4052XL 352 193 256 352 352 352
XC4062XL 384 193 256 352 384 384
XC4085XL 448 352 448 448 6

1/29/99
Table 28: User I/O Chart for XC4000E FPGAs
Maximum User Accessible I/O by Package Type

HQ208
HQ240
HQ304
PQ100
VQ100
PG120
PG156
PQ160
PG191
PQ208
PG223
BG225
PQ240
PG299
TQ144
PC84
Max
Device I/O
XC4003E 80 61 77 77 80
XC4005E 112 61 77 112 112 112 112
XC4006E 128 61 113 125 128 128
XC4008E 144 61 129 144 144
XC4010E 160 61 129 160 160 160 160
XC4013E 192 129 160 160 192 192 192 192
XC4020E 224 160 192 193
XC4025E 256 192 193 256 256
1/29/99
Table 29: User I/O Chart for XC4000EX FPGAs
Max Maximum User Accessible I/O by Package Type

Device I/O HQ208 HQ240 PG299 HQ304 BG352 PG411 BG432
XC4028EX 256 160 193 256 256 256
XC4036EX 288 193 256 288 288 288

1/29/99
May 14, 1999 (Version 1.6) 6-71

R
XC4000 Series Electrical Characteristics and Device-Specific Pinout Table

For the latest Electrical Characteristics and package/pinout information for each XC4000 Family, see the Xilinx web site at
http://www.xilinx.com/partinfo/databook.htm#xc4000
Ordering Information
Example: XC4013E-3HQ240C
Device Type
Temperature Range
Speed Grade C = Commercial (TJ = 0 to +85°C)
-6 I = Industrial (TJ = -40 to +100°C)
-5 M = Military (TC = -55 to+125°C)
-4
-3 Number of Pins
-2
-1
Package Type
PC = Plastic Lead Chip Carrier BG = Ball Grid Array
PQ = Plastic Quad Flat Pack PG = Ceramic Pin Grid Array
VQ = Very Thin Quad Flat Pack HQ = High Heat Dissipation Quad Flat Pack
TQ = Thin Quad Flat Pack MQ = Metal Quad Flat Pack
CB = Top Brazed Ceramic Quad Flat Pack
X9020
Revision Control
Version Description
3/30/98 (1.5) Updated XC4000XL timing and added XC4002XL
1/29/99 (1.5) Updated pin diagrams
5/14/99 (1.6) Replaced Electrical Specification and pinout pages for E, EX, and XL families with separate updates and
added URL link for electrical specifications/pinouts for WebLINX users
6-72 May 14, 1999 (Version 1.6)

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© 1994-2006 Xilinx, Inc. All Rights Reserved.
El archivo http://www.dacya.ucm.es/mendias/143/docs/w78c31b.pdf es un documento seguro que se ha incrustado en este
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• Organization: 32,768 words × 8 bits • TTL-compatible, three-state I/O
• High speed • 28-pin JEDEC standard packages
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- 10/12/15/20 ns address access time - 300 mil PDIP and SOJ
- 3/3/4/5 ns output enable access time Socket compatible with 7C512 and 7C1024
• Low power consumption - 8×13.4 TSOP
- Active: 660 mW max (10 ns cycle) • ESD protection ≥ 2000 volts
- Standby: 11 mW max, CMOS I/O • Latch-up current ≥ 200 mA
- Very low DC component in active power • Industrial temperature available (-40° to +85°C)
• 2.0V data retention
• Equal access and cycle times
• Easy memory expansion with CE and OE inputs
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TSOP 8×13.4 DIP, SOJ
Vcc
GND
OE 1 28 A10 A14 1 28 Vcc
Input buffer
A11 2 27 CE A12 2 27 WE
A9 3 26 I/O7 A7 3 26 A13
A8 4 25 I/O6 A6 4 25 A8
A0 A13 5 24 I/O5
I/O7 A5 5 24 A9
A1 WE 6 23 I/O4 A4 6 23 A11
AS7C256
Row decoder
A2 Vcc 7 I/O3
Sense amp
256×128×8 AS7C256 22 A3 7 22 OE
A3 A14 8 21 GND A2 8 21 A10
Array A12 9 20 I/O2 A1 9 20 CE
A4
(262,144) A7 10 19 I/O1 A0 10 19 I/O7
A5
A6 11 18 I/O0 I/O0 11 18 I/O6
A6 12
I/O0 A5 17 A0 I/O1 12 17 I/O5
A14 A4 13 16 A1 I/O2 13 16 I/O4
A3 14 15 A2 GND 14 15 I/O3
Column decoder WE
Control
OE
circuit
CE
A A A A A A A
7 8 9 10 11 12 13
6HOHFWLRQJXLGH
7C256-10 7C256-12 7C256-15 7C256-20 Unit
Maximum address access time 10 12 15 20 ns
Maximum output enable access time 3 3 4 5 ns
Maximum operating current 110 105 100 90 mA
Maximum CMOS standby current 2.0 2.0 2.0 2.0 mA
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Copyright ©1998 Alliance Semiconductor. All rights reserved.
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The AS7C256 is a high performance CMOS 262,144-bit Static Random Access Memory (SRAM) organized as 32,768 words × 8 bits. It is
designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 3/3/4/5 ns are ideal for
high performance applications. A chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations.
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When CE is HIGH the device enters standby mode. The standard AS7C256 is guaranteed not to exceed 11 mW power consumption in
standby mode; the L version is guaranteed not to exceed 2.75 mW, and typically requires only 500 µW. The L version also offers 2.0V data
retention, with maximum power consumption in this mode of 300 µW.
A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is written on the
rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs
have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) HIGH. The chip drives I/O
pins with the data word referenced by the input address. When chip enable or output enable is HIGH, or write enable is LOW, out put drivers
stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply. The AS7C256 is packaged in all high volume
industry standard packages.
$EVROXWHPD[LPXPUDWLQJV
Voltage on any pin relative to GND Vt –0.5 +7.0 V
Power dissipation PD – 1.0 W
Storage temperature (plastic) Tstg –55 +150 oC
Temperature under bias Tbias –10 +85 oC
DC output current Iout – 20 mA

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute max-
imum rating conditions for extended periods may affect reliability.
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CE WE OE Data Mode
H X X High Z Standby (ISB, ISB1)
L H H High Z Output disable
L H L Dout Read
L L X Din Write
X = Don’t Care, L = LOW, H = HIGH
5HFRPPHQGHGRSHUDWLQJFRQGLWLRQV 7D &WR&

Parameter Symbol Min Typ Max Unit
VCC 4.5 5.0 5.5 V
Supply voltage
GND 0.0 0.0 0.0 V
VIH 2.2 – VCC+1 V
Input voltage *
VIL –0.5 – 0.8 V
*VIL min = –3.0V for pulse width less than tRC/2.
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-10 -12 -15 -20
Parameter Symbol Test Conditions Min Max Min Max Min Max Min Max Unit
Input leakage VCC = max,
|ILI| – 1 – 1 – 1 – 1 µA
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current Vin = GND to VCC
Output leakage CE = VIH, VCC = max,
|ILO| – 1 – 1 – 1 – 1 µA
current Vout = GND to VCC
Operating power CE = VIL, f = fmax,
ICC – 110 – 105 – 100 – 90 mA
supply current Iout = 0 mA
ISB CE = VIH, f = fmax – 45 – 40 – 30 – 30 mA
Standby power CE > VCC–0.2V, f = 0,
supply current ISB1 Vin ≤ 0.2V or – 2.0 – 2.0 – 2.0 – 2.0 mA
Vin ≥ VCC–0.2V
VOL IOL = 8 mA, VCC = min – 0.4 – 0.4 – 0.4 – 0.4 V
Output voltage
VOH IOH = –4 mA, VCC = min 2.4 – 2.4 – 2.4 – 2.4 – V
&DSDFLWDQFH2 I 0+]7D 5RRPWHPSHUDWXUH9 && 9

Parameter Symbol Signals Test conditions Max Unit
Input capacitance CIN A, CE, WE, OE Vin = 0V 5 pF
I/O capacitance CI/O I/O Vin = Vout = 0V 7 pF
5HDGF\FOH3,9 9&& 9*1' 97 D &WR&

-10 -12 -15 -20
Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes
Read cycle time tRC 10 – 12 – 15 – 20 – ns
Address access time tAA – 10 – 12 – 15 – 20 ns 3
Chip enable (CE) access time tACE – 10 – 12 – 15 – 20 ns 3
Output enable (OE) access time tOE – 3 – 3 – 4 – 5 ns
Output hold from address change tOH 2 – 3 – 3 – 3 – ns 5
CE LOW to output in Low Z tCLZ 3 – 3 – 3 – 3 – ns 4, 5
CE HIGH to output in High Z tCHZ – 3 – 3 – 4 – 5 ns 4, 5
OE LOW to output in Low Z tOLZ 0 – 0 – 0 – 0 – ns 4, 5
OE HIGH to output in High Z tOHZ – 3 – 3 – 4 – 5 ns 4, 5
Power up time tPU 0 – 0 – 0 – 0 – ns 4, 5
Power down time tPD – 10 – 12 – 15 – 20 ns 4, 5
.H\WRVZLWFKLQJZDYHIRUPV
Rising input Falling input Undefined output/don’t care
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tRC
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tOLZ tOHZ
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Dout Data valid
tCLZ
tPD
ICC
tPU
Supply 50% 50% ISB
current
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-10 -12 -15 -20
Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes
Write cycle time tWC 10 – 12 – 15 – 20 – ns
Chip enable to write end tCW 9 – 10 – 12 – 12 – ns
Address setup to write end tAW 9 – 10 – 12 – 12 – ns
Address setup time tAS 0 – 0 – 0 – 0 – ns
Write pulse width tWP 7 – 8 – 9 – 12 – ns
Address hold from end of write tAH 0 – 0 – 0 – 0 – ns
Data valid to write end tDW 6 – 6 – 8 – 10 – ns
Data hold time tDH 0 – 0 – 0 – 0 – ns 4, 5
Write enable to output in High Z tWZ – 5 – 5 – 5 – 5 ns 4, 5
Output active from write end tOW 3 – 3 – 3 – 3 – ns 4, 5
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tAS tCW
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Dout
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Parameter Symbol Test conditions Min Max Unit
VCC for data retention VDR 2.0 – V
VCC = 2.0V
Data retention current ICCDR – 150 µA
CE ≥ VCC–0.2V
Chip enable to data retention time tCDR 0 – ns
Vin ≥ VCC–0.2V or
Operation recovery time tR tRC – ns
Vin ≤ 0.2V
Input leakage current | ILI | – 1 µA
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VCC 4.5V VDR ≥ 2.0V 4.5V
tCDR tR
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– Output load: see Figure B,
Thevenin equivalent:
except for tCLZ and tCHZ see Figure C.
168W
– Input pulse level: GND to 3.0V. See Figure A. Dout +1.728V
– Input rise and fall times: 5 ns. See Figure A.
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480W 480W
Dout Dout
+3.0V
90% 90% 255W 30 pF* 255W 5 pF* *including scope
and jig capacitance
10% 10%
GND GND GND
Figure A: Input waveform Figure B: Output load Figure C: Output load for tCLZ, tCHZ
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1 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
2 This parameter is sampled and not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A, B, C.
4 tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500mV from steady-state voltage.
5 This parameter is guaranteed but not tested.
6 WE is HIGH for read cycle.
7 CE and OE are LOW for read cycle.
8 Address valid prior to or coincident with CE transition LOW.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE or WE must be HIGH during address transitions.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
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Normalized supply current ICC, ISB Normalized supply current ICC, ISB Normalized supply current ISB1
vs. supply voltage VCC vs. ambient temperature Ta vs. ambient temperature Ta
1.4 1.4
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1.2 1.2 625
Normalized ISB1 (log scale)

ICC ICC VCC = 5.0V
Normalized ICC, ISB
Normalized ICC, ISB

1.0 1.0 25
0.8 0.8 5
0.6 0.6 1
0.4 ISB 0.4 0.2
ISB
0.2 0.2 0.04
0.0 0.0
4.0 4.5 5.0 5.5 6.0 –55 –10 35 80 125 -55 -10 35 80 125
Supply voltage (V) Ambient temperature (°C) Ambient temperature (°C)
Normalized access time tAA Normalized access time tAA Normalized supply current ICC
vs. supply voltage VCC vs. ambient temperature Ta vs. cycle frequency 1/tRC, 1/tWC
1.5 1.5 1.4
1.4 1.4 1.2

Normalized access time
Normalized access time
Ta = 25°C VCC = 5.0V VCC = 5.0V

1.3 1.3 1.0 Ta = 25°C
1.2 1.2 Normalized ICC 0.8
1.1 1.1 0.6
1.0 1.0 0.4
0.9 0.9 0.2
0.8 0.8 0.0

4.0 4.5 5.0 5.5 6.0 –55 –10 35 80 125 0 25 50 75 100
Supply voltage (V) Ambient temperature (°C) Cycle frequency (MHz)
Output source current IOH Output sink current IOL Typical access time change ∆tAA
vs. output voltage VOH vs. output voltage VOL vs. output capacitive loading
140 140 35
Output source current (mA)
120 120 30
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THE I2C-BUS SPECIFICATION
VERSION 2.0
DECEMBER 1998
Philips Semiconductors
The I2C-bus specification
CONTENTS 13.5.1 F/S-mode transfer in a

mixed-speed bus system 25
1 PREFACE 3 13.5.2 Hs-mode transfer in a
1.1 Version 1.0- 1992 3 mixed-speed bus system 25
1.2 Version 2.0- 1998 3 13.5.3 Timing requirements for the bridge in a
1.3 Purchase of Philips I2C-bus components 3 mixed-speed bus system 27
2 THE I2C-BUS BENEFITS DESIGNERS 14 10-BIT ADDRESSING 27
AND MANUFACTURERS 4 14.1 Definition of bits in the first two bytes 27
2.1 Designer benefits 4 14.2 Formats with 10-bit addresses 27
2.2 Manufacturer benefits 6 14.3 General call address and start byte
with 10-bit addressing 30
3 INTRODUCTION TO THE I2C-BUS
SPECIFICATION 6 15 ELECTRICAL SPECIFICATIONS
AND TIMING FOR I/O STAGES
4 THE I2C-BUS CONCEPT 6
AND BUS LINES 30
5 GENERAL CHARACTERISTICS 8
15.1 Standard- and Fast-mode devices 30
6 BIT TRANSFER 8 15.2 Hs-mode devices 34
6.1 Data validity 8 16 ELECTRICAL CONNECTIONS OF
6.2 START and STOP conditions 9 I2C-BUS DEVICES TO THE BUS LINES 37
7 TRANSFERRING DATA 10 16.1 Maximum and minimum values of
7.1 Byte format 10 resistors Rp and Rs for Standard-mode
7.2 Acknowledge 10 I2C-bus devices 39
8 ARBITRATION AND CLOCK 17 APPLICATION INFORMATION 41
GENERATION 11 17.1 Slope-controlled output stages of
8.1 Synchronization 11 Fast-mode I2C-bus devices 41
8.2 Arbitration 12 17.2 Switched pull-up circuit for Fast-
8.3 Use of the clock synchronizing mode I2C-bus devices 41
mechanism as a handshake 13 17.3 Wiring pattern of the bus lines 42
9 FORMATS WITH 7-BIT ADDRESSES 13 17.4 Maximum and minimum values of
resistors Rp and Rs for Fast-mode
10 7-BIT ADDRESSING 15 I2C-bus devices 42
10.1 Definition of bits in the first byte 15 17.5 Maximum and minimum values of
10.1.1 General call address 16 resistors Rp and Rs for Hs-mode
10.1.2 START byte 17 I2C-bus devices 42
10.1.3 CBUS compatibility 18 18 BI-DIRECTIONAL LEVEL SHIFTER
11 EXTENSIONS TO THE STANDARD- FOR F/S-MODE I2C-BUS SYSTEMS 42
MODE I2C-BUS SPECIFICATION 19
18.1 Connecting devices with different
12 FAST-MODE 19 logic levels 43
13 Hs-MODE 20 18.1.1 Operation of level shifter 44
13.1 High speed transfer 20 19 DEVELOPMENT TOOLS AVAILABLE
13.2 Serial data transfer format in Hs-mode 21 FROM PHILIPS 45
13.3 Switching from F/S- to Hs-mode and back 23 20 SUPPORT LITERATURE 46
13.4Hs-mode devices at lower speed modes24
13.5 Mixed speed modes on one serial
bus system 24
2
1 PREFACE 1.2 Version 2.0 - 1998

1.1 Version 1.0 - 1992 The I2C-bushas become a de facto world standard that is
now implemented in over 1000 different ICs and licensed
This version of the 1992 I2C-bus specification includes the
to more than 50 companies. Many of today’s applications,
following modifications:
however, require higher bus speeds and lower supply
• Programming of a slave address by software has been voltages. This updated version of the I2C-bus specification
omitted. The realization of this feature is rather meets those requirements and includes the following
complicated and has not been used. modifications:
• The “low-speed mode” has been omitted. This mode is, • The High-speed mode (Hs-mode) is added. This allows
in fact, a subset of the total I2C-bus specification and an increase in the bit rate up to 3.4 Mbit/s. Hs-mode
need not be specified explicitly. devices can be mixed with Fast- and Standard-mode
• The Fast-mode is added. This allows a fourfold increase devices on the one I2C-bus system with bit rates from 0
of the bit rate up to 400 kbit/s. Fast-mode devices are to 3.4 Mbit/s.
downwards compatible i.e. they can be used in a 0 to • The low output level and hysteresis of devices with a
100 kbit/s I2C-bus system. supply voltage of 2 V and below has been adapted to
• 10-bit addressing is added. This allows 1024 additional meet the required noise margins and to remain
slave addresses. compatible with higher supply voltage devices.
• Slope control and input filtering for Fast-mode devices is • The 0.6 V at 6 mA requirement for the output stages of
specified to improve the EMC behaviour. Fast-mode devices has been omitted.
NOTE: Neither the 100 kbit/s I2C-bus system nor the • The fixed input levels for new devices are replaced by
100 kbit/s devices have been changed. bus voltage-related levels.
• Application information for bi-directional level shifter is
added.
1.3 Purchase of Philips I2C-bus components
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips.
3
2 THE I2C-BUS BENEFITS DESIGNERS AND • The number of ICs that can be connected to the same
MANUFACTURERS bus is limited only by a maximum bus capacitance of
400 pF.
In consumer electronics, telecommunications and
industrial electronics, there are often many similarities Figure 1 shows two examples of I2C-bus applications.
between seemingly unrelated designs. For example,
nearly every system includes: 2.1 Designer benefits
• Some intelligent control, usually a single-chip I2C-bus compatible ICs allow a system design to rapidly
microcontroller progress directly from a functional block diagram to a
• General-purpose circuits like LCD drivers, remote I/O prototype. Moreover, since they ‘clip’ directly onto the
ports, RAM, EEPROM, or data converters I2C-bus without any additional external interfacing, they
allow a prototype system to be modified or upgraded
• Application-oriented circuits such as digital tuning and
simply by ‘clipping’ or ‘unclipping’ ICs to or from the bus.
signal processing circuits for radio and video systems,
or DTMF generators for telephones with tone dialling. Here are some of the features of I2C-bus compatible ICs
which are particularly attractive to designers:
To exploit these similarities to the benefit of both systems
designers and equipment manufacturers, as well as to • Functional blocks on the block diagram correspond with
maximize hardware efficiency and circuit simplicity, Philips the actual ICs; designs proceed rapidly from block
developed a simple bi-directional 2-wire bus for efficient diagram to final schematic.
inter-IC control. This bus is called the Inter IC or I2C-bus. • No need to design bus interfaces because the I2C-bus
At present, Philips’ IC range includes more than 150 interface is already integrated on-chip.
CMOS and bipolar I2C-bus compatible types for • Integrated addressing and data-transfer protocol allow
performing functions in all three of the previously systems to be completely software-defined
mentioned categories. All I2C-bus compatible devices
incorporate an on-chip interface which allows them to • The same IC types can often be used in many different
communicate directly with each other via the I2C-bus. This applications
design concept solves the many interfacing problems • Design-time reduces as designers quickly become
encountered when designing digital control circuits. familiar with the frequently used functional blocks
represented by I2C-bus compatible ICs
Here are some of the features of the I2C-bus:
• ICs can be added to or removed from a system without
• Only two bus lines are required; a serial data line (SDA)
affecting any other circuits on the bus
and a serial clock line (SCL)
• Fault diagnosis and debugging are simple; malfunctions
• Each device connected to the bus is software
can be immediately traced
addressable by a unique address and simple
master/slave relationships exist at all times; masters can • Software development time can be reduced by
operate as master-transmitters or as master-receivers assembling a library of reusable software modules.
• It’s a true multi-master bus including collision detection In addition to these advantages, the CMOS ICs in the
and arbitration to prevent data corruption if two or more I2C-bus compatible range offer designers special features
masters simultaneously initiate data transfer which are particularly attractive for portable equipment and
• Serial, 8-bit oriented, bi-directional data transfers can be battery-backed systems.
made at up to 100 kbit/s in the Standard-mode, up to They all have:
400 kbit/s in the Fast-mode, or up to 3.4 Mbit/s in the
• Extremely low current consumption
High-speed mode
• High noise immunity
• On-chip filtering rejects spikes on the bus data line to
preserve data integrity • Wide supply voltage range
• Wide operating temperature range.
4
handbook, full pagewidth SDA SCL
MICRO-
CONTROLLER
PCB83C528
PLL
SYNTHESIZER
TSA5512
NON-VOLATILE
MEMORY
PCF8582E
M/S COLOUR
DECODER
TDA9160A
STEREO / DUAL
SOUND
DECODER
SDA SCL
TDA9840
PICTURE DTMF
SIGNAL GENERATOR
IMPROVEMENT
TDA4670 PCD3311
HI-FI LINE
AUDIO INTERFACE
PROCESSOR
TDA9860 PCA1070
VIDEO ADPCM
PROCESSOR
TDA4685 PCD5032
SINGLE-CHIP BURST MODE

TEXT CONTROLLER
SAA52XX PCD5042
ON-SCREEN MICRO-
DISPLAY CONTROLLER
PCA8510 P80CLXXX
MSB575
(a) (b)
Fig.1 Two examples of I2C-bus applications: (a) a high performance highly-integrated TV set
(b) DECT cordless phone base-station.
5
2.2 Manufacturer benefits • A system that performs a control function doesn’t

require high-speed data transfer
I2C-bus compatible ICs don’t only assist designers, they
also give a wide range of benefits to equipment • Overall efficiency depends on the devices chosen and
manufacturers because: the nature of the interconnecting bus structure.
• The simple 2-wire serial I2C-bus minimizes To produce a system to satisfy these criteria, a serial bus
interconnections so ICs have fewer pins and there are structure is needed. Although serial buses don’t have the
not so many PCB tracks; result - smaller and less throughput capability of parallel buses, they do require
expensive PCBs less wiring and fewer IC connecting pins. However, a bus
• The completely integrated I2C-bus protocol eliminates is not merely an interconnecting wire, it embodies all the
the need for address decoders and other ‘glue logic’ formats and procedures for communication within the
system.
• The multi-master capability of the I2C-bus allows rapid
testing and alignment of end-user equipment via Devices communicating with each other on a serial bus
external connections to an assembly-line must have some form of protocol which avoids all
possibilities of confusion, data loss and blockage of
• The availability of I2C-bus compatible ICs in SO (small
information. Fast devices must be able to communicate
outline), VSO (very small outline) as well as DIL
with slow devices. The system must not be dependent on
packages reduces space requirements even more.
the devices connected to it, otherwise modifications or
These are just some of the benefits. In addition, I2C-bus improvements would be impossible. A procedure has also
compatible ICs increase system design flexibility by to be devised to decide which device will be in control of
allowing simple construction of equipment variants and the bus and when. And, if different devices with different
easy upgrading to keep designs up-to-date. In this way, an clock speeds are connected to the bus, the bus clock
entire family of equipment can be developed around a source must be defined. All these criteria are involved in
basic model. Upgrades for new equipment, or the specification of the I2C-bus.
enhanced-feature models (i.e. extended memory, remote
control, etc.) can then be produced simply by clipping the
appropriate ICs onto the bus. If a larger ROM is needed, 4 THE I2C-BUS CONCEPT
it’s simply a matter of selecting a micro-controller with a The I2C-bus supports any IC fabrication process (NMOS,
larger ROM from our comprehensive range. As new ICs CMOS, bipolar). Two wires, serial data (SDA) and serial
supersede older ones, it’s easy to add new features to clock (SCL), carry information between the devices
equipment or to increase its performance by simply connected to the bus. Each device is recognized by a
unclipping the outdated IC from the bus and clipping on its unique address (whether it’s a microcontroller, LCD driver,
successor. memory or keyboard interface) and can operate as either
a transmitter or receiver, depending on the function of the
device. Obviously an LCD driver is only a receiver,
3 INTRODUCTION TO THE I2C-BUS SPECIFICATION
whereas a memory can both receive and transmit data. In
For 8-bit oriented digital control applications, such as addition to transmitters and receivers, devices can also be
those requiring microcontrollers, certain design criteria can considered as masters or slaves when performing data
be established: transfers (see Table 1). A master is the device which
• A complete system usually consists of at least one initiates a data transfer on the bus and generates the clock
microcontroller and other peripheral devices such as signals to permit that transfer. At that time, any device
memories and I/O expanders addressed is considered a slave.
• The cost of connecting the various devices within the
system must be minimized
6
Table 1 Definition of I2C-bus terminology 1) Suppose microcontroller A wants to send information to

microcontroller B:
TERM DESCRIPTION
• microcontroller A (master), addresses microcontroller B
Transmitter The device which sends data to the (slave)
bus
• microcontroller A (master-transmitter), sends data to
Receiver The device which receives data from microcontroller B (slave- receiver)
the bus
• microcontroller A terminates the transfer
Master The device which initiates a transfer,
generates clock signals and 2) If microcontroller A wants to receive information from
terminates a transfer microcontroller B:
Slave The device addressed by a master • microcontroller A (master) addresses microcontroller B
(slave)
Multi-master More than one master can attempt to
control the bus at the same time • microcontroller A (master- receiver) receives data from
without corrupting the message microcontroller B (slave- transmitter)
Arbitration Procedure to ensure that, if more • microcontroller A terminates the transfer.
than one master simultaneously tries
Even in this case, the master (microcontroller A) generates
to control the bus, only one is allowed
the timing and terminates the transfer.
to do so and the winning message is
not corrupted The possibility of connecting more than one
Synchronization Procedure to synchronize the clock microcontroller to the I2C-bus means that more than one
signals of two or more devices master could try to initiate a data transfer at the same time.
To avoid the chaos that might ensue from such an event -
an arbitration procedure has been developed. This
The I2C-bus is a multi-master bus. This means that more procedure relies on the wired-AND connection of all I2C
than one device capable of controlling the bus can be interfaces to the I2C-bus.
connected to it. As masters are usually micro-controllers,
let’s consider the case of a data transfer between two If two or more masters try to put information onto the bus,
microcontrollers connected to the I2C-bus (see Fig.2). the first to produce a ‘one’ when the other produces a
‘zero’ will lose the arbitration. The clock signals during
This highlights the master-slave and receiver-transmitter arbitration are a synchronized combination of the clocks
relationships to be found on the I2C-bus. It should be noted generated by the masters using the wired-AND connection
that these relationships are not permanent, but only to the SCL line (for more detailed information concerning
depend on the direction of data transfer at that time. The arbitration see Section 8).
transfer of data would proceed as follows:
MICRO - LCD STATIC

CONTROLLER DRIVER RAM OR
A EEPROM
SDA
SCL
MICRO -
GATE CONTROLLER
ARRAY ADC B
MBC645
Fig.2 Example of an I2C-bus configuration using two microcontrollers.
7
Generation of clock signals on the I2C-bus is always the 6 BIT TRANSFER

responsibility of master devices; each master generates its
Due to the variety of different technology devices (CMOS,
own clock signals when transferring data on the bus. Bus
NMOS, bipolar) which can be connected to the I2C-bus,
clock signals from a master can only be altered when they
the levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not
are stretched by a slow-slave device holding-down the
fixed and depend on the associated level of VDD (see
clock line, or by another master when arbitration occurs.
Section 15 for electrical specifications). One clock pulse is
generated for each data bit transferred.
5 GENERAL CHARACTERISTICS
6.1 Data validity
Both SDA and SCL are bi-directional lines, connected to a
positive supply voltage via a current-source or pull-up The data on the SDA line must be stable during the HIGH
resistor (see Fig.3). When the bus is free, both lines are period of the clock. The HIGH or LOW state of the data line
HIGH. The output stages of devices connected to the bus can only change when the clock signal on the SCL line is
must have an open-drain or open-collector to perform the LOW (see Fig.4).
wired-AND function. Data on the I2C-bus can be
transferred at rates of up to 100 kbit/s in the
Standard-mode, up to 400 kbit/s in the Fast-mode, or up to
3.4 Mbit/s in the High-speed mode. The number of
interfaces connected to the bus is solely dependent on the
bus capacitance limit of 400 pF. For information on
High-speed mode master devices, see Section 13.
VDD
pull-up
Rp Rp
resistors
SDA (Serial Data Line)
SCL (Serial Clock Line)
SCLK SCLK
SCLKN1 DATAN1 SCLKN2 DATAN2

OUT OUT OUT OUT
SCLK DATA SCLK DATA

IN IN IN IN
DEVICE 1 DEVICE 2 MBC631
Fig.3 Connection of Standard- and Fast-mode devices to the I2C-bus.
8
handbook, full pagewidth

SDA
SCL
data line change

stable; of data
data valid allowed MBC621
Fig.4 Bit transfer on the I2C-bus.
6.2 START and STOP conditions The bus stays busy if a repeated START (Sr) is generated
instead of a STOP condition. In this respect, the START
Within the procedure of the I2C-bus, unique situations
(S) and repeated START (Sr) conditions are functionally
arise which are defined as START (S) and STOP (P)
identical (see Fig.6). For the remainder of this document,
conditions (see Fig.5).
therefore, the S symbol will be used as a generic term to
A HIGH to LOW transition on the SDA line while SCL is represent both the START and repeated START
HIGH is one such unique case. This situation indicates a conditions, unless Sr is particularly relevant.
START condition.
Detection of START and STOP conditions by devices
A LOW to HIGH transition on the SDA line while SCL is connected to the bus is easy if they incorporate the
HIGH defines a STOP condition. necessary interfacing hardware. However,
microcontrollers with no such interface have to sample the
START and STOP conditions are always generated by the
SDA line at least twice per clock period to sense the
master. The bus is considered to be busy after the START
transition.
condition. The bus is considered to be free again a certain
time after the STOP condition. This bus free situation is
specified in Section 15.
SDA SDA
SCL SCL
S P
START condition STOP condition

MBC622
Fig.5 START and STOP conditions.
9
7 TRANSFERRING DATA during the HIGH period of this clock pulse (see Fig.7). Of
course, set-up and hold times (specified in Section 15)
7.1 Byte format must also be taken into account.
Every byte put on the SDA line must be 8-bits long. The Usually, a receiver which has been addressed is obliged to
number of bytes that can be transmitted per transfer is generate an acknowledge after each byte has been
unrestricted. Each byte has to be followed by an received, except when the message starts with a CBUS
acknowledge bit. Data is transferred with the most address (see Section 10.1.3).
significant bit (MSB) first (see Fig.6). If a slave can’t
receive or transmit another complete byte of data until it When a slave doesn’t acknowledge the slave address (for
has performed some other function, for example servicing example, it’s unable to receive or transmit because it’s
an internal interrupt, it can hold the clock line SCL LOW to performing some real-time function), the data line must be
force the master into a wait state. Data transfer then left HIGH by the slave. The master can then generate
continues when the slave is ready for another byte of data either a STOP condition to abort the transfer, or a repeated
and releases clock line SCL. START condition to start a new transfer.
In some cases, it’s permitted to use a different format from If a slave-receiver does acknowledge the slave address
the I2C-bus format (for CBUS compatible devices for but, some time later in the transfer cannot receive any
example). A message which starts with such an address more data bytes, the master must again abort the transfer.
can be terminated by generation of a STOP condition, This is indicated by the slave generating the
even during the transmission of a byte. In this case, no not-acknowledge on the first byte to follow. The slave
acknowledge is generated (see Section 10.1.3). leaves the data line HIGH and the master generates a
STOP or a repeated START condition.
7.2 Acknowledge If a master-receiver is involved in a transfer, it must signal
Data transfer with acknowledge is obligatory. The the end of data to the slave- transmitter by not generating
acknowledge-related clock pulse is generated by the an acknowledge on the last byte that was clocked out of
master. The transmitter releases the SDA line (HIGH) the slave. The slave-transmitter must release the data line
during the acknowledge clock pulse. to allow the master to generate a STOP or repeated
START condition.
The receiver must pull down the SDA line during the
acknowledge clock pulse so that it remains stable LOW
handbook, full pagewidth P

SDA
MSB acknowledgement acknowledgement Sr

signal from slave signal from receiver
byte complete,
interrupt within slave
clock line held low while

interrupts are serviced
SCL S Sr
or 1 2 7 8 9 1 2 3-8 9 or
Sr P
ACK ACK
START or STOP or
repeated START repeated START
condition condition
MSC608
Fig.6 Data transfer on the I2C-bus.
10
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER 1 2 8 9
S
clock pulse for
START acknowledgement
condition
MBC602
Fig.7 Acknowledge on the I2C-bus.
8 ARBITRATION AND CLOCK GENERATION that a HIGH to LOW transition on the SCL line will cause
the devices concerned to start counting off their LOW
8.1 Synchronization period and, once a device clock has gone LOW, it will hold
All masters generate their own clock on the SCL line to the SCL line in that state until the clock HIGH state is
transfer messages on the I2C-bus. Data is only valid during reached (see Fig.8). However, the LOW to HIGH transition
the HIGH period of the clock. A defined clock is therefore of this clock may not change the state of the SCL line if
needed for the bit-by-bit arbitration procedure to take another clock is still within its LOW period. The SCL line
place. will therefore be held LOW by the device with the longest
LOW period. Devices with shorter LOW periods enter a
Clock synchronization is performed using the wired-AND HIGH wait-state during this time.
connection of I2C interfaces to the SCL line. This means
start counting
wait HIGH period
state
CLK
1
counter
CLK reset
2
SCL
MBC632
Fig.8 Clock synchronization during the arbitration procedure.
11
When all devices concerned have counted off their LOW to address the same device, arbitration continues with
period, the clock line will be released and go HIGH. There comparison of the data-bits if they are master-transmitter,
will then be no difference between the device clocks and or acknowledge-bits if they are master-receiver. Because
the state of the SCL line, and all the devices will start address and data information on the I2C-bus is determined
counting their HIGH periods. The first device to complete by the winning master, no information is lost during the
its HIGH period will again pull the SCL line LOW. arbitration process.
In this way, a synchronized SCL clock is generated with its A master that loses the arbitration can generate clock
LOW period determined by the device with the longest pulses until the end of the byte in which it loses the
clock LOW period, and its HIGH period determined by the arbitration.
one with the shortest clock HIGH period.
As an Hs-mode master has a unique 8-bit master code, it
will always finish the arbitration during the first byte (see
8.2 Arbitration
Section 13).
A master may start a transfer only if the bus is free. Two or
If a master also incorporates a slave function and it loses
more masters may generate a START condition within the
arbitration during the addressing stage, it’s possible that
minimum hold time (tHD;STA) of the START condition which
the winning master is trying to address it. The losing
results in a defined START condition to the bus.
master must therefore switch over immediately to its slave
Arbitration takes place on the SDA line, while the SCL line mode.
is at the HIGH level, in such a way that the master which
Figure 9 shows the arbitration procedure for two masters.
transmits a HIGH level, while another master is
Of course, more may be involved (depending on how
transmitting a LOW level will switch off its DATA output
many masters are connected to the bus). The moment
stage because the level on the bus doesn’t correspond to
there is a difference between the internal data level of the
its own level.
master generating DATA 1 and the actual level on the SDA
Arbitration can continue for many bits. Its first stage is line, its data output is switched off, which means that a
comparison of the address bits (addressing information is HIGH output level is then connected to the bus. This will
given in Sections 10 and 14). If the masters are each trying not affect the data transfer initiated by the winning master.
handbook, full pagewidth master 1 loses arbitration

DATA 1 SDA
DATA
1
DATA
2
SDA
SCL
S MSC609
Fig.9 Arbitration procedure of two masters.
12
Since control of the I2C-bus is decided solely on the then hold the SCL line LOW after reception and
address or master code and data sent by competing acknowledgment of a byte to force the master into a wait
masters, there is no central master, nor any order of state until the slave is ready for the next byte transfer in a
priority on the bus. type of handshake procedure (see Fig.6).
Special attention must be paid if, during a serial transfer, On the bit level, a device such as a microcontroller with or
the arbitration procedure is still in progress at the moment without limited hardware for the I2C-bus, can slow down
when a repeated START condition or a STOP condition is the bus clock by extending each clock LOW period. The
transmitted to the I2C-bus. If it’s possible for such a speed of any master is thereby adapted to the internal
situation to occur, the masters involved must send this operating rate of this device.
repeated START condition or STOP condition at the same
position in the format frame. In other words, arbitration isn’t In Hs-mode, this handshake feature can only be used on
allowed between: byte level (see Section 13).
• A repeated START condition and a data bit

9 FORMATS WITH 7-BIT ADDRESSES
• A STOP condition and a data bit
• A repeated START condition and a STOP condition. Data transfers follow the format shown in Fig.10. After the
START condition (S), a slave address is sent. This
Slaves are not involved in the arbitration procedure. address is 7 bits long followed by an eighth bit which is a
data direction bit (R/W) - a ‘zero’ indicates a transmission
8.3 Use of the clock synchronizing mechanism as (WRITE), a ‘one’ indicates a request for data (READ). A
a handshake data transfer is always terminated by a STOP condition (P)
In addition to being used during the arbitration procedure, generated by the master. However, if a master still wishes
the clock synchronization mechanism can be used to to communicate on the bus, it can generate a repeated
enable receivers to cope with fast data transfers, on either START condition (Sr) and address another slave without
a byte level or a bit level. first generating a STOP condition. Various combinations of
read/write formats are then possible within such a transfer.
On the byte level, a device may be able to receive bytes of
data at a fast rate, but needs more time to store a received
byte or prepare another byte to be transmitted. Slaves can
SDA
SCL 1–7 8 9 1–7 8 9 1–7 8 9
S P
START ADDRESS R/W ACK DATA ACK DATA ACK STOP

condition condition
MBC604
Fig.10 A complete data transfer.
13
Possible data transfer formats are: NOTES:

• Master-transmitter transmits to slave-receiver. The 1. Combined formats can be used, for example, to
transfer direction is not changed (see Fig.11). control a serial memory. During the first data byte, the
internal memory location has to be written. After the
• Master reads slave immediately after first byte (see
START condition and slave address is repeated, data
Fig.12). At the moment of the first acknowledge, the
can be transferred.
master- transmitter becomes a master- receiver and the
slave-receiver becomes a slave-transmitter. This first 2. All decisions on auto-increment or decrement of
acknowledge is still generated by the slave. The STOP previously accessed memory locations etc. are taken
condition is generated by the master, which has by the designer of the device.
previously sent a not-acknowledge (A). 3. Each byte is followed by an acknowledgment bit as
• Combined format (see Fig.13). During a change of indicated by the A or A blocks in the sequence.
direction within a transfer, the START condition and the 4. I2C-bus compatible devices must reset their bus logic
slave address are both repeated, but with the R/W bit on receipt of a START or repeated START condition
reversed. If a master receiver sends a repeated START such that they all anticipate the sending of a slave
condition, it has previously sent a not-acknowledge (A). address, even if these START conditions are not
positioned according to the proper format.
5. A START condition immediately followed by a STOP
condition (void message) is an illegal format.

,,,,,,
S
,,,
,,,,,, ,,,
,,, ,,
,,,
,,
SLAVE ADDRESS R/W A DATA A DATA A/A P
,,
data transferred
'0' (write) (n bytes + acknowledge)
from master to slave

A = acknowledge (SDA LOW)
A = not acknowledge (SDA HIGH)
from slave to master
S = START condition
MBC605 P = STOP condition
Fig.11 A master-transmitter addressing a slave receiver with a 7-bit address.

The transfer direction is not changed.
,,,,,, ,,,, 1
,,,,,, ,,,,
S SLAVE ADDRESS R/W A DATA A DATA A P
data transferred
MBC606 (read) (n bytes + acknowledge)
Fig.12 A master reads a slave immediately after the first byte.
14
,,,,,
S SLAVE ADDRESS R/W A
read or write
,,,,, ,
DATA A/A Sr SLAVE ADDRESS
(n bytes
+ ack.) *
R/W A DATA A/A
(n bytes
+ ack.) *
P
read or write direction

of transfer
may change
* not shaded because Sr = repeated START condition at this point.
transfer direction of
data and acknowledge bits MBC607
depends on R/W bits.
Fig.13 Combined format.
10 7-BIT ADDRESSING
The addressing procedure for the I2C-bus is such that the
first byte after the START condition usually determines
which slave will be selected by the master. The exception MSB
handbook, halfpage LSB
is the ‘general call’ address which can address all devices. R/W
When this address is used, all devices should, in theory,
respond with an acknowledge. However, devices can be slave address
MBC608
made to ignore this address. The second byte of the
general call address then defines the action to be taken. Fig.14 The first byte after the START procedure.
This procedure is explained in more detail in
Section 10.1.1. For information on 10-bit addressing, see
Section 14
A slave address can be made-up of a fixed and a
programmable part. Since it’s likely that there will be
10.1 Definition of bits in the first byte
several identical devices in a system, the programmable
The first seven bits of the first byte make up the slave part of the slave address enables the maximum possible
address (see Fig.14). The eighth bit is the LSB (least number of such devices to be connected to the I2C-bus.
significant bit). It determines the direction of the message. The number of programmable address bits of a device
A ‘zero’ in the least significant position of the first byte depends on the number of pins available. For example, if
means that the master will write information to a selected a device has 4 fixed and 3 programmable address bits, a
slave. A ‘one’ in this position means that the master will total of 8 identical devices can be connected to the same
read information from the slave. bus.
When an address is sent, each device in a system The I2C-bus committee coordinates allocation of I2C
compares the first seven bits after the START condition addresses. Further information can be obtained from the
with its address. If they match, the device considers itself Philips representatives listed on the back cover. Two
addressed by the master as a slave-receiver or groups of eight addresses (0000XXX and 1111XXX) are
slave-transmitter, depending on the R/W bit. reserved for the purposes shown in Table 2. The bit
combination 11110XX of the slave address is reserved for
10-bit addressing (see Section 14).
15
Table 2 Definition of bits in the first byte

SLAVE LSB
R/W BIT DESCRIPTION
ADDRESS
0 0 0 0 0 0 0 0 A X X X X X X X B A
0000 000 0 General call address
first byte second byte
0000 000 1 START byte(1) (general call address) MBC623
0000 001 X CBUS address(2)

0000 010 X Reserved for different bus
format(3) Fig.15 General call address format.
0000 011 X Reserved for future purposes

0000 1XX X Hs-mode master code
When bit B is a ‘zero’; the second byte has the following
1111 1XX X Reserved for future purposes definition:
1111 0XX X 10-bit slave addressing
• 00000110 (H‘06’). Reset and write programmable part
Notes of slave address by hardware. On receiving this 2-byte
sequence, all devices designed to respond to the
1. No device is allowed to acknowledge at the reception
general call address will reset and take in the
of the START byte.
programmable part of their address. Pre-cautions have
2. The CBUS address has been reserved to enable the to be taken to ensure that a device is not pulling down
inter-mixing of CBUS compatible and I2C-bus the SDA or SCL line after applying the supply voltage,
compatible devices in the same system. I2C-bus since these low levels would block the bus.
compatible devices are not allowed to respond on
• 00000100 (H‘04’). Write programmable part of slave
reception of this address.
address by hardware. All devices which define the
3. The address reserved for a different bus format is programmable part of their address by hardware (and
included to enable I2C and other protocols to be mixed. which respond to the general call address) will latch this
Only I2C-bus compatible devices that can work with programmable part at the reception of this two byte
such formats and protocols are allowed to respond to sequence. The device will not reset.
this address.
• 00000000 (H‘00’). This code is not allowed to be used as
the second byte.
10.1.1 GENERAL CALL ADDRESS
Sequences of programming procedure are published in
The general call address is for addressing every device the appropriate device data sheets.
connected to the I2C-bus. However, if a device doesn’t
need any of the data supplied within the general call The remaining codes have not been fixed and devices
structure, it can ignore this address by not issuing an must ignore them.
acknowledgment. If a device does require data from a When bit B is a ‘one’; the 2-byte sequence is a ‘hardware
general call address, it will acknowledge this address and general call’. This means that the sequence is transmitted
behave as a slave- receiver. The second and following by a hardware master device, such as a keyboard
bytes will be acknowledged by every slave- receiver scanner, which cannot be programmed to transmit a
capable of handling this data. A slave which cannot desired slave address. Since a hardware master doesn’t
process one of these bytes must ignore it by know in advance to which device the message has to be
not-acknowledging. The meaning of the general call transferred, it can only generate this hardware general call
address is always specified in the second byte (see and its own address - identifying itself to the system (see
Fig.15). Fig.16).
There are two cases to consider: The seven bits remaining in the second byte contain the
• When the least significant bit B is a ‘zero’. address of the hardware master. This address is
• When the least significant bit B is a ‘one’. recognized by an intelligent device (e.g. a microcontroller)
connected to the bus which will then direct the information
from the hardware master. If the hardware master can also
act as a slave, the slave address is identical to the master
address.
16
,,,,,,,,
S
,,,,
00000000 A MASTER ADDRESS
general second
(B)
1 A DATA A DATA A
(n bytes + ack.)
P
call address byte MBC624
Fig.16 Data transfer from a hardware master-transmitter.
In some systems, an alternative could be that the an interface, it must constantly monitor the bus via
hardware master transmitter is set in the slave-receiver software. Obviously, the more times the microcontroller
mode after the system reset. In this way, a system monitors, or polls the bus, the less time it can spend
configuring master can tell the hardware master- carrying out its intended function.
transmitter (which is now in slave-receiver mode) to which There is therefore a speed difference between fast
address data must be sent (see Fig.17). After this hardware devices and a relatively slow microcontroller
programming procedure, the hardware master remains in which relies on software polling.
the master-transmitter mode.
In this case, data transfer can be preceded by a start
10.1.2 START BYTE procedure which is much longer than normal (see Fig.18).
The start procedure consists of:
Microcontrollers can be connected to the I2C-bus in two
• A START condition (S)
ways. A microcontroller with an on-chip hardware I2C-bus
interface can be programmed to be only interrupted by • A START byte (00000001)
requests from the bus. When the device doesn’t have such • An acknowledge clock pulse (ACK)
• A repeated START condition (Sr).
,,,,,,,,,,,, ,,
,,,,,,,,,,,,,,
S SLAVE ADDR. H/W MASTER R/W A DUMP ADDR. FOR H/W MASTER X A P
write
,,,,,,,
,, ,,
,,
(a)
,,,,,,,
,,,,,,
S DUMP ADDR. FROM H/W MASTER R/W A DATA A DATA A/A P
MBC609
write
(n bytes + ack.)
(b)
Fig.17 Data transfer by a hardware-transmitter capable of dumping data directly to slave devices.
(a) Configuring master sends dump address to hardware master
(b) Hardware master dumps data to selected slave.
17
SDA dummy
acknowledge
(HIGH)
SCL 1 2 7 8 9
S ACK Sr
start byte 00000001 MBC633
Fig.18 START byte procedure.
After the START condition S has been transmitted by a 10.1.3 CBUS COMPATIBILITY
master which requires bus access, the START byte
CBUS receivers can be connected to the Standard-mode
(00000001) is transmitted. Another microcontroller can
I2C-bus. However, a third bus line called DLEN must then
therefore sample the SDA line at a low sampling rate until
be connected and the acknowledge bit omitted. Normally,
one of the seven zeros in the START byte is detected.
I2C transmissions are sequences of 8-bit bytes; CBUS
After detection of this LOW level on the SDA line, the
compatible devices have different formats.
microcontroller can switch to a higher sampling rate to find
the repeated START condition Sr which is then used for In a mixed bus structure, I2C-bus devices must not
synchronization. respond to the CBUS message. For this reason, a special
CBUS address (0000001X) to which no I2C-bus
A hardware receiver will reset on receipt of the repeated
compatible device will respond, has been reserved. After
START condition Sr and will therefore ignore the START
transmission of the CBUS address, the DLEN line can be
byte.
made active and a CBUS-format transmission sent (see
An acknowledge-related clock pulse is generated after the Fig.19). After the STOP condition, all devices are again
START byte. This is present only to conform with the byte ready to accept data.
handling format used on the bus. No device is allowed to
Master-transmitters can send CBUS formats after sending
acknowledge the START byte.
the CBUS address. The transmission is ended by a STOP
condition, recognized by all devices.
NOTE: If the CBUS configuration is known, and expansion
with CBUS compatible devices isn’t foreseen, the designer
is allowed to adapt the hold time to the specific
requirements of the device(s) used.
18
SDA
SCL
DLEN
S P
START CBUS R/W ACK n - data bits CBUS STOP

condition address bit related load pulse condition
clock pulse
MBC634
Fig.19 Data format of transmissions with CBUS transmitter/receiver.
11 EXTENSIONS TO THE STANDARD-MODE I2C-BUS apparent that more address combinations were required
SPECIFICATION to prevent problems with the allocation of slave
addresses for new devices. This problem was resolved
The Standard-mode I2C-bus specification, with its data with the new 10-bit addressing scheme, which allowed
transfer rate of up to 100 kbit/s and 7-bit addressing, has about a tenfold increase in available addresses.
been in existence since the beginning of the 1980’s. This
concept rapidly grew in popularity and is today accepted New slave devices with a Fast- or Hs-mode I2C-bus
worldwide as a de facto standard with several hundred interface can have a 7- or a 10-bit slave address. If
different compatible ICs on offer from Philips possible, a 7-bit address is preferred as it is the cheapest
Semiconductors and other suppliers. To meet the hardware solution and results in the shortest message
demands for higher speeds, as well as make available length. Devices with 7- and 10-bit addresses can be mixed
more slave address for the growing number of new in the same I2C-bus system regardless of whether it is an
devices, the Standard-mode I2C-bus specification was F/S- or Hs-mode system. Both existing and future masters
upgraded over the years and today is available with the can generate either 7- or 10-bit addresses.
following extensions:
• Fast-mode, with a bit rate up to 400 kbit/s. 12 FAST-MODE
• High-speed mode (Hs-mode), with a bit rate up to With the Fast-mode I2C-bus specification, the protocol,
3.4 Mbit/s. format, logic levels and maximum capacitive load for the
• 10-bit addressing, which allows the use of up to 1024 SDA and SCL lines quoted in the Standard-mode I2C-bus
additional slave addresses. specification are unchanged. New devices with an I2C-bus
interface must meet at least the minimum requirements of
There are two main reasons for extending the regular
the Fast- or Hs-mode specification (see Section 13).
I2C-bus specification:
• Many of today’s applications need to transfer large Fast-mode devices can receive and transmit at up to
amounts of serial data and require bit rates far in excess 400 kbit/s. The minimum requirement is that they can
of 100 kbit/s (Standard-mode), or even 400 kbit/s synchronize with a 400 kbit/s transfer; they can then
(Fast-mode). As a result of continuing improvements in prolong the LOW period of the SCL signal to slow down the
semiconductor technologies, I2C-bus devices are now transfer. Fast-mode devices are downward-compatible
available with bit rates of up to 3.4 Mbit/s (Hs-mode) and can communicate with Standard-mode devices in a
without any noticeable increases in the manufacturing 0 to 100 kbit/s I2C-bus system. As Standard-mode
cost of the interface circuitry. devices, however, are not upward compatible, they should
not be incorporated in a Fast-mode I2C-bus system as
• As most of the 112 addresses available with the 7-bit they cannot follow the higher transfer rate and
addressing scheme were soon allocated, it became unpredictable states would occur.
19
The Fast-mode I2C-bus specification has the following current-source of one master is enabled at any one time,
additional features compared with the Standard-mode: and only during Hs-mode.
• The maximum bit rate is increased to 400 kbit/s. • No arbitration or clock synchronization is performed
• Timing of the serial data (SDA) and serial clock (SCL) during Hs-mode transfer in multi-master systems, which
signals has been adapted. There is no need for speeds-up bit handling capabilities. The arbitration
compatibility with other bus systems such as CBUS procedure always finishes after a preceding master
because they cannot operate at the increased bit rate. code transmission in F/S-mode.
• The inputs of Fast-mode devices incorporate spike • Hs-mode master devices generate a serial clock signal
suppression and a Schmitt trigger at the SDA and SCL with a HIGH to LOW ratio of 1 to 2. This relieves the
inputs. timing requirements for set-up and hold times.
• The output buffers of Fast-mode devices incorporate • As an option, Hs-mode master devices can have a
slope control of the falling edges of the SDA and SCL built-in bridge(1). During Hs-mode transfer, the high
signals. speed data (SDAH) and high-speed serial clock (SCLH)
lines of Hs-mode devices are separated by this bridge
• If the power supply to a Fast-mode device is switched from the SDA and SCL lines of F/S-mode devices. This
off, the SDA and SCL I/O pins must be floating so that reduces the capacitive load of the SDAH and SCLH
they don’t obstruct the bus lines. lines resulting in faster rise and fall times.
• The external pull-up devices connected to the bus lines • The only difference between Hs-mode slave devices
must be adapted to accommodate the shorter maximum and F/S-mode slave devices is the speed at which they
permissible rise time for the Fast-mode I2C-bus. For bus operate. Hs-mode slaves have open-drain output buffers
loads up to 200 pF, the pull-up device for each bus line on the SCLH and SDAH outputs. Optional pull-down
can be a resistor; for bus loads between 200 pF and transistors on the SCLH pin can be used to stretch the
400 pF, the pull-up device can be a current source LOW level of the SCLH signal, although this is only
(3 mA max.) or a switched resistor circuit (see Fig.43). allowed after the acknowledge bit in Hs-mode transfers.
• The inputs of Hs-mode devices incorporate spike
13 Hs-MODE suppression and a Schmitt trigger at the SDAH and
SCLH inputs.
High-speed mode (Hs-mode) devices offer a quantum
leap in I2C-bus transfer speeds. Hs-mode devices can • The output buffers of Hs-mode devices incorporate
transfer information at bit rates of up to 3.4 Mbit/s, yet they slope control of the falling edges of the SDAH and SCLH
remain fully downward compatible with Fast- or signals.
Standard-mode (F/S-mode) devices for bi-directional Figure 20 shows the physical I2C-bus configuration in a
communication in a mixed-speed bus system. With the system with only Hs-mode devices. Pins SDA and SCL on
exception that arbitration and clock synchronization is not the master devices are only used in mixed-speed bus
performed during the Hs-mode transfer, the same serial systems and are not connected in an Hs-mode only
bus protocol and data format is maintained as with the system. In such cases, these pins can be used for other
F/S-mode system. Depending on the application, new functions.
devices may have a Fast or Hs-mode I2C-bus interface,
although Hs-mode devices are preferred as they can be Optional series resistors Rs protect the I/O stages of the
designed-in to a greater number of applications. I2C-bus devices from high-voltage spikes on the bus lines
and minimize ringing and interference.
13.1 High speed transfer Pull-up resistors Rp maintain the SDAH and SCLH lines at
To achieve a bit transfer of up to 3.4 Mbit/s the following a HIGH level when the bus is free and ensure the signals
improvements have been made to the regular I2C-bus are pulled up from a LOW to a HIGH level within the
specification: required rise time. For higher capacitive bus-line loads
(>100 pF), the resistor Rp can be replaced by external
• Hs-mode master devices have an open-drain output
current source pull-ups to meet the rise time requirements.
buffer for the SDAH signal and a combination of an
Unless proceeded by an acknowledge bit, the rise time of
open-drain pull-down and current-source pull-up circuit
the SCLH clock pulses in Hs-mode transfers is shortened
on the SCLH output(1). This current-source circuit
by the internal current-source pull-up circuit MCS of the
shortens the rise time of the SCLH signal. Only the
active master.
(1) Patent application pending.
20
handbook, full pagewidth VDD
Rp Rp
SDAH
SCLH
Rs Rs Rs Rs Rs Rs Rs Rs
(1) (1) (1) (1)
SDAH SCLH SDAH SCLH SDAH SCLH SDA SCL SDAH SCLH SDA SCL
(2) (2) (2) (2) (2) (2) (2) (2)
MCS MCS
(4) (4) (3) (3)
VDD VDD
VSS VSS VSS VSS
SLAVE SLAVE MASTER/SLAVE MASTER/SLAVE

MSC612
(1) SDA and SCL are not used here but may be used for other functions.
(2) To input filter.
(3) Only the active master can enable its current-source pull-up circuit
(4) Dotted transistors are optional open-drain outputs which can stretch the serial clock signal SCLH.
Fig.20 I2C-bus configuration with Hs-mode devices only.
13.2 Serial data transfer format in Hs-mode master code for an Hs-mode master device is software
programmable and is chosen by the System Designer.
Serial data transfer format in Hs-mode meets the
Standard-mode I2C-bus specification. Hs-mode can only Arbitration and clock synchronization only take place
commence after the following conditions (all of which are during the transmission of the master code and
in F/S-mode): not-acknowledge bit (A), after which one winning master
1. START condition (S) remains active. The master code indicates to other
devices that an Hs-mode transfer is to begin and the
2. 8-bit master code (00001XXX) connected devices must meet the Hs-mode specification.
3. not-acknowledge bit (A) As no device is allowed to acknowledge the master code,
the master code is followed by a not-acknowledge (A).
Figures 21 and 22 show this in more detail. This master
code has two main functions: After the not-acknowledge bit (A), and the SCLH line has
• It allows arbitration and synchronization between been pulled-up to a HIGH level, the active master switches
competing masters at F/S-mode speeds, resulting in to Hs-mode and enables (at time tH, see Fig.22) the
one winning master. current-source pull-up circuit for the SCLH signal. As other
devices can delay the serial transfer before tH by stretching
• It indicates the beginning of an Hs-mode transfer.
the LOW period of the SCLH signal, the active master will
Hs-mode master codes are reserved 8-bit codes, which enable its current-source pull-up circuit when all devices
are not used for slave addressing or other purposes. have released the SCLH line and the SCLH signal has
Furthermore, as each master has its own unique master reached a HIGH level, thus speeding up the last part of the
code, up to eight Hs-mode masters can be present on the rise time of the SCLH signal.
one I2C-bus system (although master code 0000 1000
The active master then sends a repeated START condition
should be reserved for test and diagnostic purposes). The
(Sr) followed by a 7-bit slave address (or 10-bit slave
21
address, see Section 14) with a R/W bit address, and SCLH signal reaches a HIGH level, and so speeds up the
receives an acknowledge bit (A) from the selected slave. last part of the SCLH signal’s rise time.
After each acknowledge bit (A) or not-acknowledge bit (A) Data transfer continues in Hs-mode after the next
the active master disables its current-source pull-up repeated START (Sr), and only switches back to
circuit. This enables other devices to delay the serial F/S-mode after a STOP condition (P). To reduce the
transfer by stretching the LOW period of the SCLH signal. overhead of the master code, it’s possible that a master
The active master re-enables its current-source pull-up links a number of Hs-mode transfers, separated by
circuit again when all devices have released and the repeated START conditions (Sr).
,,,,,,,,,, ,,
handbook, full pagewidth Hs-mode (current-source for SCLH enabled)
F/S-mode F/S-mode
,,,,,,,,,,
S MASTER CODE A Sr SLAVE ADD. R/W A DATA
,,
A/A P
,,,,
(n bytes + ack.)
Hs-mode continues
Fig.21 Data transfer format in Hs-mode.

,,,, Sr SLAVE ADD.
MSC616
t1
8-bit Master code 00001xxx A
handbook, full pagewidth S tH
SDAH
SCLH 1 2 to 5 6 7 8 9
F/S mode
7-bit SLA R/W A n × (8-bit DATA + A/A)

Sr Sr P
SDAH
SCLH 1 2 to 5 6 7 8 9 1 2 to 5 6 7 8 9
If P then
Hs-mode F/S mode
If Sr (dotted lines)
then Hs-mode
tH
tFS MSC618
= MCS current source pull-up
= Rp resistor pull-up
Fig.22 A complete Hs-mode transfer.
22
13.3 Switching from F/S- to Hs-mode and back The non-active, or loosing masters:
After reset and initialization, Hs-mode devices must be in 1. Adapt their SDAH and SCLH input filters according to
Fast-mode (which is in effect F/S-mode as Fast-mode is the spike suppression requirement in Hs-mode.
downward compatible with Standard-mode). Each 2. Wait for a STOP condition to detect when the bus is
Hs-mode device can switch from Fast- to Hs-mode and free again.
back and is controlled by the serial transfer on the I2C-bus.
All slaves:
Before time t1 in Fig.22, each connected device operates 1. Adapt their SDAH and SCLH input filters according to
in Fast-mode. Between times t1 and tH (this time interval the spike suppression requirement in Hs-mode.
can be stretched by any device) each connected device
must recognized the “S 00001XXX A” sequence and has 2. Adapt the set-up and hold times according to the
to switch its internal circuit from the Fast-mode setting to Hs-mode requirements. This requirement may already
the Hs-mode setting. Between times t1 and tH the be fulfilled by the adaptation of the input filters.
connected master and slave devices perform this 3. Adapt the slope control of their SDAH output stages, if
switching by the following actions. necessary. For slave devices, slope control is
applicable for the SDAH output stage only and,
The active (winning) master:
depending on circuit tolerances, both the Fast- and
1. Adapts its SDAH and SCLH input filters according to Hs-mode requirements may be fulfilled without
the spike suppression requirement in Hs-mode. switching its internal circuit.
2. Adapts the set-up and hold times according to the At time tFS in Fig.22, each connected device must
Hs-mode requirements. recognize the STOP condition (P) and switch its internal
3. Adapts the slope control of its SDAH and SCLH output circuit from the Hs-mode setting back to the Fast-mode
stages according to the Hs-mode requirement. setting as present before time t1. This must be completed
4. Switches to the Hs-mode bit-rate, which is required within the minimum bus free time as specified in Table 5
after time tH. according to the Fast-mode specification.
5. Enables the current source pull-up circuit of its SCLH
output stage at time tH.
23
13.4 Hs-mode devices at lower speed modes F/S-mode and communicate at F/S-mode speeds with
their current-source disabled. The SDAH and SCLH pins
Hs-mode devices are fully downwards compatible, and
are used to connect to the F/S-mode bus system, allowing
can be connected to an F/S-mode I2C-bus system (see
the SDA and SCL pins (if present) on the Hs-mode master
Fig.23). As no master code will be transmitted in such a
device to be used for other functions.
configuration, all Hs-mode master devices stay in
handbook, full pagewidth VDD
Rp Rp
SDA
SCL
Rs Rs Rs Rs Rs Rs Rs Rs Rs Rs
(1) (1)
SDAH SCLH SDAH SCLH SDAH SCLH SDA SCL SDA SCL SDA SCL
(2) (2) (2) (2) (2) (2) (2) (2) (2) (2)
(3)
(4) (4) (4)
VDD
VSS VSS VSS VSS VSS
Hs-mode Hs-mode Hs-mode F/S-mode F/S-mode

SLAVE SLAVE MASTER/SLAVE MASTER/SLAVE SLAVE MSC613
(1) Bridge not used. SDA and SCL may have an alternative function.
(3) The current-source pull-up circuit stays disabled.
(4) Dotted transistors are optional open-drain outputs which can stretch the serial clock signal SCL.
Fig.23 Hs-mode devices at F/S-mode speed.
13.5 Mixed speed modes on one serial bus system a high impedance between the drain and source of each
switched on transistor. In the latter case, the transistors will
If a system has a combination of Hs-, Fast- and/or
act as a level shifter as SDAH and SCLH will be pulled-up
Standard-mode devices, it’s possible, by using an
to VDD1 and SDA and SCL will be pulled-up to VDD2
interconnection bridge, to have different bit rates between
different devices (see Figs 24 and 25). During F/S-mode speed, a bridge on one of the Hs-mode
masters connects the SDAH and SCLH lines to the
One bridge is required to connect/disconnect an Hs-mode
corresponding SDA and SCL lines thus permitting
section to/from an F/S-mode section at the appropriate
Hs-mode devices to communicate with F/S-mode devices
time. This bridge includes a level shift function that allows
at slower speeds. Arbitration and synchronization is
devices with different supply voltages to be connected. For
possible during the total F/S-mode transfer between all
example F/S-mode devices with a VDD2 of 5 V can be
connected devices as described in Section 8. During
connected to Hs-mode devices with a VDD1 of 3 V or less
Hs-mode transfer, however, the bridge opens to separate
(i.e. where VDD2 ≥ VDD1), provided SDA and SCL pins are
the two bus sections and allows Hs-mode devices to
5 V tolerant. This bridge is incorporated in Hs-mode
communicate with each other at 3.4 Mbit/s. Arbitration
master devices and is completely controlled by the serial
between Hs-mode devices and F/S-mode devices is only
signals SDAH, SCLH, SDA and SCL. Such a bridge can be
performed during the master code (00001XXX), and
implemented in any IC as an autonomous circuit.
normally won by one Hs-mode master as no slave address
TR1, TR2 and TR3 are N-channel transistors. TR1 and has four leading zeros. Other masters can win the
TR2 have a transfer gate function, and TR3 is an open- arbitration only if they send a reserved 8-bit code
drain pull-down stage. If TR1 or TR2 are switched on they (00000XXX). In such cases, the bridge remains closed
transfer a LOW level in both directions, otherwise when and the transfer proceeds in F/S-mode. Table 3 gives the
both the drain and source rise to a HIGH level there will be possible communication speeds in such a system.
24
VDD1 VDD2
Rp Rp BRIDGE Rp Rp
Rs TR1
SDAH SDAH SDA
Rs TR2
SCLH SCLH SCL
Rs Rs Rs Rs Rs Rs Rs Rs Rs Rs
TR3
(1) (1)
SDAH SCLH SDAH SCLH SDAH SCLH SDA SCL VSS SDA SCL SDA SCL
(2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2)
MCS MCS
(4) (4) (3) (3) (4)
VDD VDD
VSS VSS VSS VSS VSS VSS
Hs-mode Hs-mode Hs-mode Hs-mode F/S-mode F/S-mode

SLAVE SLAVE MASTER/SLAVE MASTER/SLAVE MASTER/SLAVE SLAVE
MSC614
(1) Bridge not used. SDA and SCL may have an alternative function.
(3) Only the active master can enable its current-source pull-up circuit.
(4) Dotted transistors are optional open-drain outputs which can stretch the serial clock signal SCL or SCLH.
Fig.24 Bus system with transfer at Hs- and F/S-mode speeds.
Table 3 Communication bit-rates in a mixed speed bus system

SERIAL BUS SYSTEM CONFIGURATION
TRANSFER
BETWEEN Hs + FAST + FAST +
Hs + FAST Hs + STANDARD
STANDARD STANDARD
Hs <–> Hs 0 to 3.4 Mbit/s 0 to 3.4 Mbit/s 0 to 3.4 Mbit/s –
Hs <–> Fast 0 to 100 kbit/s 0 to 400 kbit/s – –
Hs <–> Standard 0 to 100 kbit/s – 0 to 100 kbit/s –
Fast <–> Standard 0 to 100 kbit/s – – 0 to 100 kbit/s
Fast <–> Fast 0 to 100 kbit/s 0 to 400 kbit/s – 0 to 100 kbit/s
Standard <–> Standard 0 to 100 kbit/s – 0 to 100 kbit/s 0 to 100 kbit/s
13.5.1 F/S-MODE TRANSFER IN A MIXED-SPEED BUS 13.5.2 HS-MODE TRANSFER IN A MIXED-SPEED BUS
SYSTEM SYSTEM
The bridge shown in Fig.24 interconnects corresponding Figure 25 shows the timing diagram of a complete
serial bus lines, forming one serial bus system. As no Hs-mode transfer, which is invoked by a START condition,
master code (00001XXX) is transmitted, the a master code, and a not-acknowledge A (at F/S-mode
current-source pull-up circuits stay disabled and all output speed). Although this timing diagram is split in two parts, it
stages are open-drain. All devices, including Hs-mode should be viewed as one timing diagram were time point tH
devices, communicate with each other according the is a common point for both parts.
protocol, format and speed of the F/S-mode I2C-bus
specification.
25
t1
handbook, full pagewidth 8-bit Master code 00001xxx A
S tH
SDAH
SCLH 1 2 to 5 6 7 8 9
SDA
SCL 1 2 to 5 6 7 8 9
F/S mode
7-bit SLA R/W A n × (8-bit DATA + A/A)

Sr Sr P
SDAH
SCLH 1 2 to 5 6 7 8 9 1 2 to 5 6 7 8 9
P
SDA t2
SCL If P then
Hs-mode F/S mode
If Sr (dotted lines)
then Hs-mode
tH
tFS
MSC611
Fig.25 A complete Hs-mode transfer in a mixed-speed bus system.
The master code is recognized by the bridge in the active 2. When both SCLH and SCL become HIGH (tH in
or non-active master (see Fig.24). The bridge performs the Fig.25), transistor TR2 opens to separate the SCLH
following actions: and SCL lines. TR2 must be opened before SCLH
goes LOW after Sr.
1. Between t1 and tH (see Fig.25), transistor TR1 opens
to separate the SDAH and SDA lines, after which Hs-mode transfer starts after tH with a repeated START
transistor TR3 closes to pull-down the SDA line to VSS. condition (Sr). During Hs-mode transfer, the SCL line
stays at a HIGH and the SDA line at a LOW steady-state
level, and so is prepared for the transfer of a STOP
condition (P).
26
After each acknowledge (A) or not-acknowledge bit (A) the seven bits of the first byte following a START (S) or
active master disables its current-source pull-up circuit. repeated START (Sr) condition as explained in Section
This enables other devices to delay the serial transfer by 10.1. The 10-bit addressing does not affect the existing
stretching the LOW period of the SCLH signal. The active 7-bit addressing. Devices with 7-bit and 10-bit addresses
master re-enables its current-source pull-up circuit again can be connected to the same I2C-bus, and both 7-bit and
when all devices are released and the SCLH signal 10-bit addressing can be used in F/S-mode and Hs-mode
reaches a HIGH level, and so speeds up the last part of the systems.
SCLH signal’s rise time. In irregular situations, F/S-mode
Although there are eight possible combinations of the
devices can close the bridge (TR1 and TR2 closed, TR3
reserved address bits 1111XXX, only the four
open) at any time by pulling down the SCL line for at least
combinations 11110XX are used for 10-bit addressing.
1 µs, e.g. to recover from a bus hang-up.
The remaining four combinations 11111XX are reserved
Hs-mode finishes with a STOP condition and brings the for future I2C-bus enhancements.
bus system back into the F/S-mode. The active master
disables its current-source MCS when the STOP condition 14.1 Definition of bits in the first two bytes
(P) at SDAH is detected (tFS in Fig.25). The bridge also
The 10-bit slave address is formed from the first two bytes
recognizes this STOP condition and takes the following
following a START condition (S) or a repeated START
actions:
condition (Sr).
1. Transistor TR2 closes after tFS to connect SCLH with
SCL; both of which are HIGH at this time. Transistor The first seven bits of the first byte are the combination
TR3 opens after tFS, which releases the SDA line and 11110XX of which the last two bits (XX) are the two
allows it to be pulled HIGH by the pull-up resister Rp. most-significant bits (MSBs) of the 10-bit address; the
This is the STOP condition for the F/S-mode devices. eighth bit of the first byte is the R/W bit that determines the
TR3 must open fast enough to ensure the bus free direction of the message. A ‘zero’ in the least significant
time between the STOP condition and the earliest next position of the first byte means that the master will write
START condition is according to the Fast-mode information to a selected slave. A ‘one’ in this position
specification (see tBUF in Table 5). means that the master will read information from the slave.
2. When SDA reaches a HIGH (t2 in Fig.25) transistor If the R/W bit is ‘zero’, then the second byte contains the
TR1 closes to connect SDAH with SDA. (Note: remaining 8 bits (XXXXXXXX) of the 10-bit address. If the
interconnections are made when all lines are HIGH, R/W bit is ‘one’, then the next byte contains data
thus preventing spikes on the bus lines). TR1 and TR2 transmitted from a slave to a master.
must be closed within the minimum bus free time
according to the Fast-mode specification (see tBUF in 14.2 Formats with 10-bit addresses
Table 5).
Various combinations of read/write formats are possible
within a transfer that includes 10-bit addressing. Possible
13.5.3 TIMING REQUIREMENTS FOR THE BRIDGE IN A
data transfer formats are:
MIXED-SPEED BUS SYSTEM
• Master-transmitter transmits to slave-receiver with a
It can be seen from Fig.25 that the actions of the bridge at 10-bit slave address.
t1, tH and tFS must be so fast that it does not affect the The transfer direction is not changed (see Fig.26). When
SDAH and SCLH lines. Furthermore the bridge must meet a 10-bit address follows a START condition, each slave
the related timing requirements of the Fast-mode compares the first seven bits of the first byte of the slave
specification for the SDA and SCL lines. address (11110XX) with its own address and tests if the
eighth bit (R/W direction bit) is 0. It is possible that more
14 10-BIT ADDRESSING than one device will find a match and generate an
acknowledge (A1). All slaves that found a match will
This section describes 10-bit addressing and can be compare the eight bits of the second byte of the slave
disregarded if only 7-bit addressing is used. address (XXXXXXXX) with their own addresses, but
10-bit addressing is compatible with, and can be combined only one slave will find a match and generate an
with, 7-bit addressing. Using 10 bits for addressing acknowledge (A2). The matching slave will remain
exploits the reserved combination 1111XXX for the first addressed by the master until it receives a STOP
27
condition (P) or a repeated START condition (Sr) • Combined format. A master transmits data to one slave
followed by a different slave address. and then transmits data to another slave (Fig.29). The
• Master-receiver reads slave- transmitter with a 10-bit same master occupies the bus all the time.
slave address. • Combined format. 10-bit and 7-bit addressing combined
The transfer direction is changed after the second R/W in one serial transfer (Fig.30). After each START
bit (Fig.27). Up to and including acknowledge bit A2, the condition (S), or each repeated START condition (Sr), a
procedure is the same as that described for a 10-bit or 7-bit slave address can be transmitted.
master-transmitter addressing a slave-receiver. After Figure 27 shows how a master-transmits data to a slave
the repeated START condition (Sr), a matching slave with a 7-bit address and then transmits data to a second
remembers that it was addressed before. This slave slave with a 10-bit address. The same master occupies
then checks if the first seven bits of the first byte of the the bus all the time.
slave address following Sr are the same as they were
NOTES:
after the START condition (S), and tests if the eighth
(R/W) bit is 1. If there is a match, the slave considers 1. Combined formats can be used, for example, to
that it has been addressed as a transmitter and control a serial memory. During the first data byte, the
generates acknowledge A3. The slave-transmitter internal memory location has to be written. After the
remains addressed until it receives a STOP condition START condition and slave address is repeated, data
(P) or until it receives another repeated START can be transferred.
condition (Sr) followed by a different slave address. 2. All decisions on auto-increment or decrement of
After a repeated START condition (Sr), all the other previously accessed memory locations etc. are taken
slave devices will also compare the first seven bits of the by the designer of the device.
first byte of the slave address (11110XX) with their own 3. Each byte is followed by an acknowledgment bit as
addresses and test the eighth (R/W) bit. However, none indicated by the A or blocks in the sequence.
of them will be addressed because R/W = 1 (for 10-bit
devices), or the 11110XX slave address (for 7-bit 4. I2C-bus compatible devices must reset their bus logic
devices) does not match. on receipt of a START or repeated START condition
such that they all anticipate the sending of a slave
• Combined format. A master transmits data to a slave address.
and then reads data from the same slave (Fig.28). The
same master occupies the bus all the time. The transfer
direction is changed after the second R/W bit.
,,,,,
,,,,
,, ,,,,
,,,,,
,,,,
,, ,,,,
handbook, full pagewidth 1 1 1 1 0 X X 0
SLAVE ADDRESS SLAVE ADDRESS
S R/W A1 A2 DATA A DATA A/A P
1st 7 BITS 2nd BYTE
MBC613
(write)
Fig.26 A master-transmitter addresses a slave-receiver with a 10-bit address.
,,,,,,,,
,,,,, , ,,
handbook, full pagewidth1 1 1 1 0 X X 0 1 1 1 1 0 X X 1
SLAVE ADDRESS SLAVE ADDRESS SLAVE ADDRESS
S R/W A1 A2 Sr R/W A3 DATA A DATA A P
1st 7 BITS 2nd BYTE 1st 7 BITS
MBC614
(write) (read)
Fig.27 A master-receiver addresses a slave-transmitter with a 10-bit address.
28
,,,,,,,,,,,,
,,,,,,,,,,,,
1 1 1 1 0 X X 0
S R/W A A DATA A DATA A/A
,,,,,,, ,,
1st 7 BITS 2nd BYTE
,,,,,,, ,,
(write)
1 1 1 1 0 X X 1
Sr SLAVE ADDRESS R/W A DATA A DATA A P

1st 7 BITS
MBC615
(read)
Fig.28 Combined format. A master addresses a slave with a 10-bit address,

then transmits data to this slave and reads data from this slave.
,,,,,,,,,
,,
,,,,,,,,, ,,
,,,,
handbook, full pagewidth 1 1 1 1 0 X X
S
SLAVE ADDRESS
R/W A
0
SLAVE ADDRESS
A DATA A DATA A/A
,,,,,
,,,,,,,,,,
1st 7 BITS 2nd BYTE
(write)
,,,,,
,,,,,,,,,,
1 1 1 1 0 X X 0
Sr R/W A A DATA A DATA A/A P
1st 7 BITS 2nd BYTE
(write) MBC616
Fig.29 Combined format. A master transmits data to two slaves, both with 10-bit addresses.
,,,,,,,,
,,,,,,,,
dbook, full pagewidth 0
S 7 - BIT DATA A DATA A/A

R/W A
SLAVE ADDRESS
(write)
,,,,,
,,,,,,,,, 1 1 1 1 0 X X 0
,,,,,
,,,,,,,,,
1st 7 BITS OF 10-BIT 2nd BYTE OF 10-BIT
Sr R/W A SLAVE ADDRESS A DATA A DATA A/A P
SLAVE ADDRESS
(write) MBC617
Fig.30 Combined format. A master transmits data to two slaves, one with a 7-bit address,
and one with a 10-bit address.
29
14.3 General call address and start byte with 10-bit 15 ELECTRICAL SPECIFICATIONS AND TIMING FOR
addressing I/O STAGES AND BUS LINES
The 10-bit addressing procedure for the I2C-bus is such 15.1 Standard- and Fast-mode devices
that the first two bytes after the START condition (S)
The I/O levels, I/O current, spike suppression, output slope
usually determine which slave will be selected by the
control and pin capacitance for F/S-mode I2C-bus devices
master. The exception is the “general call” address
are given in Table 4. The I2C-bus timing characteristics,
00000000 (H‘00’). Slave devices with 10-bit addressing
bus-line capacitance and noise margin are given in
will react to a “general call” in the same way as slave
Table 5. Figure 31 shows the timing definitions for the
devices with 7-bit addressing (see Section 10.1.1).
I2C-bus.
Hardware masters can transmit their 10-bit address after a
The minimum HIGH and LOW periods of the SCL clock
‘general call’. In this case, the ‘general call’ address byte is
specified in Table 5 determine the maximum bit transfer
followed by two successive bytes containing the 10-bit
rates of 100 kbit/s for Standard-mode devices and
address of the master-transmitter. The format is as shown
400 kbit/s for Fast-mode devices. Standard-mode and
in Fig.16 where the first DATA byte contains the eight
Fast-mode I2C-bus devices must be able to follow
least-significant bits of the master address.
transfers at their own maximum bit rates, either by being
The START byte 00000001 (H‘01’) can precede the 10-bit able to transmit or receive at that speed or by applying the
addressing in the same way as for 7-bit addressing (see clock synchronization procedure described in Section 8
Section 10.1.2). which will force the master into a wait state and stretch the
LOW period of the SCL signal. Of course, in the latter case
the bit transfer rate is reduced.
30
Table 4 Characteristics of the SDA and SCL I/O stages for F/S-mode I2C-bus devices
STANDARD-MODE FAST-MODE
PARAMETER SYMBOL UNIT
MIN. MAX. MIN. MAX.
LOW level input voltage: VIL
fixed input levels −0.5 1.5 n/a n/a V
VDD-related input levels −0.5 0.3VDD −0.5 0.3VDD (1) V
HIGH level input voltage: VIH
fixed input levels 3.0 (2) n/a n/a V
VDD-related input levels 0.7VDD (2) 0.7VDD(1) (2) V
Hysteresis of Schmitt trigger inputs: Vhys
VDD > 2 V n/a n/a 0.05VDD – V
VDD < 2 V n/a n/a 0.1VDD – V
LOW level output voltage (open drain or
open collector) at 3 mA sink current:
VDD > 2 V VOL1 0 0.4 0 0.4 V
VDD < 2 V VOL3 n/a n/a 0 0.2VDD V
Output fall time from VIHmin to VILmax with
a bus capacitance from 10 pF to 400 pF tof – 250(4) 20 + 0.1Cb(3) 250(4) ns
Pulse width of spikes which must be tSP n/a n/a 0 50 ns
suppressed by the input filter
Input current each I/O pin with an input Ii −10 10 −10(5) 10(5) µA
voltage between 0.1VDD and 0.9VDDmax
Capacitance for each I/O pin Ci − 10 − 10 pF
Notes
1. Devices that use non-standard supply voltages which do not conform to the intended I2C-bus system levels must
relate their input levels to the VDD voltage to which the pull-up resistors Rp are connected.
2. Maximum VIH = VDDmax + 0.5 V.
3. Cb = capacitance of one bus line in pF.
4. The maximum tf for the SDA and SCL bus lines quoted in Table 5 (300 ns) is longer than the specified maximum tof
for the output stages (250 ns). This allows series protection resistors (Rs) to be connected between the SDA/SCL
pins and the SDA/SCL bus lines as shown in Fig.36 without exceeding the maximum specified tf.
5. I/O pins of Fast-mode devices must not obstruct the SDA and SCL lines if VDD is switched off.
n/a = not applicable
31
Table 5 Characteristics of the SDA and SCL bus lines for F/S-mode I2C-bus devices(1)
STANDARD-MODE FAST-MODE
MIN. MAX. MIN. MAX.
SCL clock frequency fSCL 0 100 0 400 kHz
Hold time (repeated) START condition. tHD;STA 4.0 – 0.6 − µs
After this period, the first clock pulse is
generated
LOW period of the SCL clock tLOW 4.7 – 1.3 – µs
HIGH period of the SCL clock tHIGH 4.0 – 0.6 – µs
Set-up time for a repeated START tSU;STA 4.7 – 0.6 – µs
condition
Data hold time: tHD;DAT
for CBUS compatible masters (see NOTE,
Section 10.1.3) 5.0 – – – µs
for I2C-bus devices 0(2) 3.45(3) 0(2) 0.9(3) µs
Data set-up time tSU;DAT 250 − 100(4) – ns
Rise time of both SDA and SCL signals tr – 1000 20 + 0.1Cb (5) 300 ns
Fall time of both SDA and SCL signals tf – 300 20 + 0.1Cb(5) 300 ns
Set-up time for STOP condition tSU;STO 4.0 – 0.6 – µs
Bus free time between a STOP and tBUF 4.7 – 1.3 – µs
START condition
Capacitive load for each bus line Cb – 400 – 400 pF
Noise margin at the LOW level for each VnL 0.1VDD – 0.1VDD – V
connected device (including hysteresis)
Noise margin at the HIGH level for each VnH 0.2VDD – 0.2VDD – V
Notes
1. All values referred to VIHmin and VILmax levels (see Table 4).
2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
3. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max
+ tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is
released.
5. Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times according to Table 6 are
allowed.
n/a = not applicable
32
SDA
tf tLOW tr tSU;DAT tf tHD;STA tSP tr tBUF
SCL
tHD;STA tSU;STA tSU;STO

S tHD;DAT tHIGH P S
Sr
MSC610
Fig.31 Definition of timing for F/S-mode devices on the I2C-bus.
33
15.2 Hs-mode devices With an internally generated SCLH signal with LOW and
HIGH level periods of 200 ns and 100 ns respectively, an
The I/O levels, I/O current, spike suppression, output slope
Hs-mode master can fulfil the timing requirements for the
control and pin capacitance for I2C-bus Hs-mode devices
external SCLH clock pulses (taking the rise and fall times
are given in Table 6. The noise margin for HIGH and LOW
into account) for the maximum bit rate of 3.4 Mbit/s. So a
levels on the bus lines are the same as specified for
basic frequency of 10 MHz, or a multiple of 10 MHz, can
F/S-mode I2C-bus devices.
be used by an Hs-mode master to generate the SCLH
Figure 32 shows all timing parameters for the Hs-mode signal. There are no limits for maximum HIGH and LOW
timing.The “normal” START condition S does not exist in periods of the SCLH clock, and there is no limit for a lowest
Hs-mode. Timing parameters for Address bits, R/W bit, bit rate.
Acknowledge bit and DATA bits are all the same. Only the
Timing parameters are independent for capacitive load up
rising edge of the first SCLH clock signal after an
to 100 pF for each bus line allowing the maximum possible
acknowledge bit has an larger value because the external
bit rate of 3.4 Mbit/s. At a higher capacitive load on the bus
Rp has to pull-up SCLH without the help of the internal
lines, the bit rate decreases gradually. The timing
current-source.
parameters for a capacitive bus load of 400 pF are
The Hs-mode timing parameters for the bus lines are specified in Table 7, allowing a maximum bit rate of
specified in Table 7. The minimum HIGH and LOW periods 1.7 Mbit/s. For capacitive bus loads between 100 pF and
and the maximum rise and fall times of the SCLH clock 400 pF, the timing parameters must be interpolated
signal determine the highest bit rate. linearly. Rise and fall times are in accordance with the
maximum propagation time of the transmission lines
SDAH and SCLH to prevent reflections of the open ends.
34
Table 6 Characteristics of the SDAH, SCLH, SDA and SCL I/O stages for Hs-mode I2C-bus devices
Hs-MODE
MIN. MAX.
LOW level input voltage VIL −0.5 0.3VDD(1) V
HIGH level input voltage VIH 0.7VDD(1) VDD + 0.5(2) V
Hysteresis of Schmitt trigger inputs Vhys 0.1VDD(1) – V
LOW level output voltage (open drain) at 3 mA sink VOL
current at SDAH, SDA and SCLH for:
VDD > 2 V 0 0.4 V
VDD < 2 V 0 0.2VDD V
On resistance of the transfer gate, for both current RonL − 50 Ω
directions at VOL level between SDA and SDAH or
SCL and SCLH at 3 mA
On resistance of the transfer gate between SDA and RonH(2) 50 – kΩ
SDAH or SCL and SCLH if both are at VDD level
Pull-up current of the SCLH current-source. Applies for ICS 3 12 mA
SCLH output levels between 0.3VDD and 0.7VDD
Output rise time (current-source enabled) and fall time trCL, tfCL 10 40 ns
at SCLH with a capacitive load from 10 to 100 pF
Output rise time (current-source enabled) and fall time trCL(3), tfCL(3) 20 80 ns
at SCLH with an external pull-up current source of 3 mA
and a capacitive load of 400 pF
Output fall time at SDAH with a capacitive load from 10 tfDA 20 80 ns
to 100 pF
Output fall time at SDAH with a capacitive load of tfDA(3) 40 160 ns
400 pF
Pulse width of spikes at SDAH and SCLH that must be tSP 0 10 ns
suppressed by the input filters
Input current each I/O pin with an input voltage between Ii(4) – 10 µA
0.1VDD and 0.9VDD
Capacitance for each I/O pin Ci – 10 pF
Notes
1. Devices that use non-standard supply voltages which do not conform to the intended I2C-bus system levels must
relate their input levels to the VDD voltage to which the pull-up resistors Rp are connected.
2. Devices that offer the level shift function must tolerate a maximum input voltage of 5.5 V at SDA and SCL.
3. For capacitive bus loads between 100 and 400 pF, the rise and fall time values must be linearly interpolated.
4. SDAH and SCLH I/O stages of Hs-mode slave devices must have floating outputs if their supply voltage has been
switched off. Due to the current-source output circuit, which normally has a clipping diode to VDD, this requirement
is not mandatory for the SCLH or the SDAH I/O stage of Hs-mode master devices. This means that the supply voltage
of Hs-mode master devices cannot be switched off without affecting the SDAH and SCLH lines.
35
Table 7 Characteristics of the SDAH, SCLH, SDA and SCL bus lines for Hs-mode I2C-bus devices(1)
Cb = 100 pF MAX. Cb = 400 pF(2)

MIN. MAX. MIN. MAX.
SCLH clock frequency fSCLH 0 3.4 0 1.7 MHz
Set-up time (repeated) START condition tSU;STA 160 − 320 − ns
Hold time (repeated) START condition tHD;STA 160 − 320 − ns
LOW period of the SCLH clock tLOW 160 − 320 − ns
HIGH period of the SCLH clock tHIGH 60 − 120 − ns
Data set-up time tSU;DAT 10 − 10 − ns
Data hold time tHD;DAT 0(3) 70 0(3) 150 ns
Rise time of SCLH signal trCL 10 40 20 80 ns
Rise time of SCLH signal after trCL1 20 80 40 160 ns
acknowledge bit
Fall time of SCLH signal tfCL 10 40 20 80 ns
Rise time of SDAH signal trDA 20 80 40 160 ns
Fall time of SDAH signal tfDA 20 80 40 160 ns
Set-up time for STOP condition tSU;STO 160 − 320 − ns
Capacitive load for SDAH and SCLH lines Cb(2) − 100 − 400 pF
Capacitive load for SDAH + SDA line and Cb − 400 − 400 pF
SCLH + SCL line
Noise margin at the LOW level for each VnL 0.1VDD − 0.1VDD − V
Noise margin at the HIGH level for each VnH 0.2VDD − 0.2VDD − V
Notes
1. All values referred to VIHmin and VILmax levels (see Table 6).
2. For bus line loads Cb between 100 and 400 pF the timing parameters must be linearly interpolated.
3. A device must internally provide a Data hold time to bridge the undefined part between VIH and VIL of the falling edge
of the SCLH signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal
minimizes this hold time.
36
handbook, full pagewidth Sr Sr P

tfDA trDA
SDAH
tHD;DAT
tSU;STO
tSU;STA tHD;STA tSU;DAT
SCLH
tfCL
trCL1 trCL1
trCL (1) (1)
tHIGH tLOW tLOW tHIGH

MGK871
(1) Rising edge of the first SCLH clock pulse after an acknowledge bit.
Fig.32 Definition of timing for Hs-mode devices on the I2C-bus.
16 ELECTRICAL CONNECTIONS OF I2C-BUS must be connected to one common supply line of

DEVICES TO THE BUS LINES 5 V ± 10% and must have pull-up resistors connected to
their SDA and SCL pins as shown in Fig.35.
The electrical specifications for the I/Os of I2C-bus devices
and the characteristics of the bus lines connected to them New Fast- and Hs-mode devices must have supply
are given in Section 15. voltage related input levels as specified in Tables 4 and 6.
I2C-bus devices with fixed input levels of 1.5 V and 3 V can Input levels are defined in such a way that:
each have their own appropriate supply voltage. Pull-up • The noise margin on the LOW level is 0.1VDD
resistors must be connected to a 5 V ± 10% supply
• The noise margin on the HIGH level is 0.2VDD
(Fig.33). I2C-bus devices with input levels related to VDD
must have one common supply line to which the pull-up • As shown in Fig.36, series resistors (RS) of e.g. 300 Ω
resistor is also connected (Fig.34). can be used for protection against high-voltage spikes
on the SDA and SCL lines (resulting from the flash-over
When devices with fixed input levels are mixed with of a TV picture tube, for example).
devices with input levels related to VDD, the latter devices
37
handbook, full pagewidth VDD2 - 4 are device dependent (e.g. 12 V)
V DD1 = 5 V 10 % V DD2 V DD3 V DD4
Rp Rp NMOS BiCMOS CMOS BIPOLAR
SDA
SCL
MBC610
Fig.33 Fixed input level devices connected to the I2C-bus.
handbook, full pagewidth V DD = e.g. 3 V
Rp Rp CMOS CMOS CMOS CMOS
SDA
SCL
MBC625
Fig.34 Devices with wide supply voltage range connected to the I2C-bus.
handbook, full pagewidth V DD2,3 are device dependent (e.g. 12 V)

V DD1 =
5V 10 % V DD2 V DD3
Rp Rp CMOS CMOS NMOS BIPOLAR
SDA
SCL
MBC626
Fig.35 Devices with input levels related to VDD (supply VDD1) mixed with fixed input level devices
(supply VDD2,3) on the I2C-bus.
38
handbook, full pagewidth V DD V DD
I2 C I2 C
DEVICE DEVICE
Rp Rp
Rs Rs Rs Rs
SDA
SCL
MBC627
Fig.36 Series resistors (Rs) for protection against high-voltage spikes.
16.1 Maximum and minimum values of resistors Rp Rp min is shown in Fig.37. The required noise margin of
and Rs for Standard-mode I2C-bus devices 0.1VDD for the LOW level, limits the maximum value of Rs.
Rs max as a function of Rp is shown in Fig.38.
For Standard-mode I2C-bus systems, the values of
resistors Rp and Rs in Fig.35 depend on the following The bus capacitance is the total capacitance of wire,
parameters: connections and pins. This capacitance limits the
maximum value of Rp due to the specified rise time. Fig.39
• Supply voltage shows Rp max as a function of bus capacitance.
• Bus capacitance
The maximum HIGH level input current of each
• Number of connected devices (input current + leakage input/output connection has a specified maximum value of
current). 10 µA. Due to the required noise margin of 0.2 VDD for the
The supply voltage limits the minimum value of resistor Rp HIGH level, this input current limits the maximum value of
due to the specified minimum sink current of 3 mA at Rp. This limit depends on VDD. The total HIGH level input
VOLmax = 0.4 V for the output stages. VDD as a function of current is shown as a function of Rp max in Fig.40.
39
MBC635
20
MBC628 maximum
6
handbook,
minimum halfpage value R p
value R p (kΩ)
(kΩ ) 16
5
RS = 0
4 12
RS = 0
3
8
max. R S
2
max. R S
4
@ V DD = 5 V
1
0
0 100 200 300 400
0
0 4 8 12 16 bus capacitance (pF)
V DD (V)
Fig.37 Minimum value of Rp as a function of supply Fig.39 Maximum value of Rp as a function of bus
voltage with the value os Rs as a parameter. capacitance for a Standard-mode I2C-bus.
MBC630
MBC629 20
10 maximum
value R p
Rp
(kΩ )
(kΩ ) V DD = 2.5 V 5V 16
8
12
6
15 V
VDD= 15 V
8
4
10 V
10 V
4
2 5V
2.5 V
0
0 0 40 80 120 160 200
0 400 800 1200 1600 total high level input current (µA)
maximum value R s (Ω)
Fig.40 Total HIGH level input current as a function

Fig.38 Maximum value of Rs as a function of the of the maximum value of Rp with supply voltage as
value of Rp with supply voltage as a parameter. a parameter.
40
17 APPLICATION INFORMATION 17.2 Switched pull-up circuit for Fast-mode I2C-bus

devices
17.1 Slope-controlled output stages of Fast-mode
I2C-bus devices The supply voltage (VDD) and the maximum output LOW
level determine the minimum value of pull-up resistor Rp
The electrical specifications for the I/Os of I2C-bus devices
(see Section 16.1). For example, with a supply voltage of
and the characteristics of the bus lines connected to them
VDD = 5 V ± 10% and VOLmax = 0.4 V at 3 mA, Rp min =
are given in Section 15.
(5.5 − 0.4)/0.003 = 1.7 kΩ. As shown in Fig.43, this value
Figures 41 and 42 show examples of output stages with of Rp limits the maximum bus capacitance to about 200 pF
slope control in CMOS and bipolar technology. The slope to meet the maximum tr requirement of 300 ns. If the bus
of the falling edge is defined by a Miller capacitor (C1) and has a higher capacitance than this, a switched pull-up
a resistor (R1). The typical values for C1 and R1 are circuit as shown in Fig.43 can be used.
indicated on the diagrams. The wide tolerance for output
The switched pull-up circuit in Fig.43 is for a supply voltage
fall time tof given in Table 4 means that the design is not
of VDD = 5 V ± 10% and a maximum capacitive load of
critical. The fall time is only slightly influenced by the
400 pF. Since it is controlled by the bus levels, it needs no
external bus load (Cb) and external pull-up resistor (Rp).
additional switching control signals. During the
However, the rise time (tr) specified in Table 5 is mainly
rising/falling edges, the bilateral switch in the HCT4066
determined by the bus load capacitance and the value of
switches pull-up resistor Rp2 on/off at bus levels between
the pull-up resistor.
0.8 V and 2.0 V. Combined resistors Rp1 and Rp2 can
pull-up the bus line within the maximum specified rise time
(tr) of 300 ns.
VDD Series resistors Rs are optional. They protect the I/O
VDD
stages of the I2C-bus devices from high-voltage spikes on
P1 to input the bus lines, and minimize crosstalk and undershoot of
circuit Rp
R1 the bus line signals. The maximum value of Rs is
50 kΩ C1 I/O SDA or SCL determined by the maximum permitted voltage drop
bus line
N1 2 pF across this resistor when the bus line is switched to the
N2 Cb
LOW level in order to switch off Rp2.
VSS
VSS
MBC618
nY VDD
Fig.41 Slope-controlled output stage in CMOS 1/4 HCT4066
VCC 5V 10 %
nE
technology.
P N
nZ GND
1.3 kΩ R p2 1.7 kΩ R p1
SDA or SCL
Vp bus line
VDD
100 Ω Rs 100 Ω Rs
to input
R1 circuit I/O I/O
20 kΩ Rp Cb
C1
I/O SDA or SCL 400 pF
bus line max.
5 pF N N
T1 T2 Cb
MBC620 VSS
GND VSS
FAST - MODE I 2 C BUS DEVICES
MBC619
Fig.42 Slope-controlled output stage in bipolar

technology. Fig.43 Switched pull-up circuit.
41
17.3 Wiring pattern of the bus lines

In general, the wiring must be so chosen that crosstalk and MBC612
7.5
interference to/from the bus lines is minimized. The bus handbook, halfpage
maximum
lines are most susceptible to crosstalk and interference at value R p
the HIGH level because of the relatively high impedance of (kΩ)
6.0
the pull-up devices.
If the length of the bus lines on a PCB or ribbon cable
4.5
exceeds 10 cm and includes the VDD and VSS lines, the
wiring pattern must be:
RS = 0
SDA 3.0
VDD
max. R S
1.5
VSS @ V DD = 5 V
SCL
0
If only the VSS line is included, the wiring pattern must be: 0 100 200 300 400
bus capacitance (pF)
SDA
VSS Fig.44 Maximum value of Rp as a function of bus
capacitance for meeting the tr max requirement for
SCL a Fast-mode I2C-bus.
These wiring patterns also result in identical capacitive
loads for the SDA and SCL lines. The VSS and VDD lines
can be omitted if a PCB with a VSS and/or VDD layer is 17.5 Maximum and minimum values of resistors Rp
used. and Rs for Hs-mode I2C-bus devices
If the bus lines are twisted-pairs, each bus line must be The maximum and minimum values for resistors Rp and Rs
twisted with a VSS return. Alternatively, the SCL line can be connected to an Hs-mode I2C-bus can be calculated from
twisted with a VSS return, and the SDA line twisted with a the data in Tables 6 and 7. Many combinations of these
VDD return. In the latter case, capacitors must be used to values are possible, owing to different rise and fall times,
decouple the VDD line to the VSS line at both ends of the bus line loads, supply voltages, mixed speed systems and
twisted pairs. level shifting. Because of this, no further graphs are
included in this specification.
If the bus lines are shielded (shield connected to VSS),
interference will be minimized. However, the shielded
cable must have low capacitive coupling between the SDA 18 BI-DIRECTIONAL LEVEL SHIFTER FOR
and SCL lines to minimize crosstalk. F/S-MODE I2C-BUS SYSTEMS
17.4 Maximum and minimum values of resistors Rp Present technology processes for integrated circuits with
clearances of 0.5 µm and less, limit the maximum supply
and Rs for Fast-mode I2C-bus devices
voltage and consequently the logic levels for the digital I/O
The maximum and minimum values for resistors Rp and Rs signals. To interface these lower voltage circuits with
connected to a Fast-mode I2C-bus can be determined existing 5 V devices a level shifter is needed. For
from Figs 37, 38 and 40 in Section 16.1. Because a bi-directional bus systems as like the I2C-bus, such a level
Fast-mode I2C-bus has faster rise times (tr) the maximum shifter must also be bi-directional, without the need of a
value of Rp as a function of bus capacitance is less than direction control signal(1). The simplest way to solve this
that shown in Fig.39 The replacement graph for Fig.39 problem is by connecting a discrete MOS-FET to each bus
showing the maximum value of Rp as a function of bus line.
capacitance (Cb) for a Fast-mode I2C-bus is given in
Fig.44.
(1) US 5,689,196 granted; corresponding patent applications
pending.
42
In spite of its surprising simplicity, such a solution not only interconnect two sections of an I2C-bus system, with each
fulfils the requirement of bi-directional level shifting without section having a different supply voltage and different logic
a direction control signal, it also: levels. Such a configuration is shown in Fig.45. The left
• isolates a powered-down bus section from the rest of the “low-voltage” section has pull-up resistors and devices
bus system connected to a 3.3 V supply voltage, the right
“high-voltage” section has pull-up resistors and devices
• protects the “lower voltage” side against high voltage connected to a 5 V supply voltage. The devices of each
spikes from the “higher-voltage” side.
section have I/Os with supply voltage related logic input
The bi-directional level shifter can be used for both levels and an open drain output configuration.
Standard-mode (up to100 kbit/s) or in Fast-mode (up to
The level shifter for each bus line is identical and consists
400 kbit/s) I2C-bus systems. It is not intended for Hs-mode
of one discrete N-channel enhancement MOS-FET; TR1
systems, which may have a bridge with a level shifting
for the serial data line SDA and TR2 for the serial clock line
possibility (see Section 13.5)
SCL. The gates (g) have to be connected to the lowest
supply voltage VDD1, the sources (s) to the bus lines of the
18.1 Connecting devices with different logic levels “lower-voltage” section, and the drains (d) to the bus lines
Section 16 described how different voltage devices could of the “higher-voltage” section. Many MOS-FETs have the
be connected to the same bus by using pull-up resistors to substrate internally connected with its source, if this is not
the supply voltage line. Although this is the simplest the case, an external connection should be made. Each
solution, the lower voltage devices must be 5 V tolerant, MOS-FET has an integral diode (n-p junction) between the
which can make them more expensive to manufacture. By drain and substrate.
using a bi-directional level shifter, however, it’s possible to
VDD1 = 3.3 V
handbook, full pagewidth VDD2 = 5 V
Rp Rp g TR1 Rp Rp
SDA1 s d SDA2
g TR2
SCL1 s d SCL2
3.3 V DEVICE 3.3 V DEVICE 5 V DEVICE 5 V DEVICE
MGK879
Fig.45 Bi-directional level shifter circuit connecting two different voltage sections in an I2C-bus system.
43
18.1.1 OPERATION OF THE LEVEL SHIFTER 3. A 5 V device pulls down the bus line to a LOW level.
The drain-substrate diode of the MOS-FET the
The following three states should be considered during the
“lower-voltage” section is pulled down until VGS
operation of the level shifter:
passes the threshold and the MOS-FET starts to
1. No device is pulling down the bus line. conduct. The bus line of the “lower-voltage” section is
The bus line of the “lower-voltage” section is pulled up then further pulled down to a LOW level by the 5 V
by its pull-up resistors Rp to 3.3 V. The gate and the device via the conducting MOS-FET. So the bus lines
source of the MOS-FET are both at 3.3 V, so its VGS is of both sections go LOW to the same voltage level.
below the threshold voltage and the MOS-FET is not
conducting. This allows the bus line at the The three states show that the logic levels are transferred
“higher-voltage” section to be pulled up by its pull-up in both directions of the bus system, independent of the
resistor Rp to 5 V. So the bus lines of both sections are driving section. State 1 performs the level shift function.
HIGH, but at a different voltage level. States 2 and 3 perform a “wired AND” function between
the bus lines of both sections as required by the I2C-bus
2. A 3.3 V device pulls down the bus line to a LOW level. specification.
The source of the MOS-FET also becomes LOW,
while the gate stay at 3.3 V. VGS rises above the Supply voltages other than 3.3 V for VDD1 and 5 V for VDD2
threshold and the MOS-FET starts to conduct. The bus can also be applied, e.g. 2 V for VDD1 and 10 V for VDD2 is
line of the “higher-voltage” section is then also pulled feasible. In normal operation VDD2 must be equal to or
down to a LOW level by the 3.3 V device via the higher than VDD1 (VDD2 is allowed to fall below VDD1 during
conducting MOS-FET. So the bus lines of both switching power on/off).
sections go LOW to the same voltage level.
44
19 DEVELOPMENT TOOLS AVAILABLE FROM PHILIPS
Table 8 I2C evaluation boards

PRODUCT DESCRIPTION
OM4151/ I2C-bus evaluation board with microcontroller, LCD, LED, Par. I/O, SRAM, EEPROM, Clock, DTMF
S87C00KSD generator, AD/DA conversion.
OM5027 I2C-bus evaluation board for low-voltage, low-power ICs & software
OM5500 Demo kit for the PCF2166 LCD driver and PCD3756A telecom microcontroller
Table 9 Development tools for 80C51-based systems

PRODUCT DESCRIPTION
PDS51 A board-level, full featured, in-circuit emulator:
RS232 interface to PC, universal motherboard, controlled via terminal emulation
Table 10 Development tools for 68000-based systems

PRODUCT DESCRIPTION
OM4160/2 Microcore-2 demonstration/evaluation board with SCC68070
OM4160/4 Microcore-4 demonstration/evaluation board with 90CE201
OM4160/5 Microcore-5 demonstration/evaluation board with 90CE301
Table 11 I2C analyzers
PRODUCT DESCRIPTION
OM1022 PC I2C-bus analyzer with multi-master capability. Hardware and software (runs on IBM or
compatible PC) to experiment with and analyze the behaviour of the I2C-bus (includes
documentation)
OM4777 Similar to OM1022 but for single-master systems only
PF8681 I2C-bus analyzer support package for the PM3580 logic analyzer family
45
20 SUPPORT LITERATURE
Table 12 Data handbooks
TITLE ORDERING CODE
IC01: Semiconductors for Radio, Audio and CD/DVD Systems 9397 750 02453
IC02: Semiconductors for Television and Video Systems 9397 750 01989
IC03: Semiconductors for Wired Telecom Systems (parts a & b) 9397 750 00839,
9397 750 00811
IC12: I2C Peripherals 9397 750 01647
IC14: 8048-based 8-bit microcontrollers 9398 652 40011
IC17: Semiconductors for wireless communications 9397 750 01002
IC18: Semiconductors for in-car electronics 9397 750 00418
IC19: ICs for data communications 9397 750 00138
IC20: 80C51-based 8-bit microcontrollers + Application notes and Development tools 9397 750 00963
IC22: Multimedia ICs 9397 750 02183
Table 13 Brochures/leaflets/lab. reports/books etc.

TITLE ORDERING CODE
Can you make the distance... with I2C-bus (information about the P82B715 I2C-bus 9397 750 00008
extender IC)
I2C-bus multi-master & single-master controller kits 9397 750 00953
Desktop video (CD-ROM) 9397 750 00644
80C51 core instructions quick reference 9398 510 76011
80C51 microcontroller selection guide 9397 750 01587
OM5027 I2C-bus evaluation board for low-voltage, low-power ICs & software 9398 706 98011
P90CL301 I2C driver routines AN94078
User manual of Microsoft Pascal I2C-bus driver (MICDRV4.OBJ) ETV/IR8833
C routines for the PCF8584 AN95068
Using the PCF8584 with non-specified timings and other frequently asked questions AN96040
User's guide to I2C-bus control programs ETV8835
The I2C-bus from theory to practice (book and disk) Author: D. Paret
Publisher: Wiley
ISBN: 0-471-96268-6
Bi-directional level shifter for I2C-bus and other systems AN97055
OM5500 demo kit for the PCF2166 LCD driver and PCD3756A telecom microcontroller 9397 750 00954
For more information about Philips Semiconductors and how we can help in your I2C-bus design, contact your nearest
Philips Semiconductors national organization from the address list of the back of this book, or visit our worldwide web
site at http://www.semiconductors.philips.com
46
NOTES
47
NOTES
48
El archivo http://www.dacya.ucm.es/mendias/143/docs/usb.pdf es un documento seguro que se ha incrustado en este documento.
El archivo http://www.dacya.ucm.es/mendias/143/docs/74HC594.pdf es un documento seguro que se ha incrustado en este
Order this document by ULN2803/D

The eight NPN Darlington connected transistors in this family of arrays
OCTAL PERIPHERAL
are ideally suited for interfacing between low logic level digital circuitry (such DRIVER ARRAYS
as TTL, CMOS or PMOS/NMOS) and the higher current/voltage
requirements of lamps, relays, printer hammers or other similar loads for a
broad range of computer, industrial, and consumer applications. All devices SEMICONDUCTOR
feature open–collector outputs and free wheeling clamp diodes for transient TECHNICAL DATA
suppression.
The ULN2803 is designed to be compatible with standard TTL families
while the ULN2804 is optimized for 6 to 15 volt high level CMOS or PMOS.
MAXIMUM RATINGS (TA = 25°C and rating apply to any one device in the
package, unless otherwise noted.)
Rating Symbol Value Unit
Output Voltage VO 50 V
Input Voltage (Except ULN2801) VI 30 V A SUFFIX
PLASTIC PACKAGE
Collector Current – Continuous IC 500 mA CASE 707
Base Current – Continuous IB 25 mA
Operating Ambient Temperature Range TA 0 to +70 °C
Storage Temperature Range Tstg – 55 to +150 °C
Junction Temperature TJ 125 °C PIN CONNECTIONS
RθJA = 55°C/W
Do not exceed maximum current limit per driver.
1 18
ORDERING INFORMATION 2 17
Characteristics
3 16
Operating
Input Temperature
Compatibility 4 15
D i
Device VCE(Max)/IC(Max) Range
ULN2803A TTL, 5.0 V CMOS 5 14

50 V/500 mA TA = 0 to + 70°C
ULN2804A 6 to 15 V CMOS, PMOS
6 13
7 12
8 11
Gnd 9 10
 Motorola, Inc. 1996 Rev 1

MOTOROLA ANALOG IC DEVICE DATA 1
ULN2803 ULN2804
ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
Output Leakage Current (Figure 1) ICEX µA
(VO = 50 V, TA = +70°C) All Types – – 100
(VO = 50 V, TA = +25°C) All Types – – 50
(VO = 50 V, TA = +70°C, VI = 6.0 V) ULN2802 – – 500
(VO = 50 V, TA = +70°C, VI = 1.0 V) ULN2804 – – 500
Collector–Emitter Saturation Voltage (Figure 2) VCE(sat) V
(IC = 350 mA, IB = 500 µA) All Types – 1.1 1.6
Input Current – On Condition (Figure 4) II(on) mA
(VI = 17 V) ULN2802 – 0.82 1.25
(VI = 3.85 V) ULN2803 – 0.93 1.35
(VI = 5.0 V) ULN2804 – 0.35 0.5
(VI = 12 V) ULN2804 – 1.0 1.45
Input Voltage – On Condition (Figure 5) VI(on) V
(VCE = 2.0 V, IC = 300 mA) ULN2802 – – 13
(VCE = 2.0 V, IC = 200 mA) ULN2803 – – 2.4
(VCE = 2.0 V, IC = 250 mA) ULN2803 – – 2.7
(VCE = 2.0 V, IC = 300 mA) ULN2803 – – 3.0
(VCE = 2.0 V, IC = 125 mA) ULN2804 – – 5.0
(VCE = 2.0 V, IC = 200 mA) ULN2804 – – 6.0
(VCE = 2.0 V, IC = 275 mA) ULN2804 – – 7.0
(VCE = 2.0 V, IC = 350 mA) ULN2804 – – 8.0
Input Current – Off Condition (Figure 3) All Types II(off) 50 100 – µA
(IC = 500 µA, TA = +70°C)
DC Current Gain (Figure 2) ULN2801 hFE 1000 – – –

(VCE = 2.0 V, IC = 350 mA)
Input Capacitance CI – 15 25 pF
Turn–On Delay Time ton – 0.25 1.0 µs
(50% EI to 50% EO)
Turn–Off Delay Time toff – 0.25 1.0 µs

(50% EI to 50% EO)
Clamp Diode Leakage Current (Figure 6) TA = +25°C IR – – 50 µA

(VR = 50 V) TA = +70°C 100
Clamp Diode Forward Voltage (Figure 7) VF – 1.5 2.0 V
(IF = 350 mA)
2 MOTOROLA ANALOG IC DEVICE DATA

ULN2803 ULN2804
TEST FIGURES
(See Figure Numbers in Electrical Characteristics Table)
Figure 1. Figure 2.
Open
Open VCE
+ IC
I
h FE
in
µA
Open ICEX DUT

Vin
DUT IC
V
VCE
Figure 3. Figure 4.
Open VCE Open
µA
Iin
µA DUT µA DUT Open
Vin Vin
Figure 5. Figure 6.
VR
Open
µA
IR
DUT
DUT
IC Open
V VCE V
Vin
Figure 7.
IF
V
VF
DUT
Open

ULN2803 ULN2804
TYPICAL CHARACTERISTIC CURVES – TA = 25°C, unless otherwise noted

Output Characteristics
Figure 8. Output Current versus Figure 9. Output Current versus

Saturation Voltage Input Current
IC , COLLECTOR CURRENT (mA)
IC , COLLECTOR CURRENT (mA)

600 600
All Types All Types

400 400
200 200
0 0
0 0.5 1.0 1.5 2.0 0 200 400 600 800
VCE(sat), SATURATION VOLTAGE (V) IIN, INPUT CURRENT (µA)
Input Characteristics
Figure 10. ULN2803 Input Current Figure 11. ULN2804 Input Current
versus Input Voltage versus Input Voltage
2.0 2.0
IIN , INPUT CURRENT (mA)
IIN , INPUT CURRENT (mA)
1.5 1.5
1.0 1.0
0.5 0.5
0 0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 5.0 6.0 7.0 8.0 9.0 10 11 12 13
VIN, INPUT VOLTAGE (V) VIN, INPUT VOLTAGE (V)
Figure 12. Representative Schematic Diagrams
1/8 ULN2803 1/8 ULN2804
2.7 k Pin 10 10.5 k Pin 10
7.2 k 7.2 k
3.0 k 3.0 k
4 MOTOROLA ANALOG IC DEVICE DATA

ULN2803 ULN2804
OUTLINE DIMENSIONS
A SUFFIX
PLASTIC PACKAGE
CASE 707–02
ISSUE C NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
18 10 MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
B 2. DIMENSION L TO CENTER OF LEADS WHEN
1 9 FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
A MILLIMETERS INCHES
DIM MIN MAX MIN MAX
L A 22.22 23.24 0.875 0.915
C B 6.10 6.60 0.240 0.260
C 3.56 4.57 0.140 0.180
D 0.36 0.56 0.014 0.022
F 1.27 1.78 0.050 0.070
N K G 2.54 BSC 0.100 BSC
J H 1.02 1.52 0.040 0.060
F D SEATING M J 0.20 0.30 0.008 0.012
PLANE K 2.92 3.43 0.115 0.135
H G L 7.62 BSC 0.300 BSC
M 0_ 15_ 0_ 15 _
N 0.51 1.02 0.020 0.040

ULN2803 ULN2804
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
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Circuit Symbols of Electronic Components

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[Copias de transparencias] [Guiones de prácticas guiadas][Cómo diseñar un ...

❍ Tema 2. Especificación a nivel lógico de sistemas HW.

❍ Tema 3. Especificación a nivel lógico-RT de sistemas HW usando VHDL.

❍ Tema 4. Análisis de circuitos de nivel lógico.

❍ Tema 5. Técnicas de diseño de nivel lógico.

❍ Tema 6. Batería de diseños

■ Pulsadores, teclados y ratones.

■ Leds, displays, LCDs y monitores.

■ Zumbadores, altavoces y audio CODECs.

■ Comunicación serie: RS-232, USB.

■ Buses I2C, ISA y PCI.

❍ Anexo. Material docente en los laboratorios de la Facultad de Informática.

especificar circuitos a un alto nivel de abstracción.

❍ Synopsys Design Tools - Arquitectura del entorno de síntesis.

Guiones de prácticas guiadas

● Eliminador de rebotes (estructura, vhdl).

● Interfaz con un teclado PS-2 (estructura, vhdl):

● Interfaz con un ratón PS-2 (estructura, vhdl):

● Interfaz síncrono de SRAM (estructura).

● Refresco de bancos multiplexados

● Interfaces con un monitor VGA:

❍ Interfaz gráfico monocromo direccionable X-Y (estructura, vhdl).

❍ Interfaz alfanumérico monocromo direccionable X-Y (estructura, vhdl).

❍ Interfaz alfanumérico monocromo tipo terminal (estructura, vhdl).

● Interfaz con un stereo CODEC (estructura, vhdl).

❍ Conversores entre códigos binario y BCD-8421 (estructura, vhdl).

❍ Generador de números pseudo-aleatorios (estructura, vhdl).

❍ Manual de usuario (v1.2, v1.3, v1.4).

❍ Manual de usuario de las herramientas software para el manejo de la placa (v1.3).

❍ Compilador cruzado de C para los microcontroladores de la familia 8051.

❍ Manual de usuario (v1.2).

❍ Manual de usuario (v1.2, v1.3, v1.3.2, v2.0).

❍ Manual de usuario (v1.0).

❍ Manual de usuario (v1.0).

● Banco de displays 7-segmentos:

❍ Control básico de LCDs.

● Banco de interruptores, pulsadores y leds

● XS40-010XL v1.2 (Xess Corporation):

❍ W24257AK - 32Kx8 SRAM (Winbond Electronics).

❍ XC4010XL - FPGA de 10K puertas (Xilinx).

● XS40-010XL v1.3 (Xess Corporation):

❍ AS7C256 - 32Kx8 SRAM (Alliance Semiconductor).

❍ XC4010XL - FPGA de 10K puertas (Xilinx).

❍ DS1075 - Oscilador programable (Dallas Semiconductor).

● XS40-010XL v1.4 (Xess Corporation):

❍ AS7C256 / AS7C1024 - 32Kx8 / 128Kx8 SRAM (Alliance Semiconductor).

❍ XC4010XL - FPGA de 10K puertas (Xilinx).

❍ DS1075 - Oscilador programable (Dallas Semiconductor).

● XSA-100 v1.2 (Xess Corporation):

❍ AT49F002 - 256Kx8 Flash RAM (Atmel Corporation).

❍ XC2S100 - FPGA de 100K puertas (Xilinx).

❍ XC9572XL - CPLD de 1600 puertas (Xilinx).

❍ DS1075 - Oscilador programable (Dallas Semiconductor).

● XStend v1.2 (Xess Corporation):

● XStend v1.3, v1.3.2 (Xess Corporation):

● XStend v2.0 (Xess Corporation):

❍ PDIUSBD11 - Interfaz USB con conexión I2C (Philips Semiconductors).

❍ XC95108 - CPLD de 2400 puertas (Xilinx).

❍ AS7C4096 - 512Kx8 SRAM (Alliance Semiconductor).

❍ 28F016S5 - 16Mbit Flash RAM (Intel Corporation).

❍ BT481A - RAMDAC de 256 entradas y 24 bits de color (Brooktree Corporation).

❍ LXT970A - Transceiver Ethernet PHY (Level One Communications).

❍ PDIUSBP11A - Transceiber USB (Philips Semiconductors).

❍ DS1075 - Oscilador programable (Dallas Semiconductor).