Dynamic RAM DRAM Interfacing

Dynamic RAM (DRAM) is the highest density, lowest cost Internally, DRAMs are much like other memories, except:
memory currently available. For these reasons it is univerally
used in any microprocessor-based system that requires more • RAS and CAS signals strobe latches row and column
than a small amount of non-volatile writable storage. halves of multiplexed address

• One transistor per cell (drain acts as capacitor) • CAS may also serve as output enable

• Very small charges involved • Most x1 devices have separate input and output data
pins
• bit lines must be precharged to detect bit values

• voltage swing on bit lines is small; sense amp required

to convert to logic levels

decoder
A0
• reads are destructive; DRAM devices internally write Memory

latch
data back on read A1 Array

• leakage current can flip 1s to 0s: values must be RAS

refreshed (rewritten) every few milliseconds or data will
be lost
CAS
• To reduce package cost and size, DRAM devices minimize sense amps
pin count by:
4:1 mux/demux
• using narrow logical configurations (x1, x4)

latch
• multiplexing the internal row and column addresses on WE
the same pins

D D
IN OUT

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EECS 373 F99 Notes 9-1 © 1998, 1999 Steven K. Reinhardt

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 DRAM Timing: Reads DRAM Timing: Writes
Write timing is similar. If WE is asserted on the falling edge of
• The falling edges of RAS and CAS strobe the address bits
into the row and column latches, respectively. These must be CAS, data is written from DIN instead of being read to
separated by at least tRCD. DOUT. Note that this is different from SRAMs, which
perform writes at the end of the cycle (rising edge of WE).
• As with other memories, multiple access times are
specified, and the time to valid data out will depend on which t
RC
is the critical path. For DRAMs, there are two access times,
ADDR row col
tRAC and tCAC, for access time from valid row address and
valid column address, respectively.
t t
RAS RP
t
RC RAS
ADDR row col t
RCD

t t t
CAS
RAC RP
CAS
RAS
t WE
RCD
t
CAC
CAS D
IN valid
D
OUT valid

• Most timing parameters are identical to the read cycle. tRAS

• Setup and hold times for both row and column and tCAS are minimum pulse widths that also apply to the read
addresses exist but are not shown. cycle but were left out of that diagram for clarity.

• The read cycle time (tRC) is typically much larger than • Required setup and hold times on DIN and WE not shown.
the access time due to the required precharge time tRP (not
drawn to scale).

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EECS 373 F99 Notes 9-2 © 1998, 1999 Steven K. Reinhardt

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 Refresh
Each cell must be refreshed every few milliseconds to avoid
losing data. Whenever a row is read, the sense amps
automatically write back entire row, so we only need to
access every row once during the refresh interval.
• Do one row at a time (not in big burst) to avoid tying up
DRAM for long period
• Typically done in hardware using counter (to track next
row index) and timer (to initiate one refresh)
• Example: Hitachi 64Mbit DRAM requires 8192 refreshes
every 64 ms. Access one row every (64 ms/8192) = 7.8 s.
• Need not provide column address: “RAS-only refresh”
• Can also insert refresh cycle at end of unrelated read
access; if CAS is not deasserted, read data remains valid:
“hidden refresh”
• Some DRAMs have internal counter; system needs only to
indicate when to refresh “next” row by asserting CAS then
RAS (opposite of regular access): “CAS-before-RAS (CBR)
refresh”
Other solutions?
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Interface Optimizations
Problem: DRAM bandwidth (bits/second) has not kept up with
CPU speed increases over the years.
Simple observation: reading out entire row and throwing out
all but one bit is inefficient. Wider chips (x4, x8, x16) help
some, but only as a stopgap. A number of DRAM
enhancements let systems read out many bits from each row:
nibble mode: pusling CAS 4 times w/o deasserting RAS gives
4 adjacent bits (only first column address used)
fast page mode (FPM): pulsing CAS w/o deasserting RAS
takes new column address (do as often as desired)
static column: like FPM, but no need to deassert CAS (latch
is transparent); just change address and it flow through
extended data out (EDO): like FPM, but data stays valid
after deasserting CAS (limited pipelining, lets you pump
in column addresses faster)
EECS 373 F99 Notes 9-3 © 1998, 1999 Steven K. Reinhardt

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 Synchronous DRAM (SDRAM)
As the name implies, a synchronous DRAM has a clock
input, and all signals are defined with respect to clock edges.
• After providing row and column addresses, a
programmable number of bits can be provided one per clock
without any other control inputs
• The next pair of row and column addresses can be
provided while the previous access is still completing
• SDRAMs have multiple (e.g., 4) memory arrays (banks) so
that independent accesses can be even further overlapped:
• provide row address for bank 1
• provide row address for bank 2
• provide column address for bank 1
• provide column address for bank 2
• get data from bank 1
• get data from bank 2
• Clock speeds of 66, 100, 125 MHz
• Sega Saturn was one of the earliest widespread users
• Becoming common in PCs now
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Rambus
Rambus is a revolutionary new DRAM interface that combines
multiple banks per chip with a high-speed bus interface. Two
earlier generations (“Rambus” and “Concurrent Rambus”)
have been superseded by the latest “Direct Rambus” protocol.
Intel is pushing this to be the high-end PC memory technology
by 2000.
• 400 Mhz clock, data transferred on both edges
• 16-bit bus
• result: 1.6 Gbytes per second on one “channel”
• high-end servers will have multiple channels
• 16 banks per chip: if enough accesses go to different
banks, a single chip can provide the full 1.6 GB/s
• nice solution to granularity problem: what is minimum
memory system size/increment given very dense chips?
• SDRAM vendors using two-edge trick in new “dual data
rate” (DDR) SDRAMs
• Sync-Link DRAM (SLDRAM) uses similar ideas as
Rambus (with a few key changes, mostly at the electrical
level), but is standards-based instead of proprietary
 BUSES
 The PCI bus

o Main features:

• coupling of the processor and expansion bus by means of a bridge,

• 32-bit standard bus width with a maximum transfer rate of 133 Mbytes/s,
• expansion to 64 bits with a maximum transfer rate of 266 Mbytes/s,
– PCI-64/66 532 Mbytes/s,PCI-X 64/133 1064 Mbytes/s

• supporting of multi-processor systems,

• burst transfers with arbitrary length,
• supporting of 5 V and 3.3 V power supplies,
• write posting and read prefetching,
• multimaster capabilities,
• operating frequencies from 0 MHz to a maximum of 33 MHz,
– PCI-66 3.3V only, PCI-X 100MHz-133MHz
[Type here]
 • multiplexing of address and data bus reducing the number of pins,
• supporting of ISA/EISA/MCA,
• configuration through software and registers,

• processor independent specification

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[Type here]
 PCI Chipset on Motherboard

Peripheral Component Interconnect (PCI) is a term used to describe a common connection interface
for attaching computer peripherals to a PC's motherboard.

PCI was popular between 1995 and 2005, and was most often used to connect sound cards and
network cards. PCI was also used to connect video cards to the motherboard, but graphics demand
from gaming made it inadequate for that use.

Modern computers mainly use other interface technologies like USB or PCI Express (PCIe). Some
desktop computers might have PCI slots on the motherboard in order to maintain backward
compatibility, but the devices that used to be attached as PCI expansion cards are now either
integrated onto motherboards or attached by other connectors like PCIe.

Note:PCI is also an abbreviation for other technical terms that have nothing to do with Peripheral
Component Interconnect, like protocol capability indicator, program-controlled interrupt, Palm
Computing, panel call indicator, personal computer interface, and more.

Other Names for PCI

PCI is also called a PCI bus; a bus is a term for a path between the components of a computer. You
might also see this term described as Conventional PCI.

However, don't confuse PCI with PCI compliance, which means payment card industry compliance,
or PCI DSS, which means payment card industry data security standard.

How Does PCI Work?

A PCI bus lets you change different peripherals that are attached to the computer system, so it allows
the use of different sound cards and hard drives.

Usually, there are three or four PCI slots on a motherboard. With PCI, you can unplug the component
you want to swap and plug in the new one in the PCI slot. Or, if you have an open slot, you can add
another peripheral like a second hard drive to dual boot your computer, or a special sound card if you
deal with music a lot.

Computers might have more than one type of bus handling different traffic types. The PCI bus used to
come in both 32-bit and 64-bit versions. PCI runs at 33 MHz or 66 MHz.

PCI Cards

PCI cards exist in several shapes and sizes called form factors. Full-size PCI cards are 312 millimeters
long. Short cards range from 119 to 167 millimeters to fit into smaller slots. There are further
variations, too, such as compact PCI, Mini PCI, Low-Profile PCI, and others.

PCI cards use 47 pins to connect, and PCI supports devices that use 5 volts or 3.3 volts.

Peripheral Component Interconnect History

The original bus that allowed expansion cards was the ISA bus invented in 1982 for the original IBM
PC, and which was in use for decades. Intel developed the PCI bus in the early 1990s. It provided
direct access to system memory for connected devices via a bridge connecting to the front-side bus
and eventually to the CPU.

PCI 1.0 was released in 1992, PCI 2.0 in 1993, PCI 2.1 in 1995, PCI 2.2 in 1998, PCI 2.3 in 2002, and
PCI 3.0 in 2004.

PCI became popular when Windows 95 introduced its Plug and Play (PnP) feature in 1995. Intel had
incorporated the PnP standard into PCI, which gave it the advantage over ISA. PCI didn't require
jumpers or dip switches like ISA did.

PCIe improved on PCI and has a higher maximum system bus throughput, a lower I/O pin count, and
is smaller physically. It was developed by Intel and the Arapaho Work Group (AWG). It became the
primary motherboard-level interconnect for PCs by 2012 and replaced Accelerated Graphics Port
(AGP) as the default interface for graphics cards for new systems.

PCI-X is a similar technology to PCI. Standing for Peripheral Component Interconnect eXtended,
PCI-X improves bandwidth on the 32-bit PCI bus for servers and workstations.
 VME Bus:

VME Bus Description

VMEbus System configuration

VME Bus Description

The VME bus is a scalable backplane bus interface.
VME Cards may be produced which respond to the following
Address widths or Data widths:
A01 - A15, A01 - A23, A01 - A31, or A01 - A40
D00 - D07, D00 - D15, D00 - D23, D00 - D31, or D00 - D63 (undefined
before Rev. C).
The tables below detail the required control signals to produce the different
bus widths.
Three main types of cards reside on the VME bus. The Controller, which
supervises bus activity. A Master which Reads/Writes data to a Slave
board, and a Slave interface which simply allows data to be accessed via a
Read or Write from a Master.

VME Controller
The VMEbus Controller 'controls' access to the bus. Upon receiving a
"Bus Request" signal from a bus Master, the Controller will "Bus Grant"
that Master access to the bus. The Controller also handles Interrupts on the
bus. When an Interrupt is received on one of the IRQ lines the Controller
will process that Interrupt by accessing the Interrupting card, and
acknowledge the Interrupt. Only one Controller may reside on the VME
bus.
VME Bus-Master
The VMEbus Master Reads and Writes data to or from a Slave board. The
Master "Bus Requests" access to the VME bus from the Controller. Once
the Controller "Bus Grants" the Master access, the Master drives the
Address and Data bus to perform a data transfer to a Slave board. Any
number of bus Masters may reside on the VME bus, but only one may
have control of the bus at any one time.

VME Bus-Slave
A VMEbus Slave interface simply monitors the Address and Data bus for
Reads or Writes sent to it. Once a correctly decoded address is received the
Slave will either receive information {for a Write}, or output information
onto the Data bus in the case of a Read. The bus Master continues to
control the Data bus during either interface. A Slave may also generate
Interrupts over any of 7 IRQ lines. The Interrupts are acknowledged by the
bus Controller. Any number of Slave boards may reside on the VME bus.

 EISA Bus - Extended Industry Standard Architecture:

Extended Industry Standard Architecture (EISA) is a bus architecture designed for PCs using
an Intel 80386, 80486, or Pentium microprocessor. EISA buses are 32 bits wide and support
multiprocessing.

The EISA bus was designed by nine IBM competitors (sometimes called the Gang of Nine):
AST Research, Compaq Computer, Epson, Hewlett-Packard, NEC, Olivetti, Tandy, WYSE,
and Zenith Data Systems. They designed the architecture to compete with IBM's own high-
speed bus architecture called the Micro Channel architecture (MCA).

The principal difference between EISA and MCA is that EISA is backward compatible with
the ISA bus (also called the AT bus), while MCA is not. This means that computers with an
EISA bus can use new EISA expansion cards as well as old ATexpansion cards. Computers
with an MCA bus can use only MCA expansion cards.

EISA and MCA are not compatiblewith each other. This means that the type of bus in your
computer determines which expansion cards you can install.

Neither EISA nor MCA has been very successful. Instead, a new technology called local bus
(PCI) is being used in combination with the old ISA bus.

 IEEE 488/489 Bus/ General Purpose Interface Bus (GPIB) and Hewlett-
Paekard interface:
It is a 24-pin standard bus which is used for connecting different I/O devices like
measuring instrument, CRT, keyboard with CPU in a multiterminal system (UNIX
System). The device which can be connected with the help of IEEE 488 bus can be
classified into following types.
1) LISTNER :- (Output Device)
A device which can only receive data from system bus is called as listner.
Example: Printer, CRT Screen, Voltmeter etc.
2) TALKER:- (Input Device)
A device which can only transfer data to system bus is called Talker.
Example: Keyboard.
3) LISTNER AND TALKER:
A device which can receive as well as transfer data to system bus is called as Listners and
Talker.
Example: Audio Cassettes, Floppy Disk, RAM Memory.
4) Controller:
A device which controls devices which are connected with system bus is called Controller.
With the help of control signals the controller will specify that which device will talk and
which device will listen.
Example: CPU 8086, 8088, 8085, 8089.
Using IEEE 488 bus the different devices can be connected and data transfer rate is 1MB
per second.
Also GPIB has 8-bidirectional data pins this pins are used to transfer data. The GPIB has
full bus management lines which functions basically as follows:-
1) IFC (Interface Clear Line):
The IFC when asserted by the controller reset all devices on the bus to a starting state. It is
essentially a system reset.
2) ATN (Attention Line):
The ATN Line when asserted (low) indicates that the controller is putting a universal
command on an address command such as listner on the data bus. When ATN is high, then
data line contain data on status byte.
3) SRQ (Service Request):
The SRQ is similar to an interrupt. Any device that needs to transfer data on the bus asserts
the SRQ line low. The controller then poles all the devices to determine which one needs
services, when asserted by the system controller.
4) REN (Remote Enable Signal):
REN allows an instrument to be controlled directly by the controller rather than by its front
panel switches.
5) EOI (End Of Identify Signal):
The END of identify signal is usually asserted by a talker to indicate that the transfer of
 block of data is completed. Finally the bus has three hand shake lines that Co-ordinates the
transfer of data bytes on data bus. There are three hand shake
a) Data valid (DAV) b) Not ready for data (NRED) c) Not data accepted (NDAC)
Advantages:
The importance of GPIB is that it allows a microcomputer to be connected with several test
instruments to form an integrated test system.

 8087 Math Co-processor

8087 numeric data processor is also known as Math co-processor, Numeric processor
extension and Floating point unit. It was the first math coprocessor designed by Intel to pair
with 8086/8088 resulting in easier and faster calculation.

Once the instructions are identified by the 8086/8088 processor, then it is allotted to the 8087
co-processor for further execution.

The data types supported by 8087 are −

 Binary Integers
 Packed decimal numbers
 Real numbers
 Temporary real format

The most prominent features of 8087 numeric data processor are as follows −

 It supports data of type integer, float, and real types ranging from 2-10 bytes.
 The processing speed is so high that it can calculate multiplication of two 64-bits real
numbers in ~27 µs and can also calculate square-root in ~35 µs.
 It follows IEEE floating point standards.

8087 Architecture
8087 Architecture is divided into two groups, i.e., Control Unit (CU) and Numeric
Extension Unit (NEU).

 The control unit handles all the communication between the processor and the memory
such as it receives and decodes instructions, reads and writes memory operands,
maintains parallel queue, etc. All the coprocessor instructions are ESC instructions, i.e.,
they start with ‘F’, the coprocessor only executes the ESC instructions while other
instructions are executed by the microprocessor.
  The numeric extension unit handles all the numeric processor instructions like
arithmetic, logical, transcendental, and data transfer instructions. It has 8 register stack,
which holds the operands for instructions and their results.

The architecture of 8087 coprocessor is as follows −

8087 Pin Description

Let us first take a look at the pin diagram of 8087 −
The following list provides the Pin Description of 8087 −

 AD0 – AD15 − These are the time multiplexed address/data lines, which carry addresses
during the first clock cycle and data from the second clock cycle onwards.
 A19 / S6 – A16/S − These lines are the time multiplexed address/status lines. It functions
in a similar way to the corresponding pins of 8086. The S6, S4 and S3 are permanently
high, while the S5 is permanently low.
 $\overline{BHE}$/S7 − During the first clock cycle, the $\overline{BHE}$/S7 is used to
enable data on to the higher byte of the 8086 data bus and after that works as status line
S7.
 QS1, QS0 − These are queue status input signals which provides the status of instruction
queue, their conditions as shown in the following table −

QS0 QS1 Status

0 0 No operation
0 1 First byte of opcode from the queue
1 0 Empty the queue
1 1 Subsequent byte from the queue

 INT − It is an interrupt signal, which changes to high when an unmasked exception has
been received during the execution.
 BUSY − It is an output signal, when it is high it indicates a busy state to the CPU.
 READY − It is an input signal used to inform the coprocessor whether the bus is ready
to receive data or not.
  RESET − It is an input signal used to reject the internal activities of the coprocessor
and prepare it for further execution whenever required by the CPU.
 CLK − The CLK input provides the basic timings for the processor operation.
 VCC − It is a power supply signal, which requires +5V supply for the operation of the
circuit.
 S0, S1, S2 − These are the status signals that provide the status of the operation which is
used by the Bus Controller 8087 to generate memory and I/O control signals. These
signals are active during the fourth clock cycle.

S2 S1 S0 Queue Status
0 XX Unused
1 0 0 Unused
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive

 RQ/GT1 & RQ/GT0 − These are the Request/Grant signals used by the 8087
processors to gain control of the bus from the host processor 8086/8088 for operand
transfers.

DMA-Direct Memory Access:

DMA stands for Direct Memory Access. It is designed by Intel to transfer data at the fastest
rate. It allows the device to transfer the data directly to/from memory without any interference
of the CPU.

Using a DMA controller, the device requests the CPU to hold its data, address and control bus,
so the device is free to transfer data directly to/from the memory. The DMA data transfer is
initiated only after receiving HLDA signal from the CPU.

How it functions:

 Initially, when any device has to send data between the device and the memory, the
device has to send DMA request (DRQ) to DMA controller.
 The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to
assert the HLDA.
 Then the microprocessor tri-states all the data bus, address bus, and control bus. The
CPU leaves the control over bus and acknowledges the HOLD request through HLDA
signal.
 Now the CPU is in HOLD state and the DMA controller has to manage the operations
over buses between the CPU, memory, and I/O devices.
 Function of DMA:

DMA stands “Direct Memory Access” . It is a mechanism that allows I/O devices to access
main memory without having to go through the CPU , which is a time consuming process.

I made a couple slides to visualize it further .

Let’s present an example : we’ll assume we only have 3 components in our system : the CPU
itself , RAM , and an I/O device , in this case storage.

Let’s say i want to transfer a large 1GB contiguous file from a specified location on the hard
drive, let’s say sector A , and i want to put in in memory at address N .Let’s ignore any latency
associated with memory or the storage medium itself.We’ll also assume the CPU is a standard
Register-register machine , with loads and stores as it’s only way of interacting with the
outside world.

The processor will load the first byte/word found sector A into a register , then store it to
address N .

It then loads the second byte/word into a register and stores it to address N+1 .

Then it does the same for the third byte , and the forth , and fifth etc . Each byte/word needs to
go through the CPU , and the CPU needs to calculate the addresses where this data needs to go
, and store it there. It does so for .Every. Single .Byte. For very small things this isn’t much of
an issue , but with anything larger than a couple bytes , the CPU ends up spending a lot of time
in a tight loop transferring data around . That’s not a very efficient use of our limited cpu
cycles. This goes for everything that needs to access RAM too , not just a hard drive .
Enter the DMA controller : this is a small bit of logic that takes on the job of transferring stuff
around . It will calculate the addresses required for indexing memory instead of the CPU ,
leaving it free to do other things.

image from slideshare :”Input output in computer Organization and architecture”

Essentially , with DMA , the CPU will tell the DMA controller that it wishes to access data
from I/O device 1 , which is 1GB long , is present at location A , and needs to be put in RAM
starting from location N . The controller will then acknowledge that and go fetch it from the
required I/O device , then put it into RAM. Once that is done , it will send an interrupt to the
CPU , signaling the processor that the transfer is done . This also works for writes , where data
is fetched from RAM at a specified location and is sent to the requested I/O device , again at a
specified location.

The DMA controller offers quite a few options for transferring data between system memory
and a peripheral device, like burst transfer and cycle stealing, as you mentioned.
Burst Transfer Mode:
Burst transfer is the fastest way to transfer memory. The DMA controller assumes that source
and destination memory address/IO port can transfer and accept the data as quickly as the
DMA controller can produce them, so after the controller is set up and the CPU has released
control of the address and data buses, the entire block of memory is copied to the destination
as a single contiguous block. For the entire duration of the transfer, the CPU stays idle and the
DMA controller and the peripheral device gets complete access to the system buses.

Cycle Stealing Mode:

Cycle Stealing mode is similar to Burst Transfer mode, but instead of the data being
transferred all at once, it is transferred one byte at a time. The DMA controller, after
transferring one byte of data, releases control of the system buses by sending a bus grant signal
through the control bus, lets the CPU process an instruction and then requests access to the bus
by sending the bus request signal through the control bus and then transfers another byte of
data. This keeps going on until all the data has been transferred. The transfer rate is slower but
it prevents the CPU from staying idle for a long period of time.

8089 processor / I/O processor:

What is I/O processor? What are its functions? Draw an internal block diagram of 8089 and
explain function of each block in detail?
8089 is known as I/O processor and it is designed to work with Intel 8086 family of
processor. An I/O processor is supposed to take care of all system I/O activities.
Functions: - 8089 IOP communication with host processor uses a memory table
which contains details of task to be executed. These tables are prepared by host CPU
to allot the task to the IOP 8089. The host interrupts IOP after allotting a task to it
once IOP interrupted and reads the memory table prepared by host CPU to get the
detail of allotted task. This memory table has an address of program written in 8089
instruction called as channel program 8089 executes the channel program.
Unlike 8087, the 8089 can fetch and execute its instruction on its own 8089 may be
operated in tightly as loosely coupled configuration.
NOTE: In a tightly coupled configuration the 8089 shares the system bus and
memory with the host CPU using its RQ¯/GTO pin.
In a loosely coupled configuration 8089 has its own local bus and communicated
with the host using bus arbiter and controller.
Description of Block Diagram:-
The 8089 is divided into following functional unit.
A) CCU (Common Control Unit) :
1) All IOP operations (instructions), (DMA transfer channel attention response etc)
are composed of sequences of more basic process called internal cycle.
2) A bus cycle takes one internal cycle, the execution of an instruction require
several internal cycle.
3) The common control unit co ordinates the activities of IOP primarily by allocating
 internal cycles to various procedure units i.e. it determines which unit will execute
next internal cycle.
B) ALU (Arithmetic and Logic Unit):
As usually ALU can perform unsigned binary arithmetic on 8 and 16 bit binary
numbers. Arithmetic result may be up to 20 bits in length.
The available arithmetic instruction is addition, increment, and decrement. The
available logical instruction are AND, OR, NOT.
C) Assembly/Disassembly Registers:
IOP 8089 allows user flexibility of data transfer between different widths buses for
example 8 bit peripherals to 16 bit memory. Therefore all data entering the chip,
flows through these registers and IOP uses assembly/disassembly registers when we
use different width buses.
D) Instruction fetch unit:
This unit controls instruction fetching further executing channel (one at a time).
If the bus over which the instruction are being fetched is 8-bit wide the instruction
are obtained on byte at a time and each fetch requires one bus cycle.
E) Bus interface unit:
The BIU runs all bus cycles, transferring instruction and data between IOP and
external memory/peripherals.
BIU interact with following signals: - a)Ready b) CLH c) RQ¯/GT¯ d) S0¯-S2¯ e)
LOCK¯ f) BHE¯
F) Channels:
The 8089 has two internal IO channels which can be programmed independently to
handle separate IO task for the host CPU. The common ALU is shared by both the
channels channel contain.
a) IO control
b) Registers 1) General Purpose A: - (GA)
2) General purpose B: - (GB)
3) General Purpose C: - (GC)
4) Tast Pointer
5) Parameter Block Pointer
6) Index (IX)
7) Byte Count (BC) 8) Mask Compare 9) Channel Control (PP) 10) PSW

 Minimum Mode and Maximum Mode operations on 8086

processors:
General BusOperation
 The 8086 has a combined address and data bus commonly referred as a time
multiplexed addressand databus.
 The main reason behind multiplexing address and data over the same pins is the
maximum utilization of processor pins and it facilitates the use of 40 pin standard DIP
package.
 The bus can be demultiplexed using afew latches and transreceivers, when ever required.
 Basically, all the processor bus cycles consist of at least four clock cycles. These are
referred to as T1, T2, T3, and T4. The address is transmitted by the processor during T1. It
is present on the bus only for one cycle.
 The negative edge of this ALE pulse is used to separate the address and the data or status
information. In maximum mode, the status lines S0, S1and S2 are used to indicate the type
of operation.
 Status bits S3 to S7 are multiplexed with higher order address bits and the BHE
signal. Addressisvalid during T1while statusbits S3to S7 are valid during T2 through
T4.

 M aximum mode

 In the maximum mode, the 8086 isoperated by strapping the M N/ M X pin to ground.
 In this mode, the processor derives the status signal S2, S1, S0. Another chip called
bus controller derivesthe control signal using thisstatusinformation.
 In the maximum mode, there may be more than one microprocessor in the
system configuration.
 M inimum mode

 In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum

mode by strapping its M N/ M X pin to logic 1.
 In this mode, all the control signals are given out by the microprocessor chip itself.
 There is asingle microprocessor in the minimum mode system.

 M inimum M ode 8086 System

 In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum

mode by strapping its M N/ M X pin to logic 1.

 In this mode, all the control signals are given out by the microprocessor chip itself. There
is a single microprocessor in the minimum mode system.

 The remaining components in the system are latches, transreceivers, clock generator,
memory and I/ O devices. Some type of chip selection logic may be required for
selecting memory or I/ O devices, depending upon the address map of the system.

 Latches are generally buffered output D-type flip-flops like 74LS373 or 8282. They are
used for separating the valid address from the multiplexed address/ data signals and are
controlled by the ALEsignal generated by 8086.

 Transreceivers are the bidirectional buffers and some times they are called as data
amplifiers. They are required to separate the valid data from the time multiplexed
address/ datasignals.

 They are controlled by two signals namely, DEN and DT/ R.

 The DEN signal indicates the direction of data, i.e. from or to the processor. The
system contains memory for the monitor and users program storage.

 Usually, EPROM is used for monitor storage, while RAM for user’s program
storage. A system may contain I/ O devices.
 W rite Cycle Timing Diagram for M inimum M ode

 The working of the minimum mode configuration system can be better described in
terms of the timing diagrams rather than qualitatively describing the operations.

 The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized
in two parts, the first is the timing diagram for read cycle and the second is the timing
diagram for write cycle.

 The read cycle begins in T1with the assertion of address latch enable (ALE) signal and
also M
/ IO signal. During the negative going edge of this signal, the valid address is latched on
the local bus.

 The BHE and A0 signals address low, high or both bytes. From T1 to T4, the M / IO
signal indicates a memory or I/ O operation.

 At T2, the address is removed from the local bus and is sent to the output. The bus is
then tristated. The read (RD) control signal is also activated in T2.

 The read (RD) signal causes the address device to enable its data bus drivers. After RD
goes low, the valid data is available on the data bus.
 The addressed device will drive the READY line high. When the processor returns the
read signal to high level, the addressed device will again tristate its bus drivers.

 A write cycle also begins with the assertion of ALE and the emission of the address.
The M / IO signal is again asserted to indicate a memory or I/ O operation. In T2, after
sending the address in T1, the processor sends the data to be written to the addressed
location.

 The data remains on the bus until middle of T4 state. The WR becomes active at
the beginning of T2 (unlike RD is somewhat delayed in T2 to provide time for floating).

 The BHEand A0 signals are used to select the proper byte or bytesof memory or I/ O
word to be read or write.

 The M / IO, RD and WR signals indicate the type of datatransfer asspecified in table
below.

 BusRequest and Bus Grant Timings in M inimum M ode System of 8086

 Hold Response sequence: The HOLD pin is checked at leading edge of each clock pulse.
If it is received active by the processor before T4 of the previous cycle or during T1
state of the current cycle, the CPU activates HLDA in the next clock cycle and for
succeeding bus cycles, the buswill be given to another requesting master.

 The control of the bus is not regained by the processor until the requesting master does
not drop the HOLD pin low. When the request is dropped by the requesting master, the
HLDA is dropped by the processor at the trailing edge of the next clock.
 M aximum M ode 8086 System

 In the maximum mode, the 8086 isoperated by strapping the M N/ M X pin to ground.

 In this mode, the processor derives the status signal S2, S1, S0. Another chip called
bus controller derivesthe control signal using thisstatusinformation.

 In the maximum mode, there may be more than one microprocessor in the system
configuration.

 The componentsin the system are same as in the minimum mode system.

 The basic function of the bus controller chip IC8288 is to derive control signals like
RD and WR (for memory and I/ O devices), DEN, DT/ R, ALE etc. using the
information by the processor on the statuslines.

 The bus controller chip has input lines S2, S1, S0 and CLK. These inputs to 8288 are driven
by CPU.

 It derives the outputs ALE, DEN, DT/ R, M RDC, M WTC, AM WC, IORC, IOWC
and AIOWC. The AEN, IOB and CEN pins are especially useful for multiprocessor
systems.
 AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The
significance of the M CE/ PDEN output dependsupon the status of the IOB pin.
 If IOB is grounded, it acts as master cascade enable to control cascade 8259A,
else it acts as peripheral data enable used in the multiple bus configurations.
 INTA pin used to issue two interrupt acknowledge pulses to the interrupt
controller or to an interrupting device.
 IORC, IOWC are I/ O read command and I/ O write command
signalsrespectively.
 These signals enable an IO interface to read or write the datafrom or to the
address port.
 The M RDC, M WTC are memory read command and memory write
command signals respectively and may be used as memory read or write
signals.
 All these command signalsinstructs the memory to accept or send data from or to
the bus.
 For both of these write command signals, the advanced signals namely AIOWC
and AM WTC are available.
 Here the only difference between in timing diagram between minimum mode
and maximum mode is the statussignalsused and the available control and
advanced command signals.
 R0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will
output a pulse as on the ALEand apply a required signal to its DT / R pin
during T1.
 In T2, 8288 will set DEN=1thus enabling transceivers, and for an input it will
activate M RDC or IORC. These signals are activated until T4. For an output,
the AM WC or AIOWC is activated from T2 to T4 and M WTC or IOWC
is activated from T3to T4.
 The status bit S0 to S2 remains active until T3and become passive during T3and
T4.
 If reader input is not activated before T3, wait state will be inserted between
T3and T4.
 M emory Read Timing Diagram in M aximum M ode of 8086

 M emory W rite Timing in M aximum mode of 8086

 RQ/ GT Timings in M aximum M ode

 The request/ grant response sequence contains a series of three pulses. The
request/ grant pins are checked at each rising pulse of clock input.

 When a request is detected and if the condition for HOLD request is

satisfied, the processor issues agrant pulse over the RQ/ GT pin
immediately during T4 (current) or T1( next) state.

 When the requesting master receives this pulse, it accepts the control of
the bus; it sends a release pulse to the processor using RQ/ GT pin.
 Unit 2

 8251 UNIVERSAL SYNCHRONOUS

ASYNCHRONOUS RECEIVER TRANSMITTER
(USART)
The 8251 is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for
serial data communication. As a peripheral device of a microcomputer system, the 8251
receives parallel data from the CPU and transmits serial data after conversion. This
device also receives serial data from the outside and transmits parallel data to the CPU
after conversion.

Block diagram of the 8251 USART (Universal Synchronous Asynchronous

Receiver Transmitter)
The 8251 functional configuration is programed by software. Operation between the
8251 and a CPU is executed by program control. Table 1 shows the operation between
a CPU and the device.

Table 1 Operation between a CPU and 8251

Control Words

There are two types of control word.

1. Mode instruction (setting of function)

2. Command (setting of operation)

1) Mode Instruction

Mode instruction is used for setting the function of the 8251. Mode instruction will be in
"wait for write" at either internal reset or external reset. That is, the writing of a control
word after resetting will be recognized as a "mode instruction."

Items set by mode instruction are as follows:

• Synchronous/asynchronous mode

• Stop bit length (asynchronous mode)

• Character length
• Parity bit

• Baud rate factor (asynchronous mode)

• Internal/external synchronization (synchronous mode)

• Number of synchronous characters (Synchronous mode)

The bit configuration of mode instruction is shown in Figures 2 and 3. In the case of
synchronous mode, it is necessary to write one-or two byte sync characters. If sync
characters were written, a function will be set because the writing of sync characters
constitutes part of mode instruction.
2) Command

Command is used for setting the operation of the 8251. It is possible to write a
command whenever necessary after writing a mode instruction and sync characters.

Items to be set by command are as follows:

• Transmit Enable/Disable

• Receive Enable/Disable

• DTR, RTS Output of data.

• Resetting of error flag.

• Sending to break characters

• Internal resetting
• Hunt mode (synchronous mode)

Status Word

It is possible to see the internal status of the 8251 by reading a status word. The bit
configuration of status word is shown in Fig. 5.
Pin Description

D 0 to D 7 (l/O terminal)

This is bidirectional data bus which receive control words and transmits data from the
CPU and sends status words and received data to CPU.

RESET (Input terminal)

A "High" on this input forces the 8251 into "reset status." The device waits for the writing
of "mode instruction." The min. reset width is six clock inputs during the operating status
of CLK.

CLK (Input terminal)

CLK signal is used to generate internal device timing. CLK signal is independent of RXC
or TXC. However, the frequency of CLK must be greater than 30 times the RXC and
TXC at Synchronous mode and Asynchronous "x1" mode, and must be greater than 5
times at Asynchronous "x16" and "x64" mode.

WR (Input terminal)

This is the "active low" input terminal which receives a signal for writing transmit data
and control words from the CPU into the 8251.

RD (Input terminal)

This is the "active low" input terminal which receives a signal for reading receive data
and status words from the 8251.

C/D (Input terminal)

This is an input terminal which receives a signal for selecting data or command words
and status words when the 8251 is accessed by the CPU. If C/D = low, data will be
accessed. If C/D = high, command word or status word will be accessed.

CS (Input terminal)

This is the "active low" input terminal which selects the 8251 at low level when the CPU
accesses. Note: The device won’t be in "standby status"; only setting CS = High.

TXD (output terminal)

This is an output terminal for transmitting data from which serial-converted data is sent
out. The device is in "mark status" (high level) after resetting or during a status when
transmit is disabled. It is also possible to set the device in "break status" (low level) by a
command.

TXRDY (output terminal)

This is an output terminal which indicates that the 8251is ready to accept a transmitted
data character. But the terminal is always at low level if CTS = high or the device was
set in "TX disable status" by a command. Note: TXRDY status word indicates that
transmit data character is receivable, regardless of CTS or command. If the CPU writes
a data character, TXRDY will be reset by the leading edge or WR signal.

TXEMPTY (Output terminal)

This is an output terminal which indicates that the 8251 has transmitted all the
characters and had no data character. In "synchronous mode," the terminal is at high
level, if transmit data characters are no longer remaining and sync characters are
automatically transmitted. If the CPU writes a data character, TXEMPTY will be reset by
the leading edge of WR signal. Note : As the transmitter is disabled by setting CTS
"High" or command, data written before disable will be sent out. Then TXD and
TXEMPTY will be "High". Even if a data is written after disable, that data is not sent out
and TXE will be "High".After the transmitter is enabled, it sent out. (Refer to Timing
Chart of Transmitter Control and Flag Timing)

TXC (Input terminal)

This is a clock input signal which determines the transfer speed of transmitted data. In
"synchronous mode," the baud rate will be the same as the frequency of TXC. In
"asynchronous mode", it is possible to select the baud rate factor by mode instruction. It
can be 1, 1/16 or 1/64 the TXC. The falling edge of TXC sifts the serial data out of the
8251.

RXD (input terminal)

This is a terminal which receives serial data.

RXRDY (Output terminal)

This is a terminal which indicates that the 8251 contains a character that is ready to
READ. If the CPU reads a data character, RXRDY will be reset by the leading edge of
RD signal. Unless the CPU reads a data character before the next one is received
completely, the preceding data will be lost. In such a case, an overrun error flag status
word will be set.

RXC (Input terminal)

This is a clock input signal which determines the transfer speed of received data. In
"synchronous mode," the baud rate is the same as the frequency of RXC. In
"asynchronous mode," it is possible to select the baud rate factor by mode instruction. It
can be 1, 1/16, 1/64 the RXC.

SYNDET/BD (Input or output terminal)

This is a terminal whose function changes according to mode. In "internal synchronous

mode." this terminal is at high level, if sync characters are received and synchronized. If
a status word is read, the terminal will be reset. In "external synchronous mode, "this is
an input terminal. A "High" on this input forces the 8251 to start receiving data
characters.

In "asynchronous mode," this is an output terminal which generates "high level"output

upon the detection of a "break" character if receiver data contains a "low-level" space
between the stop bits of two continuous characters. The terminal will be reset, if RXD is
at high level. After Reset is active, the terminal will be output at low level.

DSR (Input terminal)

This is an input port for MODEM interface. The input status of the terminal can be
recognized by the CPU reading status words.

DTR (Output terminal)

This is an output port for MODEM interface. It is possible to set the status of DTR by a
command.

CTS (Input terminal)

This is an input terminal for MODEM interface which is used for controlling a transmit
circuit. The terminal controls data transmission if the device is set in "TX Enable" status
by a command. Data is transmitable if the terminal is at low level.

RTS (Output terminal)

This is an output port for MODEM interface. It is possible to set the status RTS by a
command.

RS-232:
 What is RS232?
RS232C “Recommended Standard 232C” is the recent version of Standard 25 pin
whereas,RS232D which is of 22 pins. In new PC’s male D-type which is of 9 pins.
RS232 is a standard protocol used for serial communication, it is used for connecting
computer and its peripheral devices to allow serial data exchange between them. As it
obtains the voltage for the path used for the data exchange between the devices. It is used
in serial communication up to 50 feet with the rate of 1.492kbps. As EIA defines, the
RS232 is used for connecting Data Transmission Equipment (DTE) and Data
Communication Equipment (DCE).

Universal Asynchronous Data Receiver &Transmitter (UART) used in connection with

RS232 for transferring data between printer and computer. The microcontrollers are not
able to handle such kind of voltage levels, connectors are connected between RS232
signals. These connectors are known as the DB-9 Connector as a serial port and they are
of two type’sMale connector (DTE) & Female connector (DCE).
 Electrical Specifications
Let us discuss the electrical specifications of RS232 given below:
 Voltage Levels: RS232 also used as ground & 5V level. Binary 0 works with
voltages up to +5V to +15Vdc. It is called as ‘ON’ or spacing (high voltage level)
whereas Binary 1 works with voltages up to -5V to -15Vdc. It is called as ‘OFF’ or
marking (low voltage level).
 Received signal voltage level: Binary 0 works on the received signal voltages up to
+3V to +13 Vdc & Binary 1 works with voltages up to -3V to - 13 Vdc.
 Line Impedances: The impedance of wires is up to 3 ohms to 7 ohms & the
maximum cable length are 15 meters, but new maximum length in terms of
capacitance per unit length.
 Operation Voltage: The operation voltage will be 250v AC max.
 Current Rating: The current rating will be 3 Amps max.
 Dielectric withstanding voltage: 1000 VAC min.
 Slew Rate: The rate of change of signal levels is termed as Slew Rate. With its slew
rate is up to 30 V/microsecond and the maximum bitrate will be 20 kbps.

 How RS232 Works?

RS232 works on the two-way communication that exchanges data to one another. There
are two devices connected to each other,(DTE) Data Transmission Equipment& (DCE)
Data Communication Equipment which has the pins like TXD, RXD, and RTS& CTS.
Now, from DTE source, the RTS generates the request to send the data. Then from the
other sideDCE, the CTS, clears the path for receiving the data. After clearing a path, it will
give a signal to RTS of the DTE source to send the signal. Then the bits are transmitted
fromDTE to DCE. Now again from DCE source, the request can be generated by RTS
and CTS of DTE sources clears the path for receiving the data and gives a signal to send
the data. This is the whole process through which data transmission takes place.
TXD TRANSMITTER

RXD RECEIVER

RTS REQUEST TO SEND

CTS CLEAR TO SEND

GND GROUND

For example: The signals set to logic 1, i.e., -12V. The data transmission starts from next
bit and to inform this, DTE sends start bit to DCE. The start bit is always ‘0’, i.e., +12 V
& next 5 to 9 characters is data bits. If we use parity bit, then 8 bits data can be transmitted
whereas if parity doesn’t use, then 9 bits are being transmitted. The stop bits are sent by
the transmitter whose values are 1, 1.5 or 2 bits after the data transmission.
 Mechanical Specification

For mechanical specifications, we have to study about two types of connectors that is
DB-25 and DB-9. In DB-25, there are 25 pins available which are used for many of the
applications, but some of the applications didn’t use the whole 25 pins. So, the 9 pin
connector is made for the convenience of the devices and equipments.

Now, here we are discussing the DB-9 pin connector which is used for connection
between microcontrollers and connector. These are of two types: Male Connector
(DTE) & Female Connector (DCE). There are 5 pins on the top row and 4 pins in the
bottom row. It is often called DE-9 or D-type connector.

Pin Structure of DB-9 Connector:

RS232 or DB9 male connector

 RS232 or DB9 female connector

Pin Description DB-9 Connector:

PIN No. Pin Name Pin Description

1 CD (Carrier Detect) Incoming signal from DCE

2 RD (Receive Data) Receives incoming data from DTE

3 TD (Transmit Data) Send outgoing data to DCE

DTR (Data Terminal

4 Ready) Outgoing handshaking signal

5 GND (Signal ground) Common reference voltage

6 DSR (Data Set Ready) Incoming handshaking signal

7 RTS (Request to Send) Outgoing signal for controlling flow

8 CTS (Clear to Send) Incoming signal for controlling flow

9 RI (Ring Indicator) Incoming signal from DCE

  RS-422 Standard:
 Introduction to RS-422: serial data standard:
RS422 provides much higher data speeds than RS232 as a result of the differential
signal and other techniques used.

RS422 was introduced to enable higher data rates to be transferred over serial data lines than was
possible with RS232.

RS422 is able to provide data rates of up to 10 Mbps at distances up to 50 feet (15.24 metres).
However using reduced data rates, RS422 is able to transmit data over distances of 4000 feet
(~1220 metres): the maximum is 100 kbps at this distance.

The key reason why RS422 is able to achieve these improvements results from the use of
differential or balanced transmission techniques.

RS422 uses both differential transmitters and receivers which means that it is much more
resilient to common mode interference, a key issue with long lines.

Lower voltage line levels are used for RS422: A space is represented by a line voltage level in
the band between +2 and +6 volts while a mark is represented by a voltage in the range -2 to -6
volts. The range between +2 and -2 volts provides a good noise margin for the system.
Additionally the RS422 standard allows for line impedances down to 50 ohms while supporting
the high data rates.

To enable the differential driver to be used, the RS-422 standard uses a four conductor cable.
Additionally up to ten receivers can be placed on a single cable, providing a multi-point network
or bus.

Although RS422 is significantly different to RS232, it can often be used as a direct interface in
many instances.

RS422 specification

RS422 Standard Summary

Attribute Specification
Single ended
Cabling
Multi-drop
5 transmitters
Number of devices
10 receivers
half duplex
Communications modes
full duplex
 RS422 Standard Summary
Attribute Specification
Maximum distance 4000 feet @ 100 kbps
Maximum data rate 10 Mbps @ 50 feet
Signaling Balanced
Mark (data = 1)
2V to 6V (B greater than A)
condition
Space (data = 0)
2V to 6 V (A greater than B)
condition
Driver output current capability 150 mA

Although RS232 has been the most popular standard for serial data transmission, the
higher speeds offered by RS422 are a distinct advantage and as a result, it is being used
more widely. In addition to this, it can be used almost interchangeably with RS232 and
this provides a significant advantage.

 RS-499/RS-449 Standards:
 RS449: Interface and Pinout:
RS449 was a standard that was intended to provide fast serial data transmission:-
discover the technology, pinout & interface.

The RS449 serial data standard was intended as an enhancement to RS232. It was aimed at
providing serial data transmission at speeds up to 2 Mbps whilst still being able to maintain
compatibility with RS232.

Though never applied on personal computers, this interface was found on some network
communication equipment. The RS449 standard has now been discontinued and may also be
seen in some references as EIA-449, TIA-449 and ISO 4902

RS449 interface
One of the ways in which the RS449 data communications standard is able to send at high speeds
without stray noise causing interference is to use a differential form of signalling. Earlier data
communications standards such as RS232 used signalling that was referenced to earth and while
this was easier to implement and cheaper to cable, it introduced limitations into the system.

By using twisted wire pairs for the data lines, any unwanted noise will be picked up by both
wires together. As the RS449 receivers use a differential input, and they are not referenced to
ground, any noise that is picked up does not affect the input. This means that higher levels of
noise can be tolerated without any degradation to the performance to the data communications
system.
For the RS449 interface, ten additional circuits functions have been provided when compared to
RS232. Additionally three of the original interchange circuits have been abandoned.

In order to minimise any confusion that could easily occur, the circuit abbreviations have been
changed. In addition to this the RS449 interface requires the use of 37 way D-type connectors
and 9 way D-type connectors, the latter being necessary when use is made of the secondary
channel interchange circuits.

RS449 Primary connector pinout and interface connections

The RS449 primary connector, which is used the one that is used as standard uses a 37 way D-
type connector. The pinout and connections are given in the table below:
Pin Signal Name Description
1 Shield
2 SI Signal Rate Indicator
3 n/a unused
4 SD- Send Data (A)
5 ST- Send Timing (A)
6 RD- Receive Data (A)
7 RS- Request To Send (A)
8 RT- Receive Timing (A)
9 CS- Clear To Send (A)
10 LL Local Loopback
11 DM- Data Mode (A)
12 TR- Terminal Ready (A)
13 RR- Receiver Ready (A)
14 RL Remote Loopback
15 IC Incoming Call
16 SF/SR+ Signal Freq./Sig. Rate Select.
17 TT- Terminal Timing (A)
18 TM- Test Mode (A)
19 SG Signal Ground
20 RC Receive Common
21 n/a unused
22 SD+ Send Data (B)
23 ST+ Send Timing (B)
24 RD+ Receive Data (B)
25 RS+ Request To Send (B)
26 RT+ Receive Timing (B)
27 CS+ Clear To Send (B)
28 IS Terminal In Service
29 DM+ Data Mode (B)
30 TR+ Terminal Ready (B)
31 RR+ Receiver Ready (B)
32 SS Select Standby
33 SQ Signal Quality
34 NS New Signal
35 TT+ Terminal Timing (B)
36 SB Standby Indicator
37 SC Send Common
 RS449 primary connector pinout and connections

Within the RS449 interface a number of differential connections are defined. In the pinout table
above they are labelled as either "A and B" or "+" and "-". When setting up a connection, it is
necessary to ensure that the correct polarities are used. As twisted pairs are used for the A and B
connections it is often possible to mix the. If this happens the interface will not work.

RS449 auxilliary connector

A second connector is defined for use when the secondary channel interchange circuits are
needed.. This connector uses a 9 way D-type connector.

Pin Signal Name Description

1 Shield
2 SRR Secondary Receive Ready
3 SSD Secondary Send Data
4 SRD Secondary Receive Data
5 SG Signal Ground
6 RC Receive Common
7 SRS Secondary Request to Send
8 SCS Secondary Clear to Send
9 SC Send Common
RS449 secondary connector

The RS449 data communications interface is an interface standard that is able to provide data
communications with speeds of up to 2 Mbps. Retaining some similarities to RS232, it is a more
comprehensive interface capable of greater speeds and operation with greater levels of data
integrity.

Synchronous Transmission
In synchronous transmission, data moves in a complete paired approach in the form of chunks
or frames. Synchronisation between the source and target is required so that the source knows
where the new byte begins since there is no space between the data.
Synchronous transmission is effective, dependable and is utilised for transmitting a large amount
of data. It offers real-time communication between linked devices.
A comparison of synchronous transmission would be the transfer of a large text file. Before the
file is transmitted, it is first dissected into blocks of sentences. The blocks are then transferred
over the communication link to the target location.
Because there is no beginning and end bits the data transfer rate is quicker but there’s a
possibility of more errors to occur. Over time, clocks will get out of sync and the target device
would have the incorrect time, so some bytes could become tampered due to lost bits. To resolve
this issue, there is a need for regular re-synchronisation of the clocks as well as the use of check
digits to make sure that the bytes are correctly received and translated.

Characteristics of Synchronous Transmission

 There are no spaces in between characters being sent.

 Timing is provided by modems or other devices at the end of the transmission.
 Special syn characters goes before the data being sent.
 The syn characters are applied between chunks of data for timing functions.

Examples of Synchronous Transmission

 Chatrooms
 Video conferencing
 Telephonic conversations
 Face-to-face interactions

Asynchronous Transmission
In asynchronous transmission data moves in a half-paired approach, 1 byte or 1 character at a
time. It sends the data in a constant current of bytes. The size of a character transmitted is 8 bits
where a parity bit is added each at the beginning and at the end which makes it a total of 10
bits. It doesn’t need a clock for integration; rather it utilises the parity bits to inform the receiver
how to translate the data.
It is straightforward, quick, cost-effective and doesn’t need a 2-way communication.

Characteristics of Asynchronous Transmission

 Each character is headed by a beginning bit and superseded by one or more end bits.
 There may be gaps or spaces in between characters.

Examples of Asynchronous Transmission

 Emails
 Forums
 Letters
 Radios
 Televisions

Synchronous and Asynchronous Transmission

Asynchronous
Point of Comparison Synchronous Transmission
Transmission
 Transmits data in the form of chunks or Transmits 1 byte or character
Definition
frames at a time
Speed of
Quick Slow
Transmission
Cost Expensive Cost-effective
Time Interval Constant Random
With gap between the
Yes None
data?
Chat Rooms, Telephonic Conversations,
Examples Email, Forums, Letters
Video Conferencing

Synchronous vs. Asynchronous Transmission

1. In synchronous transmission data is transmitted in the form of chunks, while in
asynchronous transmission data is transmitted one byte at a time.
2. Synchronous transmission needs a clock signal between the source and target to let the
target know of the new byte. While in asynchronous transmission, a clock signal is not
needed because of the parity bit attached to the data sent which serves as a start indicator
of the new byte.
3. Data transfer rate of synchronous transmission is faster since it transmits in chunks of
data, compared to asynchronous transmission which transmits one byte at a time.
4. Asynchronous transmission is straightforward and cost-effective while synchronous
transmission is complicated and pricey.
5. Synchronous transmission is systematic and needs lower overhead compared to
asynchronous transmission.

Both synchronous and asynchronous transmission have their benefits and

limitations. Asynchronous is used for sending a small amount of data while synchronous
transmission is used for sending bulk of data. Therefore, that both synchronous and
asynchronous transmissions are essential for data transmission.

 Cathode Ray Tube (CRT):

Cathode ray tube is a display device that is used for displaying an electrical
signal upon two-dimensional display screens by using principle of
fluorescence that is resulted from reaction of electrons and fluorescent
chemicals. It is very important part of cathode ray oscilloscope being like
 heart of whole oscilloscope system.

What are the parts of Cathode ray tube?

1. Electron gun assembly
2. Deflection plate assembly for deflection of electron beam
3. Fluorescent screen for production of displaying
4. Glass envelope to assemble whole cathode ray tube
5. Base to provide connection to external circuitry

The following figure shows the main part of cathode ray tube. Before we
go to study all these parts in detail it will be suitable to have some
basic knowledge regarding the function of these parts on individual
and constitutive basis.
Operation of CRT:
Cathode Ray Tube (CRT) is a computer display screen, used to display the
output in a standard composite video signal. The working of CRT
depends on movement of an electron beam which moves back and
forth across the back of the screen. The source of the electron beam is
the electron gun; the gun is located in the narrow, cylindrical neck at
the extreme rear of a CRT which produces a stream of electrons
through thermionic emission. Usually, A CRT has a fluorescent
screen to display the output signal. A simple CRT is shown in below.

The operation of a CRT monitor is basically very simple. A cathode ray

tube consists of one or more electron guns, possibly internal
electrostatic deflection plates and a phosphor target. CRT has three
electron beams – one for each (Red, Green, and Blue) is clearly
shown in figure. The electron beam produces a tiny, bright visible
spot when it strikes the phosphor-coated screen. In every monitor
device the entire front area of the tube is scanned repetitively and
systematically in a fixed pattern called a raster. An image (raster) is
displayed by scanning the electron beam across the screen. The
phosphor’s targets are begins to fade after a short time, the image
needs to be refreshed continuously. Thus CRT produces the three
colour images which are primary colors. Here we used a 50 Hz rate to
 eliminate the flicker by refreshing the screen.

Main parts of the cathode ray tube are cathode, control grid, deflecting plates
and screen.
Cathode:
The heater keeps the cathode at a higher temperature and electrons flow
from the heated cathode towards the surface of the cathode. The
accelerating anode has a small hole at its centre and is maintained at a
high potential, which is of positive polarity. The order of this voltage
is 1 to 20 kV, relative to the cathode. This potential difference creates
an electric field directed from right to left in the region between the
accelerating anode and the cathode. Electrons pass through the hole in
the anode travel with constant horizontal velocity from the anode to
the fluorescent screen. The electrons strike the screen area and it
glows brightly.
TheControlGrid:
The control grid regulates the brightness of the spot on the screen. By
controlling the number of electrons by the anode and hence the
focusing anode ensures that electrons leaving the cathode in slightly
different directions are focused down to a narrow beam and all arrive
at the same spot on the screen. The whole assembly of cathode,
control grid, focusing anode, and accelerating electrode is called the
electron gun.

Deflecting Plates:
Two pairs of deflecting plates allow the beam of electrons. An electric
field between the first pair of plates deflects the electrons
horizontally, and an electric field between the second pair deflects
them vertically, the electrons travel in a straight line from the hole
in the accelerating anode to the center of the screen when no
deflecting fields are present, where they produce a bright spot.
Screen:
This may be circular or rectangular. Screen is coated with special type of
fluorescent material. Fluorescent material absorbs its energy and re-
emits light in the form of photons when electron beam hits the screen.
When it happens some of them bounces back just like bouncing of
cricket ball from a wall. These are called as secondary electrons.
They must be absorbed and returned back to cathode, if it is not so
they accumulate near screen and produce space charge or electrons
cloud. To avoid this, aquadag coating is applied on funnel part of
CRT from inside.

Advantages of CRT:
1. CRT’s are less expensive than other display technologies.
2. They operate at any resolution, geometry and aspect ratio
without decreasing the image quality.
3. CRTs produce the very best color and gray-scale for all
professional calibrations.
4. Excellent viewing angle.
5. It maintains good brightness and gives long life service.

Features of CRT:
The use of CRT technology has quickly declined since the introduction of
LCDs but they are still unbeatable in certain ways. CRT monitors are
widely used in a number of electrical devices such as computer
screens, television sets, radar screens, and oscilloscopes used for
scientific and medical purposes.

 Display Adaptors:
A plug-in card in a desktop computer that performs graphics processing. Also commonly called
a "graphics card" or "video card," modern display adapters use the PCI Express interface, while
earlier cards used PCI and AGP. The display adapter determines the maximum resolution,
refresh rate and number of colors that can be displayed, which the monitor must also be able
to support. On many PC motherboards, the graphics circuits are built into the chipset, and a
separate plug-in card is not required.
1 - The Graphics Pipeline
The modern display adapter performs two operations. The first is the graphics rendering, which
moves the graphics data through a pipeline that creates the image frames and adds texture
and shading, all functions previously done by the CPU in the first PCs. A high-end display
adapter is a sophisticated parallel processing computer. See GPU and graphics pipeline.

2 - Analog and Digital Outputs

The second and more elementary purpose is to continuously convert the graphic patterns
(bitmaps) that have been rendered in the memory frame buffers into signals for the monitor's
screen.

The first PC display adapters (CGA, EGA, PGA) output digital signals, and the monitor converted
them to analog for the CRT. Starting with VGA in 1987, adapters sent analog signals to the
monitor; however, modern adapters output digital DVI or DisplayPort. Flat panel monitors use
DVI but also include a VGA socket to accommodate older machines. On laptops, the display
circuitry has been digital from end to end. See shared video memory and how to select a PC
monitor.