With PE4312: Obsolete

Product Specification
PE4306
50Ω RF Digital Attenuator
Product Description 5-bit, 31 dB, 1 – 4000 MHz
The PE4306 is a high linearity, 5-bit RF Digital Step Attenuator Features

(DSA) covering a 31 dB attenuation range in 1dB steps, and is  Attenuation: 1 dB steps to 31 dB
pin compatible with the PE430x series. This 50-ohm RF DSA  Flexible parallel and serial programming
provides both parallel (latched or direct mode) and serial interfaces
CMOS control interface, operates on a single 3-volt supply and  Latched or direct mode
maintains high attenuation accuracy over frequency and  Unique power-up state selection
3 E
temperature. It also has a unique control interface that allows  Positive CMOS control logic
the user to select an initial attenuation state at power-up. The  High attenuation accuracy and linearity
PE4306 exhibits very low insertion loss and low power over temperature and frequency
consumption. This functionality is delivered in a 4x4 mm QFN
 Very low power consumption
T
footprint.
 Single-supply operation
12
The PE4306 is manufactured on Peregrine’s UltraCMOS®  50Ω impedance
process, a patented variation of silicon-on-insulator (SOI)  Pin compatible with PE430x series
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
LE  Packaged in a 20 Lead 4x4 mm QFN
4
Figure 1. Functional Schematic Diagram
Switched Attenuator Array
PE Figure 2. Package Type
4x4 mm 20-lead QFN
O
RF Input RF Output
H
Parallel Control 5
BS
IT
Control Logic Interface

Serial Control 3
Power-Up Control 2
W
DOC-02145
Table 1. Electrical Specifications @ +25°C, VDD = 3.0V

E
Parameter Test Conditions Frequency Minimum Typical Maximum Units

O
Operation Frequency 1 4000 MHz

AC
Insertion Loss2 1–2200 MHz - 1.5 2.25 dB

Any bit or bit 1 ≤ 1000 MHz ±(0.3 + 3% of atten setting) dB
Attenuation Accuracy - -
combination 1000 < 2200 MHz ±(0.3 + 5% of atten setting) dB
1 dB Compression3 1–2200 MHz 30 34 - dBm
L
1, 2 Two-tone inputs
Input IP3 1–2200 MHz - 52 - dBm
+18 dBm
EP
Return Loss 1–2200 MHz 15 20 - dB

50% control to 0.5 dB
Switching Speed - - 1 s
of final value
Notes: 1. Device linearity will begin to degrade below 1 MHz
R
2. See max input rating in Table 3 & Figures 3-13 for data across frequency
3. Note absolute maximum in Table 3
Document No. DOC-30007-2 │ www.psemi.com ©2003-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11
PE4306
Typical Performance Data @ 25°C, VDD = 3.0V unless otherwise noted
Figure 3. Insertion Loss Figure 4. Attenuation at Major steps
0 35
31 dB
30
-1
25
Normalized Error (dB)
3 E
Insertion Loss (dB)
-2
20
16 dB
15
-3
T
insertion loss @ 25 C
insertion loss @ -40 C 10 8 dB
insertion loss @ 85 C
12
-4
5 4 dB
2 dB
-5
0 500 1000 1500 2000
Frequency (MHz)
2500 LE
3000 3500 4000
0
0
1 dB
500 1000 1500 2000 2500
Frequency (MHz)
3000 3500 4000
4
PE
O
Figure 5. Input Return Loss at Major Figure 6. Output Return Loss at Major
Attenuation Steps Attenuation Steps
H
0 0
BS
IT
-10 -10
W
-20 -20
S22 (dB)
s11 (dB)
-30
16 dB -30
O
AC
31 dB 31 dB 16 dB
-40 -40
-50 -50
L
0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000
Frequency (MHz) Frequency (MHz)

EP
R
©2003-2013 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-30007-2 │ UltraCMOS® RFIC Solutions
Page 2 of 11
PE4306
Figure 7. Attenuation Error vs. Frequency Figure 8. Attenuation Error vs. Attenuation
Setting at 10 MHz and 510 MHz
2 1.5
0 1
-2 0.5
3 E
31 dB
Error (dB)
Error (dB)
-4 0
T
-6 -0.5
10 MHz @ 25 C
510 MHz @ 25 C
10 MHz @ -40 C
12
-8 -1 510 MHz @ -40 C
10 MHz @ 85 C
-10
0 500 1000 1500 2000
Frequency (MHz)
2500 3000LE 3500 4000
-1.5
0 5
510 MHz @ 85 C
10 15 20
Attenuation State (dB)

25 30 35
4
PE
O
Figure 9. Attenuation Error vs. Attenuation Figure 10. Attenuation Error vs. Attenuation
Setting 1010 MHz and 1210 MHz Setting at 1510 MHz and 2010 MHz
H
1.5 1.5
BS
IT
1 1
W
0.5 0.5
Error (dB)
Error (dB)
0 0
E
-0.5 -0.5
O
1210 MHZ @ 25 C 1510 MHz @ 25 C

1210 MHz @ -40 C 2010 MHz @ 25 C
AC
1210 MHz @ 85 C 1510 MHz @ -40 C

-1 -1 2010 MHz @ -40 C
1010 MHz @ 25 C
1010 MHz @ -40 C 1510 MHz @ 85 C
1010 MHz @ 85 C 2010 MHz @ 85 C
-1.5 -1.5
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
L
Attenuation State (dB) Attenuation State (dB)

EP
Note: Positive attenuation error indicates higher attenuation than target value
R
Page 3 of 11
PE4306
Figure 11. Attenuation Error vs. Attenuation Figure 12. 1 dB Compression vs. Frequency
Setting at 2010 MHz and 2510 MHz
1.5 40
35
1 dB Compression (dBm)
0.5
3 E
Error (dB)
0 30
0 dB
T
-0.5 1 dB
2210 MHz @ 25 C
2 dB
2510 MHz @ 25 C 25
31 dB
12
2210 MHz @ -40 C
-1 2510 MHz @ -40 C
2210 MHz @ 85 C
-1.5
0 5
2510 MHz @ 85 C
10 15 20
Attenuation State (dB)

25 LE 30 35
20
1000 1500 2000
Frequency (MHz)
2500 3000
4
PE
O
Figure 13. Input IP3 vs. Frequency
H
60
BS
IT
55
50
W
45
IP3 (dBm)
40
E
35
0 dB 8 dB
O
30 1 dB 16 dB
AC
2 dB 31 dB
25 4 dB
20
1000 1500 2000 2500 3000
L
Frequency (MHz)
EP
Note: Positive attenuation error indicates higher attenuation than target value
R
Page 4 of 11
PE4306
Figure 14. Pin Configuration (Top View) Table 3. Absolute Maximum Ratings
GND
N/C
Symbol Parameter/Conditions Min Max Units
C1
C2
C4
VDD Power supply voltage -0.3 4.0 V
20
19
18
17
16
VDD+
VI Voltage on any DC input -0.3 V
C16 1 15 C8 0.3
20-lead TST Storage temperature range -65 150 °C

RF1 2 14 RF2
QFN PIN Input power (50Ω) +30 dBm
Data 3 13 P/S
4x4 mm
ESD voltage (Human Body
Clock 4
Exposed Solder Pad
12 Vss/GND VESD 500 V
Model)
LE GND
3 E
5 11
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted to
10
6
the limits in the Operating Ranges table. Operation

between operating range maximum and absolute
VDD
VDD
GND
PUP1
PUP2
maximum for extended periods may reduce reliability.
T
Table 2. Pin Descriptions Table 4. Operating Ranges
12
Pin Parameter Min Typ Max Units
Pin No. Description
1
2
3
Name
C16
RF1
Data
Attenuation control bit, 16 dB (Note 4)
RF port (Note 1)
Serial interface data input (Note 4)
LE VDD Power Supply
Voltage
IDD Power Supply
Current
2.7 3.0 3.3
100
V
μA
4
4 Clock Serial interface clock input Digital Input High 0.7xVDD V
5
6
LE
VDD
Latch Enable input (Note 2)
Power supply pin
PE
Digital Input Low
Digital Input Leakage

0.3xVDD
1
V
μA
O
7 PUP1 Power-up selection bit
8 PUP2 Power-up selection bit Input Power +24 dBm
9 VDD Power supply pin Temperature range -40 85 °C

H
10 GND Ground connection
Exposed Solder Pad Connection
S

The exposed solder pad on the bottom of the package
IT
Negative supply voltage or GND connection must be grounded for proper device operation.
12 Vss/GND
(Note 3)
13 P/S Parallel/Serial mode select Electrostatic Discharge (ESD) Precautions
W
14 RF2 RF port (Note 1) When handling this UltraCMOS® device, observe the
AC B
15 C8 Attenuation control bit, 8 dB same precautions that you would use with other ESD-
16 C4 Attenuation control bit, 4 dB sensitive devices. Although this device contains
17 C2 Attenuation control bit, 2 dB circuitry to protect it from damage due to ESD,
E
precautions should be taken to avoid exceeding the

O

rate specified in Table 3.
19 C1 Attenuation control bit, 1 dB
20 N/C No connect. Can be connected to any bias Latch-Up Avoidance
Paddle GND Ground for proper operation Unlike conventional CMOS devices, UltraCMOS®
Notes: 1. Both RF ports must be held at 0 VDC or DC blocked with an external
devices are immune to latch-up.
series capacitor
Switching Frequency
L
2. Latch Enable (LE) has an internal 100 kΩ resistor to VDD

3. Connect pin 12 to GND to enable internal negative voltage generator. The PE4306 has a maximum 25 kHz switching rate.
Connect pin 12 to VSS (-VDD) to bypass and disable internal negative
EP
voltage generator
4. Place a 10 kΩ resistor in series, as close to pin as possible to avoid Resistor on Pin 1 & 3
frequency resonance. See “Resistor on Pin 1 & 3” paragraph A 10 kΩ resistor on the inputs to Pin 1 & 3 (see
Figure 16) will eliminate package resonance between
Moisture Sensitivity Level the RF input pin and the two digital inputs. Specified
The Moisture Sensitivity Level rating for the 5x5 mm QFN
R
attenuation error versus frequency performance is

package is MSL1. dependent upon this condition.
Page 5 of 11
PE4306
Programming Options The LE input controls the latch. When LE is HIGH,

the latch is transparent and the contents of the serial
Parallel/Serial Selection
shift register control the attenuator. When LE is
Either a parallel or serial interface can be used to
brought LOW, data in the shift register is latched.
control the PE4306. The P/S bit provides this
selection, with P/S = LOW selecting the parallel
The shift register should be loaded while LE is held
interface and P/S = HIGH selecting the serial
LOW to prevent the attenuator value from changing
interface.
as data is entered. The LE input should then be
toggled HIGH and brought LOW again, latching the
Parallel / Direct Mode Interface
new data. The stop bit (B0) of the data should
The parallel interface consists of five CMOS-
always be low to prevent an unknown state in the
3 E
compatible control lines that select the desired
device. The timing for this operation is defined by
attenuation state, as shown in Table 5.
Figure 17 (Serial Interface Timing Diagram) and
Table 8 (Serial Interface AC Characteristics).
The parallel interface timing requirements are
T
defined by Figure 18 (Parallel Interface Timing
Power-up Control Settings
Diagram), Table 9 (Parallel Interface AC
The PE4306 always assumes a specifiable
Characteristics), and switching speed (Table 1).
12
attenuation setting on power-up. This feature exists
for both the Serial and Parallel modes of operation,
For parallel programming the Latch Enable (LE)
should be held LOW while changing attenuation
state control values, then pulse LE HIGH to LOW
(per Figure 18) to latch new attenuation state into
LE and allows a known attenuation state to be
established before an initial serial or parallel control
word is provided.
4
device.
When the attenuator powers up in Serial mode
For direct programming, the Latch Enable (LE) line
should be pulled HIGH. Changing attenuation state
PE
(P/S = 1), the five control bits and a stop bit are set
to whatever data is present on the five parallel data
O
inputs (C1 to C16). This allows any one of the 32
control values will change device state to new
attenuation settings to be specified as the power-up
attenuation. Direct Mode is ideal for manual control
state.
of the device (using hardwire, switches, or jumpers).
H
When the attenuator powers up in Parallel mode (P/
BS
Table 5. Truth Table S = 0) with LE = 0, the control bits are automatically

IT
P/S C16 C8 C4 C2 C1 Attenuation State set to one of four possible values. These four values
are selected by the two power-up control bits, PUP1
0 0 0 0 0 0 Reference Loss
and PUP2, as shown in Table 6 (Power-Up Truth
W
0 0 0 0 0 1 1 dB Table, Parallel Mode).

0 0 0 0 1 0 2 dB
0 0 0 1 0 0 4 dB Table 6. Power-Up Truth Table, Parallel
Interface Mode
E
0 0 1 0 0 0 8 dB
O
0 1 0 0 0 0 16 dB P/S LE PUP2 PUP1 Attenuation State

AC
0 1 1 1 1 1 31 dB 0 0 0 0 Reference Loss
Note: Not all 32 possible combinations of C1-C16 are shown 0 0 1 0 8 dB
0 0 0 1 16 dB
Serial Interface 0 0 1 1 31 dB
L
The PE4306’s serial interface is a 6-bit serial-in, 0 1 X X Defined by C1-C16
parallel-out shift register buffered by a transparent Note: Power up with LE = 1 provides normal parallel operation with C1-C16,
EP
and PUP1 and PUP2 are not active.

latch. The latch is controlled by three CMOS-
compatible signals: Data, Clock, and Latch Enable
(LE). The Data and Clock inputs allow data to be
serially entered into the shift register, a process that
R
is independent of the state of the LE input.
Page 6 of 11
PE4306
Evaluation Kit Figure 15. Evaluation Board Layout
The Digital Attenuator Evaluation Kit board was

designed to ease customer evaluation of the
PE4306 DSA.
J9 is used in conjunction with the supplied DC
cable to supply VDD, GND, and –VDD. If use of the
internal negative voltage generator is desired,
then connect –VDD (black banana plug) to ground.
If an external –VDD is desired, then apply -3V.
3 E
J1 should be connected to the LPT1 port of a PC
with the supplied control cable. The evaluation
software is written to operate the DSA in serial
T
mode, so switch 7 (P/S) on the DIP switch SW1
should be ON with all other switches off. Using the
12
software, enable or disable each attenuation
setting to the desired combined attenuation. The
software automatically programs the DSA each
LE
time an attenuation state is enabled or disabled.
To evaluate the power up options, first disconnect
4
the control cable from the evaluation board. The
control cable must be removed to prevent the PC
port from biasing the control pins. PE
O
During power up with P/S = 1 high and LE = 0 or
P/S = 0 low and LE = 1, the default power-up
H
signal attenuation is set to the value present on DOC-02344
the five control bits on the five parallel data inputs
BS
IT
(C1 to C16). This allows any one of the 32

attenuation settings to be specified as the power-
up state.
W
During power up with P/S = 0 high and LE = 0, the

control bits are automatically set to one of four
possible values presented through the PUP
E
interface. These four values are selected by the

O
two power-up control bits, PUP1 and PUP2, as

AC
shown in the Table 6.
Pin 20 is open and can be connected to any bias.
Resistor on Pin 1 & 3

L
A 10 kΩ resistor on the inputs to pins 1 & 3

EP
(Figure 16) will eliminate package resonance

between the RF input pin and the two digital
inputs. Specified attenuation error versus
frequency performance is dependent upon this
R
condition.
Page 7 of 11
PE4306
Figure 16. Evaluation Board Schematic

J2 J3
DNI Z=75 Ohm Z=75 Ohm DNI
R1 DNI R2 DNI
C0.5
1 1
C1
C2
C4
2
2
20
19
18
17
16
C5
C1
C2
C4
GND
J4 C16 R3 10K 1 15 C8 J5
SMASM Z=50 Ohm C16 C8 Z=50 Ohm SMASM
1 R6 0 OHM 2 14 R7 0 OHM 1
RFin U1 RFout
DATA R8 10K 3 MLPQ4X4 13 PS J9
2
2
DATA PS SUPPLY
CLK 4 12
CLK VNEG VDD 4
VDD_D
LE 5 11 -VDD 3
PUP1
PUP2
GND
LE GND
VDD
2
3 E
-3V 1
10
C17 C18
100pF 0.1μF
PUP1
PUP2
DOC-02201
T
R5 0 OHM
VDD
C13 C16
12
100pF 0.1μF
LE
Note: Resistors on pins 1 and 3 are required and should be placed as close to the part as
possible to avoid package resonance and meet error specifications over frequency
4
PE
W O
H
BS
IT
E
O
L AC
EP
R
Page 8 of 11
PE4306
Figure 17. Serial Interface Timing Diagram Table 7. 5-Bit Attenuator Serial Programming
Register Map
LE
B5 B4 B3 B2 B1 B0
C16 C8 C4 C2 C1 0
Clock  
MSB (first in) LSB (last in)
Data MSB LSB

Note: The stop bit (B0) must always be low to prevent the attenuator from
entering an unknown state.
3 E
tLESUP tLEPW
tSDSUP tSDHLD
T
Figure 18. Parallel Interface Timing Diagram
12
LE
LE
4
Parallel Data
C16:C1
PE
O
tLEPW
tPDSUP tPDHLD
H
BS
IT
Table 8. Serial Interface AC Characteristics Table 9. Parallel Interface AC Characteristics

VDD = 3.0V, -40°C < TA < 85°C, unless otherwise specified VDD = 3.0V, -40°C < TA < 85°C, unless otherwise specified
W
Symbol Parameter Min Max Unit Symbol Parameter Min Max Unit
Serial data clock tLEPW LE minimum pulse width 10 ns
fClk 10 MHz
frequency (Note 1)
Data set-up time before
tClkH Serial clock HIGH time 30 ns tPDSUP 10 ns
rising edge of LE
E
Data hold time after

tClkL Serial clock LOW time 30 ns tPDHLD 10 ns
O
falling edge of LE
LE set-up time after last
AC
tLESUP 10 ns
clock falling edge
tLEPW LE minimum pulse width 30 ns
Serial data set-up time
tSDSUP 10 ns
before clock rising edge
L
Serial data hold time

tSDHLD 10 ns
after clock falling edge
EP
Note 1: fClk is verified during the functional pattern test. Serial programming
sections of the functional pattern are clocked at 10 MHz to verify fclk
specification
R
Page 9 of 11
PE4306
Figure 19. Package Drawing

20-lead 4 x 4 mm QFN
0.10 C
A 4.00 (2X) 2.15±0.05 0.28
0.55±0.05 0.50
B (x20)
(x20)
11 15
0.75
0.50 (x20)
10 16
2.15±0.05 2.20 4.40

4.00
3 E
6 20
0.23±0.05
0.10 C (x20)
(2X) 5 1
0.18 2.20
2.00
T
Pin #1 Corner 4.40
0.18 0.435 SQ
REF
TOP VIEW BOTTOM VIEW RECOMMENDED LAND PATTERN
12
DOC-01880
0.10 C
0.05 C
SEATING PLANE
0.203
SIDE VIEW
0.05
0.90 MAX
C
LE 0.10
0.05
ALL FEATURES
C A B
C
4
PE
O
Figure 20. Marking Specifications
H
BS
IT
W
4306
YYWW
E
O
ZZZZZ
AC
17-0007
L
YYWW = Date Code

EP
ZZZZZ = Last five digits of PSC Lot Number

R
Page 10 of 11
PE4306
Figure 21. Tape and Reel Drawing
3 E
T
12
LE
4
PE
O
Table 10. Ordering Information
H
Order Code Part Marking Description Package Shipping Method
BS
4306-00 PE4306-EK PE4306-20MLP 4x4mm-EK Evaluation Kit 1 / Box

IT
4306-52 4306 PE4306G-20MLP 4x4mm-3000C Green 20-lead 4x4mm QFN 3000 units / T&R
W
E
O
AC
Sales Contact and Information

L
For sales and contact information please visit www.psemi.com.

EP
Advance Information: The product is in a formative or design stage. The datasheet contains design target No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party.
specifications for product development. Specifications and features may change in any manner without notice. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant,
Preliminary Specification: The datasheet contains preliminary data. Additional data may be added at a later or in other applications intended to support or sustain life, or in any application in which the failure of the
date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no
possible product. Product Specification: The datasheet contains final data. In the event Peregrine decides to liability for damages, including consequential or incidental damages, arising out of the use of its products in
change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer such applications.
Notification Form). The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE
R
The information in this datasheet is believed to be reliable. However, Peregrine assumes no liability for the use are trademarks of Peregrine Semiconductor Corp. Peregrine products are protected under one or more of
of this information. Use shall be entirely at the user’s own risk. the following U.S. Patents: http://patents.psemi.com.
Page 11 of 11

With PE4312: Obsolete

Transféré par

Informations du document

Titre original

Copyright

Formats disponibles

Partager ce document

Partager ou intégrer le document

Options de partage

Avez-vous trouvé ce document utile ?

Ce contenu est-il inapproprié ?

Droits d'auteur :

Formats disponibles

With PE4312: Obsolete

Transféré par

Droits d'auteur :

Formats disponibles

Product Specification

The PE4306 is a high linearity, 5-bit RF Digital Step Attenuator Features

Control Logic Interface

Table 1. Electrical Specifications @ +25°C, VDD = 3.0V

Parameter Test Conditions Frequency Minimum Typical Maximum Units

Operation Frequency 1 4000 MHz

Insertion Loss2 1–2200 MHz - 1.5 2.25 dB

Return Loss 1–2200 MHz 15 20 - dB

Typical Performance Data @ 25°C, VDD = 3.0V unless otherwise noted

Figure 3. Insertion Loss Figure 4. Attenuation at Major steps

Normalized Error (dB)

Frequency (MHz) Frequency (MHz)

Typical Performance Data @ 25°C, VDD = 3.0V unless otherwise noted

Attenuation State (dB)

1210 MHZ @ 25 C 1510 MHz @ 25 C

1210 MHz @ 85 C 1510 MHz @ -40 C

Attenuation State (dB) Attenuation State (dB)

Typical Performance Data @ 25°C, VDD = 3.0V unless otherwise noted

Attenuation State (dB)

20-lead TST Storage temperature range -65 150 °C

the limits in the Operating Ranges table. Operation

maximum for extended periods may reduce reliability.

Digital Input Leakage

9 VDD Power supply pin Temperature range -40 85 °C

11 GND Ground connection

precautions should be taken to avoid exceeding the

18 GND Ground connection

2. Latch Enable (LE) has an internal 100 kΩ resistor to VDD

attenuation error versus frequency performance is

Programming Options The LE input controls the latch. When LE is HIGH,

Table 5. Truth Table S = 0) with LE = 0, the control bits are automatically

0 0 0 0 0 1 1 dB Table, Parallel Mode).

0 1 0 0 0 0 16 dB P/S LE PUP2 PUP1 Attenuation State

The PE4306’s serial interface is a 6-bit serial-in, 0 1 X X Defined by C1-C16

and PUP1 and PUP2 are not active.

is independent of the state of the LE input.

Evaluation Kit Figure 15. Evaluation Board Layout

The Digital Attenuator Evaluation Kit board was

(C1 to C16). This allows any one of the 32

During power up with P/S = 0 high and LE = 0, the

interface. These four values are selected by the

two power-up control bits, PUP1 and PUP2, as

shown in the Table 6.

Pin 20 is open and can be connected to any bias.

Resistor on Pin 1 & 3

A 10 kΩ resistor on the inputs to pins 1 & 3

(Figure 16) will eliminate package resonance

Figure 16. Evaluation Board Schematic

Data MSB LSB

Table 8. Serial Interface AC Characteristics Table 9. Parallel Interface AC Characteristics

Data hold time after

Serial data hold time

Figure 19. Package Drawing

2.15±0.05 2.20 4.40

YYWW = Date Code

ZZZZZ = Last five digits of PSC Lot Number

Figure 21. Tape and Reel Drawing

4306-00 PE4306-EK PE4306-20MLP 4x4mm-EK Evaluation Kit 1 / Box

Sales Contact and Information

For sales and contact information please visit www.psemi.com.

Vous aimerez peut-être aussi