9.

Single-end operational
amplifier (OPA)

Kanazawa University
Microelectronics Research Lab.
Akio Kitagawa
9.1 Specification of OPA

2
 Parameters of OPA
Parameter Design constraint Description
VDD [V] max/typ/min Power supply voltage
IBias [uA] max Total bias current
Open loop gain Ad [dB] min Differential gain
Sampling frequency fS [Hz] max For discrete CMFB OPA
GBP [Hz] min Unity gain frequency
SR [V/us] min >> 2*VDD/fS
Settling time [us] max < 2/fs
Phase margin [deg] min > 60 deg.
Common-mode input range [V] min/max
Differential input range [V] min/max
Output swing [V] min/max > Differential input range
Input-referred noise level [uV @Hz] max In frequency range
Common-mode voltage VCM [V] typ
Input-referred offset VOS [V] max
CMRR min Common Mode Rejection Ratio
PSRR min Power Supply Rejection Ratio
3
Load resistance, capacitance [ohm, F] typ Possible external load
Specification of typical commercial OPA
Parameter Ideal Bipolar CMOS
value Standard High Standard High
performance performance
Ad [dB] ∞ 100 120 90
fu [MHz] ∞ 1 200 2 30
VOS [V] 0 2m 10 < 10m 0.2m
Iin [A] 0 100n 1n 0.1p 0.1p
CMRR [dB] ∞ 100 120 75
SR [V/us] ∞ 0.4 2000 3 20
Noise level [nV/Hz½] 0 10 4 25
IBias [A] 0 1m 1m 1
4
 Format of the specification sheet
Parameter Target Simulation Measured value Unit Comment
value
min. typ. max. min. typ. max.
VDD 1.8 V
Bias current 312 uA No input
Open loop gain 82 dB
GBP 320M Hz Load=100fF
SR 244 V/us Load=100fF
Settling time 24n us Error 1%
CMRR -185 dB
PSRR -150 dB
Noise level 50 nV/Hz0.5 @1MHz
Common- upper -0.5 V
mode input
lower 0.9 V
range

Estimated from the host system of the circuit 5

Circuit configuration of OPA
Phase compensation

Differential amp. Voltage amp. Output buffer

2 stage voltage amplifier Class A or AB output buffer

(CS + CS or CS + CG)

The output buffer may be omitted to reduce the power consumption,

when the OPA drive only the capacitive load.

6
 AC characteristic of OPA
Placed by the phase
RF C F
compensation at u < p2
|A|
Vin
+
u（GBP）
+
A Av 1
Vin
-
- d -20dB/DEC
p2
+
CL Vout
p1 
Small-signal
-40dB/DEC
V1 RF C F V2 Placed by CF
Rout 1 Rout 2 Rout 3 Depending on CL
Vin
+ 
+
CL Vout
+
0

Vin
- + + -90
+ -
Ad (Vin -Vin ) AVV1 V2 -180
 1 1
Vout  V2  V2
1  j  Rout 3C L 1  j /  p 2 The phase margin is decreased
for the very large CL. 7
9.2 Analysis of 2-stage CS OPA

8
Configuration of 2-stage OPA

M3 M4 M6

Cc
in
- M1 M2 in
+ out

Bias M7
M5a M5b

Differential amplifier CS amplifier (without an output

Ad  g m1  (rds 2 // rds 4 )  g m 6  (rds 6 // rds 7 ) buffer)
9
 Bias current dependence of the
differential gain
Differential amplifier stage CS amplifier stage
AV 1   g m1  (rds 2 // rds 4 ) AV 2   g m 6  (rds 6 // rds 7 )
g m1  21 I DS1 g m 6  2  6 I DS 6
1 1 1 1
rds 2   rds 6  
2 I DS 2 2 I DS1 6 I DS 6 6 I DS 6
1 1 1 1
rds 4   rds 7  
4 I DS 4 4 I DS1 7 I DS 7 7 I DS 6

Total gain
g m1 g m 6 2 1 6 1
Ad  AV 1 AV 2  
( g ds 2  g ds 4 )( g ds 6  g ds 7 ) (2  4 )(6  7 ) I DS1 I DS 6
10
 Phase compensation (1)
Constraint for p2 and u
Cannot used for the NFB circuit
0
V -20dB/Dec
-40dB/Dec
0dB Phase compensation
 p1’ p1 u’ p2 u 


･p2 ･p2
 p1   p 2  u 　
(bad stability) Margin

 p1  u   p 2 　
(good stability) Phase rotation
11
 Phase compensation (2)
Constraint for z and u
 p 2  2  u
Constraint for p2 and z
 z  10  u
(The generation of zero is inevitable in the
V -20dB/Dec
feedback phase compensation circuit.)

-40dB/Dec
0dB

p1 u p2 Z 



Phase margin °  p1   u   p 2   z

2 times

10 times 12
 Miller capacitance phase
compensation technique
c

-
V1 V2
+
gs6 L

o1 o2

The input parasitic capacitance of M6 is Cgs6, but the input capacitance of

the 2nd amplifier is controlled by the Miller capacitance CM.
C M  AV 2  CC  C gs 6  AV 2  CC 13
Design of the frequency response
Pole and Zero frequency and the circuit parameters
1
 p1  (Miller effect)
( AV 2CC )  Ro1
AV 1 g
u  AV 1  AV 2 　
  p1   m1 (Miller effect)
CC  Ro1 CC
g m6
Z 
CC (The feedforward through Cc)
1 g
 p2   m6 (The output capacitance of 2nd amplifier)
C L  Ro 2 C L

In the frequency range more than u, the input signal and output signal
level is comparable, approximately, AV2=Gm2･Ro2= -gm6･Ro2≒ -1.
14
Constraint of the phase compensation
60°Phase margin Separation between z and u
 p 2  2 u  Z  10 u

g m6 g m1 g m6 g m1
2  10
CL CC CC CC

Phase compensation g m 6  10 g m1
Constraint CC  0.2C L

15
 Control of the zero (1)
The phase compensation using CC requires the constraint
gm6 > 10gm1 to remove the influence of ωZ. this method
requires the very large gm6. RC phase compensation can be
used to evade this problem.
ZC

add Rc
1 1
RO g m (1  )
RO g m (1  j  CC ) vout ZC gm
vout gm 
 vin R
vin 1  j  CC RO 1 O
ZC
16
 Control of the zero (2)
ZC
1
RO g m (1  )
vout ZC gm

vin R
1 O
ZC
1
RO g m {1  j  CC (  RC )}
gm

1 1  j  CC ( RO  RC )
Z  RO g m {1  j /  Z }
1 
CC (  RC ) 1  j /  p 3
gm

Method (1) : If RC = 1/gm, ωZ → ∞ (Nulling resi)

Method (2) : If RC > 1/gm, ωZ is located in the left half plane (the
phase turns counterclockwise.)
17
 Rc implementation with MOSFET
Practical RC implementation
Same size
p
I DS 6  (VGS 6  VTp ) 2
2
From S I
D g m6  DS 6   p (VGS 6  VTp )
Differential VGS 6
Amp. 1 2
I DS _ MC1   p {(VGS _ MC1  VTp )VDS _ MC1  VDS _ MC1}
2
I DS _ MC1
g ds _ MC1    p (VGS _ MC1  VTp )
VDS _ MC1
VDS _ MC 1  0

M7 and MC4 are the same size.

gm6 = gds_MC1, z→ ∞
M6, MC1, MC2, and MC3 are the same size.
(see slide 17)
VGS_MC3 + VGS_MC2 = VGS6 + VGS_MC1
VGS_MC1 = VGS_MC3 + VGS_MC2 - VGS6 = VGS6 + VGS6 - VGS6 = VGS6 18
Indirect phase compensation (1)

Blocking the feedforward path by the feedback buffer amplifier

C
1

Feedback path

-A
in out
iin  j  C (vin  vout )
vout   A  vin
＝

iin
 j  C (1  A)
vout

19
Indirect phase compensation (2)
Source follower feedback buffer Common-gate feedback buffer

VDD
v1

vout
CC

VBias

VSS
Advantages:
• High SR, High p2, High u, small Cc
Disadvantage:
• Additional power consumption
20
 Indirect phase compensation (3)
100/1 Common gate feedback buffer
100/1
100/2
Long L will help the adjustment
100/1 100/1 of the output offset voltage.
100/2
50/2 50/2

200/4 200/4
50/2

200/4 200/4 50/2

The cascode current mirror load is used in place of the feedback buffer.
There is no additional power consumption.
21
9.3 Optimization of MOSFET size

22
 ISS and SR
Vin＋－Vin－

t out
VCap I DS 5
t
CC c

t in
+
in
-
VCap -Iout
1 I DS 5
IDS5
VCap 
CC  I DS 5 dt 
CC
t Bias

I DS 5
SR 
CC
SR is limited by the current ISS (IDS5).

23
 Saturation of M4 (1)
GS4 DS4 GS6
VDS 3  VGS 3  VTp  VDS 3  VTp
M3 always operates in the saturation region. out
c
+ -
in in
VDS 4  VGS 6
If VGS 4  VGS 6 ,
Bias
VDS 4  VGS 6  VGS 4  VGS 4  VTp
M4 always operates in the saturation region.

MOSFET size should be optimized for VGS4 = VGS6.

24
 Saturation of M4 (2)

If VGS 4  VGS 6 ,
GS4 GS6
W 
 
I DS 6 L 6
 out
I DS 4 W  c
  + -
L 4 in in

VGS 5  VGS 7
W  Bias
 
I DS 7  L 7 GS5 GS7

I DS 5  W 
 
L 5
25
 Saturation of M4 (3)
I DS 6  I DS 7
より
I DS 5  2 I DS 4
GS4 GS6
I DS 6 I DS 7
2
I DS 4 I DS 5 out
c
+ -
in in
Saturation condition of M4
W  W 
    Bias
 L 6  L 7
2 GS5 GS7
W  W 
   
 L 4  L 5

26
 Systematic offset (1)
Systematic offset
IDS6 Current balance of M6 and M7
Random offset
Process variation of VT
VA VB

IDS7

When VA = VB ( differential input = 0),

the output current = 0 or IDS6 = IDS7.

27
 Systematic offset (2)
3
I DS 3  (V A  VTp ) 2
2 This constraint is same as the
5 saturation constraint of M4.
I DS 5  (VBias  VTn ) 2
2
6 6 7
I DS 6  (VB  VTp ) 2 2
2 3 5
7
I DS 7  (VBias  VTn ) 2 W  W 
2    
 L 6  L 7
When V A  VB , 2
W  W 
I DS 6  I DS 7    
p.27  L 4  L 5
I DS 5
I DS 3 
2
28
 Input-referred noise (1)
Channel noise model of MOSFET

Vn 2 (f) Thermal noise Flicker noise

g ds K p/n 1
V ( f )  4kT 2 
n
2
(V 2 / Hz )
　　
g m WLCOX f

 = 2/3 (Long Channel) K p  10 24 　　

(V 2 / F )
1 (Short Channel) K n  10  23 　　
(V 2 / F )
The channel noise is observed in NOTE: Large L is better
the output terminal, but the noise for the low noise amplifier,
PSD is normally described as a because of large L*W.
input-referred noise PSD. 29
 Input-referred noise (2)

Intrinsic noise density of the differential amplifier

1 g
Thermal noise Vn2 ( f )  4kT (  m2 3 ) (Total noise from M1 and M3)
g m1 g m1

Kn K p W1 L1 1
Flicker noise V (f)
n
2
(1  )
W1 L1COX K n W3 L3 f
NOTE: Assuming that the differential pair consists n-ch MOFET
and current mirror load consists p-ch MOSFETs.

30
 Mismatch of MOSFETs by the
 V V
process variation
V OS _ 1 2 GS 1 GS 2 Vout
I DS 5 I DS 5
 VTn1   VTn 2 
1 2
I DS 5 1
 (VTn1  VTn 2 )  [1  ]
1 2
Vin1 – Vin2
1 I DS 5 1   2
 (VTn1  VTn 2 )  [ ]
2 1 1 VOS
VGS 1  VTn1   
 VTn1 2  [ ]1 2  VTn1 2  OV 1 [ ]1 2
2 1 2 1
VOS _ 3 4  VGS 3  VGS 4
VGS 3  VTp 3   
 VTn 3 4  [ ]3 4  VTn 3 4  OV 3 [ ]3 4
2  2 1
 OV 1  g  
VOS  VTn1 2  [ ]1 2  m 3 [VTn 3 4  OV 3 [ ]3 4 ]
2  g m1 2  31
 Optimization for the noise and
process variation
• Thermal noise
– Differential pair MOSFETs: Large W/L
– Current mirror load MOSFETs: Small W/L
• Flicker noise
– Differential pair MOSFETs: Large W*L
– Current mirror load MOSFETs: Large L (Large W causes the
degradation of the voltage gain.)
• Mismatch offset
– Differential pair MOSFETs: Large W*L
– Current mirror load MOSFETs: Small W/L (Small gm3/gm1)

NOTE: Consider that the L and W influences the frequency response too.
32
9.4 Design example of a single-
end OPA

33
 Specification
Power supply voltage VDD/VSS 0.9/-0.9 V
Open loop gain Ad > 35 dB
GBP fu 200 MHz
Phase margin PM 60°
Slew rate SR > 100 V/us
Load capacitance CL 1 pF
Output voltage swing Voutp-p > 1.2 V
Maximum common-mode voltage Vinmax > 0.6 V
Minimum common-mode voltage Vinmin < -0.25 V
Input-referred noise vn2 < 50 uV (BW=0.1Hz~1MHz)
Power consumption PW < 1 mW

34
 Parameters of MOSFET

Parameter n-ch p-ch

VT [V] 0.45 -0.42
COX [A/V2] 215･10-6 46.2･10-6
 [1/V] 0.813 1.92
The parameters are extracted from 3600nm/360nm MOSFETs
for OV =0.2V.

35
 Design constraints
(1) Phase compensation -1 (6) Open loop gain/
(4) Maximum common-mode input Phase compensation
VDD
MC3
Iref M3 M4 M6

Cc Vout
Vin +
Vin - M1 M2
MC1
CL 1pF
(3) GBP MC2

M7
M5a M5b MC4
VSS
(5) Minimum common-mode input
(2) Slew Rate (7) Systematic offset

36
 Cc, ISS
(1) Phase compensation -1
Load capacitance CL = 1 [pF]
Phase compensation constraint CC  0.2C L
CC = 0.2 [pF]
(2) SR
I DS 5
SR 
CC
I DS 5  SR  CC  100 M [V / s ]  0.2 p[ F ]  20 [　
uA]
I DS 5
I DS 3  I DS 4  I DS 1  I DS 2   10 　
[uA]
2
37
 M1, M2
(3) GBP
g m1
u 
CC
g m1  CC u  0.2 p  2  200 M  251[ S ]

(2) IDS1, (3) gm1

W 
g m1  2 1 I DS 1  2  n COX   I DS 1  251[uS ]
 L 1
W  W  g m2 1 (251u ) 2
       14.6  20
 L 1  L  2 2  n COX I D1 2  215 10 10u
6

38
 M3, M4
(4) Maximum common-mode input (Saturation
of M1)
Vinmax  VDD   OV 3  VTp  VTn
2 I DS 3
 OV 3   VDD  VTp  VTn  Vinmax
3
2 I DS 3
3 
(VDD  VTp  VTn  Vinmax ) 2
W  W  2 I DS 3 1
    
 L 3  L  4  p COX (VDD  VTp  VTn  Vin )
max 2

2 10u 1
 6
4
46.2 10 (0.9  0.42  0.45  0.6) 2
39
 M5
(5) Minimum common-mode input
(Saturation of M5)
Vinmin  VSS  VTn   OV 1   OV 5
2 I DS 5
 OV 5   Vinmin   OV 1  VTn  VSS
5
2 I DS 1 2 10u
 OV 1    0.068　　
[　
V]
1 6
215 10  20
2 I DS 5
5 
(Vinmin   OV 1  VTn  VSS ) 2
W  2 I DS 5 1
  
 L 5  nCOX (Vin   OV 1  VTn  VSS )
min 2

2  20u 1
 6
 10 40
215 10 (0.25  0.068  0.45  0.9) 2
 M6 (without zero cancellation)
(6) Phase compensation -2
If VGS 4  VGS 6 　
,
g m 6  10 g m1 I DS 6  6

 10  2 1 I DS 1 I DS 4  4
 10  2  215 10 6  20 10u g m 6  2  6 I DS 6
 2.93　　
(mS ) 4
6  g m6
2 I DS 4
W  g m6 4
Bias current:   
 L  6  p COX 2 I DS 4
 192 2.93m 46.2 10 6  4
I DS 6  6 I DS 4  10   480uA 
4 4 46.2 10 6 2 10u
 192 41
 M7
(7) Systematic offset (Saturation of M4)

W 
 
 
W 1   L
W 6
    
 L 7 2  L 5  W 
 
L 4
1 192
 10
2 4 The circuit parameters
 240 are decided. Check the
other specification.

42
 Output swing

2 I DS 7 max
Vout  VDD   OV 6
Vmin
 VSS   OV 7  VSS 
W 
out
 n COX    VDD 
2 I DS 6
 L 7 W 
 p COX  
2  480u  L 6
 0.9 
215 10 6  240 2  480u
 0.764 　　[V ]  0 .9 
46.2 10 6 192
 0.571　　[V]

Output voltage swing Vout, p-p = 1.34 [V]

43
 Open loop gain
2 I DS1 2 10u
 OV ( M 1)    0.0682 1 = 0.813V-1
W  215 10 6  20
 nCOX  
 L 1
2 I DS 6 2  480u 6 = 0.590V-1
 OV ( M 6)    0.329
W  46.2 10 6 192
 p COX  
 L 6

Ad  AV 1  AV 2
 g m1 (rds 2 // rds 4 )  g m 6 (rds 6 // rds 7 )
2 1 I DS1 2  6 I DS 6
 
I DS 1 (n   p ) I D 6 (n   p )
2  215 10 6  20 2  46.2 10 6 192

10u (0.813  0.590) 480u (0.813  0.590)
 20.9  4.33
 90.6  39 [　
dB] 44
 Flicker noise (1)
Kn K p W1 L1 1
V 
2
nf {1  [V 2 /Hz]
} 　　
W1 L1COX K n W3 L3 f
fu Kn K p W1 L1
NL  
2
f V df 
2
nf {1  } ln( f u / f l ) 　　
(frequency range　f u ~ f u )
fl W1 L1COX K n W3 L3
Kn K p W1
 {1  (for L1  L3 　
} ln( f u / f l ) 　　 )
W1 L1COX K n W3
 0 Si
COX   5.4 10 3 [　
F/m 2 ]
tOX

The parameter COX can be loosely estimated for nCOX or pCOX.

Say n~ 400 [cm2/Vs] and p ~ 209 [cm2/Vs].
45
 Flicker noise (2)
Based on the specification sheet, at fu = 1[MHz] , Vnf =
50 [uV].
(50uV ) 2  NL2f
9 10  23 20
2.5 10  3
(1  0 . 1 ) ln(1 10 6 / 1 10 1 ) 　
[V]
W1 L1  5.4 10 4
4.477 10  20

W1 L1
W1 L1  1.791 10 11 　
[m 2 ]
W1
 20 　
L1
 L1  0.946 　
[um] L1=1 [um] 46
 Thermal noise (1)
8 1 g
Vnt2  kT (  m2 3 ) 　　
[V 2 /Hz]
3 g m1 g m1
8 1 g
NL2t  kT (  m2 3 )f　　
(frequency range 　
0 ~ fu )
3 g m1 g m1
g m1  2 1 I D1  2  215 10 6  20 10u  293　　
[uS]
g m 3  2  3 I D 3  2  46.2 10 6  4 10u  60.8　　
[uS]

at T = 300 [K]
6
8 1 60 .8  10
NL2t  1.38 10  23  300 (1  ) f 
　 (50 uV ) 2

3 293 10 6 293 10 6

Δf　 54.9 [　
MHz]  1.0[　
MHz ] 47
 Thermal noise (2)
If the thermal noise level go over the nominal value in the specification,
you have to rework for proper gm1 and gm3.
8 1 g
Vnt2  kT (  m2 3 ) 　　
[V 2 /Hz]
3 g m1 g m1

NOTE: The thermal noise is reduced for larger gm1 and smaller gm3,
but the larger gm1 causes the larger W/L for M6 for the phase
compensation.
g m1  2 1 I DS1 , 　g m 3  2  3 I DS 3
2 I DS 3
 OV 3 
3
Vinmax  VDD   OV 3  | VTp | VTn
g m 6  10 g m1 48
 Finished

Power consumption Pw = (480 + 10 + 10)･1.8V = 0.9[mW]

49
 Exercise
• Design the 2-stage OPA with the zero cancellation
circuit shown in Slide 36, with considering the
following tips.
– M6 can be acquitted from the constraint of the phase
compensation by using the zero cancellation circuit.
You can trim down the IDS6 and also set the larger gm6.
– You can design more high-gain OPA by tuning the M6
and M7 with the zero cancellation circuit.

50