DCO Presentation 4 PDF

BSc IT
Digital and Computer Organization

Semester - III
Copyright@ Amity University

INSTRUCTION FORMATS
• A computer will have a variety of code formats.
• It is the function of the control unit within the CPU to interpret each
instruction code and provide the necessary control functions needed to
process the instruction.
• The format of an instruction is usually depicted in a rectangular box

symbolizing the bits of the instruction as they appear in memory or in a
control register.
• The bits of the instruction are divided into groups called fields.
INSTRUCTION FORMATS
• The common fields found in instruction formats are:
1. An operation code field that specifies the operation to be performed.
2. An address field that designates a memory address or a processor register.
3. A mode field that specifies the way the operand or the effective address is determined.
• Other special fields are sometimes employed under certain circumstances.
• The operation code field of an instruction is a group of bits that define various processor
operations such as add, subtract etc.

INSTRUCTION FORMATS
• Computers may have instructions of varying lengths.
• The number of address fields in the instruction format of a computer depends upon the
internal organization of its registers.
• Most computers fall in one of three types of CPU organization:
1. Single accumulator organization.
2. General register organization
3. Stack organization.

INSTRUCTION FORMATS
• Single Accumulator Organization:
In single accumulator organization all operations are performed with an implied accumulator
register.
• Example:
ADD X i.e., AC <- AC + M(X)
• General Register Organization:

In general register type organization the computer needs three register address fields.
• Example:
ADD R1, R2, R3 i.e., R1 <- R2 + R3
ADD R 1R2 i.e., R1 <- R1 + R2.
• Stack Organization:
The stack-organized CPU would have PUSH and POP instruction which require an address field.
All operands are implied to be in the stack hence there is no need to specify operands with an
address field.

INSTRUCTION FORMATS
• Types of Instructions:
Based on the number of address fields present in the instruction the instructions can be
classified into:
1. Three address instructions.
2. Two address instructions.
3. One address instructions.
4. Zero address instructions.

INSTRUCTION FORMATS
• Three Address Instructions:
Computers with three address instruction formats can use each address field to specify either
a processor or a memory operand.
Let us consider the example

X=(A + B)x(C + D)
ADD R1,A,B; R1 <- M [A] + M [B]
ADD R2,C,D; R2 <- M [C] + M [D]
MUL X,R1,R2; M [X] <- Ri x R2
• It is assumed that the computer has two processor registers R1 and R2. The symbol M [A]
denotes the operand at memory address symbolized A.
• Three address format gives short programs but requires larger space to specify three addresses.

INSTRUCTION FORMATS
• Two-address Instructions:
In this format each address field specify either a processor register or a memory word
i.e., they contain two address fields.
• Consider the example

X=(A + B)-(C + D)
MOV R1,A ; R1 <- M[A]
ADD R1,B ; R1 <- R1 + M [B]
MOV R2,C ; R2 <- M [C]
ADD R2, D ; R2<-R2 + M[D]
SUB R1,R2 ; R1 <- R1 - R2
MOV X,R1 ; M[X] <- R1

INSTRUCTION FORMATS
• One-Address Instructions:
One address instructions use an implied accumulator (AC) register for all data manipulation
i.e., they contain only one address field. For multiplication and division a temporary register
is used. The address of the second register is assumed to be accumulator.
Example:
X=(A + B)X(C + D)
LOAD A ; AC <- M [A]
ADD B ; AC <- AC + M[B]
STORE T ; M [T] <- AC
LOAD C ; AC <- M [C]
ADD D ; AC <- AC + M[D]
MUL T ; AC <- AC x M[T]
STORE X ; M[X] <- AC

INSTRUCTION FORMATS
• Zero Address Instructions:
Zero address instructions can be defined as the computational instructions in which the address field
is not present.
• Generally stack organized computers use this type of addressing field. Mostly they will be using
PUSH and POP instructions.
• Example:
X=(A + B) + (C + D)
PUSH A ; TOS <- A top of the stack
PUSH B ; T0S <- B
ADD ; TOS <- A + B
PUSH C ; TOS <- C
PUSH D ; TOS <- D
ADD ; TOS <- C + D
ADD ; TOS <- (C + D) + (A + B)
POP X ; M [X] <- TOS
ALLOCATION OF BITS
• Number of addressing modes
• Number of operands
• Register versus memory
• Number of register sets
• Address range
• Address granularity

ALLOCATION OF BITS
One instruction may have several fields, which identify the logical
operation to be done, and may also include source and destination
addresses and constant values.
This is the MIPS "Add" instruction which allows selection of source

and destination registers and inclusion of a small constant.

ADDRESSING MODES
The addressing mode gives or indicates, a rule to identify the
operands location.
Computers use addressing mode techniques for the purpose of

accommodating the following provisions.
1. To give programming versatility to the user.
2. To reduce the number of bits in the address field of the

instruction.
3. To provide flexibility for writing programs.

TYPES OF ADDRESSING MODES
• The various addressing modes available are :
1. Implied mode.
2. Immediate mode.
3. Register mode.
4. Register indirect mode.
5. Auto increment or auto decrement mode.
6. Direct address mode.

TYPES OF ADDRESSING MODES
7. Indirect address mode.
8. Relative address mode.
9. Indexed addressing mode.
10. Base register addressing mode.
• Although most addressing modes modify the address field of the

instruction there are two modes that need no address field at all.
They are (i) Implied mode
(ii) Immediate mode.
IMPLIED MODES
In this mode the operands are specified implicitly in the definition
of the instruction.
All register reference instructions that use an accumulator are

implied mode instruction.
Example: CMA compliment accumulator.
The most advantage of implicit addressing of this kind is that it

results in shorter instruction formats. Shorter instructions take up
lesser space in memory.
Zero address instructions in a stack organized computer are

implied mode.
IMMEDIATE MODES
The purpose of an address is to identify an operand value to be
used in executing the instruction.
Some times the operand values is contained in the instruction

itself, this mode of operand specification is called immediate
addressing mode.
Example:
MVI A, 45.
In this mode, Operand is part of instruction

IMMEDIATE ADDRESSING
• Operand = address field
e.g. ADD 5
– Add 5 to contents of accumulator
– 5 is operand
• No memory reference to fetch data
• Fast
• Limited range
IMMEDIATE ADDRESSING DIAGRAM
OPCODE OPERAND
Instruction

REGISTER ADDRESSING MODES
• In this mode the operands are in registers which reside with in the CPU.
• The register is selected from the register field in the instruction.
• Example:
• MOV AX, BX

• Operand is held in register named in address filed
EA = R
• Limited number of registers
• Very small address field needed
– Shorter instructions
– Faster instruction fetch

• No memory access
• Very fast execution
• Very limited address space
• Multiple registers helps performance

– Requires good assembly programming or compiler writing N.B. C
programming
• register int a;
• Direct addressing
REGISTER ADDRESSING DIAGRAM
REGISTER
OPCODE
ADDRESS R
Registers
Instruction
OPERAND

REGISTER INDIRECT MODES
• An operand identifier is called an indirect address if it is address of the
storage device whose contents in turn form the direct address of the
desired operand.
• In register indirect mode the instruction specifies a register in the CPU

whose contents give the address of the operand in memory.
• The advantage of a register indirect mode instruction is that the address

field of the instruction uses fewer hits to select a register than would have
been required to specify a memory address directly.
• Example: MOV AX, [CX]

REGISTER INDIRECT ADDRESSING
• Indirect addressing
EA = (R)
• Operand is in memory cell pointed to by contents of register R
• Large address space (2n)
• One fewer memory access than indirect addressing

REGISTER INDIRECT ADDRESSING
DIAGRAM
Opcode Register Address R
Memory
Instruction
Registers
Pointer to Operand Operand

Auto Increment or Auto Decrement Mode
This is similar to the register indirect mode except that the register is
incremented or decremented after or before its value is used to access
memory.
Auto Increment increases the value by one automatically after the

completion of accessing the register from memory.
Auto Decrement decreases the value by one automatically after the

completion of accessing the register from memory.

DIRECT ADDRESSING MODES
• Very frequently an operand is identified by naming the device that stores its current
value.
• This is called direct addressing.
• The operand identifier used which is called a direct address is usually a CPU register
name or main memory address.
• In this mode the effective address is equal to the address part of the instruction.
Example: MOV AX, [3000]

DIRECT ADDRESSING MODES
• Address field contains address of operand
• Effective address (EA) = address field (A)

• e.g. ADD A
– Add contents of cell A to accumulator
– Look in memory at address A for operand
• Single memory reference to access data
• No additional calculations to work out effective address
• Limited address space

DIRECT ADDRESSING DIAGRAM
OPCODE ADDRESS A
Memory
Instruction
OPERAND

INDIRECT ADDRESSING
• In this mode the address field of the instruction gives the address
where the effective address is stored in memory.
• The instruction is obtained from memory and it uses its address part
to access memory again to read the effective address.
• Effective Address = Address part of instruction + content of CPU

register.
• The CPU register may be the program counter, an index register or a

base register.
INDIRECT ADDRESSING
• In this type of address of the data is a part of the instructions itself.
When the processor decodes the instruction, it gets the memory
address from where it can be read/store the required information.
• The instructions will have the register which has the address. So to
fetch the data, the instruction must be decoded appropriate register
selected.
• The contents of the register will be treated as the address using this
address appropriate memory location is selected and data is
read/written.
INDIRECT ADDRESSING
• Memory cell pointed to by address field contains the address of (pointer to)
the operand
EA = (A)
Look in A, find address (A) and look there for operand
e.g. ADD (A)
Add contents of cell pointed to by contents of A to accumulator.

INDIRECT ADDRESSING
• Large address space
• 2n where n = word length
• May be nested, multilevel, cascaded

– e.g. EA = (((A)))
• Multiple memory accesses to find operand
• Hence slower
INDIRECT ADDRESSING DIAGRAM
Instruction
OPCODE ADDRESS A
Memory
PIONTER TO
OPERAND
OPERAND

RELATIVE ADDRESS MODES
• In this mode the content of the program counter is added to the address
part of the instruction in order to obtain the effective address.
• The address part of the instruction is usually 2′s complement

representation which can be either positive or negative.
Effective address = Address Part of Instruction + Program Counter
Content.
• Let
Program counter contents = 2050
Address part of the instruction = 50
then the address of the operand = 2050 + 50
= 20A0 H or 2100 D.
RELATIVE ADDRESSING
• Relative addressing is used with branch type instructions when the
branch address is in the area surrounding the instruction. This gives a
shorter address field.
• A version of displacement addressing
• R = Program counter, PC
EA = A + (PC)
i.e. get operand from A cells from current location pointed to/by PC
• c.f. locality of reference & cache usage

INDEXED ADDRESSING MODES
• In this mode the content of an index register is added to the

address part of the instruction to obtain the effective address.
• If an index type instruction does not include an address field in

its format the instruction converts to the register indirect mode
of operation.
• Effective Address = content of an index register + address part

of the instruction.

INDEXED ADDRESSING MODES
• A = base
• R = displacement
• EA = A + R
• Good for accessing arrays
• EA = A + R
• R++
BASE-REGISTER ADDRESS MODES
• In this mode the content of a base register is added to the address part of
the instruction to obtain the effective address.
• This is similar to the indexed addressing mode.
• A base register holds a base address and the address field of the
instruction gives a displacement relative to this base address.
• The base register addressing mode is used in computers to facilitate the

relocation of programs in memory.

BASE-REGISTER ADDRESS MODES
• A holds displacement
• R holds pointer to base address
• R may be explicit or implicit
e.g. segment registers in 80x86

PENTIUM ADDRESSING MODES
• Virtual or effective address is offset into segment
– Starting address plus offset gives linear address
– This goes through page translation if paging enabled
• 12 addressing modes available

– Immediate
– Register operand
– Displacement
– Base
– Base with displacement
– Scaled index with displacement
– Base with index and displacement
– Base scaled index with displacement
– Relative

PENTIUM ADDRESSING MODE
CALCULATION

POWERPC ADDRESSING MODES
• Load/store architecture
– Indirect
• Instruction includes 16 bit displacement to be added to base register (may be GP register)
• Can replace base register content with new address
– Indirect indexed
• Instruction references base register and index register (both may be GP)
• EA is sum of contents
• Branch address
– Absolute
– Relative
– Indirect
• Arithmetic
– Operands in registers or part of instruction
– Floating point is register only

POWER PC MEMORY OPERAND
ADDRESSING MODES

Introduction to RISC
• Some aspects attributed to the first RISC-labeled designs around include the observations
that the memory-restricted compilers of the time were often unable to take advantage of
features intended to facilitate manual assembly coding, and that complex addressing
modes take many cycles to perform due to the required additional memory accesses.
• It was argued that such functions would be better performed by sequences of simpler
instructions if this could yield implementations small enough to leave room for many
registers, reducing the number of slow memory accesses.
• In these simple designs, most instructions are of uniform length and similar structure,
arithmetic operations are restricted to CPU registers and only
separate load and store instructions access memory.

Introduction to RISC
• Reduced instruction set computing, or RISC is a CPU design strategy
based on the insight that simplified instructions can provide higher
performance if this simplicity enables much faster execution of each
instruction.
• A computer based on this strategy is a reduced instruction set computer.

There are many proposals for precise definitions, but the term is slowly being
replaced by the more descriptive load-store architecture.
• Well known RISC families include DEC Alpha, AMD 29k, ARC, ARM, Atmel
AVR, MIPS, PA-RISC, PowerPC, SuperH, and SPARC.

RISC Terminology
• A common misunderstanding of the phrase "reduced instruction set
computer" is the mistaken idea that instructions are simply
eliminated, resulting in a smaller set of instructions.
• In fact, over the years, RISC instruction sets have grown in size, and
today many of them have a larger set of instructions than many CISC
CPUs.
• In particular, RISC processors typically have separate instructions for

I/O and data processing; as a consequence, industry observers have
started using the terms "register-register" or "load-store" to describe
RISC processors.
Typical characteristics of RISC
• Other features, which are typically found in RISC architectures are:
– Uniform instruction format, using a single word with the opcode in the same bit positions
in every instruction, demanding less decoding;
– Identical general purpose registers, allowing any register to be used in any context,
simplifying compiler design (although normally there are separate floating
point registers);
– Simple addressing modes. Complex addressing performed via sequences of arithmetic

and/or load-store operations;
– Few data types in hardware, some CISCs have byte string instructions, or
support complex numbers; this is so far unlikely to be found on a RISC.

Introduction To CISC
• A complex instruction set computer (CISC), is a computer where
single instructions can execute several low-level operations (such as
a load from memory, an arithmetic operation, and a memory store)
and/or are capable of multi-step operations or addressing
modes within single instructions.
• The term was retroactively coined in contrast to reduced instruction

set computer (RISC).
• The circuitry that performs the actions defined by the microcode in

many (but not all) CISC processors is, in itself, a processor which in
many ways is reminiscent in structure to very early CPU designs.

Introduction To CISC
• A complex instruction set computer (CISC) is a computer where
single instructions can execute several low-level operations (such
as a load from memory, an arithmetic operation, and a memory
store) and/or are capable of multi-step operations or addressing
modes within single instructions.
• The term was retroactively coined in contrast to reduced instruction

set computer (RISC).
• Examples of CISC instruction set architectures are System/

360 through z/Architecture, PDP-11, VAX, Motorola 68k, and x86.

RISC & CISC

RISC & CISC

PARALLEL PROCESSING
• The simultaneous use of more than one CPU or processor core to
execute a program or multiple computational threads. Ideally,
parallel processing makes programs run faster because there are
more engines (CPUs or cores) running it.
• In practice, it is often difficult to divide a program in such a way that

separate CPUs or cores can execute different portions without
interfering with each other.
• Most computers have just one CPU, but some models have several,
and multi-core processor chips are becoming the norm. There are
even computers with thousands of CPUs.
PARALLEL PROCESSING
• With single-CPU, single-core computers, it is possible to perform
parallel processing by connecting the computers in a network.
However, this type of parallel processing requires very sophisticated
software called distributed processing software.
• Parallel processing is also called parallel computing.
• In the quest of cheaper computing alternatives parallel processing

provides a viable option.
• The idle time of processor cycles across network can be used

effectively by sophisticated distributed computing software.
PIPELINING
• Pipelining is an implementation technique where
multiple instructions are overlapped in execution.
• The computer pipeline is divided in stages. Each stage

completes a part of an instruction in parallel.
• The stages are connected one to the next to form a

pipe - instructions enter at one end, progress through
the stages, and exit at the other en

PIPELINING
• In computing, a pipeline is a set of data processing
elements connected in series, so that the output of one
element is the input of the next one.
• The elements of a pipeline are often executed in

parallel or in time-sliced fashion; in that case, some
amount of buffer storage is often inserted between
elements.

TYPES OF PIPELINES
Computer-related pipelines include:
Instruction pipelines, such as the classic RISC pipeline, which are used in processors to
allow overlapping execution of multiple instructions with the same circuitry. The circuitry is
usually divided up into stages, including instruction decoding, arithmetic, and register fetching
stages, wherein each stage processes one instruction at a time.
Graphics pipelines, found in most graphics cards, which consist of multiple arithmetic units,
or complete CPUs, that implement the various stages of common rendering operations
(perspective projection, window clipping, color and light calculation, rendering, etc.).
Software pipelines, where commands can be written so that the output of one operation is
automatically used as the input to the next, following operation. The Unix command pipe is a
classic example of this concept; although other operating systems do support pipes as well.
Pipelining Rules
• Forward travelling signals at each stage are latched
• Only perform logic on signals in the same stage
– signal labeling useful to prevent errors,

e.g., IRR, IRA, IRM, IRW
• Backward travelling signals at each stage represent hazards

Costs, Drawbacks, and Benefits
• As the assembly line example shows, pipelining doesn't decrease the time for a
single datum to be processed; it only increases the throughput of the system when
processing a stream of data.
• High pipelining leads to increase of latency - the time required for a signal to
propagate through a full pipe.
• A pipelined system typically requires more resources (circuit elements, processing

units, computer memory, etc.) than one that executes one batch at a time, because
its stages cannot reuse the resources of a previous stage. Moreover, pipelining
may increase the time it takes for an instruction to finish.

Advantages of Pipelines
An instruction pipeline is said to be fully p i pelined it can accept a new instruction
every clock cycle.
A pipeline that is not fully pipelined has wait cycles that delay the progress of the
pipeline.
The cycle time of the processor is reduced, thus increasing instruction issue-rate in
most cases.
Some combinational circuits such as adders or multipliers can be made faster by

adding more circuitry.
If pipelining is used instead, it can save circuitry vs. a more complex combinational
circuit.

Disadvantages of Pipelines
A non-pipelined processor executes only a single instruction at a time. This prevents
branch delays (in effect, every branch is delayed) and problems with serial instructions
being executed concurrently.
Consequently the design is simpler and cheaper to manufacture.
The instruction latency in a non-pipelined processor is slightly lower than in a pipelined

equivalent. This is because extra flip flops must be added to the data path of a
pipelined processor.
A non-pipelined processor will have a stable instruction bandwidth. The performance

of a pipelined processor is much harder to predict and may vary more widely between
different programs.

An Example of Pipelines
To the right is a generic pipeline with four
stages:
1. Fetch
2. Decode
3. Execute
4. Write-back
The top gray box is the list of

instructions waiting to be executed; the
bottom gray box is the list of instructions
that have been completed; and the
middle white box is the pipeline.

Arithmetic Pipelining
Pipeline arithmetic unit are usually found in very high speed
computers.
They are used to implement floating point operation, multiplication

of fixed point number and similar computations encountered in
scientific problems.
A pipeline multiplier is essentially an array multiplier floating point

operation are easily decomposed into sub-operation that are
performed in four segments.

Arithmetic Pipelining

INSTRUCTION PIPELINING
• An instruction pipeline is a technique used in the design of computers and other
digital electronic devices to increase their instruction throughput (the number of
instructions that can be executed in a unit of time).
• The fundamental idea is to split the processing of a computer instruction into a series of
independent steps, with storage at the end of each step.
• This allows the computer's control circuitry to issue instructions at the processing rate of
the slowest step, which is much faster than the time needed to perform all steps at
once.
• The term pipeline refers to the fact that each step is carrying data at once , and each
step is connected to the next (like the links of a pipe.)

Instruction Pipelining
Cycle
1 2 3....
F R X M W
F R X M W
Instruction
F R X M W
F R X M W
F R X M
F R X

Pipeline Hazards
• Data hazards
– an instruction uses the result of a previous instruction (RAW)
ADD R1, R2, R3 or SW R1, 3(R2)
ADD R4, R1, R5 LW R3, 3(R2)
• Control hazards
– the location of an instruction depends on a previous instruction
JMP LOOP
…
LOOP: ADD R1, R2, R3
• Structural hazards
– two instructions need access to the same resource
• e.g., single memory shared for instruction fetch and load/store
• collision in reservation table
Vector Processor And Array
Processor
• A vector processor, or array processor, is a central processing unit (CPU) that
implements an instruction set containing instructions that operate on one-
dimensional arrays of data called vectors.
• This is in contrast to a scalar processor, whose instructions operate on single data

items. The vast majority of CPUs are scalar.
• Vector processors first appeared in the 1970s, and formed the basis of
most supercomputers through the 1980s and into the 1990s. Improvements in
scalar processors, particularly microprocessors, resulted in the decline of
traditional vector processors in supercomputers, and the appearance of vector
processing techniques in mass market CPUs around the early 1990s.

Vector Processor And Array Processor
• Improvements in scalar processors, particularly microprocessors, resulted in the

decline of traditional vector processors in supercomputers, and the appearance of
vector processing techniques in mass market CPUs around the early 1990s.
• Today, most commodity CPUs implement architectures that feature instructions for
some vector processing on multiple (vectorized) data sets, typically known
as SIMD (Single Instruction, Multiple Data). Common examples include MMX, SSE,
and AltiVec.
• Vector processing techniques are also found in video games console hardware
and graphics accelerators. In 2000, IBM, Toshiba and Sony collaborated to create
the Cell processor, consisting of one scalar processor and eight vector processors,
which found use in the Sony PlayStation 3among other applications.

Processor

Processor
• Vector processing was first worked on in the early 1960’s at
Westinghouse in their Solomon project.
• Solomon's goal was to dramatically increase math performance by

using a large number of simple math co-processors under the
control of a single master CPU.
• The CPU fed a single common instruction to all of the arithmetic

logic units (ALUs), one per "cycle", but with a different data point for
each one to work on.
An Example: Vector Processor And Array
Processor
• In general terms, CPUs are able to manipulate one or two pieces of data at a time. For
instance, many CPUs have an instruction that essentially says "add A to B and put the result
in C".
• The data for A, B and C could be—in theory at least—encoded directly into the instruction.
However things are rarely that simple.
• In general the data is rarely sent in raw form, and is instead "pointed to" by passing in an
address to a memory location that holds the data. Decoding this address and getting the data
out of the memory takes some time.
• As CPU speeds have increased, this memory latency has historically become a large
impediment to performance
Types of Vector Processing
• Today, most commodity CPUs implement architectures that
feature instructions for some vector processing on multiple
(vectorized) data sets, typically known as SIMD (Single
Instruction, Multiple Data). Common examples include MMX, SSE,
and AltiVec. Vector processing techniques are also found in video
game console hardware and graphics accelerators.
• Other CPU designs may include some multiple instructions for

vector processing on multiple (vectorized) data sets, typically
known as MIMD (Multiple Instruction, Multiple Data). Such designs
are usually dedicated to a particular application and not commonly
marketed for general purpose computing.
Thank You

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Digital and Computer Organization

Copyright@ Amity University

• The format of an instruction is usually depicted in a rectangular box

1. An operation code field that specifies the operation to be performed.

2. An address field that designates a memory address or a processor register.

• Other special fields are sometimes employed under certain circumstances.

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• Most computers fall in one of three types of CPU organization:

1. Single accumulator organization.

2. General register organization

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• General Register Organization:

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1. Three address instructions.

2. Two address instructions.

3. One address instructions.

4. Zero address instructions.

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Let us consider the example

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• Consider the example

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• Register versus memory

• Number of register sets

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This is the MIPS "Add" instruction which allows selection of source

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Computers use addressing mode techniques for the purpose of

1. To give programming versatility to the user.

2. To reduce the number of bits in the address field of the

3. To provide flexibility for writing programs.

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4. Register indirect mode.

5. Auto increment or auto decrement mode.

6. Direct address mode.

8. Relative address mode.

9. Indexed addressing mode.

10. Base register addressing mode.

• Although most addressing modes modify the address field of the

All register reference instructions that use an accumulator are

Example: CMA compliment accumulator.

The most advantage of implicit addressing of this kind is that it

Zero address instructions in a stack organized computer are

Some times the operand values is contained in the instruction

In this mode, Operand is part of instruction

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• No memory reference to fetch data

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• The register is selected from the register field in the instruction.

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• Limited number of registers

• Very small address field needed

– Faster instruction fetch

• Very fast execution

• Very limited address space

• Multiple registers helps performance

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• In register indirect mode the instruction specifies a register in the CPU

• The advantage of a register indirect mode instruction is that the address

• Example: MOV AX, [CX]

• Operand is in memory cell pointed to by contents of register R