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UNITI: 4 lecture hours

Binary Systems and Logic Circuits: The Advantage of Binary, Number Systems, The Use of
Binary in Digital Systems, Logic Gates, Weighted & Non-weighted codes, Sequential codes, self-
complementing codes, Cyclic codes, 8421, 5421, 2421 , BCD code, Excess-3 code, Binary to Gray
and Gray to binary code conversion. Error detecting code, Error correcting code, 7-bit Hamming
code, ASCII code, EBCDIC code. Logic Gates: Gates as Switch.

Unit II: 6 lecture hours

Boolean Algebra and Mapping Methods: Boolean Algebra, Karnaugh Maps, Three, Four and Five
variable. Mapping and minimization of SOP and POS expressions, K-MAP with Don't Care, Quine
Mc Clusky (Tabulation) Method, Variable Entered Maps, Realizing Logic Function with Gates,
Combinational Design Examples.

Unit III: 8 lecture hours

Combinational circuit: Adders & Subtractors: Half adder, Full adder, half subtractor, Full
subtractor, 4 bit Parallel Binary adder/Subtractor, Look Ahead carry adder, Serial adder, BCD
adder. Code converters, Parity bit generator/Checker, Magnitude Comparators. Decoder 2x4, 3 to
8-line decoder, BCD to Seven segment decoder. Encoders: Octal to binary and Decimal to BCD
encoder. Multiplexer 2x1, 4x1, 8x1, 16x1 demultiplexers, Multiplexer as Universal Logic Function
Generator,Boolean function realization using Multiplexers, Decoder with enable input, Multiplier
and Divider

Unit IV: 8 lecture hours

SEQUENTIAL CIRCUITS- Difference between Combinational and Sequential circuits, Latch and
Flip Flop, Flip Flop types & Timing diagram: S-R Latch, Gated S-R Latch, D Latch, D Flip Flop
,J-K flip-Flop, T Flip-Flip: Edge Triggered S-R, D, J-K and T Flips-Flops, Master - Slave Flip-
Flops, race around condition of Master JK Flip Flop, FFs Characteristics equation and excitation
tables, Flip Flops Conversions, State assignment, State table, State reeducation and analysis,
Design by Flip Flops.
Counters: Binary Counter, Counter Types Asynchronous Counter: Ripple Counters; Design of
asynchronous counters, Effects of propagation delay in Ripple counters, Synchronous Counters:
4-bit synchronous up and down counter, Design of synchronous Counters, Ring counter, Johnson
counter. Pulse train generators, Sequence Generators
Registers: PIPO, SIPO, PISO, SISO, Bi-Directional Shift Registers; Universal Shift register

Unit V: 10 lecture hours

Introduction to State Machines: The Need for State Machines, The State Machine, Basic Concepts
in State Machine Analysis. Synchronous State Machine Design, Sequential Counters, State
Changes Referenced to Clock, Number of State Flip-Flops, Input Forming Logic, Output Forming
Logic, Generation of a State Diagram from a Timing Chart, Redundant States, General State
Machine Architecture Asynchronous State Machines: The Fundamental-Mode Model, Problems
of Asynchronous Circuits Basic Design Principles, An Asynchronous Design Example.

Unit VI: 10 lecture hours

Logic Families: Transistor-Transistor Logic(TTL), Emitter-Coupled Logic(ECL),
Programmable Logic Devices: Introduction to Programmable Logic Devices, Read-Only Memory,
Programmable Logic Arrays (PLA), Programmable Array Logic (PAL), Combinational PLD-
Based State Machines, State Machines on a Chip.

Text Books
1. Morris M Mano (2001) Digital Design ISBN-13: 978-0130621214
Reference Books
1. G.K.Kharate (2012) Digital Electronics: Oxford publication ISBN 13: 780198061830
2. Thomas L. Floyd (2015) Digital Fundamentals, 11th Edition ISBN-13: 978-0132737968

Modes of Evaluation: Quiz/Assignment/ presentation/ extempore/ Written Examination

Examination Scheme:

Components MSE Internal Assessment ESE

Weightage (%) 20 30 50