SUPPLEMENTS Stanford University - Power Electronics: EE153, EE254 (Rivas) - Analog IC Circuit Design: EE114, EE214B (Murmann) Outstanding Peer Review [Apple] Electrical Engineering, BS D2-converter Project [EE254] 2017, June - Digital Design: EE108 (verilog) Folded Cascade Project [EE214B] - Computer Science: CS106A, CS106B, CS107 - Signal Processing: EE102A - Mathematics: EE103 (Linear Algebra), CME102 (Differential Equations), CME100 (Vector Calculus), EE178 (Probability)
CURRENT POSITION Apple Power Engineer
Apple - Power engineer for high-profile, high-production custom silicon SoC project Power Engineer - Carried design of high-power bus converters from functional requirements to power 2017 to 2019 architecture, detailed analysis, schematic capture, placement and layout with PCB team July - July - Defined >1k OTP values for custom PMIC, inductor selection, vendor communications - Collaborated with Apple SEG on PI simulations of on-die regulation, relative power sequencing timing of the 29x rails; thermal team for design appropriate cooling solutions; mechanical team for keepout and cold plate design; EMC team for certification - Employed FEA modeling of current plane density to iteratively drive plane fanout - Developed and owned register values of bus converters—worked on-site with ICT team at SMT house to implement automated flashing at post-SMT bed-of-nails station - Developed and executed detailed test plan of bus regulators and core-rails, employing excellent quality of techniques per Apple SiVal—under custom RDMA and virus loading - Delivered exemplary smooth bringup under intense time pressure, company-wide scrutiny - Support of lifetime of product including component sourcing issues during relatively high- quantity builds (5k), detailed FA investigations, support of Rel waterfall testing - Realization of high-current power prioritizer PCB for regenerative, safety-critical loads - Extensive characterization including self-designed automated regression testing - Exhaustive, high-profile benchmarking of competitor system from test scoping and safety review to instrumentation, field + facility testing and scripting extracting insights from very large time-series datasets - Developed Matlab-based capability to auto-pull a system-level design from a database, recursively crawl through the power tree, selectively roll-up use-case specific power numbers and present rich, user explorable, context-dependent views of power consumption on different timescales - Currently working on Class-D amplifier for high-voltage, non-audio application Apple Apple Intern Hardware Intern - Lead for expansive, high power 48V power distribution hardware investigation of eFuse 2016 March – September implementations with arc detection, mechanical fuse emulation and telemetry - Drove effort from architecture and requirement definition to 100+ page of schematic, associated peer reviews, placement and layout with PCB engineer and fabrication - Performed detailed SPICE simulations to ensure SOA compliance (e.g. switching locus during startup into highly capacitive loads at elevated ambient); FEA thermal simulations - Heavy collaboration with large set of cross-functional teams (e.g. Mechanical, PCB, DFM, Interconnect, Thermal, Rel, DFMEA, Architecture, System Integration)
PREVIOUS EXPERIENCE Renovo Motors Intern
Renovo Motors - DRI for the design and system integration of a 18kW (850V) fast charge system for the Intern Renovo Coupe EV (series combination of OTS power modules) 2015 June – - 4,650+ lines of firmware for the charging system in C for ARM-based 32-bit MCU including September interfacing with low-level SPI and CAN libraries, implementing vendor DBC
Electric Go-Kart Electric Go-Kart Team Member
Team Member - iPhone controlled electric go-kart displayed at the Bay Area Maker Faire (5/2014) 2014 February – - DRI for design of 60W monolithic switching power regulator (LM2678SD-12) PCB with H- November bridge IC (L298P); Arduino shield form-factor, personally etched and assembled PCB