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1 Introduction
coupled with hardware and software integration, which are designed to perform a
dedicated function. In an embedded system the hardware and software are optimized
for a particular application. The word embedded reflects the fact that these systems
are usually an integral part of a larger system, known as the embedded system. The
designed for one application cannot be ordinarily used for any other application. Most
of the embedded systems are reactive systems i.e. the embedded system is one that is
that environment.
In many ways virtually unimaginable just a few decades ago, embedded systems are
reshaping the way people live, work, and play. An embedded system comes in an
represent a class of dedicated computer systems designed for specific purposes. Many
of these embedded systems are reliable and predictable. The devices that embed them
are convenient, user-friendly, and dependable. Embedded systems have also changed
Perhaps the most significant application is robotic control parameters like speed and
63
position controlling which is really just a very large collection of embedded systems
Lot of industries use embedded systems for process control. The embedded systems
for industrial use are designed to carry out specific tasks such as monitoring the
temperature, pressure, humidity, voltage, current etc., and then take appropriate
action. The robotics are now becoming very powerful and carry interesting and
hardware and software components are increasingly required [1], Embedded systems
in which some specific task has to be done in a specific time period are called real
time embedded systems. The development of embedded software was done mostly in
assembly languages. However, due to the availability of cross compiler, most of the
computational power with low energy consumption constraints [2]. The embedded
world has been one of the more mature and relatively steady segments of the
computing universe. Any embedded device can be made more flexible, useful, and
have been hardware-centric, and embedded software was relatively simple and
However, more than 70% of the development cost for complex system such as
64
automotive electronics and communication systems is attributable to software
such as RS-232, SPI, I2C, or CAN. Similarly, for interactions with the non-digital
must be on timing and interrupts represent only a small fraction of the total number of
focused job. Applications such as the air conditioner, VCD player, DVD player,
printer, fax machine, mobile phone etc. are examples of embedded systems. Each of
these applications will have a processor and special hardware to meet the specific
requirement of the application along with the embedded software that is executed by
the processor for meeting that specific requirement. The embedded software is also
called “firmware”. The embedded system market is one of the highest growth area as
65
these systems are used in the market segment of consumer electronics, office
In an embedded system, the system software gets embedded with the application
stream of data [3]. Embedded system has only one build i.e. only one executable file.
In this system the operating system is not a distinct entity. Only a required amount of
system software exists to assist the application software. One of the most critical
needs of an embedded system is to decrease power consumption, cost and space. This
techniques, to the inner working of real time operating systems and multithreaded
applications.
hardware and increased efficiency. Typically, most embedded control systems are
I/O ports. Microcontrollers are used in different applications, especially in real time
66
one task. For example a printer is an embedded system since the Microcontroller
inside it performs one task only, namely getting the data and printing it.
electronic devices (generally at least one Microcomputer) that interacts with the real
world (physical environment, human users, etc.) through sensing and actuating
as well as analog components such as A/D and D/A converters, sensors, transmitters
and receivers. In the past, the system design effort has focused on these hardware
New software technologies are important for the future of control (and vice versa) in
an age of increasing complexity [4], For new automotive applications and services,
information technology (IT) has gained central importance. IT-related costs in car
manufacturing are already high and they will increase dramatically in the future [5].
In the coming years, Ada runtime and COTS RTOS supporting Generalised Rate
Monotonic Scheduling (GRMS) have met the DO 178B flight control standard [6],
Embedded operating systems such as VRTX or PSOS were simple flat address space
complexity where embedded software dominates the development cost and schedule.
Linux, for the first time in the industry, provides the potential of an open multi vendor
platform with an exploding base of software and hardware support. The growth in the
use of Linux in embedded systems over the past few years has been astonishing. The
67
success of Linux in the server or desktop arena over the last few years has received
the most attention, where the most ardent supporters of Linux are attempting to
loosen the strong hold of established operating systems such as Windows. In the
domination.
In the embedded operating system UNIX, management of the graphic display is split
between the X server, which knows the hardware and offers a unified interface to user
programs and the window and session managers, which implement a particular policy
without knowing anything about the hardware [7]. It can use the same windows
manager on different hardware, that can also run different configurations on the same
GNOME, can coexist on the same system. Another example is the layered structure
of TCP/IP networking, the operating system offers the socket abstraction, which
implements no policy regarding the data to be transferred, while different servers are
in charge of the services (and their associated policies). Moreover, server provides
the file transfer mechanism, while users can use whatever client they prefer; both
command-line and graphic clients exist, and anyone can write a new user interface to
transfer files.
A device driver plays a special role in the Linux kernel. They are distinct particular
User activities are performed by means of a set of standardized calls that are
that act on real hardware is then the role of the device driver. This programming
68
interface is such that drivers can be built separately from the rest of the kernel, and
"plugged in" at runtime when needed. This modularity makes Linux drivers easy to
write, to the point that there are now hundreds of them available. Recent trend in
The rate at which new hardware becomes available (and obsolete!) alone guarantees
that driver writers will be busy for the foreseeable future. Individuals may need to
know about drivers in order to gain access to a particular device that is of interest to
them. Hardware vendors, by making a Linux driver available for their products, can
add the large and growing Linux user base to their potential markets. The open source
nature of the Linux system means that if the driver writer wishes, the source to a
driver can be quickly disseminated to millions of users. But most of the principles and
basic techniques are the same for all drivers. Multiprocessor systems, especially those
systems [9].
time required and the flexibility of the result is vital. A driver is "flexible” because it
emphasizes that the role of a device driver is providing mechanism, not policy. The
distinction between mechanism and policy is one of the best ideas behind the UNIX
design. Most programming problems can indeed be split into two parts: "what
capabilities are to be provided" (the mechanism) and "how those capabilities can be
used" (the policy). If the two issues are addressed by different parts of the program, or
69
even by different programs altogether, the software package is much easier to develop
The driver should deal with making the hardware available, leaving all the issues
about how to use the hardware to the applications. A driver, then, is flexible if it
software development activities [10]. For example, a digital I/O driver may only offer
byte-wide access to the hardware in order to avoid the extra code needed to handle
individual bits. This privileged role of the driver allows the driver programmer to
choose exactly how the device should appear. Different drivers can offer different
capabilities, even for the same device. Many device drivers, indeed, are released
together with user programs to help with configuration and access to the target
device. Those programs can range from simple utilities to complete graphical
applications. Examples are the parallel port printer driver operation and the graphical
cadet utility, which adjusts the tunnel program that is part of the PCMCIA driver
package.
70
transducers are increasingly being applied in physiological -data acquisition and
design effort, FPGA prototypes and ASIC implementations are derived from a
domain [13].
The FPGAs and CPLDs are becoming a popular alternative to ASICs, providing
FPGA is not fixed prior and therefore the permitted programmability, connectivity,
FPGA products, including significantly larger gate counts and software tools for
development and integration, are now increasing their popularity. One of these
serial switching fabric, such as Rapid I/O. It uses Asymmetric SRAM (ASRAM)
(instead of high-Vt SRAM) cell to implement the configuration memory [15]. This
trend provides a natural, high-speed, bi-directional data path that enables data
movement at very high speeds. The FPGA is nonvolatile type and requires the battery
back to stable the program, where as CPLD is volatile type. The CPLD and FPGA use
software are test bench tools that support VHDL and Verilog languages. When
introducing VHDL, it is very important to keep emphasizing the fact that the VHDL
code is only describing the required behavior of the digital circuit or system and is not
71
being executed in some way by a ‘hidden’ interpreter or microprocessor on the FPGA
[16]. To reduce development cost and avoid duplication of design effort, FPGA
systems by providing high performance for a specific application domain [13]. This
programmable gate arrays (FPGAs) to build the SOLAR (self organizing learning
array) learning machine. SOLAR has many advantages over the traditional neural
[18].
integrate on a single chip enormous number of transistors, thus allowing the inclusion
memories, ASICs, and peripherals. The development of this new class of systems is
called Systems on Chip (SoCs) [19]. The wizard generates both the framework code
required to use the library and a project file that can be loaded into the Silicon
a low overhead and low footprint, suitable for embedded systems. Yartek has been
Yartek for the implementation of non-visual perception for mobile robots [20]. The
system for temperature measuring was realized based on microcontroller and a digital
temperature sensor [21]. Cygnal Microcontroller, which is used in the present study,
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truly a standalone system-on-a-chip solution or embedded control chip. The
pipelined architecture that greatly increases its instruction throughout the standard
8051 architecture. Here Cygnal Microcontroller C8051F020 plays very important role
in the D.C motor control system. It is having a built -in 12-bit ADC, 10-bit ADC, two
12-bit DAC, 64K bytes programmable Flash memory, 256K bytes data RAM and 4K
bytes of XRAM, which are most essential requirements to control D.C motor speed
8. Temperature sensor
microcontroller based P, PI and PID logic controllers for DC motor speed control
systems are discussed. The work element consists of microcontroller circuits, which
resources that facilitate their work and their relation with the out side world [22].
73
However, short-bit-width processors (8 bit processor) continue to dominate
worldwide microcontroller sales volumes [23-25], In 2006, the 8-bit units have
Microcontrollers account for the majority of processors produced today, yet their
3.3.1 Introduction
Microcontroller core and it can execute 25 million instructions per second. The
standard CMOS technology and on-chip signal processing, Ion-Sensitive Field Effect
platform that integrates most of hardware blocks required in the design of embedded
system chips. By integrating both the multithreaded processor and the configurable
multithreaded processor and implementing the external interface functions into the
configurable logic clusters [27], All analog and digital peripherals are
reprogrammed even in circuit i.e. it contains non-volatile data storage, and also
74
allowing field upgrades of the 8051 firmware.. On board JTAG (Joint Test Access
Group) debug circuitry allows non- intrusive (without disturbing on chip resources),
fully speed, and in-circuit debugging. This debug system supports inspection and
stepping, run and halt commands to installing the production in the final application
of MCU. All analog and digital peripherals are fully functional while debugging using
JTAG. The MCU operating voltage and temperature range is specified 2.7V-to-3.6V
and -45°C to +85°C. The Microcontroller I/O ports, Reset (RST) and JTAG pin are
3.3.2 Architecture
architecture that greatly increases its instruction throughout over the standard 8051
architecture. In a standard 8051, all instruction except for MUL and DIV take 12 or
24 system clock cycles to execute with a maximum system clock of 12-to-24 MHz.
The CIP-51 has a total of 109 instructions and it executes 70% of instructions in one
or two system clock cycles. The MCU has an internal, stand-alone clock generator,
which is used by default as the system clock after any reset. If desired, the clock
source may be switched on the fly to the external oscillator, which can use a crystal,
ceramic resonator, capacitor, RC, or external clock source to generate the system
clock. This can be extremely useful in low power applications, allowing the MCU to
run from a slow (power saving) external crystal source, while periodically switching
75
Port 4
Port 5
Port 6
Port 7
The Cygnal Microcontroller has internal on chip memories i.e. program memory and
data memory. The program memory is used to store program permanently (non
volatile memory) and the data memory is using to store the data (volatile). It consists
64K bytes of program memory (Flash) and data memory (RAM) is 256 bytes and 4K
bytes of additional memory. The CIP-51 has a standard 8051 program and data
address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes
dual-mapped. The upper 128 bytes is used as a general-purpose area in RAM which is
accessed in indirect addressing mode. The lower 128 bytes is used as a Special
Function Register (SFR) space, which accesses in direct addressing mode. Generally
all types of Microcontrollers consist only 128 bytes of RAM space. The 128 bytes of
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RAM are accessible via direct and indirect addressing. The first 32 bytes are
memory locations, and the next 16 bytes can be byte addressable or bit addressable. In
the four register banks (RB0-RB3) selecting only one enabled at a time, each bank
selecting default register bank RBO. The Register bank RB1-RB3 selecting through
the RSO and RSI control flags in a PSW (Program Status Word). This allows fast
context switching when entering subroutines and interrupt service routines. Indirect
addressing modes use registers RO and R1 as index registers. The CIP-51 in the
C8051F020 MCU additionally has an on chip 4K bytes of RAM block and an external
memory interface (EMIF) for accessing off-chip data memory (RAM). The on chip 4k
bytes block can be addressed over the entire 64K external data memory address range
either to on-chip memory or to off chip memory, or a combination of the two (address
program memory consists of 64K bytes of flash. This memory may be reprogrammed
in system in 512 bytes sectors, and requires no special off-chip programming voltage.
The 512 bytes from addresses OxFEOO to OxFFFF are reserved for factory use.
The C8051F020 family has on chip JTAG boundary scan, debugs circuitry that
provides non-intrusive, full speed, in circuit debugging. The JTAG port is folly
compliant to IEEE 1149.1 and provides foil boundary scans for test and measurement
purposes. On-chip test techniques to reduce the dependence on external testers and to
77
research and development [28]. The standard general-purpose eight ports (P0-P7) are
available on the MCU. In the eight ports, four ports (P0-P3) function as a I/O or bit
wise, like P1.0, P3.5 etc., and remaining ports (P4-P7) use only byte wise I/O. The
port I/O behaves like the standard 8051 with a few enhancements and it can be
configured as either a push pull or open drain output. Also, the “weak pull-ups” which
are normally fixed on an 8051 can be globally disabled, providing additional power
saving capabilities for low-power applications. Perhaps the most unique enhancement
is the digital crossbar. This is essentially a large digital switching network that allows
mapping of internal digital system resources to port I/O on P0, PI, P2, and P3. The
functions are supported. This design can also be made as a standalone system without
PSoC chip[30]. The four ports P0-P3 not only use I/O and also use same ports for on-
serial buses, Hardware interrupts, ADC start of conversion input (SOC), comparator
output etc., which are configured to appear on the port I/O pins with the help of
specified Crossbar control registers. This allows the user to select the exact mix of
general-purpose port I/O and digital resources needed for the particular application.
capture/compare modules. The time base is clocked from one of six sources, the
system clock divided by 12, the system divided by 4, timer 0 overflow, an External
clock input (ECI), the system clock, or the external oscillator sources divided by 8.
78
Each capture/compare module-can be configured to operate in one of six modes, edge- •
triggered capture, software timer, high speed output, frequency output, 8bit or 16 bit
timers and counters. Many embedded systems are very power-limited [30],
The MCU contains two-voltage comparators, the inputs of each comparator are
available at the package pins. The output of each comparator is optionally available at
the package pins via the I/O crossbar. When assigned to package pins, each
comparator control register (CPTOCN and CPT1CN). The program can be both the
hysteresis around the threshold voltage. The output of the comparator can be read via
register variable or interrupt source mode with the help of embedded software. Each
output default to the logic low state, its interrupt capability is suspended and its
supply current falls to less than 1 pA. Comparator inputs can be externally driven
sources with two priority levels. If interrupts are enabled for the sources, an interrupt
address to begin execution of an interrupt service routine (ISR). Each ISR must end
79
disabled through the use of an associated interrupt enable bit in an SFR (IE-EIE2
control register). Two of the external interrupt sources (INTO and INTI) are
depending on the setting of bits ITO (TCON.O) and IT1 (TCON.2). IEO (TCON.l) and
IE1 (TCON.3) serve as the interrupt-pending flag for the INTO and INTI external
The CIP-51 core has two software programmable power management modes, Idle and
Stop modes. Idle mode halts the CPU while leaving the external peripherals and
internal clocks active. In stop mode, the CPU is halted, all interrupts and timers
(except the missing clock detector) are inactive, and the system clock is stopped.
Since clocks are running in Idle mode, power consumption is dependent upon the
system clock frequency and the number of peripherals left in active mode before
entering Idle. Stop mode consumes the least power describing the power control
register PCON in CIP-51 power management mode. Using these advanced techniques
to save power and energy for commodity 8-bit microcontrollers while leveraging their
The MCU includes a programmable watchdog timer [WDT] running off the system
clock. A WDT overflow will force the MCU into the reset state. To prevent the reset,
the WDT must be restarted by application software before overflow. If the system
the WDT, the WDT will overflow and cause a reset. This should prevent the system
80
from running out of control. Following a reset the.WDT is automatically enabled and
running with the default maximum time interval. If desired the WDT can be disabled
until the next system reset. The state of the RST pin is unaffected by this reset. The
WDT consists of a 21-bit timer running from the programmed system clock. The
timer measures the period between specific writes to its control register. If this period
exceeds the programmed limit, a WDT reset is generated. The WDT can be enabled
Watchdog features are controlled via the watchdog timer control register WDTCN.
The C8051F020 consists two ADCs that are ADCO (12 bit) and ADC1 (8 bit). The
a programmable gain amplifier (PGAO), and a 100 kilo samples for second , 12-bit
Programmable Window Detector. The AMUXO, PGAO, Data Conversion Modes, and
Window Detector are all configurable under software control via the Special Function
Registers. The ADCO reference voltages are selected through voltage reference
control register (VREF). The ADCO Control register ADCOCN contain, controls for
ADCO, track-and-hold and PGAO. Eight of the AMUX channels are available for
technique for each input channel, and even accommodates mode changes "on-the-fly".
The current and voltage parameters are acquired with the help of data converter [32],
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The AMUX defaults to all single-ended inputs upon reset. There are two registers
associated with the AMUX: the Channel Selection register AMXOSL, and the
Configuration register AMXOCF. The PGA amplifies the AMUX output signal by an
amount determined by the states of the AMP0GN2-0 bits in the ADCO Configuration
The ADCO conversion speed is 100-kilo samples per second [ksps], its clock is
derived from the system clock divided by the value held in the ADCSC bits of register
ADCOCF. A conversion can be initiated in one of the four ways, depending on the
3. A rising edge detected on the external ADC convert start signal, CNVSTR;
The ADOBUSY bit is set to logic 1 during conversion and restored to logic 0 when
enabled) and sets the ADOINT interrupt flag (ADC0CN.5). Converted data is
available in the ADCO data word MSB and LSB registers, ADCOH, ADCOL.
Converted data can be either left or right justified in the ADCOH: ADCOL register
pair depending on the programmed state of the ADOLJST bit in the ADCOCN register.
82
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When initiating conversions by writing a ‘1’ to ADOBUSY, the ADOINT bit should
be polled to determine when a conversion has completed (ADCO interrupts may also
clocks (after the start-of-conversion signal). When the CNVSTR signal is used to
initiate conversions in low-power tracking mode, ADCO tracks only when CNVSTR
is low; conversion begins on the rising edge of CNVSTR. Tracking can also be
83
disabled when the entire chip is in low power standby or sleep modes. Low-power
track and-hold mode is also useful when AMUX or PGA settings are frequently
changed, to ensure that settling time requirements are when the ADCO input
minimum settling (or tracking) time is required before an accurate conversion can be
performed. In this low-power tracking mode, three SAR clocks are used for tracking
-
-
- - AIN671C AIN451C AIN231C AINO 11C
Bit 1: AIN231C: AIN2 and AIN3 are independent single ended inputs
84
R/W R/W R/W R/W R/W R/W R/W R/W
-
“ - - AIN671C AIN451C AIN231C AIN011C
The reference circuit offers full flexibility in operating the ADC and DAC modules.
Three-voltage reference inputs allow each ADC and the two DACs to reference an
external voltage reference or the on chip voltage reference output. The ADC0 may
also reference the DAC0 output internally and ADC1 may reference the analog power
The internal voltage reference circuit consists of a 1.2V band-gap voltage reference
generator and a gain of two output buffer amplifier. The internal reference may be
routed via the VREF to external system components or to the voltage reference input.
generator and selects the reference inputs for ADC0 and ADC 1.The BIASE control
bit in REF0CN enables the on board reference generator while the REFBE bit enables
the gain-of-two buffer amplifier which drives the VREF. When disabled, the supply
current drawn by the band-gap and buffer amplifier falls to less than IpA and the
85
output of the buffer amplifier enters a high impedance state. If the external band-gap
is used as the reference voltage generator, BIASE and REFBE must both be set to
logic l.If the internal reference is not used, REFBE may set to logic 0. Note that the
BIASE bit must be set to logic 1 if either DAC or ADC is used, regardless of whether
the voltage referenced is derived from the on-chip reference or supplied from the off-
chip reference. If neither the ADC nor DAC are being used, both of these bits can be
set to logic 0 to conserve power. Bits ADOVRS and AD1VRS select the ADCO and
ADC1 voltage reference sources respectively. The electrical specifications for the
The temperature sensor available in the Microcontroller connects to higher order input
of the multiplexed 12 bit Analog to digital converter ADCO, when the control bit
TEMPE bit enabled in the Reference Control Register REFOCN. While disabled, the
temperature sensor defaults to a high impedance state and any A/D measurements
-
- ADOVRS AD1VRS TEMPE BIASE REFBE
86
0:ADC 1 voltage reference from VREF1 pin
VREF pin
Fig 3.3 ADC and DAC Voltages References functional block diagram
87
. 3.3.5 12 -bit digital to analog converter (D/A)
Each C8051f020/l/2/3 device includes two on-chip 12-bit voltage mode digital to
input code range of 0x000 to OXfff.The DAC may be enabled/disabled via their
output is maintained in a high-impedance state, and the DAC supply current falls to
IpA or less. The voltage reference for each DAC is supplied at the VRED pin or the
VREF pin. The VREF device may be enabled in order for the DAC outputs to be
valid. Each DAC features a flexible output update mechanism which allows for
seamless full scale changes and supports jitter-free updates for waveform generation.
The following examples are written in terms of DACO, but DAC1 operation is
identical. Reads from DACOL return pre-latch data, meaning the value read is the
same as the last value written to this register, not the value at the DACOL latch. Reads
from DACOH always return the value at the DACOH latch. The Microcontroller
contains mixed array logic of analog, digital and digital communication blocks within
in it.
(MOO
88
In its default mode the DACO output is updated “on-demand” on a write to the high-
byte of the DACO data register. It is important to note that writes to DACOL are held
and have no effect on the DACO output until a write to DACOH takes place. If writing
a full 12-bit word to the DAC data registers, the 12-bit data word is written to the low
byte and high byte data registers. Data is latched into DACO after a write to the
DACOH if the full 12-bit resolution is required. The DAC can be used in 8-bit mode
by initializing DACOL to the desired value and writing data to only DACOH
ci*et
Update Output Based on Timer Overflow: Similar to the ADC operation, in which
the DAC output can use a Timer overflow to schedule an output update event. This
defined sampling rate by eliminating the effects of variable interrupt latency and
instruction execution on the timing of the DAC output. When the DACOMD bits are
set to 01, 10 or 11 writes to both DAC data registers are held until an associated
89
Timer overflow event occurs, at which time the DAC0H:DAC0L contents are copied •
to the DAC input latches allowing the DAC output to change the new value.
000: The most significant nibble of the DACO Data Word is in DACOH] 3:0], while the least
n DACOH |
(S'
■U UslB | | | | | i i DACIL
i i 1 i..... nl|
001; The most significant 5-bits of the DACO Data Word is in DAC0H|4:0], while the least
stanifkant 7-Wta are in DAOQL17 11
| DACOH |
■ r:"“r fT-~- '
1 ___111I1 DACIL
1 1 1 1 1 lsb Mmr|I
01ft The most significant 6-bits of the DACO Data Word is in BAC0H[5;0], while the least
significant 6-bits are in DACOLf7:2].
| DACOH | DACIL |
pBEl_ . j..._j____i 1 1 1 I
Oil: The most significant 7 -bits of the DACO Data Word is in DAC0H[6:O], while the least
significant 5-bits are in DACDLf 7:3],
DACOH I DACIL |
liilq MSB | i r ] i
............... i T t
lxxi The most significant 8-bits of the DACO Data Word is in DAC0H[7:0], while the Least
significant 4-bits are in DAOQLf7:41.
cz DACOH | DACIL |
J___1111______ 1 i i lsb
.....
Fig 3.5 DAC [high and low byte) 12 bits selection Control Register
In some instances, input data should be shifted prior to a DACO write operation to
properly justify data within the DAC input registers. This action would typically
require one or more load and shift operations, adding software overhead and slowing
90
DAC throughput. To.alleviate this problem, the data-formatting feature provides a
means for the user to program the orientation of the DACO data word within data
registers DACOH and DACOL. The three DACODF bits (DAC0CN.[2:0]) allow the
user to specify one of five data word orientations as shown in the DACOCN register
The C8051F020/1/2/3 are fully integrated mixed-signal System on Chip MCUs with
8-bit Ports. The lower ports: PO, PI, P2, and P3, are both bit- and byte-addressable
through their corresponding Port Data registers. The upper ports: P4, P5, P6, andP7
are byte-addressable. All Port pins are 5 V-tolerant, and all support configurable
Serial data transmission has become so important to the overall computing strategy of
industrial and commercial applications. This standard was enhanced in the early
transmission that was assigned that number RS 232 by the electronics industry
association. Physically the data is a series of voltage levels that re sampled, in the
center of the bit period, at a frequency that is determined by the serial data mode and
the program that controls that mode. The serial port present on the microcontroller
9 • I ^ \JF »•*»>'
91
Call.No.......
**■«*■'wrwmwiajwwv
UARTO is an enhanced serial port with frame error detection and address recognition
incoming data byte before software has finished reading the previous data byte.
UARTO is accessed via its associated SFRs, Serial control (SCONO) and Serial Data
Buffer (SBUFO).
(SCONO)
2 Baudrate 11,5000
The single SBUFO location provides accesses to both transmit and receive registers.
UARTO may be operated in polled or interrupt mode. UARTO has a two Transmit
interrupt flag, TIO (SCONO. 1) set when transmission of a data byte is complete, and a
UARTO interrupt flags are not cleared by hardware when the CPU vectors to the
92
References
[1] Albert Mo Kim Cheng “A survey of formal verification methods and tools for
[5] Marko Wolf, Andre Weimerskirch, and Thomas Wollinger “State of the Art:
pp 16,2007.
[6] Lui Sha, Chang-Gun Lee “Real-time virtual machines for avionics software
pp 156- 165,2006.
[7] Takada Hiroaki “The Current Status and Future Trends of Embedded System
[8] J.Jayapandian and Usha Rani Ravi “An embedded single chiptemperature
93
[9] Emiliano Betti, Daniel Pierre Bovet,Marco Cesati, and Roberto Gioiosa
2008.
pp 142-155,2006.
instruction set for RISC processors,” in VLSI for Artificial Intelligence and
[12] Chung-Huang Yang, Yaw-Feng Wang, Yi-Je Chan, W. Torbicz and Dorota G.
[13] Michael Gschwind” FPGA prototyping of a rise processor core for embedded
[14] Sameh Asaad and Kevin Warren, Speed Optimization of the ALR
94
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