IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO.
2, FEBRUARY 2010 275
New Reconfigurable Architectures for Implementing
FIR Filters with Low Complexity
R. Mahesh, Member, IEEE, and A. P. Vinod, Senior Member, IEEE
Abstract—Reconfigurability and low complexity are the two
key requirements of finite impulse response (FIR) filters employed
in multistandard wireless communication systems. In this paper,
two new reconfigurable architectures of low complexity FIR
filters are proposed, namely constant shifts method and pro-
grammable shifts method. The proposed FIR filter architecture
is capable of operating for different wordlength filter coefficients
without any overhead in the hardware circuitry. We show that
dynamically reconfigurable filters can be efficiently implemented
by using common subexpression elimination algorithms. The
proposed architectures have been implemented and tested on
Virtex 2v3000ff1152-4 field-programmable gate array and syn-
thesized on 0.18 µm complementary metal–oxide–semiconductor
technology with a precision of 16 bits. Design examples show
that the proposed architectures offer good area and power
reductions and speed improvement compared to the best existing
reconfigurable FIR filter implementations in the literature.
Index Terms—Channelizer, common subexpression elimina-
tion, FIR filter, high level synthesis, reconfigurability.
I. Introduction
F IR DIGITAL filters find extensive applications in mobile
communication systems for applications such as chan-
nelization, channel equalization, matched filtering, and pulse
shaping, due to their absolute stability and linear phase proper-
ties. The filters employed in mobile systems must be realized
to consume less power and operate at high speed. Recently,
with the advent of software defined radio (SDR) technology,
finite impulse response (FIR) filter research has been focused
on reconfigurable realizations. The fundamental idea of an
SDR is to replace most of the analog signal processing in the
transceivers with digital signal processing in order to provide
the advantage of flexibility through reconfiguration. This will
enable different air-interfaces to be implemented on a single
generic hardware platform to support multistandard wireless
communications [1]. Wideband receivers in SDR must be
realized to meet the stringent specifications of low power
consumption and high speed. Reconfigurability of the receiver
to work with different wireless communication standards is
another key requirement in an SDR. The most computationally
Manuscript received October 17, 2008; revised April 20, 2009 and Septem-
ber 28, 2009. Current version published January 22, 2010. This paper was
recommended by Associate Editor J. Lach.
The authors are with the School of Computer Engineering, Nanyang
Technological University, 639798 Singapore (e-mail: rpmahesh@ntu.edu.sg;
asvinod@ntu.edu.sg).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCAD.2009.2035548
0278-0070/$26.00

c 2010 IEEE
intensive part of an SDR receiver is the channelizer since it
operates at the highest sampling rate [2]. It extracts multiple
narrowband channels from a wideband signal using a bank
of FIR filters, called channel filters. Using polyphase filter
structure, decimation can be done prior to channel filtering
so that the channel filters need to operate only at relatively
low sampling rates. This can relax the speed of operation of
the filters to a good extent [22]. However due to the strin-
gent adjacent channel attenuation specifications of wireless
communication standards, higher order filters are required for
channelization and consequently the complexity and power
consumption of the receiver will be high. As the ultimate aim
of the future multi-standard wireless communication receiver
is to realize its functionalities in mobile handsets, where its full
utilization is possible, low power and low area implementation
of FIR channel filters is inevitable. In [37], the filter multipli-
cations are done via state machines in an iterative shift and
add component and as a result of this there is huge savings
in area. For lower order filters, the approach in [37] offers
good trade-off between speed and area. But in general, the
channel filters in wireless communication receivers need to be
of high order to achieve sharp transition band and low adjacent
channel attenuation requirements. For such applications, the
approach in [37] results in low speed of operation.
The complexity of FIR filters is dominated by the com-
plexity of coefficient multipliers. It is well known that the
common subexpression elimination (CSE) methods based on
canonical signed digit (CSD) coefficients produce low com-
plexity FIR filter coefficient multipliers [3]. The goal of CSE
is to identify multiple occurrences of identical bit patterns
that are present in the CSD representation of coefficients,
and eliminate these redundant multiplications. A modification
of the 2-bit CSE technique in [3] for identifying the proper
patterns for elimination of redundant computations and to
maximize the optimization impact was proposed in [4]. In [5],
the technique in [3] was modified to minimize the logic depth
(LD) (LD is defined as the number of adder-steps in a maximal
path of decomposed multiplications [27]) and thus to improve
the speed of operation. In [6], we have proposed the binary
common subexpression elimination (BCSE) method which
provided improved adder reductions and thus low complexity
FIR filters compared to [3]–[5]. In [7], a method based on
the pseudo floating point method was used to encode the filter
coefficients and thus to reduce the complexity of the filter.
But the method in [7] is limited to filter lengths less than 40.
In general, the methods in [3]–[7] are only suitable for
276 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 2, FEBRUARY 2010
application specific filters where the coefficients are fixed and
hence not suitable for reconfigurable filters.
Several implementation approaches for reconfigurable FIR
filters have been proposed in literature [8]–[15]. These de-
signs include either a fully programmable multiply-accumulate
(MAC) based filter processor or dedicated architectures where
the filter coefficients can be stored in registers. The architec-
ture of a filter processor consists of a datapath with a single
MAC unit, data and program memories, and a control unit
[8], [9]. The datapath includes a 16-bit adder/subtractor, a
multiplier, and a 32-bit accumulator. The performance of the
processor is mainly restricted by the delay of this datapath,
more specifically that of the multiplier. The main disadvantage
of the filter processors is that the area and power requirements
are significantly large. In [10], a comparison was done for
the performance of speech based algorithms on dedicated
architectures and general-purpose processors. It was shown
that the power consumption for a general-purpose processor
can be a factor of four times more than dedicated architectures
for a complex algorithm [10].
The works in [11]–[15] and [20], [21] present reconfigurable
FIR filter architectures. In [11], a CSD based digit reconfig-
urable FIR filter architecture was proposed. This architecture
was independent of the number of taps because the number of
taps and non-zero digits in each tap were arbitrarily assigned.
The intention of the authors was to reduce the precision of
coefficients and thus the filter complexity without affecting the
filter performance. But the architecture in [11] demanded huge
hardware resources and this makes the method infeasible for
power constrained SDR receiver applications. In [12], a high-
speed programmable CSD based FIR filter was proposed. The
filter architecture consisted of a programmable CSD based
Booth encoding scheme and partial product Wallace adder
tree. The final adder was a carry look-ahead adder. Though
this method offered a high speed solution, the resulting filters
consume more power. Another high-speed programmable FIR
filter based on polyphase decomposition was proposed in [13].
However, this method used the built-in block multipliers of
Virtex II field-programmable gate array (FPGA) and there
was no consideration for the complexity reduction of the
FIR filter. In [14], the concept of reconfigurable multiplier
block (ReMB) was introduced. The ReMB will generate all
the coefficient products and a multiplexer will select the
required ones depending on the input. It was shown that by
pushing the multiplexer deep into the multiplier block design,
the redundancy can be reduced. The resulting specialized
multiplier design can be more efficient in terms of area and
computational complexity compared to the general-purpose
multiplier plus the coefficient store [14]. But the ReMB pro-
posed in [14] has its area, power, and speed dependent on the
filter-length making them inappropriate for higher order FIR
filters. In [15], a multiplexed multiple constant multiplications
(MMCM) approach was proposed. This method considers the
coefficient set as a constant and uses the graph dependence
(GD) algorithms for reducing redundancy. But this method
follows a directed acyclic graph structure which will result
in long LD and thus lower speed of operation as reported
in [3], [24], [25]. Also the area of the architecture linearly
increases with the filter length as in [14] and filters with
filter-length above 40 are infeasible. In [20], the common
digital signal processing (DSP) operations such as filtering and
matrix multiplication were identified and expressed as vector
scaling operations. In order to apply vector scaling, simple
number decomposition strategies were identified. The idea was
to precompute the values such as x, 3x, 5x, 7x, 9x, 11x, 13x,
and 15x, where x is the input signal and then reuse these
precomputations efficiently using multiplexers. The presence
of multiplexers gave the option of adaptive computing for the
method in [20]. In [21], the method in [20] was modified
and efficient circuit-level techniques, namely a new carry-
select adder and conditional capture flip-flop, were used to
further improve power and performance. The architectures in
[11]–[15] and [20], [21] are appropriate only for relatively
lower order filters and hence not suitable for channel filters in
communication receivers.
Although a few works addressed the problem of reducing
the complexity of coefficient multipliers in reconfigurable
FIR filters, hardly any work demonstrated reconfigurabil-
ity in higher order filters. Moreover, we note that there is
sufficient scope for more work on complexity reduction in
reconfigurable filters especially for wireless communication
applications where higher order filters are often required to
meet the stringent adjacent channel attenuation specifications.
In this paper, we propose two architectures that integrate
reconfigurability and low complexity to realize FIR filters.
The FIR filter architectures proposed are called constant shifts
method (CSM) and programmable shifts method (PSM). We
have presented the preliminary design of these architectures in
a recent conference paper [34]. In this journal, we elaborate the
CSM and PSM architectures introduced in [34] by providing
the detailed design. The design analysis of the architectures
and their extension to high-level synthesis are presented. The
proposed architectures have been synthesized on 0.18 µm
complementary metal—oxide—semiconductor (CMOS) tech-
nology and compared with the recent methods such as
[11], [12], [14], and [15]. Also we have implemented two CSD
based methods based on our CSM and PSM to compare the
complexities of the CSD and binary based CSE techniques.
The implementation and verification of the proposed archi-
tectures on Virtex 2v3000ff1152-4 FPGA is also presented.
The proposed architectures consider coefficients as constants
(as they are stored in LUTs) and input signal as variable.
The coefficient multiplication in such a case is known as
multiple constant multiplications (MCM), i.e., multiplication
of one variable (input signal) with multiple constants (filter
coefficients) [35]. The MCM is then optimized for eliminating
redundancy using our recently proposed BCSE algorithm [6]
to minimize the filter complexity. The proposed CSM focuses
on the implementing FIR filters by partitioning the filter
coefficients into fixed groups. The PSM has a pre-analysis
part which eliminates the redundancy in filter coefficients
using the BCSE algorithm. The advantage of CSM is that
it produces high-speed filters at the cost of a slight increase
in area and power consumption. On the contrary, the PSM
produces filters with low area and power consumption at the
cost of a slight increase in delay. Another advantage of PSM is
MAHESH AND VINOD: NEW RECONFIGURABLE ARCHITECTURES FOR IMPLEMENTING FIR FILTERS WITH LOW COMPLEXITY
Fig. 1. Transposed direct form of an FIR filter.
that the wordlength of the filter coefficients can be dynamically
changed without any modification in the hardware.
The paper is organized as follows. In Section II, the BCSE
method is reviewed. Section III presents our reconfigurable
architectures. In Section IV, the proposed architectures are
extended to high-level synthesis. The synthesis and design
results of proposed architectures are presented in Section V.
In Section VI, implementation results of the proposed archi-
tectures are presented. Section VII has our conclusion.
II. Review of BCSE Method
This section reviews the BCSE algorithm [6], which deals
with the elimination of redundant binary common subex-
pressions (BCSs) that occur within the coefficients. The
BCSE technique focuses on eliminating redundant com-
putations in coefficient multipliers by reusing the most
common binary bit patterns (BCSs) present in coeffi-
cients. An n-bit binary number can form 2n − (n + 1)
BCSs among themselves. For example, a 3-bit binary rep-
resentation can form four BCSs, which are [0 1 1],
[1 0 1], [1 1 0], and [1 1 1]. These BCSs can be expressed as
[0 1 1] = x2 = 2−1 x + 2−2 x, [1 0 1] = x3 = x + 2−2 x, [1 1 0]=
x4 = x + 2−1 x, and [1 1 1]= x5 = x + 2−1 x + 2−2 x, where x is
the input signal. Note that other BCSs such as [0 0 1], [0 1 0],
and [1 0 0] do not require any adder for implementation as
they have only one nonzero bit. A straightforward realization
of above BCSs would require five adders. However x2 can be
obtained from x4 by a right shift operation (without using
any extra adders): x2 = 2−1 x + 2−2 x = 2−1 (x + 2−1 x) =
2−1 x4 . Also, x5 can be obtained from x4 using an adder:
x5 = x + 2−1 x + 2−2 x = x4 + 2−2 x. Thus, only three adders are
needed to realize the BCSs x2 to x5 . The number of adders
required for all the possible n-bit binary subexpressions is
2n−1 − 1 [6]. The number of adders needed to implement the
coefficient multipliers using the binary representation-based
BCSE is considerably less than the CSD-based CSE methods
[6]. The proposed FIR filter architecture is based on transposed
direct form as shown in Fig. 1. In the transposed direct form,
the coefficient multipliers (shown as dotted outline in Fig. 1)
share the same input and hence commonly known as multiplier
block (MB). The MB reduces the complexity of the FIR
filter implementations, by exploiting the redundancy in MCM.
Thus, redundant computations (partial product additions in the
multiplier) are eliminated using BCSE. The BCSE method in
277
Fig. 2. Architecture of the proposed method.
[6] was formulated as a low complexity solution to realize
application specific filters where the coefficients are fixed.
In the case of channel filters for SDR receivers, the coeffi-
cients need to be changed as the filter specification changes
with the communication standard. Therefore, reconfigurability
is a necessary requirement for SDR channel filters. In the
next section, we propose two architectures that incorporate
reconfigurability into the BCSE-based low complexity filter
architecture. Although we use BCSE to illustrate proposed
reconfigurable filter architectures in this paper, it must be
noted that the proposed architectures can be used for any CSE
method with appropriate modifications.
III. Proposed Filter Architectures
In this section, the architecture of the proposed FIR filter is
presented. Our architecture is based on the transposed direct
form FIR filter structure as shown in Fig. 1. The dotted portion
in Fig. 1 represents the MB. In Fig. 1, PE-i represents the
processing element corresponding to the ith coefficient. PE
performs the coefficient multiplication operation with the help
of a shift and add unit which will be explained in the latter
part of this section. The architecture of PE is different for
proposed CSM and PSM. In the CSM, the filter coefficients
are partitioned into fixed groups and hence the PE architecture
involves constant shifters. But in the PSM, the PE consists of
programmable shifters (PS). The FIR filter architecture can
be realized in a serial way in which the same PE is used for
generation of all partial products by convolving the coefficients
with the input signal (h ∗ x[n]) or in a parallel way, where
parallel PE architectures are employed. The first option is used
when power consumption and area are of prime concern. The
basic architecture of the PE (dotted portion) is shown in Fig. 2.
The functions of different blocks of the PE are explained
below.
1) Shift and Add Unit: It is well known that one of the
efficient ways to reduce the complexity of multiplication
operation is to realize it using shift and add operations.
In contrast to conventional shift and add units used in
previously proposed reconfigurable filter architectures,
we use the BCSs-based shift and add unit in our pro-
posed CSM and PSM architectures. The architecture of
278 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 2, FEBRUARY 2010
Fig. 3. Architecture of shift and add unit.
shift and add unit is shown in Fig. 3. The shift and add
unit is used to realize all the 3-bit BCSs of the input
signal ranging from [0 0 0] to [1 1 1]. In Fig. 3, “x>>k”
represents the input x shifted right by k units. All the
3-bit BCSs [0 1 1], [1 0 1], [1 1 0], and [1 1 1] of a 3-bit
number are generated using only three adders, whereas
a conventional shift and add unit would require five
adders. Since the shifts to obtain the BCSs are known
beforehand, PS are not required. All these eight BCSs
(including [000]) are then fed to the multiplexer unit.
In both the architectures (CSM and PSM) proposed in
this paper, we use the same shift and add unit. Thus,
the use of 3-bit BCSs reduces the number of adders
needed to implement the shift and add unit compared to
conventional shift and add units.
2) Multiplexer Unit: The multiplexer units are used to
select the appropriate output from the shift and add
unit. All the multiplexers will share the outputs of
the shift and add unit. The inputs to the multiplexers
are the 8/4 inputs from the shift and add unit and
hence 8:1/4:1 multiplexer units are employed in the
architecture. The select signals of the multiplexers are
the filter coefficients which are previously stored in a
look up table (LUT). The CSM and PSM architectures
basically differ in the way filter coefficients are stored in
the LUT. In the CSM, the coefficients are directly stored
in LUTs without any modification whereas in PSM, the
coefficients are stored in a coded format. The number of
multiplexers will also be different for PSM and CSM. In
CSM, the number of multiplexers will be dependent on
the number of groups after the partitioning of the filter
coefficient into fixed groups. The number of multiplexers
in the PSM is dependent on the number of non-zero
operands in the coefficient for the worst case after the
application of BCSE algorithm.
3) Final Shifter Unit: The final shifter unit will perform
the shifting operation after all the intermediate additions
(i.e., intra-coefficient additions) are done. This can be
illustrated using the output expression
y = 2−4 x + 2−6 x + 2−15 x + 2−16 x.
By coefficient-partitioning [16], we obtain
y = 2−4 (x + 2−2 x) + 2−15 (x + 2−1 x).
After obtaining the intermediate sums (x + 2−2 x) and
(x + 2−1 x) from the shift and add units with the help of
multiplexer unit, the final shifter unit will perform the
shift operations 2−4 and 2−15 in (2). The PSM and CSM
architectures also differ in the nature of final shifters. In
the CSM, the final shifts are constants and hence no PS
are required. In the PSM, we have used PS.
4) Final Adder Unit: This unit will compute the sum of all
the intermediate additions 2−4 (x + 2−2 x) and 2−15 (x +
2−1 x) as in (2). As the filter specifications of different
communication standards are different, the coefficients
change with the standards. In conventional reconfig-
urable filters, the new coefficient set corresponding to the
filter specification of the new communication standard
is loaded in the LUT. Subsequently, the shift and add
unit performs a bitwise addition after appropriate shifts.
On the contrary, the proposed CSM and PSM architec-
tures perform a binary common subexpression (BCS)-
wise addition (instead bitwise addition). Thus, the same
hardware architecture can be used for different filter
specifications to achieve the necessary reconfigurability.
Moreover, the proposed BCS-based shift and add unit
reduces addition operations and hence offers hardware
complexity reduction. In the next section, the CSM is
explained in a detailed manner.
A. Architecture of CSM
In the CSM architecture, the coefficients are stored directly
in the LUT. These coefficients are partitioned into groups of
3-bits and are used as the select signal for the multiplexers.
The number of multiplexer units required is n/3, where n is
the wordlength of the filter coefficients. The CSM can be ex-
plained with the help of an 8-bit coefficient h = “0.11111111.”
This coefficient h is the worst-case 8-bit coefficient since all
the bits are nonzero and hence needs a maximum number of
additions and shifts. In this case, n = 8, and therefore the
number of multiplexers required is 3. The output y = h ∗ x is
expressed as
y = 2−1 x + 2−2 x + 2−3 x + 2−4 x + 2−5 x + 2−6 x + 2−7 x + 2−8 x. (3)
By partitioning into groups of three bits from most signifi-
cant bit (MSB) (3), we obtain
h = 2−1 (x+2−1 x+2−2 x+2−3 x+2−4 x+2−5 x+2−6 x+2−7 x) (4)
h = 2−1 (x + 2−1 x + 2−2 x + 2−3 (x + 2−1 x + 2−2 x) + 2−6 (x + 2−1 x)).
(5)
Note that the terms x + 2−1 x + 2−2 x and x + 2−1 x can
be obtained from the shift and add unit. Then by using
the three multiplexers (mux), two 8:1 mux for the first two
3-bit groups and one 4:1 mux for the last two bits of the filter
coefficients, the intermediate sums shown inside the brackets
(1) of (5) can be obtained. The final shifter unit will perform
the shift operations 2−1 , 2−3 , and 2−6 . Since these shifts are
always constant irrespective of the coefficients, programmable
(2) shifters are not required and these shifts can be hardwired. The
MAHESH AND VINOD: NEW RECONFIGURABLE ARCHITECTURES FOR IMPLEMENTING FIR FILTERS WITH LOW COMPLEXITY
Fig. 4. Architecture of PE for CSM.
final adder unit will compute the sum of all the intermediate
sums to obtain h ∗ x[n].
The architecture of PE for CSM is shown in Fig. 4. The
coefficient wordlength is considered as 16 bits. The filter
coefficients are stored in the LUT in sign-magnitude form with
the MSB reserved for the sign bit. The first bit after the sign
bit is used to represent the integer part of the coefficient and
the remaining 16 bits are used to represent the fractional part
of the coefficient. Thus, each 16-bit coefficient is stored as
an 18-bit value in LUTs. Each row in LUT corresponds to
one coefficient. Note that only half the number of coefficients
need to be stored as FIR filter coefficients are symmetric. The
coefficient values corresponding to 20 to 2−14 are partitioned
into groups of three bits and are used as select signals to
multiplexers Mux1 to Mux5. i.e., the set (20 , 2−1 , 2−2 ) forms
the select signal to Mux1 and so on. Since there are 3-bits,
eight combinations are possible and hence Mux1 to Mux5 are
8:1 multiplexers. The value corresponding to 2−15 forms the
select to a 2:1 multiplexer, Mux6. The output from the ith
multiplexer is denoted as ri . Note that even though we are
taking coefficient with values up to a precision of 16 bits,
the shifting of 2−1 is done finally as shown in (4) and (5)
and hence the maximum shift will be 2−15 . Mux7 determines
whether the output needs to be complemented based on the
sign bit of the filter coefficient and hence it is a 2:1 multiplexer.
In FIR filters, coefficient values are always less than one. [In
our design examples, we used the Parks–McClellan algorithm
to design filters (using “firpm” command in MATLAB)].
Hence, we have not employed the integer bit. However if
an integer digit is required, the proposed architectures do not
impose any restrictions to accommodate it.
In Fig. 4, the shifts are obtained as follows. Let r1 to r6
denotes the outputs of Mux1 to Mux6, respectively. Then
y = 2−1 r1 + 2−4 r2 + 2−7 r3 + 2−10 r4 + 2−13 r5 + 2−16 r6 . (6)
279
The shifts are obtained by partitioning the 16-bit coefficient
into groups of 3-bits.
By partitioning (6)
y = 2−1 [(r1 + 2−3 r2 ) + 2−6 [(r3 + 2−3 r4 ) + 2−6 (r5 + 2−3 r6 )]]. (7)
Substituting (r1 + 2−3 r2 ), (r3 + 2−3 r4 ), and (r5 + 2−3 r6 ) by r7 ,
r8 , and r9 , respectively, we get
y = 2−1 [r7 + 2−6 (r8 + 2−6 r9 )]. (8)
By substituting (r8 + 2−6 r9 ) by r10
y = 2−1 (r7 + 2−6 r10 ). (9)
By substituting (r7 + 2−6 r10 ) by r11
y = 2−1 (r11 ). (10)
The expressions from (6)–(10) are represented in Fig. 4. The
main advantage of the CSM architecture is that all the shifts
are constants irrespective of the coefficients and hence can be
hardwired resulting in high speed operation of the filter.
We have employed the shift and add unit which can generate
all the 3-bit BCSs using only three adders. The impact of
using higher order BCSs (4-bit, 5-bit BCSs, etc.) has also
been investigated. The choice of the best shift and add unit
will depend on the complexities of: 1) shift and add unit;
2) multiplexer unit; and 3) final adder unit. The number of
adders needed to implement n-bit CSs is 2n−1 − 1 [6]. Thus,
shift and add units capable of generating 4-bit, 5-bit, and 6-bit
BCSs would require 7, 15, and 31 adders, respectively. The
LD is two adder-steps for both the 3-bit and the 4-bit BCSs-
based shift and add units, and hence they have the same speed.
The LD of 5-bit and 6-bit BCSs-based shift and add units are
same, i.e., three adder-steps, which is one adder-step more
than that of the 3-bit and 4-bit BCSs. Thus, the 3-bit BCSs-
based shift and add unit results in fewer number of adders
than the 4-bit BCSs-based shift and adder unit (reduction of
four adders) with the same LD. The requirement of additional
four adders would increase the complexity of the 4-bit BCSs-
based shift and add unit. Note that the cost of shift and
add unit is independent of the number of coefficients (filter
length) as the same shift and add unit is shared by all the
coefficients. In the proposed CSM architecture, W/3 number
of 8:1 multiplexers (W/3 8:1 multiplexers and remaining
2:1 or 4:1 multiplexers in some cases) of bit-width (x + 2)
are required, where W is the coefficient wordlength and x is
the input data wordlength. For example, if W = 16 (16-bit
coefficient), the proposed 3-bit BCSs-based approach requires
five 8:1 multiplexers and one 2:1 multiplexer. On the other
hand, if 4-bit BCSs were used instead of 3-bit BCSs, four
16:1 multiplexers are required. Assuming an 8:1 multiplexer
is equivalent to four 2:1 multiplexers and a 16:1 multiplexer
is equivalent to eight 2:1 multiplexers, then the 3-bit BCSs-
based PE requires 21 2:1 multiplexers and 4-bit BCSs-based
PE requires thirty two 2:1 multiplexers, respectively. Thus,
the multiplexer complexity would increase when 4-bit BCSs
are used. To be more precise, for each PE with 16-bit filter
coefficients, the multiplexer complexity of 4-bit BCSs-based
280 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 2, FEBRUARY 2010
PE is increased by eleven 2:1 multiplexers when compared to
3-bit BCSs based shift and add unit. But it can be noted that
the total number of adders required for 3-bit BCS-based filter
with n coefficients is 3 + 5n (three adders for shift and add
unit and five adders for each PE) and that for 4-bit BCS-based
PE is 7 + 3n (seven adders for shift and unit and three adders
for each PE). Hence, two adders are saved for 4-bit BCSs-
based filter for each PE. From the above discussion, it can be
concluded that if 4-bit BCSs were used instead of 3-bit BCSs,
the complexity of shift and add unit and multiplexer unit of
PE would have increased, whereas complexity of final adder
unit would decrease.
To provide a quantitative comparison, let us consider a
16-bit (W = 16) coefficient with an 8-bit quantized (x = 8)
input signal. The proposed 3-bit BCSs-based CSM architecture
requires twenty one 2:1 multiplexers of wordlength x + 2 =
10 bits and 4-bit BCSs-based CSM architecture requires thirty
two 2:1 multiplexers of wordlength x + 3 = 11 bits. For a
1-bit 2:1 multiplexer, we need eight 2-input NAND gates [36].
This means the 3-bit BCSs-based CSM architecture requires
21 × 8 × 10 = 1680 NAND gates whereas the 4-bit BCSs-
based CSM architecture requires 32 × 8 × 11 = 2816 NAND
gates. The 3-bit BCSs-based shift and add unit requires three
adders with adder-length [number of full adders (FAs)] of 10-
bits each. Thus, roughly 3-bit BCSs-based shift and add unit
requires 30 FAs (assuming ripple carry addition). For each
FA, we require fifteen 2-input NAND gates [36]. Thus, the
3-bit BCSs-based shift and add unit requires 30 × 15 = 450
NAND gates. Similarly the 4-bit BCSs-based shift and add unit
requires approximately seven adders of adder-length 7 × 11 =
77 FAs. Thus, the 4-bit BCSs-based shift and add unit requires
77 × 15 = 1155 NAND gates. For the final adder unit, the
proposed 3-bit BCSs-based PE requires five adders (as shown
in Fig. 4.) Adders A1 to A3 require 13 FAs {10 (output word-
length of shift and add unit) + 3 (shift-length)}, A4 requires
13 + 6 = 19 FAs and A5 requires 19 + 6 = 25 FAs. Thus,
a total of 83 FAs are required. This means the 3-bit BCSs-
based PE requires 83 × 15 = 1245 NAND gates. Similarly
the 4-bit BCSs-based PE requires three adders. These three
adders will require 15 + 15 + 15 + 8 = 53 FAs. Thus,
the 4-bit BCSs-based PE requires 53 × 15 = 795 NAND
gates. Now considering the total complexity of PE (Note
that complexity of PE is directly proportional to the number
of filter coefficients and total complexity = complexity of
multiplexers + complexity of final adder unit), the 3-bit BCSs-
based PE requires 2925 NAND gates. The 4-bit BCSs-based
PE requires 3611 NAND gates. Thus, for a filter with n taps,
the 3-bit BCSs-based CSM architecture requires (450+2925n)
NAND gates whereas the 4-bit BCSs-based CSM architecture
requires (1155 + 3611n) NAND gates. Thus, it is very evident
that the 3-bit BCSs-based shift and add unit results in low
complexity implementation when compared to the 4-bit BCSs-
based implementation. Nevertheless, it must be noted that the
CSM architecture can be easily modified to incorporate 4-bit
or 5-bit shift and add unit based CSM architectures, if there
is such a requirement.
In the CSM approach, the coefficients are directly stored
in the LUT and hence complete redundancy in coefficient
multiplication is not avoided. Also in case of the outputs of any
of the multiplexers becoming zero, the adder corresponding
to that mux will be used, which is not required if the output
is zero. But it can be seen that the adders at the output of
the multiplexers can be combined in many ways and hence
the best power solution saving can be utilized. Also carry
save adders can be employed if much faster operation is
required. The drawbacks in CSM are resolved by employing
the BCSE algorithm proposed by us in [6]. This forms the
PSM architecture which is explained in the next section.
B. Architecture of PSM
The PSM is based on the BCSE algorithm presented in
our previous work [6]. The PSM architecture presented in this
section incorporates reconfigurability into BCSE. The PSM
has a pre-analysis part in which the filter coefficients are
analyzed using the BCSE algorithm in [6]. Thus, the redundant
computations (additions) are eliminated using the BCSs and
the resulting coefficients in a coded format are stored in
the LUT. The coding format is explained in the latter part
of this section. The shift and add unit is identical for both
PSM and CSM. The number of multiplexer units required can
be obtained from the filter coefficients after the application
of BCSE [6]. The number of multiplexers is selected after
considering the number of non-zero operands (BCSs and
unpaired bits) in each of the coefficients after the application
of the BCSE algorithm. The number of multiplexers will be
corresponding to the number of non-zero operands for the
worst-case coefficient (worst-case coefficient being defined
as coefficient that has the maximum number of non-zero
operands).
The architecture of PE for PSM is shown in Fig. 5. The
coefficient wordlength is fixed as 16 bits. We have done the
statistical analysis for various filters with coefficient precision
of 16 bits and different filter lengths (20, 50, 80, 120, 200,
400, and 800 taps) and it was found that the maximum
number of non-zero operands is 5 for any coefficient. The
analysis was done for filters with different passband (ωp ) and
stopband (ωs ) frequency specifications given by 1) ωp = 0.1π,
ωs = 0.12π; 2) ωp = 0.15π, ωs = 0.25π; 3) ωp = 0.2π,
ωs = 0.22π; and 4) ωp = 0.2π, ωs = 0.3π, respectively.
Based on our statistical analysis, we have fixed the num-
ber of multiplexers as 5 (same as the number of non-zero
operands). The LUT consists of two rows of 18 bits for
each coefficient of the form SDDDDXXDDDDXXMMMML
and DDDDXXDDDDXXDDDDXX, where “S” represents the
sign bit, “DDDD” represents the shift values from 20 to 2−15
and “XX” represents the input “x” or the BCSs obtained
from the shift and add unit. In the coded format, XX =
“01” represents “x,” “10” represents x + 2−1 x, “11” represents
x + 2−2 x, and “00” represents x + 2−1 x + 2−2 x, respectively.
Thus, the two rows can store up to five operands which is
the worst case number of operands for a 16-bit coefficient. In
most of the practical coefficients, the number of operands is
less than the worst case number of operands, 5. In that case
“MMMML” can be used to avoid unnecessary additions. The
values “MMMM” will be given as select signal to the Mux6
and “L” to Mux8. “MMMML” indicates the presence of five
MAHESH AND VINOD: NEW RECONFIGURABLE ARCHITECTURES FOR IMPLEMENTING FIR FILTERS WITH LOW COMPLEXITY
Fig. 5. Architecture of PE for PSM.
operands. A “1” in each position indicates the presence of
each operand. Thus, for all operands to be present will be
indicated by “MMMML” = “11111.” This means the Mux6
will select the output from the output of adder, A4 and Mux8
will select the output of adder, A2 . If only first operand is
present, “MMMML” = “10 000.” This means the Mux8 will
select the output of PS, shr 4 and Mux6 will select the output
of PS, shr1 . As a result of this none of the adders shr1 to shr4
will be loaded saving significant amount of dynamic power.
The coding can be explained as given below. Consider the
positive coefficient h
h = [1010011001010011]. (11)
By using the BCSE [6], substituting 2 = [1 1], 3 = [1 0 1],
(11) becomes
h = [3000020003000020]. (12)
Then (12) will be stored in the LUT as
000001101011011110 and 100111111010000000. It must
be noted that as (12) has only four operands, the fifth
operand values “DDDDXX” are substituted as 000000 and
“MMMML” as “11110.” The XX values are given as select
signals for Mux1 to Mux5. The values of DDDD are fed
to corresponding PS. The multiplexer Mux6 and Mux8 will
select the appropriate output in case the number of operands
after BCSE is less than 5. The use of Mux6 and Mux8
reduces the number of adders utilized by selecting the output
from the appropriate adder as all the adders in the PE are not
always needed. For example, in (12), as only four operands
occur, output can be taken from the output of PS, shr4 without
281
using adder, shr 2 . Mux8 will do this and hence the adder
shr2 is not loaded and consumes zero current and power. The
select signals of Mux6 and Mux8 have five bits and hence
25 different control signals are possible which adds lots of
flexibility to the architecture which can be employed in future
if required. Mux7 is used to complement the output in case
of a negative coefficient and its select signal is the sign bit
“S” of the coefficient.
The PSM architecture has two advantages; first, it guaran-
tees a reduced number of additions compared to CSM, and
second it offers the flexibility of changing the wordlength
of coefficients. The same PSM architecture designed for
16-bit coefficients is capable of operating for any coefficient
wordlength less than 16 bits. This means, if the wordlength is
reduced, the format of the LUT can be changed if required.
The main advantage of reducing the precision is that some of
the adders in the PSM architecture will be unloaded resulting
in zero dynamic power. To the best of our knowledge, the
PSM architecture is the first approach toward programmable
coefficient wordlength FIR filter architecture. This means that
the coefficient wordlength of the proposed PSM architecture
can be changed dynamically without any change in hardware.
C. Comparison Between CSM and PSM
The idea of CSM is to split the filter coefficients into
groups of three bits and use these groups as selectors to
multiplexer unit and obtain the product h ∗ x[n]. This doesn’t
guarantee the minimum number of additions to be performed.
In PSM, since the BCSE algorithm is employed, the number
of additions to be performed will always be reduced compared
to CSM. This can be illustrated as follows. Consider the
coefficient h = [010100001010]. If CSM is employed, always
four multiplexers are needed and this means the shift and
add unit in Fig. 3 needs to be used four times. Thus, always
three additions are required for CSM. But if PSM is used,
first we apply BCSE, then h1 = [020000002000]. The output
computation requires only two additions, one for h1 and one
for obtaining 2 = [101]. This reduction is significant for
higher order filters. The filters used in SDR channelizers must
have a large number of taps to meet the stringent adjacent
channel attenuation specifications. Therefore, the proposed
PSM architecture is best suited for the channel filters in SDRs.
In the case of PSM, the final shifting is done based on the
values from LUT using programmable shifters whereas in the
case of CSM, the shifts are constants as we are always splitting
or partitioning the filter coefficients into groups of 3-bits. Thus,
the CSM architecture results in faster coefficient multiplication
operation at the cost of few extra adders compared to PSM
architecture whereas the PSM architecture results in fewer
number of additions and thus less area and power consumption
compared to the CSM architecture.
Another advantage of PSM is that it is independent of the
wordlength of the filter coefficients. For PSM architecture,
the number of multiplexers is fixed based on the number of
BCSs present in a given coefficient set (worst case-coefficient
of the set). Thus, even if the wordlength changes, it hardly
affects the architecture of PSM. In [11], it was pointed out
that for many filter taps, the highest coefficient precision is
282 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 2, FEBRUARY 2010
not required. Valuable hardware resources will be wasted if all
taps are implemented with the highest precision. The proposed
PSM can be implemented for dynamically varying coefficient
precision as it is wordlength independent. One of the limita-
tions of the PSM architecture is that it requires pre-analysis
of filter coefficients and hence on-the-fly reconfigurability
is not always feasible. But this restriction does not impose
constraints on popular reconfigurable filter applications like
wireless communications. This is because in such applications,
we have a distinct filter for each communication standard and
the coefficients of the filter are fixed for a specific standard.
In other words, when the communication system is operating
on a particular wireless standard, the filter coefficients do
not change, i.e., the filter is not required to be an adaptive
filter. When the system changes its mode of operation to a
different wireless communication standard (as in the case of
a multi-standard transceiver), the coefficient set corresponding
to the specification of the new standard is loaded (replacing
the current filter coefficients). Note that the coefficients of the
new standard are known beforehand (pre-stored) and therefore
the pre-analysis can be done offline and the problem with
reconfigurability can be solved.
In this paper, we have employed tree-structured adder for
the final adder unit in both CSM and PSM architectures.
But it is possible to further optimize the CSM architecture
by employing techniques such as compression techniques
[36]. 3:2 or 4:2 compressors can be employed for carry free
addition making the entire final adder unit more power efficient
with improved speed of operation. But the use of addition
structures other than tree-structured adder would impair the
flexibility of PSM architecture. For example, the multiplexer
Mux6 in our PSM architecture (Fig. 6), which is employed to
load/unload the adders, plays a significant role in achieving
low power consumption and dynamic wordlength capabilities.
If compression techniques were to be employed, the final adder
unit should be made free of multiplexers including Mux 6,
which will in turn impair above merits of PSM approach.
IV. Extension of CSM and PSM
to High Level Synthesis
In this section, we present an extension of proposed
reconfigurable architectures to high level synthesis. CSE
techniques have been used in the literature as a powerful
transformation for eliminating hardware redundancies to
reduce power consumption and area [6], [27], [35]. However
there is hardly any work that addressed the problem of
designing reconfigurable architectures using CSE techniques.
In [14], the concept of ReMB was introduced, which utilized
GD algorithms for eliminating coefficient redundancies and
thus reducing the number of additions for the ReMB. However
the approach in [14] can be considered suitable only for static
reconfigurable systems, where either the filter coefficients
are known beforehand or the filters need to switch between
coefficient sets which are already available. Also the approach
in [14] reduces the redundancies in multiplications by pushing
multiplexers deep into the ReMB design, thus increasing
the number of multiplexers. In other words, the reduction
in complexity achieved by the approach in [14] is directly
proportional to the number of multiplexers. But it is shown in
[29] that the delay imposed by multiplexers in reconfigurable
designs can heavily degrade the performance of the system,
which will have adverse effects on the architecture in [14]. In
this paper, we have used our BCSE algorithm [6] to reduce
the redundancies in multiplications in the reconfigurable filter
architecture. To the best of our knowledge, this is the first
approach that employs the CSE technique to achieve high-
level synthesis goals for reconfigurable systems. The proposed
CSM and PSM methods make use of architectures with fixed
number of multiplexers and the reduction in complexity is
achieved by applying the BCSE algorithm proposed in [6].
Also, the shift and add unit, which significantly reduces the
number of adders compared to direct implementation, has no
multiplexers in contrary to the approach in [14].
The high level synthesis literature has an extensive coverage
of employing partitioning techniques to integrate low power
realization within the scheduling process [29]–[32]. These
methods generally use some scheduling techniques or path
analysis to identify regions that can be combined to partitions.
Each partition will have an activation/deactivation mechanism,
which can be controlled. The basic idea is that the partition can
be switched off when it is not used and consequently power
can be saved. The methods in [29]–[32] have not exploited
hardware level redundancy in operations which can result in
better performances of the system. In [33], an algorithm based
on graphs was devised which reuses the hardware resulting in
less power consumption. But reusing of hardware results in
increased number of multiplexer logic being created which
degrades the system performance as discussed in [29]. The
partitioning of coefficients into 3-bit groups in our proposed
CSM is a high level synthesis transformation targeted to reduce
power consumption. In CSM architecture, the partitioned bit
groups of coefficients are given as select signals to multiplex-
ers. These multiplexers will load and unload different parts
of the circuit and thus save significant amount of power as
discussed in Section III-B. In CMOS technology, there are
three sources of power dissipation arising from switching
(dynamic) currents, short circuit currents, and leakage currents.
Among these parameters, the switching component, which is a
function of the effective capacitance, plays the most significant
role [28]. It is possible to reduce the power by employing
transformations such as reductions in LD, number of opera-
tions, and average transition activity. In [28], it was shown
that a binary tree-structured adder always ensures lowest LD
and consequently the least number of transitions. Our CSM
and PSM architectures also employ the binary tree-structured
approach so as to achieve low LD. It must be noted that as the
coefficients are synthesized sequentially in GD algorithms, the
resulting filter structures do not have a binary tree structure
and hence will always result in an increased LD. Hence, the
reconfigurable approaches in [14] and [15] which employ
GD algorithms will result in increased power consumption
when applied to high-level synthesis. In addition to reducing
the LD in our CSM and PSM architectures, the number
of operations is also reduced by employing the BCSE [6].
Furthermore, the proposed PSM architecture can make use
MAHESH AND VINOD: NEW RECONFIGURABLE ARCHITECTURES FOR IMPLEMENTING FIR FILTERS WITH LOW COMPLEXITY
Fig. 6. Implementation of the proposed CSM and PSM architecture on Virtex 2v3000ff1152-4 FPGA.
TABLE I
Synthesis Results for an FIR Filter with 20 Taps and
Coefficient Wordlength of 16 Bits
Proposed PSM Proposed CSM
Gate count 22 581 22 956
Sampling frequency (MHz) 24 26
Data arrival time (ns) 33.64 26.824
of dynamic change of coefficient wordlength which will
save significant amount of dynamic power as explained in
Section III-B. Thus, the proposed CSM and PSM approaches
improve the efficiency of reconfigurable systems in high-level
synthesis and offers a power efficient solution by reducing the
LD as well as the number of operations (additions).
V. Experimental Results
In this section, the synthesis and design results of the
proposed CSM and PSM architectures are presented and
compared with the recently proposed reconfigurable FIR filter
architectures in the literature [11], [12], [14], [15], [20], [21].
A. Synthesis Results
We have used Xilinx 8.1i ISE for synthesizing purposes. The
synthesis has been done on Xilinx’s Virtex-II 2v3000ff1152-4
FPGA. Table I shows the synthesis results of the CSM and
PSM 20-tap FIR filter that has a coefficient wordlength of 16
bits. We have done the implementation of filters with different
passband edge (ωp ) and stopband edge (ωs ) specifications
283
TABLE II
Synthesis Results for MB (PSM) with Different
Coefficient Wordlengths
Wordlength 8-bit 12-bit 16-bit
Gate count 2878 3532 3771
Sampling frequency (MHz) 35 30 24
Data arrival time (ns) 7.96 8.84 9.92
given by: 1) ωp = 0.1π, ωs = 0.12π; 2) ωp = 0.15π, ωs = 0.2π;
3) ωp = 0.2π, ωs = 0.22π; and 4) ωp = 0.2π, ωs = 0.3π,
respectively. Even though the proposed architectures are re-
configurable, the usage of adders and shifters is dependent on
the filter coefficient values. Some of the adders may not be
used by the multiplexers. As a result of this, they are unloaded
and do not consume any dynamic power. Hence, the power
and speed values of the synthesis results are dependent on the
filter coefficients and hence we have considered an average of
the synthesis results in all the tables in this paper. From the
comparison it is very evident that the CSM requires 475 gates
more than that of PSM, whereas PSM requires 6.82 ns more
for the data to arrive at the output compared to CSM. Thus,
the CSM results in higher speed whereas the PSM results in
lower area. The reason for lower speed of PSM is due to
the presence of programmable shifters and that of less area
is due to elimination of redundant additions by using BCSE
algorithm. We have also analyzed the effect of the MB for
different filter coefficient wordlengths of 8, 12, and 16 bits for
the PSM architecture. The results are shown in Table II. It can
be noted that as the precision of the coefficient is made high,
284 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 2, FEBRUARY 2010

TABLE III
Synopsys Synthesis Results for 20-Tap FIR Filter Implementation of Section V-B

Binary programmable shifts method Binary constant shifts method CSD-CSM CSD-PSM FIR Filter [15]
(BPSM) (BCSM)
Area (mm2 ) 0.2594 0.275 0.304 0.2796 0.5467
Delay (ns) 8.2 7.67 8.5 9.34 15.6
Dynamic power (mW) 5.98 7.8 10 13.97 16

TABLE IV
Synopsys Synthesis Results for 32-Tap FIR Filter Implementation of Section V-B

BPSM BCSM FIR Filter [11] FIR Filter [14]

Area (mm2 ) 0.245 0.27 1.47 1.394
Delay (ns) 4.2 3.67 5.97 7.17
Power (mW) 4.3 5.2 8.5 6.5

the area consumption is increased and the speed of operation
is reduced. Thus, by choosing the appropriate filter coefficient
wordlength, it is possible to obtain reduced area and power as
well as increased speed for the PSM architecture.
B. CSD Based Reconfigurable FIR Filter Architecture
CSD based CSE algorithms are considered to be one of
the best algorithms that can result in low complexity fixed-
coefficient FIR filter implementations. However to the best
of our knowledge, the implementation of the CSD-CSE based
reconfigurable filter architectures has not been addressed in the
literature. We have implemented a CSD based FIR filter using
the CSM architecture (CSD-CSM) and a CSD-CSE based
FIR filter using the PSM architecture (CSD-PSM). For low
complexity, we have employed the CSE algorithm in [3] on
the coefficients before they are stored in LUT. We have imple-
mented a CSD based shift and add unit to generate common
subexpression (CSs) such as [1 0 1], [1 0 −1], [1 0 0 1]
and [1 0 0 −1] and their negated versions. In the previous
works based on CSE algorithm [3]–[5], it was considered
that common subexpressions (CSs) such as [−1 0 − 1] and
[−1 0 1] can be generated from their respective negated
versions [1 0 1] and [1 0 − 1] without using any extra adder
by configuring the existing adder as a subtractor. But this is
applicable only for fixed coefficient filters. An n-bit adder
circuit would require n additional XOR gates to reconfigure the
adder to subtractor mode. These additional XOR gates would
increase the critical path of the adder circuit (equivalent to
the delay imposed by n half-adders) and impose overheads
for CSD implementation of the FIR filter. Another drawback
of CSD implementation is with the storage of coefficients in
LUT. The CSD value like [1 0 − 1 0 − 1 0 1 0 − 1] can be
stored in an LUT like [01 00 11 00 11 00 01 00 11] with
“00” corresponding to 0, “01” corresponding to 1, and “11”
corresponding to −1. Therefore, for the worst-case scenario,
an 8-bit CSD coefficient requires 16 bits for its representation.
This can be optimized as no adjacent bits in CSD are ones.
But still CSD requires more number of bits than binary. Since
all the bits in binary representation are positive, this problem
will not come. Thus, the additional half-adders required for
implementing the adder/subtractor circuit and the additional
storage space required for CSD will increase the area and
the additional half-adders in the adder/subtractor unit reduces
the speed of operation of the CSD based reconfigurable FIR
filters compared to binary based FIR filter implementations.
This becomes highly significant, as the order of the channel
filters in wireless communication transceivers is very high.
We have done the synthesis using Synopsys tool for all the
FIR filter specifications as mentioned in Section IV-A on
0.18 µm CMOS technology. The synthesis results for a 20-tap
FIR filter with 16-bit coefficient wordlength are summarized
in Table III. The proposed CSM and PSM architectures
which employ binary representation of filter coefficients are
denoted as BCSM and BPSM, respectively. The CSD based
implementations of CSM and PSM are denoted as CSD-CSM
and CSD-PSM, respectively. Table III shows that the CSD-
CSM and CSD-PSM architectures consume more area, power,
and has less speed compared to our binary representation based
BPSM and BCSM architectures. The BCSM architecture has
area reduction of 10% and 1% over CSD-CSM and CSD-PSM
architectures, respectively, and the area reduction for BPSM
architecture over CSD-CSM and CSD-PSM architectures are
15% and 7%, respectively. The improvement in the speed of
operation for the BCSM architecture over the CSD-CSM and
CSD-PSM architectures is 10% and 22%, respectively. The
BPSM architecture offers an improvement in the speed of
operation of 4% and 12% over the CSD-CSM and CSD-PSM
architectures, respectively. The dynamic power reductions for
the BCSM architecture are 22% and 44% over the CSD-CSM
and CSD-PSM architectures, respectively. The BPSM architec-
ture offers the dynamic power reductions of 40% and 57% over
the CSD-CSM and CSD-PSM architectures, respectively. The
BPSM architecture offers area and power reductions of 6%
and 23% over the BCSM architecture, respectively. The BCSM
architecture offers in improvement in the speed of operation
by 7% compared to the BPSM architecture. In Table III, the
proposed architectures are also compared with the MMCM
architecture based FIR filter in [15]. The BCSM architecture
offers an area reduction of 49.7%, power reduction of 51.3%,
and a speed improvement of 50.8% over the MMCM [15]. The
area and power reductions offered by the BPSM architecture
over MMCM [15] are 52.7% and 62.5%, respectively, with
MAHESH AND VINOD: NEW RECONFIGURABLE ARCHITECTURES FOR IMPLEMENTING FIR FILTERS WITH LOW COMPLEXITY
TABLE V
Synopsys Synthesis Results for 18-Tap FIR Filter
Implementation of Section V-B
BPSM BCSM FIR Filter [12]
Area (mm2 ) 0.137 0.14 13.872
Delay (ns) 5.7 5.47 7 Area (mm2 )
an improvement in speed of 47.7%. It must be noted that
the MMCM [15] architecture is limited to maximum filter
length of 40 whereas no such restrictions exist for the proposed
architectures. Table IV shows the comparison of a 32-tap
FIR filter with coefficient wordlength of eight bits using
the BCSM and BPSM architectures and the FIR filter given
in [11] and [14]. It can be seen from Table IV that the
BCSM architecture offers an area reduction of 81% over the
architecture in [11] with a reduction in power consumption of
38.8% and increase in speed of 38.5%. Table IV also shows
that the BPSM results in area reduction of 83.7%, reduction in
power consumption of 45.9% and increase in speed of 29.7%
over the architecture in [11], respectively. Compared to the
architecture in [14], the BCSM offers area reduction of 81%,
power reduction of 20% and speed improvement of 48.8%
whereas the BPSM offers area and power reductions of 82.8%
and 29.2% respectively, and a speed improvement of 41.4%.
Table V shows the comparison of an 18-tap FIR filter with a
coefficient wordlength of ten bits using the BCSM and BPSM
architectures and the FIR filter given in [12]. It can be seen
from Table V that the area of the filter architecture in [12] is
almost 100% more than the BPSM and BCSM architectures.
The reason for the increase in area and delay of [12] is due to
the employment of Booth encoding schemes, Wallace adder
trees, etc.
Thus from the comparisons, it can be concluded that the
proposed BCSM and BPSM architectures are equally suitable
for higher and lower order filters. In the next section, a higher
order channel filter in an SDR receiver using our architectures
is analyzed.
C. Design Results
In this example, the FIR filters employed in the filter
bank channelizer of Digital Advanced Mobile Phone Systems
(D-AMPS) in [17] are considered. The sampling rate chosen
is 34.02 MHz as in [17]. The channel filters extract 30 kHz
D-AMPS channels from the input signal after downsampling
by a factor of 350. The passband and stopband edges are 30
and 30.5 kHz, respectively. The peak passband ripple is chosen
as 0.1 dB. The filter stop-band specifications are chosen as in
the D-AMPS standard [18]. The length of the FIR filter N is
determined using [19]
−10 log10 ∂1 ∂2 − 13
N= +1 (13)
14.6f
where ∂1 and ∂2 are the peak passband and stopband ripples
respectively, and f is the normalized width of the transition
band. We have chosen a stopband ripple of −24 dB and the
transition to be 0.01 so that the optimum filter length is found
to be 350 according to (13). The coefficient wordlength used
285
TABLE VI
Synopsys Synthesis Results for D-AMPS Channel Filter
Implementations
BPSM BCSM CSD CSD
CSM PSM
4.531 4.82 5.82 5.17
Delay (ns) 9.87 9.08 13.5 15.34
Power (mW) 48.3 84 105 114.9
in our implementation is 16 bits. It must be noted that the
proposed architectures do not alter the coefficient values and
therefore the frequency response of the filter implemented
using our architectures is unaffected.
We have done the synthesis of the above channel filter
on 0.18 µm CMOS technology. The synthesis results for
a 350-tap FIR filter with 16-bit coefficient wordlength are
shown in Table VI. From Table VI, it can be seen that
the CSM and PSM architectures give much better result
compared to the CSD-CSM and CSD-PSM architectures. The
BCSM architecture has area reduction of 17% and 6.6% over
CSD-CSM and CSD-PSM architectures respectively and the
area reduction for BPSM architecture over CSD-CSM and
CSD-PSM architectures is 22.8% and 12.2%, respectively.
The improvement in the speed of operation for the BCSM
architecture over the CSD-CSM and CSD-PSM architectures
is 32.8% and 40.8%, respectively. The BPSM architecture
offers an improvement in the speed of operation of 26.9%
and 35.66% over the CSD-CSM and CSD-PSM architectures,
respectively. The dynamic power reductions for the BCSM
architecture are 20% and 24% over the CSD-CSM and CSD-
PSM architectures, respectively. The BPSM architecture offers
the dynamic power reductions of 53.3% and 57.4% over
the CSD-CSM and CSD-PSM architectures, respectively. The
BPSM architecture offers area and power reductions of 6%
and 42% over the BCSM architecture, respectively. The BCSM
architecture offers in improvement in the speed of operation
by 8% compared to the BPSM architecture.
D. Comparison with FIR Filter [11]
In this section, we present a comparison of proposed CSM
and PSM architectures with the reconfigurable architecture
proposed in a recent work [11]. In [11], a low power CSD
based digit reconfigurable FIR filter was proposed. The ar-
chitecture in [11] performs multiplication using direct shift
and add method and hence will result in low speed operation.
If we consider a coefficient of n-bit wordlength, then the
LD (critical path length) for method in [11] is n as it is
digit

based. But for our CSM architecture, the LD is only

− 1)) + 2 . Also for the PSM architecture, the
(log2 (n/3
LD is (log2 b) + 2 , where “b” is the number of non-zero
operands in the worst case coefficient after the application
of BCSE as explained in Section III-B. In both CSM and
PSM, “2” denotes the LD of the 3-bit BCS-based shift and
add unit. Note that “b” is considerably less than “n” in the
PSM as common subexpressions are used. Consequently, the
LD of the PSM is also less. It can be seen that the digit
processing unit (DPU) is used in series to form the processing
286 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 2, FEBRUARY 2010
TABLE VII
Comparison of the Proposed CSM Approach with Approach in [20], [21]
Proposed CSM Approach
Shift and Add Multiplexer Final Adder
Unit Unit Unit
4 input LUTs 2058 3026 2976
Slices 1420 1768 1678
Slice flip-flops 1125 1450 1345
element. Thus for a higher order filter, the number of DPUs
will be significantly large, which would delay the filtering
operation substantially. The proposed architectures employ
CSE techniques and hence a much faster filtering operation for
any filter-length is feasible. Also the method in [11] is CSD
based which has many inherent difficulties, as explained in a
detailed manner in Section V-B. A more detailed comparison
between method in [11] and proposed architectures is also
given in Section V-B.
E. Comparison with FIR Filters [20], [21]
The main difference of the proposed CSM architecture from
the architectures in [20], [21] is the use of the BCSs-based
shift and add unit and hardwiring of shifts. In the architectures
proposed in [20], [21], there are pre-computers which are
used to generate x, 3x, 5x, 7x, 9x, 11x, 13x, and 15x using nine
adders employing a special carry select adder, where x is the
input signal. This is in comparison with only seven adders
required by our 4-bit BCSs-based shift and add unit. Thus, the
CSM architecture offers adder reduction over the architectures
in [20], [21] and is different from the latter ones because
it employs BCSE-based shift and add unit for complexity
reduction. Another major difference is that [20], [21] employ
two programmable shifters named SHIFTER and ISHIFTER
with coefficient values as select values. The shifters were used
to identify the most significant non-zero bit (digit) in each
filter coefficient. These shifters should always be preceded
by 8:1 multiplexers as shown in Fig. 6 of [20] and hence
the multiplexer complexity is also not reduced. These pro-
grammable shifters will reduce the overall speed of operation
of the resulting filters especially for higher order channel
filter applications in wireless communication receivers. In the
proposed CSM architecture, all the shifts are constants and
hence can be hardwired using a constant propagation tool and
hence results in better speed of operation compared to methods
in [20], [21]. This can be clarified using an example. For a
16-bit coefficient, the proposed CSM (3-bit BCSs-based shift
and add unit) architecture requires five 8:1 multiplexers and
one 2:1 multiplexer (equivalent to twenty one 2:1 multiplex-
ers), eight adders (three adders for shift and add unit and five
adders for the final adder unit, i.e., 3 + 5n adders for n-tap
filter). Note that programmable shifters are not requited in
CSM since all shifts are constants which can be hardwired.
On the other hand, the approach in [20], [21] requires four
8:1 multiplexers (main multiplexers) + four 4:1 multiplexers
(for programmable shifters if not implemented using power
consuming barrel shifters) (equivalent to twenty four 2:1
multiplexers), 12 adders (nine adders for precomputers and
[20, 21]
Over-all Shift and Add Multiplexer Final Adder Over-all
Unit Unit Unit
8976 2987 5434 2342 10 875
5023 1976 2345 1245 5800
4198 1597 2467 1056 5170
three adders for final adder unit, i.e., 9 + 3n adders for
n-tap filter) and eight programmable shifters. From the above
example, it is evident that the proposed CSM is less complex
than the methods in [20], [21].
For a quantitative comparison, consider a 16-bit coefficient
with an 8-bit quantized input signal. The proposed CSM ap-
proach and the approach in [20], [21] have been implemented
on Virtex 4XC4VSX35-10ff668 FPGA and the complexities
of the shift and add unit, multiplexer unit, final adder unit and
over-all complexities have been compared. The comparison re-
sults (synthesis results on FPGA) are shown in Table VII. The
over-all complexity (shown in the right-most column under
respective methods in Table VII) is the sum of the complexities
associated with shift and add unit, multiplexer unit, final adder
unit, and that of the LUTs used for storing the coefficients,
and the complexity of the complementer. It should be noted
that the final adder unit in [20], [21] is optimized by using
carry select addition. However, the architecture implemented
for this comparison uses ripple carry adders for a fair and
straightforward comparison. We used ripple carry adders on
account of their low power consumption and simple layout.
From Table VII, it is clear that the complexity of shift and
add unit and the multiplexer unit is more for the approach
in [20], [21] and the complexity of final adder unit is more
for the proposed CSM approach. It is evident from Table VII
that over-all complexity of the proposed CSM approach is less
than that of the approach in [20], [21].
VI. Implementation Results
We have implemented the proposed CSM and PSM architec-
tures for a 20-tap FIR filter with 16-bit coefficient precision
on Xilinx’s Virtex-II 2v3000ff1152-4 FPGA associated with
the dual DSP-FPGA Signalmaster kit provided by Lyrtech
[23]. A model based design using MATLAB Simulink and
Xilinx System generator was employed for the implementation
purpose as shown in Fig. 6 (copied directly from the Simulink
environment). Fig. 6 consists of eight components/blocks
whose details are given below.
1) Multi-Tone Input Signal: A multi-tone input signal was
generated by summing up sine waves of frequencies
300 Hz, 1000 Hz, 2500 Hz, 3500 Hz, and 4200 Hz, each
sampled at 10 MHz. Note that the signal frequencies
and the sampling frequency in this example are only
for illustration purposes. By dynamically changing the
input frequencies using the function in Simulink, we
verified that the CSM and PSM architectures work well
for frequencies of several tens of MHz.
MAHESH AND VINOD: NEW RECONFIGURABLE ARCHITECTURES FOR IMPLEMENTING FIR FILTERS WITH LOW COMPLEXITY
2) Lyrtech Signal Master Controller: Lyrtech signal master
controller consists of three components: 1) the board
configuration for configuring the FPGA/DSP and for
downloading the bitstream to FPGA; 2) Xilinx system
generator for generating the bit stream to be downloaded
to the FPGA; and 3) log viewer which gives implemen-
tation information about the area and delay of the used
architecture. Xilinx XPower can be employed for the
calculation of power dissipation.
3) Coefficient Controller: The CSM and PSM architectures
have been implemented with the provision of dynamic
changing of filter coefficients. This was made possible
with the help of a multiport switch. Based on the
select signal values, the switch will select one of the
inputs, h2 to h6 , which are the coefficients stored in
LUTs, generated using MATLAB program according
to the specifications of the architecture as explained
in Sections III-A and III-B. As shown in Fig. 6, h2
corresponds to a lowpass filter with a cutoff frequency of
500 Hz, h3 corresponds to a lowpass filter with a cutoff
frequency of 1000 Hz, h4 corresponds to a lowpass filter
with a cutoff frequency of 2000 Hz, h5 corresponds to
a lowpass filter with a cutoff frequency of 3000 Hz
and h6 corresponds to a lowpass filter with a cutoff
frequency of 4000 Hz. For example, if the constant value
is 4 (as shown in Fig. 6), the specification h5 will be
chosen which corresponds to a lowpass filter that has a
cutoff frequency of 3000 Hz. Simulink provides option
to change the constant value dynamically. Hence, if we
change the constant value to 1, the coefficient h2 corre-
sponding to a lowpass filter of 500 Hz will be chosen
and the output of the filter changes dynamically. We
used this scheme to achieve dynamic reconfigurability.
We have employed only five filter specifications from h2
to h6 , but it is possible to include filters for additional
specifications.
4) Coefficient Extractor: The coefficient extractor is used
to extract the coefficients individually and to provide the
extracted coefficient to each processing element of the
proposed CSM and PSM architectures.
5) Gateways: Gateways are employed as an interface be-
tween Xilinx’s blocks which are used for developing the
proposed CSM and PSM architectures. Thus, gateways
provide the connection of the bitstream file with input
sources and output sinks of the Simulink environment.
6) Simulation Architecture: This forms the CSM and PSM
architectures developed as shown in Figs. 4 and 5,
respectively, using Xilinx block set in Simulink library.
The simulation architecture is used as a reference for
comparing with the hardware implementation on FPGA
(bit stream running on FPGA).
7) Bitstream Running on FPGA: We have generated the
bitstream of the simulation architecture using the Xilinx
system generator. The generated bitstream can be down-
loaded to FPGA and it appears as a “Lyrtech Cosim
Engine” block. The performances of the bitstream and
the simulation architecture were checked to ensure that
they are identical.
287
TABLE VIII
Implementation Results for Proposed Architectures with
20 Taps and Coefficient Wordlength of 16 Bits
Proposed CSM Proposed PSM
Gate count 27 979 25 679
Data arrival time (ns) 38.672 40.824
Sampling frequency (MHz) 26 24
Power dissipation (mW) 408.29 375.45
8) Fast Fourier transform (FFT) of Outputs: The FFT
block was employed for observing the outputs of the
simulation and FPGA architectures. The FFT block plots
the energy of the output in dB against the frequencies.
The implementation results are shown in Table VIII.
The area and delay results are obtained using log viewer
block in Fig. 6. The power dissipation is obtained using
Xilinx XPower. The results show that the proposed CSM
results in low delay compared to proposed PSM whereas
the latter results in low area and power implementations.
From Table VIII, it can be concluded that the CSM
architecture results in an improvement in speed of 5.3%
over the PSM architecture, whereas the PSM architec-
ture results in area and power reductions of 8.2% and
8% over CSM architecture, respectively.
VII. Conclusion
We have proposed two new approaches namely, CSM and
PSM, for implementing reconfigurable higher order filters
with low complexity. The CSM architecture results in high
speed filters and PSM architecture results in low area and thus
low power filter implementations. The PSM also provides
the flexibility of changing the filter coefficient wordlengths
dynamically. We have implemented the architectures on
Virtex-II 2v3000ff1152-4 FPGA and synthesized using 0.18
µm CMOS technology with a high coefficient precision of
16 bits and compared to numerous reconfigurable FIR filter
architectures. The proposed reconfigurable architectures can
be easily modified to employ any CSE (MCM) method.
Thus, our method is a general approach for low complexity
reconfigurable channel filters.
References
[1] T. Hentschel and G. Fettweis, “Software radio receivers,” in CDMA
Techniques for Third Generation Mobile Systems. Dordrecht, The
Netherlands: Kluwer Academic, 1999, pp. 257–283.
[2] J. Mitola, “Object-oriented approaches to wireless systems engineering,”
in Software Radio Architecture. New York: Wiley, 2000.
[3] R. I. Hartley, “Subexpression sharing in filters using canonic signed digit
multipliers,” IEEE Trans. Circuits Syst. II, vol. 43, no. 10, pp. 677–688,
Oct. 1996.
[4] R. Pasko, P. Schaumont, V. Derudder, S. Vernalde, and D. Durackova,
“A new algorithm for elimination of common subexpressions,” IEEE
Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 18, no. 1,
pp. 58–68, Jan. 1999.
[5] M. M. Peiro, E. I. Boemo, and L. Wanhammar, “Design of high-speed
multiplierless filters using a nonrecursive signed common subexpression
algorithm,” IEEE Trans. Circuits Syst. II, vol. 49, no. 3, pp. 196–203,
Mar. 2002.
[6] R. Mahesh and A. P. Vinod, “A new common subexpression elimination
algorithm for realizing low complexity higher order digital filters,” IEEE
Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 27, no. 2, pp.
217–219, Feb. 2008.
288 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 2, FEBRUARY 2010
[7] A. P. Vinod and E. Lai, “Low power and high-speed implementation of
FIR filters for software defined radio receivers,” IEEE Trans. Wireless
Commun., vol. 5, no. 7, pp. 1669–1675, Jul. 2006.
[8] T. Solla and O. Vainio, “Comparison of programmable FIR filter
architectures for low power,” in Proc. 28th Eur. Solid-State Circuits
Conf., Firenze, Italy, Sep. 2002, pp. 759–762.
[9] T. Solla, R. Mäkelä, M. Liljeroos, and O. Vainio, “Application-specific
filter processor for flexible receivers,” in Proc. 19th NORCHIP Conf.,
Kista, Sweden, Nov. 2001, pp. 53–58.
[10] D. Hwang, C. Mittelsteadt, and I. Verbauwhede, “Low power showdown:
Comparison of five DSP platforms implementing an LPC speech codec,”
in Proc. IEEE Int. Conf. Acoust. Speech Signal Process., Salt Lake City,
UT, May 2001, pp. 1125–1128.
[11] K. H. Chen and T. D. Chiueh, “A low-power digit-based reconfigurable
FIR filter,” IEEE Trans. Circuits Syst. II, vol. 53, no. 8, pp. 617–621,
Aug. 2006.
[12] T. Zhangwen, J. Zhang, and H. Min, “A high-speed, programmable, CSD
coefficient FIR filter,” IEEE Trans. Consumer Electron., vol. 48, no. 4,
pp. 834–837, Nov. 2002.
[13] X. Chenghuan, C. He, Z. Shunan, and W. Hua, “Design and imple-
mentation of a high-speed programmable polyphase FIR filter,” in Proc.
5th Int. Conf. Applicat.-Specific Integr. Circuit, vol. 2. Oct. 2003, pp.
783–787.
[14] S. S. Demirsoy, I. Kale, and A. G. Dempster, “Efficient implementation
of digital filters using novel reconfigurable multiplier blocks,” in Proc.
38th Asilomar Conf. Signals Syst. Comput., vol. 1. Nov. 2004, pp. 461–
464.
[15] P. Tummeltshammer, J. C. Hoe, and M. Puschel, “Multiplexed multiple
constant multiplication,” IEEE Trans. Comput.-Aided Design Integr.
Circuits, vol. 26, no. 9, pp. 1551–1563, Sep. 2007.
[16] A. P. Vinod and E. M.-K. Lai, “An efficient coefficient-partitioning
algorithm for realizing low complexity digital filters,” IEEE Trans.
Comput.-Aided Design Integr. Circuits Syst., vol. 24, no. 12, pp. 1936–
1946, Dec. 2005.
[17] K. C. Zangi and R. D. Koilpillai, “Software radio issues in cellular base
stations,” IEEE J. Select. Areas Commun., vol. 17, no. 4, pp. 561–573,
Apr. 1999.
[18] N. Spencer, “An overview of digital telephony standards,” in Proc. IEE
Colloq. Design Dig. Cellular Handsets, Mar. 1998, pp. 1/1–1/7.
[19] J. G. Proakis and D. G. Manolakis, “Design of digital filters,” in
Digital Signal Processing Principles, Algorithms, and Applications.
Upper Saddle River, NJ: Prentice-Hall, 1998, pp. 614–738.
[20] K. Muhammad and K. Roy, “Reduced computational redundancy imple-
mentation of DSP algorithms using computation sharing vector scaling,”
IEEE Trans. Very Large Scale Integr. Syst., vol. 10, no. 3, pp. 292–300,
Jun. 2002.
[21] J. Park, W. Jeong, H. Mahmoodi-Meimand, Y. Wang, H. Choo, and K.
Roy, “Computation sharing programmable FIR filter for low-power and
high-performance applications,” IEEE J. Solid State Circuits, vol. 39,
no. 2, pp. 348–357, Feb. 2004.
[22] Y. Wang, H. Mahmoodi, L.-Y. Chiou, H. Choo, J. Park, W. Jeong,
and K. Roy, “Hardware architecture and VLSI implementation of a
low-power high-performance polyphase channelizer with applications
to subband adaptive filtering,” in Proc. IEEE Int. Conf. Acoust. Speech
Signal Process., vol. 5. May 2004, pp. 97–100.
[23] http://www.lyrtech.com/index.php?act=view&pv=SignalMaster space
Quad
[24] C. Y. Yao, H. H. Chen, C. J. Chien, and C. T. Hsu, “A novel
common-subexpression-elimination method for synthesizing fixed-point
FIR filters,” IEEE Trans. Circuits Syst. I, vol. 51, no. 11, pp. 2215–2221,
Nov. 2004.
[25] I. C. Park and H. J. Kang, “FIR filter synthesis algorithms for minimizing
the delay and the number of adders,” IEEE Trans. Circuits Syst. II,
vol. 48, no. 8, pp. 770–777, Aug. 2001.
[26] R. A. Walker and D. E. Thomas, “Introduction,” in A Survey of High-
Level Synthesis Systems. Boston, MA: Kluwer, 1991, pp. 20–37.
[27] A. P. Vinod and E. M.-K. Lai, “On the implementation of efficient
channel filters for wideband receivers by optimizing common subexpres-
sion elimination methods,” IEEE Trans. Comput.-Aided Design Integr.
Circuits Syst., vol. 24, no. 2, pp. 295–304, Feb. 2005.
[28] A. Chandrakasan, M. Potkonjak, R. Mehra, J. Rabaey, and R. W.
Brodersen, “Optimizing power using transformations,” IEEE Trans.
Comput.-Aided Design Integr. Circuits Syst., vol. 14, no. 1, pp. 12–31,
Jan. 1995.
[29] M. Meribout and M. Motomura, “A combined approach to high-
level synthesis for dynamically reconfigurable systems,” IEEE Trans.
Comput., vol. 53, no. 12, pp. 1508–1522, Dec. 2004.
[30] X.-J. Zhang, K.-W. Ng, and W. Luk, “A combined approach to high-
level synthesis for dynamically reconfigurable systems,” in Proc. 10th
Int. Workshop Field Programmable Logic Applicat., 2000, pp. 361–370.
[31] R. Kress and A. Pyttel, “High-level synthesis for dynamically re-
configurable hardware/software systems,” in Proc. 8th Int. Workshop
Field-Programmable Logic Applicat. Field-Programmable Gate Arrays
Comput. Paradigm, 1998, pp. 288–297.
[32] A. Rettberg and F.-J. Rammig, “Integration of energy reduction into
high-level synthesis by partitioning,” in Proc. Working Conf. Distributed
Parallel Embedded Syst. (DIPES), Braga, Portugal, Oct. 2006, pp. 225–
234.
[33] N. Moreano, E. Borin, C. de Souza, and G. Araujo, “Efficient data-
path merging for partially reconfigurable architectures,” IEEE Trans.
Comput.-Aided Design Integr. Circuits Syst., vol. 24, no. 7, pp. 969–
980, Jul. 2005.
[34] R. Mahesh and A. P. Vinod, “Reconfigurable low complexity FIR filters
for software radio receivers,” in Proc. 17th IEEE Int. Symp. Personal
Indoor Mobile Radio Commun. (PIMRC), Helsinki, Finland, Sep. 2006,
pp. 1–5.
[35] M. Potkonjak, M. B. Srivastava, and A. P. Chandrakasan, “Multiple
constant multiplications: Efficient and versatile framework and algo-
rithms for exploring common subexpression elimination,” IEEE Trans.
Comput.-Aided Design, vol. 15, no. 2, pp. 151–165, Feb. 1996.
[36] B. Parhami, “Implementation details,” in Computer Arithmetic. New
York: Oxford Press, 2000, p. 131.
[37] Y. Linn, “Efficient loop filter design in FPGAs for phase lock loops in
high-data rate wireless receivers: Theory and case study,” in Proc. 6th
Annu. Wireless Telecommun. Symp., Pomona, CA, Apr. 2007, pp. 1–8.
R. Mahesh (M’06) received the B.Tech. degree in
electrical and electronics engineering from Mahatma
Gandhi University, Kottayam, Kerala, India, in 2003,
and the Ph.D. degree in computer engineering from
Nanyang Technological University, Singapore, in
2009.
He was a Lecturer at the College of Engineer-
ing, Mahatma Gandhi University, from August 2003
to July 2005. Currently, he is a Research Fellow
with the School of Computer Engineering, Nanyang
Technological University. His main research inter-
ests include low complexity and high speed digital signal processing circuits
and computer arithmetic.
A. P. Vinod (SM’01) received the B.Tech. degree
in instrumentation and control engineering from the
University of Calicut, Malappuram, Kerala, India, in
1994, and the M.E. and Ph.D. degrees in computer
engineering from Nanyang Technological University
(NTU), Singapore, in 2000 and 2004, respectively.
From 1993 to 1998, he was an Automation
Engineer with Kirloskar, Bangalore, India, Tata
Honeywell, Pune, India, and Shell Singapore, Sin-
gapore. From September 2000 to September 2002,
he was a Lecturer at the School of Electrical and
Electronic Engineering, Singapore Polytechnic, Singapore. He was a Lecturer
at the School of Computer Engineering, NTU from September 2002 to
November 2004. Since December 2004, he has been an Assistant Professor
with the School of Computer Engineering, NTU. He has published more than
90 papers in refereed journals and international conferences. His research
interests include digital signal processing, low power and reconfigurable
digital signal processing circuits, software radio, cognitive radio, and brain–
computer interface.
Dr. Vinod is an Editor of the International Journal of Advancements in
Computing Technology.