IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO.
6, JUNE 2006
Supply and Threshold-Voltage Trends for
Scaled Logic and SRAM MOSFETs
Eiji Morifuji, Member, IEEE, Takeshi Yoshida, Masahiko Kanda, Satoshi Matsuda, Member, IEEE,
Seiji Yamada, Member, IEEE, and Fumitomo Matsuoka, Member, IEEE
Abstract—The authors show new guidelines for Vdd and thresh-
old voltage (Vth ) scaling for both the logic blocks and the high-
density SRAM cells from low power-dissipation viewpoint. For
the logic operation, they have estimated the power and the speed
for inverter gates with a fan out = 3. They find that the optimum
Vdd is very sensitive to switching activity in addition to the oper-
ation frequency. They propose to integrate two sets of transistors
having different Vdd s on a chip. In portions of the chip with high
frequency or high switching activity, the use of H transistors in
which Vdd and Vth are moderately scaled is helpful. On the other
hand, in low switching activity blocks or relatively low frequency
portions, the use of L transistors in which Vdd should be kept
around 1–1.2 V is advantageous. A combination of H and L is
beneficial to suppress power consumption in the future. They have
investigated the yield of SRAM arrays to study the optimum Vdd
for SRAM operation. In high-density SRAM, low Vth causes yield
loss and an area penalty because of low static noise margin and
high bit leakage especially at high temperature operation. Vth
should be kept around 0.3–0.4 V from an area size viewpoint. The
minimum Vdd for SRAM operation is found to be 0.7 V in this
study. It is also found that the supply voltage for SRAM cannot be
scaled continuously.
Index Terms—CMOSFET logic devices, CMOS memory inte-
grated circuits, logic devices, power consumption, SRAM chips.
I. INTRODUCTION
C MOS-TECHNOLOGY scaling has attempted to maintain
a constant electric field while improving density, opera-
tion speed, and consumption power [1]. This law suggests that
electric field in a device can be kept constant by scaling the
device size and the operation voltage at the same pace. When
the device geometry is shrunk by a factor of k, the delay is also
reduced by the same factor. At the same time, supply voltage
(Vdd ) should be reduced by a factor of k in order to maintain a
constant electric field. This, in turn, will result in a reduction
in dynamic power consumption by a factor of square of k.
The operation frequency for large-scale integrations (LSIs) has
been increasing to satisfy the demand of high-speed systems.
The increase in operation speed causes a higher active power
dissipation. Lowering the supply voltage (Vdd ) has been applied
to decrease the power dissipation because active power is
proportional to the square of Vdd . Recently, technology has
reached the region of Vdd below 1 V and gate length below
Manuscript received October 11, 2005; revised March 6, 2006. The review
of this paper was arranged by Editor V. R. Rao.
The authors are with the System LSI Division, Semiconductor Com-
pany, Toshiba Corporation, Yokohama 235-8522, Japan (e-mail: eiji.morifuji@
toshiba.co.jp).
Digital Object Identifier 10.1109/TED.2006.874752
0018-9383/$20.00 © 2006 IEEE
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1427
40 nm [7]–[9]. However, low Vdd degrades the performance
of circuits, therefore, threshold voltage (Vth ) is also scaled
down to achieve the required performance [2], [4]. International
Roadmap for Semiconductors (ITRS) predicts the Vdd and Vth
trends for future generations [3]. In addition, each generation
results in a 30% shrinkage in the device size. In the roadmap,
the lineup is divided into two cases: the low operation power
(LOP) version and the low standby power (LSTP) version. Vdd
reduction of 0.1 V with every generation is proposed to reduce
the power consumption. In addition, the Vdd for LSTP is set to
be 0.3 V higher than that for LOP in order to set Vth at a higher
value while satisfying the speed requirement. In this paper, we
investigate what is the best scaling scenario for Vdd and Vth in
the region of Vdd below 1 V for logic circuits. In the region of
Vdd below 1 V, Vdd –Vth value becomes smaller if we continue
to reduce the standby power. It causes a drastic degradation of
the speed and a lack of noise margins [4], [10], therefore, this
scenario should be modified. In addition, system LSI requires
high-speed and high-density cache memory SRAM. In a high-
density SRAM, beta ratio, which is defined as the ratio between
the driver MOSFET and the transfer MOSFET, is limited owing
to a stringent small cell-size requirement. To reduce the power
consumption, voltage scaling for SRAM is also beneficial along
with the scaling of the device size. On the other hand, low Vdd
and limited beta ratio cause operation failure and loss of yield
[10], [12], [13]. In this paper, guidelines for Vdd and Vth scaling
in SRAM cells, with such small beta ratio, are proposed keeping
in view the yield of a high-density SRAM cell array.
II. SCALING GUIDELINES FOR Vdd AND Vth
IN L OGIC C IRCUITS
The power consumed in the logic circuits is composed of two
components. First is the switching power, which is consumed
while charging and discharging the capacitances. The second
important power is the standby power caused primarily by the
OFF-current. Total power consumption is given by the following
equation:


2
Power = aNgate CVdd f+ Ioff Vdd . (1)
Ngate
Here, a is the switching activity defined as the probability of
switching during a clock cycle. C is the total capacitance and f
is the operation clock frequency. The power and speed for the
inverters with fan-out = 3 are calculated by changing Vdd and
1428
Fig. 1. Estimated total power consumption for 1 M gates at 105 ◦ C as a
function of delay of the FO3 inverter. A 65-nm CMOS technology having
Lgate = 40 nm and EOT = 1.2 nm is assumed for this estimation. The tran-
sition point where the standby power dominates more than the active power, as
shown by the dotted line, shifts to a slower delay point as the Vdd is scaled.
Vth . Fig. 1 indicates the delay time per inverter versus the total
power consumed by 1 M gates at 105 ◦ C. The implicit variables
in the plot are Vdd and Vth . Delay time is calculated by using
the simple CV /I equation [5]. The device characteristics are
estimated using the device current–voltage (I−V ) equations
obtained from [5]. The mobility model used here is obtained
from [6]. These equations are calibrated with the published
65-nm technology data in [7]. The estimated Tpd using CV /I
shows a good agreement with the actual Tpd provided by [7].
The clock frequency is chosen to be 2 GHz. The switching
activity is 20%. The gate length and the equivalent oxide
thickness (EOT) are set to be 40 and 1.2 nm, respectively.
The standby power is calculated by taking into account the
distribution of Ioff within a chip. The average value of Ioff with
log normal distribution is used in the analysis. Vth variations
caused by fluctuation in process as well as random factors are
considered. As the required speed becomes high, Vth should be
lower in order to achieve the required speed. This causes an
increase in the standby power. At a given voltage, the standby
power increases drastically and dominates the total power in
the high-speed region. The dotted line is the boundary where
the dominant power changes from being mostly active power
to being mostly standby power. The transition point moves
toward slower delay if we decrease the Vdd . This suggests
that a low Vdd operation suffers from high standby power if
the required speed is high as well. The relation between the
active power and the standby power is sensitive to the operation
frequency and the switching activity (a). Fig. 2 depicts the
total power as a function of Vdd for 1 M gates for three
different frequencies: 500 MHz, 2 GHz, and 4 GHz. The curves
corresponding to various switching activities from 1% to 100%
are also shown. The clock generator operates at a = 100%.
On the other hand, the memory array seldom switches and
has a switching activity less than 1%. The typical switching
activity in the logic blocks is around 20%. In the case of a
chip operating at a relatively lower frequency (500 MHz in this
case), lower Vdd looks disadvantageous because the standby
power dominates the total power. In this case, Vdd should be
kept high at around 1.1–1.2 V. On the other hand, for the case
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 6, JUNE 2006
Fig. 2. Calculated results on Vdd dependence of the total power consumed
per 1 M gates to achieve 500 MHz, 2 GHz, and 4 GHz. The logic depth is set
to 20 in this calculation. Vth is tuned to achieve the given frequency at a given
supply voltage.
of 2 GHz, there is an optimum point around 0.9 V in terms
of power consumption. Lower voltage shows merit only in the
case of limited circuit operation at a = 100%. In the circuit
block with low switching activity, Vdd should be kept high
(1.2 V) even for the 2-GHz operation. For 4-GHz operation,
which is two generations ahead of the 2-GHz clock frequency,
it is not necessary to reduce Vdd lower than 0.8 V. It should
be noted that Vdd scaling should be relaxed compared to the
rate of frequency increase from the power consumption point
of view. Because Vdd should be kept high in the block with
lower switching activity, Vdd should be changed in accordance
with the switching activity and the operation frequency within a
chip in order to minimize the power. Different blocks on an LSI
chip can be divided into three categories based on their clock
frequencies and switching activities. The first case is a block
operating at a high frequency with a high switching activity.
In this case, aggressive scaling of Vdd is beneficial. But the
area of this portion on a chip is small. The second case is a
block operating at a high frequency with a moderate switching
activity such as 20%. In this case, excessive Vdd scaling causes
an increase in the standby power, therefore, the scaling of Vdd
should be relaxed more than predicted by the simple scaling.
The third portion is a block with relatively low frequency or
low switching activity. Optimum Vdd for this block is high
at approximately 1.1–1.2 V. Further, the Vdd scaling of these
blocks should stop. We propose two sets of transistors covering
the aforementioned three blocks; namely the H and the L
transistors. The H transistors, having a moderately scaled Vdd ,
are used in the first and second types of blocks. The L transistors
having almost no scaling of Vdd cover the third type of block.
Fig. 3 indicates the newly proposed scaling trend for these two
lineups. In the H version, the supply voltage is scaled gradually
every generation, and the threshold voltage is also lowered. On
the other hand, the supply voltage for the L version is fixed at
1.1–1.2 V. Fig. 4 is a table summarizing the estimated voltage,
MORIFUJI et al.: SUPPLY AND THRESHOLD-VOLTAGE TRENDS FOR SCALED LOGIC AND SRAM MOSFETs
Fig. 3. Proposed guideline and scaling trend for achieving both low power
consumption and high-speed operation. In this scaling, the operation frequency
is assumed to be 1.4 times the previous technology. H and L versions are
provided to meet the system requirement of power and speed.
Fig. 4. One example of scaling trend to meet the continuous requirement in
terms of power and frequency for H and L versions. The frequency is increased
by 1.4 times compared to the previous one. Oxide thickness and gate length are
scaled to meet the speed requirement.
frequency, oxide thickness, threshold voltage, OFF-current, and
gate leakage. The operation frequency is improved by 30%
every generation by reducing the gate length and improving
the drive current. The oxide thickness is scaled to achieve the
required speed. It is difficult to determine the scaling trend at the
32 nm and beyond technology nodes at this moment, however, it
can be concluded that the threshold voltage cannot be scaled at
the same pace, hence, the scaling of the supply voltage should
become slower. It should be noted that the future technology
nodes would need additional techniques to suppress standby
currents such as high-κ dielectrics, double gate structures, etc.
In the low-frequency blocks, a higher Vth than the one given in
this table would be helpful to minimize the power.
A multifunctional LSI system [system on chip (SOC)], in
which the microprocessor, DSP, SRAM, DRAM, and analog
circuits are placed together, is becoming very important. Fig. 5
shows an example of such a system. It is composed of a
large-scale DRAM, SRAM cash, the core block that operates
at high speed, and the logic blocks operating at moderate
speed or activity. In the current 65-nm SOC technology [14],
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1429
Fig. 5. Typical System LSI is shown. The multifunctional system LSI in
which the microprocessor, DSP, SRAM, and DRAM, analog, etc., are placed
together is becoming a major player. Portions in solid circles should use low-
voltage MOSFETs (H) and other portions should use high-voltage MOSFETs
(L) to minimize the total power consumption.
Fig. 6. Total power consumption per 1-M gate calculated in each technology
in H only and in H + L cases is shown by separating the standby-power and
active-power components. The expected power reduction is half of the previous
generation.
a multi-Vdd scheme is used only to separate the voltage of
DRAM, analog, and IO circuit from the core logic, which
operates around 1 V. For mixed signal and IO devices, 1.8-V
MOSFETs are optimized. For IO devices and DRAM cell tran-
sistors, 2.5-V MOSFETs are applied. This multi-Vth scheme
minimizes the total power of the chip while maintaining its
speed. In this type of LSI, a multipower supply for a logic-
transistor portion seems more advantageous from the power
perspective. One possible implementation is that the low-
voltage MOSFETs (H) should be used in the solid circles
and the high-voltage MOSFETs (L) should be used for the
remaining blocks. Fig. 6 shows the merit of the multi-Vdd
(H plus L) scheme. The total power consumption for 1 M gates
is calculated as a function of technology using H only and using
the H + L scheme under assumptions depicted in Fig. 4. In
H-only case, an improvement in the speed and reduction of the
power consumption cannot be realized simultaneously because
of the increase in the standby power. Power is expected to
reduce by a factor of two compared to the previous gener-
ation. This is not achievable because of the increase in the
standby power. On the other hand, when H and L are integrated
1430 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 6, JUNE 2006

Fig. 7. Factors affecting the scaling in SRAM cell are illustrated such as smaller SNMs and high OFF-currents.

together in a chip and multi-supply voltage scheme is applied,

power reduction and speed improvement can be simultaneously
achieved. This demonstrates that a multisupply-voltage system
is indispensable for future generation of chips as it minimizes
the increase in the standby component of power.

III. Vdd AND Vth SCALING FOR SRAM

A static RAM with six transistors, making a flip-flop circuit
with bistable states is widely used. The bistability of the SRAM
cell can be observed using its eye property. In order to hold data,
the static noise margin (SNM), defined by the size of the eye,
should be kept large. The specification of SNM is such that a
reliable eye property is maintained despite the process fluctua-
tions, variations in the operating conditions such as temperature
and voltage, and bit-line noise. Since SNM becomes small with
the reduction of the supply voltage, it becomes weaker against
the threshold-voltage variation. In order to obtain high SNM,
higher threshold voltage and high beta ratio are beneficial, as
shown in Fig. 7. By increasing the beta ratio, the slope becomes
steeper and the eye becomes larger. This increase of beta ratio
results in an area increase. Higher threshold voltage makes the
eye larger, though it must be kept lower than half of Vdd . If
Vth becomes much larger than half of Vdd , the eyes disappear
and SRAM does not work properly. Moreover, in the case of a
memory array (for example, 512 cells connected together on
a single bit line), the OFF-state current and the gate-leakage
current of the transfer gate will appear from each bit in a bit
line despite the word line being off. When the integral value
of this OFF-state current and the gate-leakage current becomes
comparable to the cell current, which is supposed to be turned
on by the word line, the reading operation will fail. Therefore,
both small leakage of the transfer gate and large cell current are
required. A longer gate length for transfer transistor and a wide
width for driver are stable but result in a reduced density.
In this study, a high-density SRAM with a cell size of
0.56 µm2 developed for 65-nm generation system LSIs [11] is
investigated. Symmetry cells have simple straight patterns of
active region and gate to suppress the variation of the critical
dimension. Figs. 8 and 9 indicate the yield of 2-MB SRAM
Fig. 8. Yield of 2-MB SRAM arrays as a function of Vdd and Vth operated
at room temperature. Vth is varied from 0.15 to 0.45 V. Cell sizes such as
0.56 µm2 (beta ratio = 1), 0.598 µm2 (beta ratios = 1.5 and 1.67), and
0.6292 µm2 (beta ratio = 2.17) are investigated.
arrays while varying the Vdd and Vth . The data are shown at
room temperature as well as at a high temperature of 125 ◦ C.
Four types of SRAM having different beta ratios and cell sizes
are investigated. These are 0.56 µm2 (beta ratio: 1), 0.598 µm2
(beta ratios: 1.5 and 1.67), and 0.6292 µm2 (beta ratio: 2.17).
Vth can be tuned by changing the channel doping. The SRAM
yield at low-voltage operation improves by lowering the thresh-
old voltage to between 0.15 and 0.25 V. It should be noted that
a degradation in the yield is found at high-Vdd operation for a
Vth = 0.15 V. In high-Vdd region, the OFF-current of each cell
increases and becomes comparable with the cell current, thus
causing a failure. On the other hand, SRAM with a low beta
ratio significantly degrades yield in low-Vdd operation. From
this, a low Vth is disadvantageous from the cell-size viewpoint.
This is caused by a degradation in SNM through the narrow-
channel effect in the driver and the transfer transistors. For
Vth = 0.35 V case, beta = 1 depicts the best yield. For a higher
Vth case (Vth = 0.45 V), yield degrades because the threshold
voltage is close to half of the supply voltage, and the eye

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MORIFUJI et al.: SUPPLY AND THRESHOLD-VOLTAGE TRENDS FOR SCALED LOGIC AND SRAM MOSFETs
Fig. 9. Yields of 2-MB SRAM arrays as a function of Vdd and Vth operated
at high temperature (125 ◦ C) are shown. Vth is the value at room-temperature
operation.
collapses in low-Vdd operation because of the fluctuation of
the threshold voltage. From these considerations, by applying
Vth = 0.3-0.4 V, the minimum cell size is achievable while
keeping stable operation even at 0.7 V. At high temperatures,
the increase in the OFF-current significantly affects the yield
of Vth (0.15 and 0.25 V) wafers. This cannot be secured by
increasing the cell ratio. On the other hand, the yield for
Vth = 0.35 V wafer is stable. From these results, the lower
limit of Vdd for SRAM is 0.7 V, and the lower boundary for
threshold is around 0.3 V because of Ioff increase. Vdd and Vth
scaling will stop at these voltages. Therefore, it is necessary
to form SRAM using L transistors that do not require supply-
voltage scaling.
IV. CONCLUSION
We have investigated the impact of Vdd and Vth scaling
in logic and SRAM transistors. For logic circuits, we have
estimated the power and the speed for inverter gates with a
fan-out = 3. Optimum Vdd is found to be very sensitive to the
switching activity in addition to operation frequency. For a low-
power operation, we propose to integrate two sets of transistors
having different Vdd s. In the high frequency or high switching
blocks, H transistors in which Vdd and Vth are moderately
scaled are helpful. On the other hand, in low switching activity
block or relatively low frequency portion, L transistors in
which Vdd should be kept around 1–1.2 V are advantageous.
When we think about the lineup of MOSFETs and scaling
strategy for devices, multi-Vdd and switching activity should
be taken into account especially in the down-scaled region. In
addition, it is hard to determine the scaling trend especially
at the 32-nm technology and beyond at this moment, but it
can be concluded that the threshold voltage cannot be scaled
continuously, hence, scaling of supply voltage should become
slower. A combination of H and L transistors seems useful
to reduce the power consumption in the future. It should be
noted that the future technology node would need additional
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1431
techniques such as high-κ dielectric double-gate structure to
further suppress the standby current.
In addition to the logic circuits, we have also investigated
the yield of SRAM arrays to study optimum Vdd for SRAM
operation. In high-density SRAM, low Vth causes yield loss
and an area penalty because of low SNM and high bit leakage
especially at high-temperature operation. Vth should be kept
around 0.3–0.4 V from an area-size point of view. Minimum
Vdd for SRAM operation is 0.7 V in this study. An Ioff increase
becomes a limiting factor for achieving a small SRAM cell hav-
ing small beta ratio and high-temperature operation. Therefore,
the supply voltage for SRAM cannot be scaled continuously.
ACKNOWLEDGMENT
The authors would like to thank Dr. P. Kapur at the Center
for Integrated Systems, Department of Electrical Engineering,
Stanford University, for the support in the brushup of this paper.
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Eiji Morifuji (M’98–A’01–M’03) was born in
Kyoto, Japan. He received the B.S. and M.S. de-
grees in electrical engineering from the University of
Tokyo, Tokyo, Japan, in 1993 and 1995, respectively.
In 1995, he joined the Research and Devel-
opment Center, Toshiba Corporation, Kanagawa,
Japan, where he was engaged in the research of
advanced CMOS and RF devices. He moved
to Semiconductor Company, Toshiba Corporation,
Kanagawa, Japan, and has been working on the
research and development of CMOS system large-
scale integration (LSI). From 2005 to 2006, he spent one year at Stanford
University, where he worked for the scaling and low-power optimization
of CMOS.
Takeshi Yoshida was born in Nagoya, Japan. He
received the B.S. degree in electrical engineering
from Kyoto University, Kyoto, Japan, in 1987.
In 1987, he joined the Semiconductor Device
Laboratory, Toshiba Corporation, Kanagawa, Japan,
where he was engaged in the development of SRAM
and DRAM. He moved to System LSI Division
of Semiconductor Company, Toshiba Corporation,
Kanagawa, Japan, and has been working on the
research and development of CMOS system LSI.
Masahiko Kanda was born in Saitama, Japan. He
received the B.S. and M.S. degrees in mechanical
engineering from Keio University, Kanagawa, Japan,
in 1994 and 1996, respectively.
In 1996, he joined the micro and custom LSI
division, Toshiba Corporation, Kanagawa, where he
was engaged in embedded Flash memory devices.
And then, he has been working on the development
of CMOS SRAM.
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 6, JUNE 2006
Satoshi Matsuda (M’98) was born in Toyama,
Japan. He received the B.S. and M.S. degrees from
the University of Tsukuba, Ibaraki, Japan, in 1987
and 1989, respectively.
In 1989, he joined the ULSI Research Center,
Toshiba Corporation, Kawasaki, Japan, where he
worked on the development of device technologies.
He worked on the development of trench isolation
for bipolar transistor and STI structure for submi-
crometer CMOS devices. His recent work is the
development of 65-nm node LSIs.
Seiji Yamada (M’93) received the B.S. and
M.S. degrees in metallurgical engineering from
Waseda University, Tokyo, Japan, in 1985 and 1987,
respectively.
In 1987, he joined the Semiconductor De-
vice Engineering Laboratory, Toshiba Corporation,
Kawasaki, Japan, where he was engaged in the re-
search and development of the embedded process
technologies for logic device and nonvolatile mem-
ory. Since 1990, he has been working on the de-
velopment of high-density Flash memories. From
1995 to 1997, he was a Visiting Scholar at the Department of Electrical
Engineering, Stanford University, Stanford, CA. He moved to the Advanced
Logic Technology Department of System LSI division in 2000. Currently, his
responsibilities involve establishment of process and device technologies for
CMOS platforms.
Fumitomo Matsuoka (M’91) received the B.S.,
M.S., and D.E. degrees in electrical engineering from
Waseda University, Tokyo, Japan, in 1982, 1984, and
1995, respectively.
He joined the Semiconductor Device Engineering
Laboratory, Toshiba Corporation, Kawasaki, Japan,
in 1984. He was engaged in the research and de-
velopment of CMOS process and device technology
for Logic LSI and high-density static RAM from
1984 to 1999. He moved to the Advanced Logic
Technology Department in 2000, and since then has
worked for advanced silicon device technology and integration for logic device
including embedded memories. Currently, he serves as the Senior Manager of
the Advanced Logic Technology Department. He has authored or coauthored
more than 50 technical papers and holds 8 U.S. patents.
Dr. Matsuoka is a member of IEEE Electron Device Society. He served as the
Program Committee member of the 1999 and 2000 Symposium on Very Large
Scale Integration (VLSI) Technology.