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This document provides recommendations for new designs 2 Before you begin............................... ........................1
based on the T1040, which is an advanced, multicore 3 Simplifying the first phase of design.........................2
processor that combines four e5500 processor cores built on
Power Architecture®, with high-performance datapath 4 Power design recommendations.......... ..................... 4
acceleration logic and network and peripheral bus interfaces 5 Interface recommendations......................................17
required for networking, telecom/datacom, wireless
infrastructure, and mil/aerospace applications. 6 Thermal recommendations............... .......................61
This document can also be used to debug newly-designed 7 T1042 design recommendations.......... ................... 63
systems by highlighting those aspects of a design that merit 8 Revision history.......................... ............................ 66
special attention during initial system start-up.
NOTE
This document is also applicable to the
T1042. For a list of functionality
differences, see T1042 design
recommendations.
Power Architecture®
256 KB e5500
backside
L2 cache 32/64-bit
32 KB 32 KB 256 KB DDR3L/4
D-Cache I-Cache platform cache memory controller
SATA 2.0
SATA 2.0
1G 1G 1G 1G
PCI Express 2.0
PCI Express 2.0
PCI Express 2.0
PCl Express 2.0
cross
TDM/HDLC
TDM/HDLC
4x I2C trigger
Pattern 8-port
eSPI, 4x GPIO switch
match Buffer Perf Trace
2 x USB2.0 w/PHY engine Monitor
Manager 1G 1G 1G 1G
2.2 Aurora
DIU 1G 1G 1G 1G
1. Design requirements in the device hardware specification supersede requirements mentioned in design checklist and
design requirements mentioned in design checklist supersede the design/implementation of the Freescale reference
design (RDB) system.
NOTE
1. All the power pins need to be tied to their corresponding voltages irrespective of
whether the corresponding interfaces are used.
2. L1VDD and LVDD should be configured at same voltage. When L1VDD/LVDD
are configured at 3.3V, EC2 can only be used as GPIO's.
3. Same regulator can be used to source VDD, VDDC and USB_SVDD supplies.
S1VDD needs to sourced from a different regulator.
4. Power Sequencing should be followed as per chip Hardware specifications.
5. All switchable supplies should be switched OFF in deep sleep mode, else it may
cause irreversible damage to the device.
6. The Power supplies designated as OFF in this column should be switched OFF
during Deep Sleep and those designated as ON should not be switched OFF. There
are few power supplies which can be optionally switched OFF, for more details
refer QorIQ T1040 Reference Manual.
7. Refer USB A-007992 erratum in T1040 QorIQ Chip Errata
NOTE: A higher capacitance value for C2 may be used to improve the filter as long as the other C2
parameters do not change (0402 body, X5R, ESL ≤ 0.5 nH).
NOTE: Voltage for AVDD is defined at the input of the PLL supply filter and not the pin of AVDD.
R
1.8 V source AVDD_PLAT, AVDD_CGA1, AVDD_CGA2, AVDD_D1
C1 C2
Ensure filter circuits use surface mount capacitors with minimum effective series inductance (ESL).
Place each circuit as close as possible to the specific AVDD pin being supplied to minimize noise coupled
from nearby circuits.
NOTE: If done properly, it is possible to route directly from the capacitors to the AVDD pins, without the
added inductance of vias.
NOTE: It is recommended that an area fill or power plane split be provided to provide a low-impedance
profile, which helps keep nearby crosstalk noise from inducing unwanted noise.
Ensure each of the PLLs is provided with power through independent power supply pins (AVDD_PLAT,
AVDD_CGAn, AVDD_D1, and AVDD_SD1_PLLn, respectively).
For maximum effectiveness, ensure the filter circuit is placed as close as possible to the AVDD_SD1_PLLn
ball to ensure it filters out as much noise as possible.
Ensure the ground connection is near the AVDD_SD1_PLLn ball. The 0.003-μF capacitor is closest to the
ball, followed by a 4.7-μF capacitor and 47-μf capacitors, and finally the 0.33Ω resistor to the board supply
plane.
To ensure stability of the internal clock, ensure the power supplied to the PLL is filtered using a circuit similar
to the one shown in this figure.
Note the following:
• AVDD_SD1_PLLn should be a filtered version of X1VDD.
• Signals on the SerDes interface are fed from the X1VDD power plane.
• It is recommended that an area fill or power plane split be provided for both AVDD and AGND to
provide a low-impedance profile, which helps keep nearby crosstalk noise from inducing unwanted
noise.
Table continues on the next page...
0.33 Ω
X1VDD AVDD_SD1_PLLn
47 µF 4.7 µF 0.003 µF
AGND_SD1_PLLn
Ensure the capacitors are connected from AVDD_SD1_PLLn to the ground plane.
Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces should be kept
short, wide, and direct.
Ensure AVDD_SD1_PLLn is a filtered version of X1VDD.
There must be dedicated analog ground AGND_SD1_PLLn for each AVDD_SDn_PLLn pin up to the physical
locale of the filters themselves.
S1VDD should be supplied by a linear regulator and needs a nominal voltage of 1.0V. An example solution
for S1VDD filtering, where S1VDD is sourced from a linear regulator, is shown in the following figure. The
component values in this example filter are system-dependent and are still under characterization, so
component values may need adjustment based on the system or environment noise.
Where:
• C1 = 0.003 μF ± 10%, X5R, with ESL ≤ 0.5 nH
• C2 and C3 = 2.2 μF ± 10%, X5R, with ESL ≤ 0.5 nH
• F1 and F2 = 120 Ω at 100 MHz 2A 25% 0603 Ferrite (for example, Murata BLM18PG121SH1)
• Bulk and decoupling capacitors are added, as needed, per power supply design.
Bulk and F1
S1VDD Linear regulator output
decoupling
capacitors C1 C2 C3
F2
GND
NOTE: See section "Power-on ramp rate" in the applicable chip data sheet for maximum S1VDD power-up
ramp rate.
NOTE: There must be enough output capacitance or a soft-start feature to assure the ramp-rate
requirement is met.
NOTE: Besides a linear regulator, a low-noise-dedicated switching regulator can be used. 10 mVp-p, 50
kHz-500 MHz is the noise goal.
X1VDD may be supplied by a linear regulator or sourced by a filtered G1VDD. Systems may design-in both
options to allow flexibility to address system noise dependencies. However, for initial system bring-up, the
linear regulator option is highly recommended. An example solution for X1VDD filtering, where X1VDD is
sourced from a linear regulator, is shown in the following figure. The component values in this example filter
are system-dependent and are still under characterization, so component values may need adjustment
based on the system or environment noise.
Where:
• C1 = 0.003 μF ± 10%, X5R, with ESL ≤ 0.5 nH
Table continues on the next page...
Bulk and F1
X1VDD Linear regulator
decoupling
output
capacitors
C1 C2 C3
F2
GND
NOTE: See section "Power-on ramp rate" in the applicable chip data sheet for maximum XnVDD power-up
ramp rate.
NOTE: There must be enough output capacitance or a soft-start feature to assure the ramp-rate
requirement is met.
NOTE: The ferrite beads should be placed in parallel to reduce voltage droop.
NOTE: Besides a linear regulator, a low-noise-dedicated switching regulator can be used. 10 mVp-p, 50
kHz-500 MHz is the noise goal.
USB_HVDD and USB_OVDD must be sourced by a filtered 3.3 V and 1.8 V voltage source using a star
connection. An example solution for USB_HVDD and USB_OVDD filtering, where USB_HVDD and
USB_OVDD are sourced from a 3.3 V and 1.8 V voltage source, is illustrated in the following figure. The
component values in this example filter is system-dependent and are still under characterization, so
component values may need adjustment based on the system or environment noise.
Where:
• C1 = 0.003 μF ± 10%, X5R, with ESL ≤ 0.5 nH
• C2 and C3 = 2.2 μF ± 10%, X5R, with ESL ≤ 0.5 nH
• F1 and F2 = 120 Ω at 100 MHz 2A 25% 0603 Ferrite (for example, Murata BLM18PG121SH1)
• Bulk and decoupling capacitors are added, as needed, per power supply design.
Bulk and F1
USB_HVDD or 3.3 V or
decoupling 1.8 V source
USB_OVDD
capacitors
C1 C2 C3
GND
USB_SVDD must be sourced by a filtered VDD using a star connection. An example solution for USB_SVDD
filtering, where USB_SVDD is sourced from VDD, is illustrated in the following figure. The component values
in this example filter are system-dependent and are still under characterization, so component values may
need adjustment based on the system or environment noise.
Where:
• C1 = 2.2 μF ± 20%, X5R, with low ESL (for example, Panasonic ECJ0EB0J225M)
• F1 = 120 Ω at 100-MHz 2A 25% Ferrite (for example, Murata BLM18PG121SH1)
• Bulk and decoupling capacitors are added, as needed, per power supply design
Table continues on the next page...
Bulk and
Bulk and F1
USB_SVDD
decoupling
decoupling VDD / VDDC
capacitors
capacitors
C1 C1
GND
Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces should be kept
short, wide, and direct.
Elaborating "VDDC should ramp up along with or before VDD power supply":
1. Use Case 1: VDDC and VDD are generated using single power regulator with FET control
VDDC
VDD
Regulator
DC/DC Converter
EVT_B2 (Power-en)
EVT_B2 (Power-en)
SHUT DN
VDD
VIN
VIN Regulator 2
VDDC
Regulator 1
USB digital
VDDC
SCFG_DPSLPCR[DPSLPUSB]
USB digital
VDD
SCFG_DPSLPCR[DPSLPUSB]
NOTE
1. RGMII is supported at 1.8V to help lower the deep sleep power consumption.
5 Interface recommendations
1. DDR3L signals are muxed with DDR4 signals and shown in this table
NOTE
1. Stacked memory for DDR4 are not supported
2. 1600MT/s data rate is supported in 64-bit mode only for DDR4
3. DDR4 RDIMM are not supported
NOTE
1. In the RCW configuration field SRDS_PLL_PD_S1, the respective bits for each
unused PLL must be set to power it down. SerDes module is disabled when both its
PLLs are turned off.
2. After POR, if an entire SerDes module is unused, it must be powered down by
clearing the SDEN fields of its corresponding PLL1 and PLL2 reset control
registers (SRDSxPLL1RSTCTL).
3. Unused lanes must be powered down by clearing the RRST and TRST fields and
setting the RX_PD and TX_PD fields in the corresponding lane's general control
register (SRDSxLNmG0).
4. A spread-spectrum reference clock is permitted for PCI Express. However, if any
other high-speed protocol such as SATA, SGMII, SGMII 2.5G, QSGMII,
1000Base-KX, is used concurrently on the same SerDes PLL, spread-spectrum
clocking is not permitted
NOTE
IFC interface is on OVDD power domain which is 1.8V only
For functional connection diagram, refer chip reference manual.
UC1_RTSB_TXEN O
UCC3 signals
UC3_CDB_RXER I The functionality of If UCC3 is not used, all
these signals is the pins can be
UC3_CTSB_RXDV I
determined by the QE- programmed as GPIO's
UC3_RXD7 I TDMB field in the reset and outputs.
UC3_TXD7 O configuration word.
UC3_RTSB_TXEN O
TDMA_RXD I
TDMB signals
TDMB_TXD O The functionality of If TDMB is not used, all
these signals is the pins can be
TDMB_TSYNC I
determined by the QE- programmed as GPIO's
TDMB_RQ O TDMB field in the reset and outputs.
TDMB_RSYNC I configuration word.
TDMB_RXD I
NOTE
1. DIU on T1040 is similiar to P1022 QorIQ from Freescale, former has a 12bit RGB
interface whereas latter supports a 24 bit RGB interface.
2. Refer chip Reference Manual for Pixel data mapping.
TSEC_1588_CLK_OU O
T
TSEC_1588_PULSE_ O
OUT[1:2]
NOTE
1. All IEEE 1588 pins are referenced to LVDD.
NOTE
1. These signals are muxed in 2 voltage domains (L1VDD and LVDD) and
RCW[EMI1_MODE] bit defines the operation for both. Muxing selection for
MDIO is done through the SCFG register SCFG_EMIIOCR[MDIO2SEL]
1. This pin requires an external 1 kΩ pull-down resistor to prevent the PHY from seeing a valid transmit enable before it is
actively driven.
2. Either of the EC1_GTX_CLK125 or EC2_GTX_CLK125 can be used to clock both the EC interfaces in RGMII mode. The
selection is through SCFG_EMIIOCR[GTXCLKSEL].
NOTE
1. T1040 has tSKEW R in the range of 2ns to 3ns. Hence users will have to add delay
of 2.5ns on board + PHY
2. The T1040 has tSKEW T in the range of -0.6ns to 0.5ns. Hence users will have to
add delay of 2.0ns on board + PHY
IIC3_SDA I/O The functionality of this signal is If I2C3 is not used, all pins can be
determined by the I2C3 field in the reset programmed as GPIO's and output.
IIC3_SCL I/O
configuration word (RCW[I2C3])
Tie these open-drain signals high through
a nominal 1 kΩ resistor to DVDD. Optimum
pull-up value depends on the capacitive
loading of external devices and required
operating speed.
IIC4_SDA I/O The functionality of this signal is If I2C4 is not used, all pins can be
determined by the I2C4 field in the reset programmed as GPIO's and output.
IIC4_SCL I/O
configuration word (RCW[I2C4])
Tie these open-drain signals high through
a nominal 1 kΩ resistor to DVDD. Optimum
pull-up value depends on the capacitive
loading of external devices and required
operating speed.
NOTE
1. Separate DIR signals are implemented to support card interrupt on DAT1 in single
bit mode.
2. SDHC_CLK_SYNC_OUT to SDHC_CLK_SYNC_IN connection is required in
SDR50 and DDR50 mode only.
3. In SDR50 and DDR50 mode all the input signals are sampled with respect to
SDHC_CLK_SYNC_IN
4. SDHC_CLK_SYNC_OUT and SDHC_CLK_SYNC_IN should be routed as close
as possible to card, with minimum skew with respect to SD_CLK.
5. When using 8-bit MMC/eMMC configuration, EVDD and CVDD should be set at
same voltage
3.3 V 3.3 V SD
T1040
CARD
CMD, DAT[0], DAT[1:3],
CLK, CD_B, WP
Dual Voltage
Regulator
(3.3V/1.8V)
Voltage
Select
SDHC_VS
R
SDHC_CLK_SYNC_IN
Voltage Voltage
Regulator Regulator
(1.8V) (3.3V
Voltage
Select
SDHC_VS R
DIR
SDHC_CLK_SYNC_IN
1.8V 3.3V
Voltage
Translator
eMMC (3.3V)
DIR (1.8V/3.3V)
T1040/T2081
SDHC_CLK_SYNC_IN
3.3V 1.8V
Voltage
Translator
eMMC (1.8V)
DIR (3.3V/1.8V)
T1040/T2081
SDHC_CLK_SYNC_IN
DNP
100Ω
10kΩ
+-1% 100nf
DNP
VSS
USBCLK1 I Connect to 24MHz clock oscillator This pin should be pulled low through
a 2-10 kΩ resistor to GND.
USBCLK is on O1VDD power domain
(1.8V)
Spread spectrum clocking is not
supported
1. USB PHY can optionally be provided reference clock generated internally from system clock. In that case USBCLK is
unused and must be pulled low through a 2-10 kΩ resistor to GND
USBn_DRVVBUS
VBUS VBUS charge
(USB connector) pump USBn_PWRFAULT
51.2 k Ω 0.6 VF
5 VZ
USBn_VBUSCLMP
18.1 k Ω
Chip
1. In the "Single Oscillator Source" Reference Clock Mode supported by T1040, DIFF_SYSCLK/DIFF_SYSCLK_B
(differential) clock inputs are used as primary clock input and SYSCLK is unused. Power-on-config signal cfg_eng_use0
selects between SYSCLK (single ended) and DIFF_SYSCLK/DIFF_SYSCLK_B (differential) clock inputs
2. In the "Single Oscillator Source" Reference Clock mode, DIFF_SYSCLK/DIFF_SYSCLK_B clock inputs can be selected to
feed the DDR PLL. RCW bits [DDR_REFCLK_SEL] are used for this selection and DDRCLK is unused.
3. When SYSCLK is chosen as the primary clock input to the chip, these pins are unused.
4. Control bits in USB PHY registers can be programmed to select USB reference clock generated internally from system
clock. A divide by 5 logic is used to obtain 20MHz reference to USB PHY. This requires system clock to be 100MHz,
USBCLK is unused
SYSCLK(64-133.33MHz)
OSC
MUX
DIFF_SYSCLK/DIFF_SYSCLK_B SYSTEM
100MHz CLOCK
LVDS
1.0V DDR
PHY
LVCMOS
LVDS
1.0V 1.0V
IO
1
DDRCLK
POR CONFIG
USB
(cfg_eng_use0]
PHY PLL
On board RCW[DDR_REFCLK_SEL]
oscillator
(100MHz)
3 diifferential Core
DDRPLL
outputs PLL
3 2
Platform
PLL
XTAL
SERDESPLL1
SERDESPLL2
SYSCLK Platform
64MHz - 133MHz
PLL
Oscillator
Core PLL's
SERDES PLL1
(5GHz for PCle, QSGMII,
PCle Gen2 SGMII)
compliant
Clock SERDES PLL2
Generator & (3GHz for SATA,
Buffer 3.125GHz for SGMII 2.5G)
25MHz Osc
DIFF_SYSCLK
100 Ohm LVDS
RX
DIFF_SYSCLK_B
DIFF_SYSCLK
CLK_Out
33Ω
LVDS CLK
Clock 100 Ω differential PWB trace 100 Ω Receiver
33Ω
DIFF_SYSCLK_B
CLK_Out
Freescale device
LVDS CLK Driver chip
CLK_Out DIFF_SYSCLK
LVDS CLK
Clock 100 Ω differential PWB trace 100 Ω Receiver
CLK_Out DIFF_SYSCLK_B
LVPECL CLK
Driver chip Freescale device
CLK_Out DIFF_SYSCLK
R2
R1 LVDS CLK
Clock 100 Ω differential PWB trace 100 Ω Receiver
R2
CLK_Out DIFF_SYSCLK_B
R1
R1=140 Ω to 240 Ω
Single-ended
CLK driver chip
DIFF_SYSCLK
33 Ω
Clock
DIFF_SYSCLK_B
O1VDD/2
NOTE
1. If on-board programming of NOR boot flash, NAND boot flash, SPI boot flash or
SD card is needed then an option should be kept (may be via a jumper) to keep
PORESET_B and RESET_REQ_B disconnected from each other. Booting from a
blank NOR/NAND flash or SPI flash causes pre-boot error which in turn causes
assertion of RESET_REQ_B. When RESET_REQ_B is connected with
PORESET_B, then device goes in a recurring reset loop and does not provide
enough time for JTAG to take control of the device and perform any operation.
2. For RCW override, RESET_REQ_B should be disconnected from PORESET_B or
HRESET_B. An option on board is required.
3. HRESET_B from COP connector should be connected to PORESET_B of SOC as
recommended in JTAG connection diagram.
4. PORESET_B should be asserted zero during the JTAG Boundary scan operation,
and is required to be controllable on board.
5. Use of PORESET_B is recommended, HRESET_B to be used for debug purpose
only.
6. HRESET_B input must not be asserted during deep sleep.
COP_TDO 1 2 NC
COP_TDI 3 4 COP_TRST_B
NC 5 6 COP_VDD_SENSE
COP_TCK 7 8 COP_CHKSTP_IN_B
COP_TMS 9 10 NC
COP_SRESET_B 11 12 NC
COP_HRESET_B KEY
13
No pin
COP_CHKSTP_OUT_B 15 16 GND
NOTE: The COP header adds many benefits such as breakpoints, watch points, register and memory
examination/modification, and other standard debugger features. An inexpensive option is to leave the
COP header unpopulated until needed.
Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure
25. Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions,
as most have asynchronous behavior and spurious assertion gives unpredictable results.
1 kΩ OVDD
10 kΩ
From target HRESET_B 7
board sources HRESET_B6
(if any)
PORESET_B 10 kΩ
PORESET_B1
COP_HRESET_B
13
COP_SRESET_B 10 kΩ
11
B 10 kΩ
A
5 10 kΩ
1 2
3 4 10 kΩ
5 6
COP_TRST_B TRST_B1
4
7 8 COP_VDD_SENSE2 10 Ω
6
COP header
9 10 5 NC
COP_CHKSTP_OUT_B
11 12 15 CKSTP_OUT_B
KEY
13
No pin 143 10 kΩ
15 16
COP_CHKSTP_IN_B
8 System logic
COP connector COP_TMS
physical pinout 9 TMS
COP_TDO TDO
1
COP_TDI TDI
3
COP_TCK TCK
7
2 NC
10 NC 10 kΩ
4
12
16
Notes:
1. The COP port and target board should be able to independently assert PORESET_B and TRST_B to the processor in
order to fully control the processor as shown here.
3. The KEY location (pin 14) is not physically present on the COP header.
4. Although pin 12 is defined as a no-connect, some debug tools may use pin 12 as an additional GND pin for improved signal integrity.
5. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally
asserting the TRST_B line. If BSDL testing is not being performed, this switch should be closed to position B.
6 Thermal recommendations
Adhesive or
thermal interface material
Die
Printed circuit-board
Ensure the heat sink is attached to the printed-circuit board with the spring force centered over the
package.2
Ensure the spring force does not exceed 15 pounds force (65 Newtons).
A thermal interface material is required at the package-to-heat sink interface to minimize the thermal
contact resistance.3
1. The system board designer can choose among several types of commercially available heat sinks to determine the
appropriate one to place on the device. Ultimately, the final selection of an appropriate heat sink depends on factors such
as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly and cost.
2. The performance of the thermal interface materials improves with increased contact pressure; the thermal interface vendor
generally provides a performance characteristic to guide improved performance
3. The system board designer can choose among several types of commercially available thermal interface materials.
4. A Flotherm model of the part is available.
This figure depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board.
Heat sink
Die/Package
Package/Solder balls
Printed-circuit board
7.1 Introduction
The T1042 QorIQ advanced, multicore processor combines four, e5500 Power Architecture® processor cores with high-
performance datapath acceleration logic and network and peripheral bus interfaces required for networking, telecom/
datacom, wireless infrastructure, and mil/aerospace applications.
This figure shows the major functional units within the chip.
Power Architecture
256 KB e5500
backside
L2 cache 32/64-bit
32 KB 32 KB 256 KB DDR3L/4
D-Cache I-Cache platform cache memory controller
SATA 2.0
SATA 2.0
2.5G 2.5G 1G 1G 1G cross
TDM/HDLC
TDM/HDLC
4x I2C trigger
Pattern
eSPI, 4x GPIO
match Buffer Perf CoreNet
2 x USB2.0 w/PHY engine Monitor trace
Mgr.
PCle
PCle
PCle
PCle
2.2 Aurora
DIU
Power Architecture
256 KB e5500
backside
L2 cache 32/64-bit
32 KB 32 KB 256 KB DDR3L/4
D-Cache I-Cache platform cache memory controller
1G 1G 1G 1G cross
TDM/HDLC
TDM/HDLC
4x I2C trigger
Pattern 8-port
eSPI, 4x GPIO switch
match Buffer Perf CoreNet
2 x USB2.0 w/PHY engine Monitor trace
Mgr.
PCle
PCle
PCle
PCle
1G 1G 1G 1G
2.2 Aurora
DIU 1G 1G 1G 1G
Power Architecture
256 KB e5500
backside
L2 cache 32/64-bit
32 KB 32 KB 256 KB DDR3L/4
D-Cache I-Cache platform cache memory controller
SATA 2.0
SATA 2.0
1G 1G 1G 1G cross
TDM/HDLC
TDM/HDLC
4x I2C trigger
Pattern
eSPI, 4x GPIO
match Buffer Perf CoreNet
2 x USB2.0 w/PHY engine Monitor trace
Mgr.
PCle
PCle
PCle
PCle
2.2 Aurora
DIU
TEST_SEL_B Termination
T1040/T1042 Pulled to O1VDD through a 100-ohm to 1k-ohm resistor
TEST_SEL_B Termination
T1020/T1022 Terminate to GND
8 Revision history
This table summarizes changes to this document.
Table 53. Revision history
Revision Date Change
1 04/2015 • Added MII 2.5V support to section Ethernet controller recommendations along with the update
of note.
• Added footnote to EC1_GTX_CLK125 in Table 20
• Added EC2_GTX_CLK125 signal to Table 20
0 01/2015 Initial public release