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EE141

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  No lab next week


  Midterm on Fr Febr 19 6:30-8pm in 2060 Valley
LSB
  Review Session: TBA (most likely on Th)

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  Last lecture
  Optimizing complex logic
  Today’s lecture
  Applying what we learned on memory
decoders
  Reading (Ch 6.2, 12.1,12.3)

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tpgate = tinv (pγ + LE×f)

Measure everything in units of tinv (divide by tinv):

p – intrinsic delay (kγg) - gate parameter ≠ f(W)


LE – logical effort (k) – gate parameter ≠ f(W)
f – electrical effort (effective fanout)

Normalize everything to an inverter:


LEinv =1, pinv = γ

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  Compute the path effort: PE = (ΠLE)BF


  Find the best number of stages N ~ log4PE
  Compute the effective fanout/stage EF = PE1/N
  Sketch the path with this number of stages
  Work either from either end, find sizes:
Cin = Cout*LE/EF

Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.

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LE=10/3 1 LE=2 5/3 LE=4/3 5/3 4/3 1


ΠLE = 10/3 ΠLE = 10/3 ΠLE = 80/27
P= 8 + 1 P=4 + 2 P= 2 + 2 + 2 + 1

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Branching effort:

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Branching Example 1
15 LE = 1
FO = 90/5 = 18
90
PE = 18 (wrong!)
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SE1 = (15+15)/5 = 6
15 90 SE2 = 90/15 = 6
PE = 36, not 18!
Introduce new kind of effort to account for branching:
Con-path + Coff-path
•  Branching Effort: b=
Con-path
•  Path Branching Effort: B= Πb i

Now we can compute the path effort:


•  Path Effort: PE = ∏LE·FO·B
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Branching Example 2
Select gate sizes y and z to minimize delay from A to B

Logical Effort: LE = (4/3)3

Electrical Effort: FO = Cout/Cin = 9

Branching Effort: B = 2•3 = 6

Path Effort: PE = ∏LE·FO·B= 128


Work backward for sizes:
Best Stage Effort: SE = PE1/3 ≈ 5 9C•(4/3)
z= = 2.4C
5
Delay: D = 3•5 + 3•2 = 21 3z•(4/3)
y= = 1.9C
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  Compute the path effort: PE = (ΠLE)BF


  Find the best number of stages N ~ log4PE
  Compute the effective fanout/stage EF = PE1/N
  Sketch the path with this number of stages
  Work either from either end, find sizes:
Cin = Cout*LE/EF

Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.

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Schematic Physical

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All-inclusive model Capacitance-only

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  Interconnect and its parasitics can affect all of


the metrics we care about
  Cost, reliability, performance, power consumption

  Parasitics associated with interconnect:


  Capacitance
  Resistance
  Inductance

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SLocal = STechnology

SGlobal = SDie

From Magen et al., “Interconnect Power Dissipation in a Microprocessor”

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  Use Better Interconnect Materials


  e.g. copper, silicides

  More Interconnect Layers


  reduce average wire-length

  Selective Technology Scaling


  (More later)

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Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi

Conductivity: 8-10 times better than Poly

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•  Analysis method:
•  Break the wire up into segments of length dx
•  Each segment has resistance (r dx) and
capacitance (c dx)

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Model the wire with N equal-length segments:

For large values of N:

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