RTL Coding tips

Lecture 7,8

Prepared by: Engr. Qazi Zia , Assistant Professor EED, COMSATS Attock
What is RTL (register transfer level)?

 Combining data flow and behavioral modeling

 Each digital system has both combinational and sequential parts
 Use data flow for combinational and behavioral for sequential

combinational Register

 Hint: It is important to note that, while coding at RTL, the non blocking
procedural assignment should be used only to model sequential logic and the
blocking procedural assignment to model combinational logic
 RTL Coding Guideline: Avoid
Combinational Feedback
x 10
5 x 5
5 If first cloud is an
adder (add input and
0 feedback but
10 feedback is unknown),
x 2nd cloud is multiplier
x with integer 2 (it will
multiply unknown
output of 1st cloud
with 2, so produces
unknown output.)
How to use a register

reg [7:0]acc;
always@(acc)
acc = acc +1;

Any such code does not make sense in design and simulation. The simulator will
never come out of this block as the change in acc will bring it back into the
procedural block.
If logic demands any such functionality, a register should be used to break the
combinational logic
How to use register

// Register with asynchronous active-low reset

always @ (posedge clk or negedge rst ) rst
clk
begin
if(!rst )
acc_reg <= 16’b0;
reg
else 1
acc_reg <= 1+acc_reg;
end
If either +ve edge of clk or –ve acc_reg
edge of reset occurs, the code
from begin-to-end will execute
Register with Synchronous Reset

always @ (posedge clk )

begin
if(!rst )
acc_reg <= 16’b0;
else
acc_reg <= 1+acc_reg;
end
Example 1 : N bit Counter with asynchronous
clear
module counter
#(parameter N = 4)
(input wire clr ,
input wire clk ,
output reg [N-1:0] q
);
// N-bit counter
always @(posedge clk or posedge clr)
begin
if(clr == 1)
q <= 0;
else
q <= q + 1;
end
endmodule
4-bit behavioral adder
module adder4b (
input wire [3:0] a ,
input wire [3:0] b ,
output reg [3:0] s ,
output reg cf
);
reg [4:0] temp;
always @(*)
begin
temp = {1'b0,a} + {1'b0,b};
s = temp[3:0];
cf = temp[4];
end
endmodule
Example : N-bit behavioral adder

module adder
#(parameter N = 8)
(input wire [N-1:0] a,
input wire [N-1:0] b,
output reg [N-1:0] y
);
always @(*)
begin
y = a + b;
end
endmodule
Example : N-bit comparator using relational
operators

module comp eq = 0;
#(parameter N = 8) lt = 0;
(input wire [N-1:0] x, if(x > y)
input wire [N-1:0] y, gt = 1;
output reg gt, if(x == y)
output reg eq, eq = 1;
output reg lt if(x < y)
); lt = 1;
always @(*) end
begin endmodule
gt = 0;
About Stimulus: Loading memory from a
file
 System tasks $readmemb and $readmemh are used to load data from a text
file written in binary or hexadecimal, respectively, into specified memory.
 The example here illustrates the use of these tasks. First memory needs to be
defined as:
reg [7:0] mem[0:63];
 The following statement loads data from memory.dat file into mem:
$readmemb (“memory.dat”, mem);
Macros

 Like #define in C, Verilog provides ‘define to assign a constant value to a tag:

‘define DIFFERENCE 6’b011001

 The tag can then be used instead of a constant in the code. This gives better
readability to the code. The use of the ‘define tag is shown here:
if (ctrl == ‘DIFFERENCE)
Digital Signal Processing Design
Example: Filters
 Digital filters are a very important part of DSP. In fact, their extraordinary performance is one of
the key reasons that DSP has become so popular.
 filters have two uses: signal separation and signal restoration.
 Signal separation is needed when a signal has been contaminated with interference, noise, or
other signals.
 For example, imagine a device for measuring the electrical activity of a baby's heart (EKG) while still in
the womb. The raw signal will likely be corrupted by the breathing and heartbeat of the mother. A filter
might be used to separate these signals so that they can be individually analyzed.
 Signal restoration is used when a signal has been distorted in some way.
 For example, an audio recording made with poor equipment may be filtered to better represent the
sound as it actually occurred.
 Another example is the deblurring of an image acquired with an improperly focused lens, or a shaky
camera.
Digital Signal Processing Design Example

y[n]= 0.5 y[n-1]+ x[n]

 Example
module iir(
input signed [15:0] x,
input clk, rst _n,
output reg signed [31:0] y);

reg signed [31:0] y_reg;

y[n]= 0.5 y[n-1]+ x[n]
always @(*) \\ combinational logic block
y = (y_reg>>>1) + x;
always @(posedge clk or negedge rst n) \\ sequential logic block
begin
if (!rst_n)
y_reg <= 0;
else
y_reg <= y;
end
endmodule
module stimulus_irr;
reg [15:0] X;
reg CLK, RST N;
wire [31:0] Y;
integer i;
iir IRR0(X, CLK, RST_N, Y); \\ instantiation of the module
initial
begin
CLK =0;
#5 RST_N =0; \\ resetting register before first posedge clk
#2 RST_N= 1;
end
initial
begin
X= 0;
for(i =0; i<10; i =i+1) \\ generating input values every clk cycle
#20 X =X + 1;
$finish;
end
always \\ clk generation
#10 CLK = ~CLK;
initial
begin
#60 $stop;
end
endmodule
Simulation waveform
Verilog Tasks

 Verilog task can be used to code functionality that is repeated multiple times
in a module. A task has input, output and inout and can have its local
variables.
 All the variables defined in the module are also accessible in the task.
 The task must be defined in the same module using task and end task
keywords.
 To use a task in other modules, the task should be written in a separate file
and the file then should be included using an ‘include directive in these
modules.
A simple task example

module simple_task();
task convert;
input [7:0] temp_in;
output [7:0] temp_out;
begin
temp_out = (9/5) *( temp_in + 32) ;
end
endtask
endmodule
Global variables in task

module task_global();
reg [7:0] temp_out;
reg [7:0] temp_in;
task convert;
begin
temp_out = (9/5) *( temp_in + 32);
end
endtask
endmodule
Calling a task

module task_calling (temp_a, temp_b,

temp_c, temp_d);
input [7:0] temp_a, temp_c;
output [7:0] temp_b, temp_d;
reg [7:0] temp_b, temp_d;
`include "mytask.v“
always @ (temp_a)
begin convert (temp_a, temp_b);
end
always @ (temp_c)
begin convert (temp_c, temp_d);
end endmodule
Using TASK within another module

module RCA( input [3:0] a, input [3:0] b, carry[0]= c_in;

input c_in, output reg c_out, output reg
for(i =0; i<4; i= i+1)
[3:0] sum );
begin
reg carry[4:0];
FA(a[i], b[i], carry[i], sum[i], carry[i+1]);
integer i;
end
task FA( input in1, input in2, input carry
in, output reg out,output carry_out); C_out = carry[4];
{carry_out, out} = in1 + in2 + carry_in; end
endtask endmodule
always@*
begin
Verilog Functions

 Verilog function is in many respects like task as it also implements code that
can be called several times inside a module.
 A function is defined in the module using function and endfunction keywords.
The function can compute only one output.
 To compute this output, the function must have at least one input.
 The output must be assigned to an implicit variable bearing the name and
range of the function. The range of the output is also specified with the
function declaration.
Function Example
A simple function

module simple_function();
function myfunction;
input a, b, c, d;
begin
myfunction = ((a+b) + (c-d));
end
endfunction
endmodule
Calling function

module function_calling(a, b, c, d, e, f);

input a, b, c, d, e ;
output f; If myfunction() is 1 then f
is assigned e otherwise 0
reg f;
`include "myfunction.v“
assign f = (myfunction (a,b,c,d)) ? e :0;
endmodule
How to use function

module MUX4to1( input [3:0] in, input [1:0] sel, output out);
reg out1, out2;
function MUX2to1;
input in1, in2;
input select;
assign MUX2to1 = select ? in2:in1;
endfunction
assign out1 = MUX2to1(in[0], in[1], sel[0]);
assign out2= MUX2to1(in[2], in[3], sel[0]);
assign out= MUX2to1(out1, out2, sel[1]);
endmodule
Stimulus

 /* stimulus for testing the module #5 IN =7; SEL =0;

MUX4to1 */
#5 IN= 2; SEL =1;
module testFunction;
#5 IN= 4; SEL= 2;
reg [3:0] IN;
#5 IN =8; SEL= 3;
reg [1:0] SEL;
end
wire OUT;
initial
MUX4to1 mux(IN, SEL, OUT);
$monitor($time, " %b %b %b\n", IN, SEL,
initial OUT);
begin endmodule
IN =1; SEL =0;