NS Analog Signal Path Design Seminar 2006

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Section 1: Sensors and Sensor Interfacing
Measurement systems and sensor types
Sensor characteristics
Active and passive sensors, sensitivity
Amplifier characteristics
Offset voltage and drift, CMRR, gain bandwidth, error
sources
Temperature sensors 1-19
RTDs, thermocouples
pH electrodes 1-23
Section 2: Stability Issues

Graphical stability analysis 2-1
Compensation examples 2-7
Compensating high-speed voltage feedback amplifiers,
bench evaluation and fine tuning
Capacitive loads and practical techniques to avoid instability 2-14
Section 3: Open-Loop, Closed-Loop, and Programmable Buffers

Buffer definitions, circuit architecture and analysis 3-1
LMH6321 A new standard 3-8
Improved specifications, circuit architecture, using with
high-speed amplifiers
LMH6704 Programmable gain buffer 3-12
Driving routers and transmission lines 3-15
Open-loop and closed-loop buffers, programmable gain buffers,
signal integrity, termination
Section 4: RF Detectors
Integrated RF detectors
Logarithmic and mean square detection, measurement
resolution
LMV225/26/28 Series
Specifications, applications
Section 5: Amplifier-to-ADC Interfaces

Driving switched capacitor loads
High-speed interfaces
Variable gain amplifiers, level detectors and agc circuits,
ultra-sound application
Differential input amplifiers
Advantages of common-mode feedback, single and split
supply applications, AC and DC coupling
Using WEBENCH@tools to design anti-aliasing filters
Table of Contents (cont'd)
Section 6: Temperature Sensing
Semiconductor temperature sensors
TruTherm™ technology, driving capacitive loads,
hardware monitors
Interfacing to the sampling ADC
Input glitches, solving problems, input overdrive
Section 7: Noise and Offset in Data Converters

Solving PSRR problems
AC and DC PSRR
The importance of the reference
Resolution and SNR
Output capacitance
High capacitance, output to input coupling
Amplifier and ADC offset errors
Gain errors, offset drift, adjusting errors
Section 8: Managing Jitter

Causes of jitter
Clock considerations, measuring jitter, techniques to
minimize jitter
Board layout and signal integrity
Transmission lines, solving problems, layout rules
Section 9: Data Converter Products and Applications

General-purpose ADCs
8-, 10-, and 12-bit converters, competitive performance,
specifications, nomenclature
Sensorless brush less DC motor monitoring 9-12
Peripheral control 9-13
Medical patient monitors 9-14
Camera auto focus 9-16
Blood glucose monitor 9-17
12-, 14-, and 16-bit converters 9-18
Communications receiver, radar system
Converters with L VDS outputs
Section 10: Signal Translations, LVDS, LVPECL, and CML

Differential I/O Comparisons 10-1
Level translation considerations 10-4
LVDS, LVPECL, and CML I/O structures and interfaces
Section 10: (contd)
LVDS to LVPECL 10-11
LVPECL to LVDS 10-19
CMLto LVDS 10-23
LVDSto CML 10-25
CML to L VPECL 10-26
AC coupling considerations 10-30
Data dependent jitter, selecting capacitors, data encoding
differential signaling
DC coupling 10-41
Using WEBENCH 10-45
Section 11: Using MUX-Buffers

Mux-Buffer signal conditioning
Redundancy, internal architecture, features
Input equalisation and output de-emphasis
Section 12: Buffering and Cable Driving Solutions

Cable Driving
Cable types, signal conditioning options, serial data characteristics
Cable loss 12-6
M-LVDS cable driving 12-9
Section 13: Clock Distribution
Multipoint-LVD 13-1
Family specifications, functionality, receiver thresholds, common
mode range, edge specifications
Backplane clocks 13-13
Section 14: High-Performance Audio Op Amps
Low-noise amplification 14-2
Noise sources, slew rate and bandwidth, THD+N
LM4562 low-noise, high-voltage op amp 14-11
Measuring distortion 14-12
Calculating noise voltages 14-16
Section 15: High-Fidelity Audio Power Amplifiers

Increasing output power 15-3
LM4702 Overture® amplifier driver 15-5
100 W amplifier, power scaling
Power supply requirements 15-11
Options, unregulated supplies, load/line conditions
Low-voltage power amplifiers , 15-17
Boosted supply amplifiers, signal integrity, differential
amplifiers
Class D 15-21
Efficiency, PWM architecture, LM4673 Boomer® amp
Section 16: Analog Video Solutions
Analog video formats
SDTV, EDTV, HDTV, HD ready
Composite video, S video, Component video, PC/Graphics

LMHI251 video converter
Specifications, applications, evaluation board
Section 17: Video Sync Separation

The importance of sync separation 17-2
LMHI981 sync separator 17-6
Vertical interval detection, bi-level and tri-level sync,
jitter and jitter measurement
Broadcast video applications, Analog-to-SDV converter,

studio systems
~National
PSemiconductor
Sensors and Sensor

Interfacing
Many signal paths start with that most universal of analog components, the operational amplifier.
First named for its ability to perform mathematical operations (addition, subtraction, integration,
differentiation, etc.) the modem op amp provides the interface to many transducers and sensors,
starting the process of converting real-world sensations such as sound, temperature, pressure,
and light into electrical signals. Many signal sources simply require amplification or buffering,
while others require manipulation to correct transducer or transmission errors. Op amps often
can combine many of these functions, because the transfer characteristic of an op amp is
determined primarily by the external components connected around the op amp.
Physical Measurement System
Physical
Environment
Buffering
and Eni>edded System
Scaling Input Side
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l'" National
Semiconductor
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Sensors are used to provide an input from the physical world, which is an analog environment, to
control systems.
Sensors provide the interface from the physical environment to the electrical environment by
converting the stimulus of interest into a voltage or current. In other words, there is a
dependency between the physical measurement of interest and an electrical property of the
sensor, and the sensor uses these dependencies to create an analog output signal.
For example, a thermocouple's output voltage will change as the temperature difference between
the hot junction and cold junction changes. This is known as the Peltier Effect. For a Resistance
Temperature Detector (RTD), the resistance to an electrical current changes as the temperature
of the resistive element changes. This can be monitored by applying a constant (known) current
to the sensor and measuring the change in voltage across the sensor as the temperature increases
or decreases.
Most of the time the output of a sensor is not usable without additional buffering and scaling.
This is the function of the amplifier and its input and feedback networks.
SensorlTransducerTypes
Property SensorlTransducer Output

Force/ Strain Gauge Resistance
Pressure Piezoelectric Voltage
Temperature Thermocouple Voltage
RTO (Resistance Temperature Detectors) Resistance
Thermistor Resistance
Silicon Voltage/current
Acceleration Accelerometer Capacitance
Position LVOT (Linear Variable Differential Transformer) AC Voltage
Light Intensity Photodiode Current
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-Active or passive
-Voltage or current output
- Source impedance
- Sensitivity
-Linearity
- Dynamic range
- Frequency response
-Common-mode signal components
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All sensors will have a set of characteristics that will determine their suitability for a specific
application. This list shows eight characteristics that are common and important.
An active sensor requires an excitation source in order to generate an output signal, while a
passive sensor can generate an output signal directly.
The resistive measurement bridge is an example of an active sensor. It senses force by changing
the resistance of one or more of the bridge's elements. The bridge is driven with a constant
current source or a constant voltage source, and the output is a voltage proportional to the
amount of force the sensor is being exposed to.
The thermocouple is a passive sensor, which will generate a voltage based on the temperature
difference between the hot junction and the cold junction.
Typically, the voltage output sensor will interface with a voltage amplifier, while the current
output sensor uses a trans impedance amplifier to convert the current to a voltage.
Examples of voltage output sensors include bridges, thermocouples, and pH electrodes.
Photodiodes, photomultiplier tubes, and ion chambers are a few current output sensors.
High-impedance sensors will require amplifiers with very low input bias currents. This is
because the amplifier's input bias current will load the sensor's output. For a high-impedance
sensor, the amplifier must have bias currents in picoamps. Low-impedance sensors can use
amplifiers with higher input bias currents, typically in nano-volts.
The sensitivity of a sensor specifies how much the output of the sensor changes for a unit change
in the measured variable. Using a thermocouple and semiconductor temperature sensor as an
example, a Chromel-Constantan thermocouple has a sensitivity of about 76 IlV/oC,
while a semiconductor temperature sensor has a sensitivity of 10 mV/OC.
Temperature Sensor Sensitivity
1- - TC - - .RTD at 1 mA -- RTD at 0.1 mA -+-- LM3s1

1.6
Chromel - Constantan Thenmo Couple -76 ~VI'C
1.4
Platnium RID(100) at 1 mA - 390 ~V/'C
Platnium RID(100) at 0.1 mA - 39~V/'C
1.2
~ LM35 - 10 mV/'C
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0 100 200 300 400 500 600 700 800 900 1000
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Here are several examples for sensitivity of a sensor. The graph and table show the LM35, a
semiconductor temperature sensor, a Chromel-Constantan thermocouple, and an RTD with two
excitation current levels.
This shows how the sensitivity of an active sensor can be changed to meet specific requirements.
A Platinum RTD (100) has won resistance at O°C. With 0.1 mA excitation current, it has an
output of about 39 flV/oC. At 1.0 mA excitation current, it has an output of about 390 flV/oC.
The choice on which current to use could be based on other factors, such as minimizing the self-
heating of the RTD.
-Active or passive
- Source impedance
- Sensitivity
-Linearity
- Dynamic range
- Common-mode signal components
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Linearity specifies how close the sensor's transfer function is to a straight line. A linear transfer
function is usually desirable because it simplifies converting the sensor's output to a useable
form for monitoring the sensor output, or using it in a control loop. Some types of sensors such
as RTDs, thermocouples, and bridges have linear, or close to linear, transfer functions. In
contrast, other sensors, such as thermistors, have very non-linear transfer functions. Many non-
linear transfer functions are most easily linearized after the Analog-to-Digital Converter (ADC)
with a microcontroller performing this task by utilizing look-up tables.
Driving Active Sensors
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How an active sensor is excited also can affect its linearity. This graph shows the effect of using
constant current excitation versus constant voltage excitation on a RTD.
The ideal (upper) curve is the slope of the RTD's transfer function extended to 800°C. The
middle curve is the transfer curve of the RTD using I mA excitation current. This curve shows
the small reduction in sensitivity of the RTD as the temperature increases.
The lower curve shows the results of using a constant voltage source and a series resistor to
excite the RTD. The series resistance (2.4 ill) is sized to provide a I mA current at O°C when
the RTD's resistance is lOOn. The curve shows the second error term introduced by this type of
excitation. As the resistance of the RTD increases, the RTD and the series resistor form a voltage
divider that further decreases the linearity at higher temperatures.
-Active or passive
- Source impedance
- Sensitivity
- Linearity
- Dynamic range
-Common-mode components
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The dynamic range of a sensor is the span of the stimulus for which a usable output is available.
In other words, dynamic range defines the minimum to the maximum value of the physical
phenomena that can be measured. Saturation or material failure could limit the dynamic range.
Saturation is the rapid loss of sensitivity above or below a given level of the stimulus. Material
failure sets a limit level of the stimulus beyond which the sensor will be damaged or destroyed.
The thermocouple metals can melt if the temperature is too high, or a pressure transducer can
rupture if the pressure being measured is to high. Some typical dynamic ranges are as follows:
Chromel- Constantan Thermocouple: Max Temperature -IOOO°C, Min Temperature - -200°C
=> Dynamic Range = 1200°C
Semiconductor Temperature Sensor: Max Temperature - 125°C, Min Temperature - -40°C =>
Dynamic Range = 165°C
The signal frequencies of the sensor's output will depend on the type of measurement being
made and can range from cycles per day for geophysical measurements to hundreds of
megahertz for some types of radiation measurements. The required closed-loop bandwidth of the
amplifier will depend on the frequency components of the sensor's output and the gain accuracy
needed for those components.
Several types of sensors have small differential signals combined with large common-mode
voltages. This large common-mode voltage must be removed to recover the data portion of the
signal, or the small differential signal.
Bridge sensors will typically have the sensor's output signal riding on top of a common-mode
voltage equal to about one half of the excitation voltage.
The current sensing resistor on a high-side current measurement circuit will have a common-
mode voltage that is close to the supply voltage. The common-mode voltage must be removed to
recover the sensor's signal.
Typical Embedded System Input
Microcontroller's Power Supply +V
5V ±10% = 4.5 to 5.5V
3.3V ±10% = 2.97 to 3.63V
2.5V ±10% = 2.25 to 2.75V
Internal
or
External
Analog to Digital
Converter
Amplifier With an ADC full scale input range = 2.048V

Buffering and Scaling 1/2 LSB at 10-bit resolution = 1 mV = 1000 ~V
(Amplifier's error contribution 1/2 LSB at 12-bit resolution = 0.250 mV = 250 ~V
should be less then 1/2 LSB) 1/2 LSB at 14-bit resolution = 0.0625 mV = 62.5 ~V
1/2 LSB at 16-bit resolution = 0.0156 mV = 15.6 ~V
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Many of the microcontrollers used in embedded control systems are being forced to lower supply
voltages as the semiconductor processes are migrating to smaller geometries. Digital logic
supply voltages have decreased from 5V down to 3.3V and 2.5V. These voltages are now in the
process of migrating to 1.8V and lower.
In the interest of power supply economics, analog amplifier supply voltages are following a
similar trend. Recent analog semiconductor processes have also reduced the supply voltage
ratings because of similar needs for smaller transistor geometries. These trends emphasize the
need for DC accuracy because of smaller error budgets. Lower supply voltages reduce the
dynamic range available for both amplifiers and ADCs. At the same time the required resolution
of the signal-processing path is increasing.
A few years ago, a 12- to 14-bit ADC with a lOV full-scale input was considered good. Now,
16 bits and higher are expected with full-scale inputs of only 1 to 2V. This results in very low
error budgets in the tens of microvolt range. This slide shows the typical error allocated to the
amplifier's total system using a 2.048V ADC with different bit-accuracy requirements.
The Amplifiers' Roles
• Accurately scale the sensor's signal

• The amplifier has two additional key roles
-It must provide a suitable interface to the sensor
• Dependent on the sensor's characteristics
- Source impedance
- Sensitivity
- Dynamic range
Interface to the ADC
• What type of load is presented by the ADC
-Resistive
- Switched capacitor
~ National
P Semiconductor
TII, Sight & Sound of Inform,tion
Amplifying the sensor's output is often thought of as the primary function of the amplifier. As a
result, it is common to think of the amplifier as the only factor that contributes to the precision of
the system, but the sensor's output characteristics and ADC's input characteristics also have a
significant effect on the total precision.
On the input side, each type of sensor has a unique set of parameters to consider. Characteristics
such as source impedance, signal level, dynamic range, etc. are all part of the design constraints
for the input and feedback network of the amplifier.
On the output side, the input characteristics of the ADC will affect the output of the amplifier.
Most of the new ADCs have a switched capacitor input which presents a dynamic reactive load
to the amplifier. The amplifier must be designed for settling quickly with this type of load or the
ADC's input must be isolated from the amplifier's output.
When the ADC's input is connected directly to the output of the amplifier, the sampling
capacitor in the ADC is connected to the amplifier's output. In this case, a charging current flows
from the amplifier to the ADC. This current causes a momentary glitch that takes some time to
settle. One way to minimize this effect is to slow down the sampling rate. This provides the
amplifier with the time required to stabilize its output.
A second way to minimize the error caused by the switch capacitor is to have a capacitor
connected to the ADC's input. This capacitor, much larger than the internal sampling capacitor,
provides the charge needed to quickly charge the ADC's sampling capacitor. An isolation
resistor also may be needed to isolate the additional load capacitance from the amplifier's output.
Note that an isolation resistor will reduce the swing of the signal coming out of the amplifier
since there is a voltage drop across the isolation resistor.
The amplifier, in conjunction with the input and feedback networks, has several tasks which
include: Accurately scaling the signal to match the ADC's input voltage range, removing any
common-mode components, and removing offsets that are inherent in the sensor's output.
The Amplifier's Requirements
• Precision sensor interface requirements

- High open-loop gain
- Low max offset voltage
• Low offset voltage drift
- Low noise
• Voltage noise
• Current noise
- Low input bias current
- High Common-Mode Voltage Rejection ratio (CMRR)
- High Power Supply Rejection Ratio (PSRR)
- Bandwidth (appropriate for the signal frequency)
• Effective signal bandwidth is a function of the amplifier's
gain bandwidth, closed-loop gain, AND the measurement
system resolution
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The amplifier's characteristics set the baseline for how much precision can be achieved.
The open-loop gain is a factor in the closed-loop gain error and should be as high as possible.
Offset voltage and offset voltage drift are multiplied by the noise gain of the feedback network
and should be as low as possible.
The voltage noise and current noise should be small compared to the sensor's signal.
The input bias current should be low relative to the source impedances of the sensor and the
input and feedback networks.
Several types of sensors have a common-mode voltage associated with their output that must be
removed by the amplifier. Therefore, the Common-Mode Rejection Ratio (CMRR) of the
amplifier should be as high as possible.
The power supply may be shared with active digital loads that will generate noise and ripple on
power supply distribution circuit. The amplifier needs to have a high Power Supply Rejection
Ratio (PSRR).
The amplifier's bandwidth must be calculated based on the precision required for the signal and
is a function of the gain bandwidth and the closed-loop gain. The effective bandwidth drops
rapidly as the required precision increases.
Offset Voltage and Drift
• Definition of offset voltage

- Usually modeled as a voltage source on the
non-inverting input
• Definition of offset voltage drift

- Also known as offset voltage error
• TeVos (temperature drift)
• Life time drift
• TeVos: Variation of one part over temperature

• Vos: General area that one part is expected to be in
at room temperature
~ National
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Offset voltage is one of the many characteristics of a "non-ideal" op amp. For an ideal op amp,
the output voltage sits at mid-supply when there is no differential voltage applied between the
inputs of an op amp. However, in reality, the output will be away from mid-supply value by a
minimal amount. To correct this, a small amount of differential voltage needs to be applied
between the inputs of the amplifier. The amount of differential voltage required between the
inputs to bring the output back to mid-supply is referred to as input offset voltage or offset
voltage.
Another way of looking at this: When there is no external differential voltage applied between
the input of the amplifier, a small amount of voltage present in the circuit will be gained up by
the amplifier's gain and will show up on the output. So, if the amount of output offset voltage is
known, we can calculate the input offset voltage using this relationship:
Input offset voltage = (output offset voltage) / (op amp's gain)
The value of offset voltage changes under different conditions, or it "drifts." The two main
elements contributing to this drift are the passage of time and change in temperature. The term
offset voltage drift usually refers to the temperature component.
Input offset voltage is temperature dependent. This means the value of offset will be different at
different temperatures. Offset voltage drift usually refers to the change in offset voltage per
degree (Celsius) change in temperature. For general purpose op amps, this value is not very
important since it is usually orders of magnitude smaller than the actual offset voltage. In
precision amplifiers with very low offset voltages, drift is of special importance, since it could
easily cause the offset voltage to double or triple at temperature extremes.
Input offset drift over time is the change in offset voltage per year (or any other specified time
frame).
• Definition of CMRR
• DC CMRR vs AC CMRR
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Op amps are designed so that they will respond only to a differential voltage between their two
input pins. This means that for an ideal op amp, if the same voltage is applied to both input pins,
the output will remain unchanged. This common signal between the two input pins is referred to
as a common-mode signal. For an ideal op amp, common-mode signal does not change the
output at all, meaning the op amp completely rejects this common-mode signal. In real op amps,
parts of this signal will get through and show up on the output, while another portion of it will be
rejected. The ability of an op amp to reject this common-mode signal is shown by ratio of the
common-mode signal seen on the output to the ratio of the common-mode signal on the input.
This is called Common-Mode Rejection Ratio (CMRR). An ideal op amp has a CMRR of
infinity. Real op amps have finite CMRR values which are usually expressed in dB.
CMRR = 20*log[( Change in offset voltage)/(change in common mode voltage)] or equally:
CMRR = 20*log[( differential gain of amplifier)/(comrnon mode gain of amplifier)]
AC CMRR and DC CMRR: whenever there is a reference to CMRR, we are talking about DC
CMRR or the ratio of differential gain to common-mode gain at zero frequency. The fact is that
CMRR is heavily frequency dependent. As we know, the differential gain of an amplifier is
relatively frequency independent and remains somewhat the same over a frequency range (it
decreases a bit), while the common-mode gain of an amplifier increases with frequency (not a
good thing) This means CMRR decreases over frequency.
• Gain-bandwidth product:
conventional definition
Gain
• Gain error
- AC gain error
- DC gain error
Frequency
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Gain-bandwidth product refers to the product of an amplifier's gain (in VN) by the frequency at
which that gain is achieved. This product remains constant for a voltage feedback op amp.
3 dB point refers to the point at which the amplifier's gain drops by 3 dB or it is 0.707 of its
original value. For the most part, gain deviations of up to 3 dB have been deemed acceptable and
have been working in most application circuits; however, we are using smaller and smaller
signals everyday. On smaller signals, 0.707 of the original may already be too far away from our
accuracy level needed. 0.707 of accuracy implies a margin of error of 0.293 (or 29.3%). In
reality, with this margin of error, we cannot even have an accurate 4-bit converter! (4-bit
converters have a maximum margin of error of 25%). This means we need to pick a frequency
point much closer to the flat band with a much smaller margin of error. For instance, at the I dB
point, we are only 10.87% away from the signal level. At 0.1 dB from flat band, we are 1.14%
from the original signal level. Now, let's look at it from the other end. For a 12-bit converter, the
maximum flat-band deviation is 0.002 dB!! (0.0244% error)
There are two main factors causing gain errors: one is a gain error due to frequency or AC-gain
error, another is the result of the op amp being non-ideal and is referred to as the DC-gain error.
For an ideal op amp, gain remains constant until the roll-off point (the pole) and then the gain
drops at 20 dB/dec or another multiple of this value (depending on number of poles present).
However in real op amps, the gain starts drifting from the flat-band line much sooner. As we've
discussed already, at the frequency comer, our gain has already been reduced by 3 dB.
DC-gain error of a non-ideal op amp: even without DC offset voltage, the output will be away
from mid-supply. This is due to the fact that the gain of a non-ideal op amp is not infinite. This
output voltage is modeled as DC-gain error.
Op Amp Error Sources
eid =~ + Vos + (Is )(Rs +)+ (Is -)(Rs _)+

+ eCM
A VOL CMRR
• Major input referred error sources of an op amp

eid = 0 for ideal op amp
• Precision requires error terms to be small

relative to the signal being processed
• AVOL and CMRR are frequency dependent
~ National
P Semiconductor
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This equation considers four of the major contributors to errors in op amps. The value eid is the
voltage between the two inputs of the op amp and is equal to zero for an ideal op amp.
The first term, e/AVOL results from the finite gain of the amplifier. There must be a small
differential voltage across the input to produce an output voltage. For example, if the output of
an amplifier is 1.0 VDC and the open-loop gain is 100 dB, then the error voltage across the
inputs is 1/105 = 10 I.N
The second term, input offset voltage or Vos , is a result of small imbalances on the differential
input stage of the amplifier. The input offset voltage is also multiplied by the noise gain of the
amplifier with its feedback. At high gains, the Vos can become a large offset error.
The third and fourth terms result from the input bias currents in conjunction with any source
resistance. Any current flowing into the amplifier's input will cause a voltage drop across the
source resistance of (Is x Rs)' This has two effects. The first is to generate an apparent offset
voltage at the input to the op amp if the equivalent source impedances on each input are not
equal. The second is to add an error voltage to the signal that changes its apparent magnitude.
The last term brings in the effect of the common-mode voltage seen by the amplifier's input. The
common-mode voltage, eCM' is defined as the average voltageon the amplifier's inputs, (e+ + e)/2.
For example, if the common-mode voltage is 1V and the CMRR is 80 dB, the error on the
amplifier's input due to the common-mode voltage is 11104 = 100 !lV.
Each of the above error sources needs to be evaluated with respect to the specifications of the
amplifier being considered.
As the frequency of the signal increases, the open-loop gain (AVOL) and the CMRR will roll off
with increasing frequency. This means a larger error term at higher frequencies.
Input Bias Current Induced Errors
Example: Rs 1MO
Amplifier Input Bias Current (typical) Error
lM321 250 nA 250mV
OP07 4nA 4mV
lMC6081 4pA 41J\f
lMP7701 0.2pA 0.21J\f
lMP7711 50 fA 50nV
/-
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lMC 6001 25 fA 25nV
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V
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Error due to Amplifier's input
bias current and the source
resistance of the sensor.
~ National
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Here is an example ofthe effect the input bias current has on the sensor's output. This sensor is a
voltage output sensor with a source impedance of 1 MO. The table lists the typical input bias
currents for five different amplifiers. The LM324 and OPO? are bipolar input amplifiers, while
the LMC608l, LMP770l, LMP77ll, and LMC600l are FET input amplifiers.
The bipolar input amplifiers have a large error relative to the FET input amplifiers. It is also
useful to note that precision amplifiers are available with guaranteed very low, sub pico-amp
input bias currents. Some examples include the LMP770l, LMP77ll, and LMC6001.
Closed-Loop Bandwidth
Normalized Bandwidth
System Resolution for < 1/2 LSB Error
B-bit 0.062592
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12-M - 0015626
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14-M 0007813
15-blt 0.005524
_ -10
16-bi_t_~ 0:003906
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c
~ -15 What bandwidth is available?
Example:
LMP2011: GBW = 3 MHz
-25 At a gain of 20 BW 150 kHz =
0.001 0.01 0.1
For 12-bit accuracy
Normalized Frequency max signal frequency is
0.0156(150 kHz) = 2.34 kHz
~National
(iI" Semiconductor
Th.Sighr&SfJundoflnform'tJon
This graph and table is a method for estimating the effective bandwidth of an amplifier given its
gain bandwidth, closed-loop gain, and the resolution of the system.
The normalized bode plot represents the specification given in the amplifier datasheet which is
the gain bandwidth (GBW). Typically, the GBW is the frequency where the amplifier's output is
down by 3 dB. The -3 dB point represents a 29.3% error (100% - 70.7%). This can be
interpreted as the bandwidth needed to maintain a specified precision is substantially less then
the -3 dB frequency.
The table shows how much bandwidth is available for a given precision_
Using the LMP20ll with a 3 MHz GBW as an example: at a closed-loop gain of20 and a l2-bit
accuracy requirement, the effective bandwidth of the amplifier is only 2.34 kHz. If the accuracy
is increased to 16 bits, the effective bandwidth is only 0.59 kHz.
CMRR Error Example
LM4140
4.096V
Load Cell
VOUT = VN1 VN2
V OUT = 20 IlV/lb
-
V COMMON MODE = (V N1 + V N2 )/2

R3
With zero weight on the scale: R1 = R2 = R3 = R4
V COMMON MODE = 4.096/2 = 2.048V
Amplifier's CMRR CMRR Error Weight Error
-100 dB 20.481lV 1.021b
-80 dB 204.81lV 10.21b
-60 dB 20481lV 102 Ib
d National
(II" Semiconductor
1M Sighta StJund oIlnforruriotl
In this example, the effect of the amplifier's CMRR and its contribution to the system's error is
shown. This is a resistive bridge being used on a load cell to measure weight. The sensitivity of
the load cell is 20 IlV/lb and has a 4.096 excitation voltage. The common-mode voltage at the
bridge's output is 2.048V. The table shows the error with three values of CMRR. Even with
100 dB of CMRR there is an error of about 1 lb.
Temperature Sensors
• Common contact temperature sensors

- Resistance Temperature Detectors (RTD)
• Platinum, copper, nickel
- Thermocouples
• Many alloys available
- Thermistors
-Semiconductor diodes
-Semiconductor sensors (LM34, LM35)
• Non-contact sensors
-Infrared thermometry
dNattonal
(/I'Semiconductor
The Sight '" Sound of Information
Temperature is one of the most commonly measured properties and a variety of sensors have
been developed for this. Of these, the RTD and the thermocouple are widely used in industrial
processes.
The next several slides show an RTD and a thermocouple amplifier circuit.
+V - Current source design
low drift components
- RTD self-heating WR)
thermal impedance
- For a temperature range of
O°C to 600°C, sensor
resistance: 1000 to 329.640
vOJT= I x Rmu - VOUT: 0.1 to 0.32964V
(Plus 2.5V CMV)

- Scale signal to 2.5V
Av = 2.5/0.32964 = 7.58
1= VRE,!R8 =2.512500 = 1 mA (Includes the non-zero signal
offset)
.:]Nattonal
(il'Semiconductor
Th,S/f1ht!Soundoflnmrmllt1Otl
Here is the I mA constant current excitation for the RTD. The LM4130A-2.500 is the reference
for the current source and the 2.5 kil resistor is the current sense resistor. The combination of the
LMP2011, the LM4130, and a precision 2.5 kil resistor creates an accurate and stable current
source.
The LMP2011 is a good operational amplifier choice for this application. The LMP2011 has
very low input offset voltage of less than I flY, with an offset voltage drift of only 15 nyrC.
These impressive specifications, along with the low input voltage noise of only 35 nY/-VI-h,
mean that the LMP20 II will introduce minimal noise to the overall system, allowing for a much
more accurate measurement.
The RTD is shown with a 4-wire Kelvin connection. The current flows through the force leads
while the sense leads, which are precisely connected to the active resistor element, connect the
voltage that is across the resistor to the signal amplifier.
Note that the RTD signal has three components: the temperature signal represented by change in
resistance, an offset voltage due the non-zero resistance at the starting temperature, and a
common-mode signal of 2.5Y due to the current sense resistor.
RTD with Amplifier
R4 R3
10kO 10kO
Av=(1 +2R5/R7)(RlIR2)
~ National
()I'Semiconductor
Th,Sight&SOllndoflnform,riOfl
The RTD signal is being scaled to 2.5V full scale and the required gain is 7.58. See the previous
slide for the calculation. Three LMP20 II amplifiers are used to build an instrumentation
amplifier with a fourth LMP2011 used to buffer the reference voltage. The LMP2011 provides a
very high CMRR and low offset voltage and drift.
The LMP2011 is the single amplifier in a family which includes the LMP2012 dual and
LMP2014 quad precision amplifiers. Any combination of the single, dual, or quad amplifiers can
be used in this application, depending on available board space.
Thermocouple Interface
Chromel - Alumel thermocouple

sensitivity = 38.81J.VrC
Temperature range to measure

= 50°C to 850°C
Thermocouple output - 0.97 mV

Amplified to 32.01 mV
Thermocouple
Output
Scale to ADC full-scale input with
Av = xRlR VREF = 2.048V using a differential
amplifier.
Al = lMP7701
Thermocouple wire picks up common-mode
noise from environment Av = 2.048/0.032 = 64
For R = 2 kO ideal xR = 128 kO
Nearest 1% value = 127 kO
Actual gain - 63.5 ± 1.3
dNational
l'"
Semiconductor
nr, Sighr & Sound of Inform,bon
Here is an example of a thermocouple amplifier. The thermocouple has a low source impedance
so a single differential amplifier can be used. The differential amplifier is used to remove
common-mode noise that the wires pick up from the environment.
The thermocouple has a full-scale output of 32 mV in the temperature range of interest, and it is
desired to scale this to 2.048V full scale. The required ideal gain is 64.
Also shown is an LM35 being used to measure the cold-junction reference temperature. The
amplified thermocouple signal and the LM35 output go to an ADC for conversion.
The LMP7701 is a single precision operational amplifier with very high DC precision, offset
voltage of only 37 IJ.V,with an offset drift of 1 IJ.VI"C,and a GBW of 2.5 MHz. This amplifier
can be used in higher gain settings without losing accuracy or running out of bandwidth.
pH Electrode Interface
IIY
110
NIl
UIl Maximum output voltage range
IIlI = -0.51828 to 0.51828 V
ZIO Requirement
1.
I Shift signal: O.OV sensor signal
••
ZIO
= y, ADC input range
••
UIl
Scale signal: 1.03656V sensor signal range
to ADC input voltage range
NIl
••
~ National
Ii" Semiconductor
a
Th. Sight Sound ",lnIr;Hm,bon
pH electrodes are used to measure the pH of a solution. The graphs above show the physical
relationship between the pH of a solution and the output voltage of the pH electrode and its
temperature dependence. The source impedance of the pH electrode is typically I060 to 1070.
For most practical uses, the pH electrode must be buffered before driving the cable to the
measurement instrument. Additionally, to obtain an accurate measurement of pH, the
temperature of the pH electrode must be known.
Note that the output signal is bipolar and will require level shifting to be used in a single supply
system.
pH Electrode Interface Ex1
Single supply
pH electrode
buffer with
temperature
compensation
pH electrode's
output is shifted
positive by O.5012V
R2
10 kG A1 and A2 = LMP2011
OR
LMP7701 (different pinout)
~ National
PSemiconductor
Th,Sight&Soundoflnfofm'fion
The output voltage of a pH electrode is high enough to use without additional amplification. In
this single-supply circuit, the pH electrode is offset by a little more the O.5V by amplifier AI.
The second amplifier, A2, buffers the output of the pH electrode and drives the ADC. This
circuit shifts the bipolar pH electrode signal to a unipolar signal for use in a single supply
system.
The LM35 is used to measure the temperature of the electrode so a temperature corrected pH
measurement can be taken.
pH Electrode Interface Ex2
pH Electrode Temperature
Dual supply
+V
pH electrode
amplifier with
temperature
compensation
pH electrode's
output is amplified
by two and shifted
positive by 1.024V
A 1 and A2 = LMP2011
OR
LMP7711 (different pinout)
~ National
P Semiconductor
T1l,Ssllhr&Soundoflnform,tKHl
In this circuit, the pH electrode is amplified and level shifted. The amplifier Al has a gain of two
in addition to providing a high input-impedance buffer to the pH electrode. Amplifier A2 does
the level shifting function so the signal is unipolar.
LMP77 11 is a precision single operational amplifier with a high gain bandwidth of 17 MHz and
very low voltage noise of 5.8 nV/-YHZ at I kHz with a corner frequency at 400 Hz. These
characteristics along with an input offset voltage of only 20 /lV and offset drift of I /lVre make
this op amp ideal for precision applications. Both the LMP20 11 and LMP7711 are excellent for
this application.
The LM35 is used to measure the electrode temperature.
~National
PSemiconductor
Stability Issues
Oscillators don'tl
Amplifiers do!
Graphical Stability Analysis 1
" CASE 2:
,/~UNSTABLE
• A and 1/F plots and where
.' they intercept each other
/
include all information
necessary to say if a c1osed-
\.1 loop circuit is stable or not
F
and to what degree!
• Case 1 is "stable" and Case
2 is not.
~National
P Semiconductor
1h.SighriSoundrtflnform,tJon
It is possible to look at the stability of a closed-loop amplifier (or any feedback circuit) by
analyzing the behavior of the forward path ("A" or open-loop gain plot) alongside the feedback
factor (lfF) as shown above.
As you may recall, instability at any frequency occurs when the there is a gain of ~I around the
loop with 180 of phase shift at that frequency. So, it is reasonable to see that stability involves
0
both the forward path (A) and the feedback path (F) information (both gain and phase). The
closed-loop transfer function denominator, in both inverting and non-inverting configurations, is
I + AF, where both A and F are complex numbers (magnitude and phase) and frequency
dependent. It is easy to understand that having the denominator approach zero is a bad thing and
in most real circuits, when this happens, the circuit breaks into oscillations.
Mathematically, that is the same as the term AF becoming I in value, because AF with a value
of I and 1800 phase is the same as a real number of value -I. If I + AF = 0 at a frequency where
A = IfF, oscillations can occur.
This means that the stability condition stated above is nothing but observing the phase shift
around the loop when the two curves (A and IfF) intercept each other. If there is less than 180 0
of phase shift, the oscillation criteria is not met and things are (almost) OK. Looking at the
above diagram, with A and IfF plotted, a single pole or zero at any frequency produces a 450
phase shift at that frequency, a 900 phase shift, and a 20 dB/decade change in the slope of the
curve above that frequency. It is easy to decipher the phase information based on the gain plots
shown above. In a nutshell, if the two curves approach each other at a rate of closure greater
than 40 dB/decade, then there is chance of oscillation. The following foils explain further. For
the plot shown, Case I will be stable and Case 2 will not.
Let's see why that is.
Determining the Feedback Function
• Expand the circuit to see what

portion of output is fed back to the
differential inputs
• Replace sources by their equivalent

impedance
• Apply circuit analysis techniques

(e.g. Laplace, etc.) and simplify
assumptions to arrive at the results
~National
P Semiconductor
Th,S,ghraSoundoflnfomllJfion
Let's look and see how the feedback factor is determined for an arbitrary circuit.
The IfF function referred to in the last slide is the ratio of what is fed back to the amplifier's
inputs from the amplifier's output. In the diagram shown above to the left, that would be
F = (VA - V B)N o'
To be able to do stability analysis, graphical or otherwise, it is essential to be able to come up
with the F function expression. It is easier to do so by expanding out the whole circuit as is done
here to the right. Done this way, you can see that coming up with F is an exercise in circuit
analysis techniques. Note that when doing this:
• The inputs have been removed and replaced by their equivalent impedance (ZGEN in this
case).
• This analysis will also work for two terminal devices.
• The calculation for F is for stability analysis only. This value will not arrive at the correct
closed-loop gain if substituted inside the overall transfer function.
Note that the expanded schematic is further simplified by swapping the position of ZID and ZE
blocks. This change does not significantly alter the final result (because of an op amp's high
CMRR) and thus simplifies the analysis as the voltage across ZID is now ground-referenced.
Graphical Stability Analysis 2
Cases 1 through 7 are variations of "1/F" function

Case 8 is variation on "A" relative to the original "1/F"
•..'1 National
Ii" n..Semiconductor
Sighta Sound of Infrmn,tJon
Notice that until now we have not done anything with the phase information of A or IIF. That is,
because the magnitude Bode approximations contain a lot of information about phase within
them.
Each break in the A or IIF magnitude plot corresponds to up to 90° of phase shift (either positive
or negative). Assuming the A and IIF plots look as shown for the case shown labeled as
"nominal," there will be complete stability. The horizontal axis show is of course log frequency.
The reason is that at the frequency of intercept, "A" dominant pole (not shown) would have
contributed to 90° of phase lag and the "IIF" is flat, corresponding to no additional phase shift.
So, assuming that the op amp's higher order poles are at least one decade beyond the intercept
point, this is a super stable case with up to 90° of phase margin. Most systems will not behave
this way, and even if they did, they will have non-optimized bandwidth.
The other cases shown will have other stability results. We will explore them in the following
slides.
Stability Case Study 1
Table 2: Stability Summary for the Cases Shown
Notes:
IP: Intercept point_ Rdtrring to the frequency wbere A and IIF intercept
FB: Fudback
PM: Phase Margin
Case Condition Estimated Loop Estimated Comment
• No FB phase shift
Phase(de
90
.) PM (d.g.)
90 Overdamped
~'ponu
FB pole at 0.3 decade above IP 90+27: 117 63 Stable
FB pole at 0.3 decadti beklw IP 90+63=153 27 C_lo
Instabili
FB pole at 0.3 decade below and 90+63-38:115 65 Stable
FB zero at 0.1 decade above IP
FBpolealmorelhan 1 decade 90+90=180 Unslable
below IP
FB pole al more than 1 decade 90+90-0=180 0 Unstable. The
below and FB zero at more than 1 FBzeroistoo
decacle above IP fSffromlPpoint
FB pole at more than 1 decade 90 .•90- 38:: 1-42 38 C_to
below & FB zero al 0.1 decade optimlmPM
above IP
""""pole at 0.5 decade above IP 90 .• 18" 108 72 Stable
log Axis Frequency Total Phase Total Phase

Distance Ratio below pole above pole
I (decade) I (zero)· (zero)
0 1.0 45 45
0.1 1.3 38 52
0.3 2 27 63
0.5 3 18 72
0.7 5 11 79
0.9 8 7 83
1.0 10 6 84 •..'1Nattonal
2 100 0.6 89 P Semiconductor
nt. Si{Jht a Sound of Inform,bon
The table to the top, Table 2, shows the stability result for each case shown. It uses Table 1,
bottom, to estimate the phase due to each inflection point (pole or zero) in order to arrive at the
total phase shift around the loop at the Intersection Point (IP). Note that in each case, IP refers to
when the A plot intercepts the IIF plot.
Let's take one of the cases shown and see if we can reconstruct the values shown in Table 2.
Stability Case Study Z
Log Axis Frequency Total Phase Total Phase
Distance Ratio below pole above pole
(decade) (zero) (zero)
0.1 1.3 38 52
0.3 2 27 63
Case # Condition Comment

~~~~:~~~gL~OP ~~I~:~e~
4 FB pole at 0.3 decade below 90 + 63 - 38 = 115 65 Stable
and FB zero at 0.1 decade
above lP
dNattonal
P Semiconductor
Th,Sighr"Sourldoflnform,tion
For example, let's take Case 4, which is highlighted from Tables 1 and 2 of the previous slide for
clarity:
As you can see, there are two inflection points on the IIF plot for this case. First is a zero at
about 0.3 decades below IP and second is a pole at about 0.1 decade above IP. Note that it is
assumed that the IIF plot is flat all the way down to DC below the first inflection point. The A
plot sloping downward at -20 dB/decade is indicative of one pole prior to lP. Taking a look at
Table 1 shows that the first IIF zero will cause an additional phase shift of 63° at IP frequency.
However, the IIF pole at 0.1 dB above IP is close enough to have its own effect at IP. Looking
up 0.1 decade in Table 1 shows that this pole will have a phase reducing effect of 38°. Taken
together, you will see the total loop phase is 115° corresponding to about 65°of Phase Margin
(PM).
Compensation Example ,
(Schematic and Compensation Defined}
•..'1 National
PSemiconductor
The Sight & Soundoflnformafion
Let's put to use what we have already discussed in a real application.

The LMH6624, a very low-noise, high-speed op amp, is used in an inverting unity-gain
application. However, the LMH6624 is optimized for bandwidth and is internally compensated
for closed-loop gains larger than 20 dB (10 VN). A well-known technique that allows the user
to compensate a non-unity gain stable part (such as the LMH6624) for stable operation at any
gain is the lead-lag compensation shown (due to the action ofRc, C, and Rp). The compensation
components added to the circuit allow the user to shape the feedback function to make sure there
is sufficient phase margin when the loop gain is 0 dB.
Let's see if we can take advantage of this technique using the LMH6624 at a gain lower than the
recommended minimum gain stated in the datasheet.
(LMH66Z4 Data}
iD
~
z 40
~
10k 100k 1M 10M
FREQUENCY (Hz)
AC)National
P Semiconductor
Th.Sighr&Soundoflnform'tlfJn
The LMH6624 datasheet shows the open-loop gain/phase that is invaluable in this situation
where we have to customize the circuitry around the part for stability. We will take advantage of
the data shown here in its simplified form and labeled as A. As you can see, the LMH6624 has a
dominant pole at around 100 kHz and a second one falls at about 100 MHz. Just looking at the
plot of A, you would be able to say that if the device is run at gains below about 20 dB (10 VN),
there is the possibility of instability, even if the feedback circuit adds no additional phase shift.
At exactly 20 dB, the phase margin will be around 45° (90 due to the first pole and 45 for the
0 0
100 MHz pole).

To tackle this problem using the techniques discussed so far, it is imperative that the "IfF"
function needs to be obtained before anything else.
(Feedbac/c Analysis}
where: R.., ~ (RI)(RF)

RI+RF
R.+1/
F = V"" = ( / sc )( Vn. ) fz= 1
Va (Rc+ Xd+Rno V.
2nC(R.+R,+R..)
F=( l+sCRc )(~)()«.) f,= 1

p 211CR.
1+sC(R.+ R,.+R..) RI+RF )«.
2. = (1 + RI') ( 1 + sC(R. + R,. + R •• ) )

F RI l+sCR. ~F If-O = 1 + RFRI
~Nattonal
()" Semiconductor
T"-Sighf4iSoumJoflnform_tIOn
Therefore, we will expand the feedback path as we had already discussed, as shown here. In
addition, we will swap the position of Rp and Rc, C combination in order to get the quantity in
which we are interested, the voltage across the Rc to C combination, ground-referenced to ease
calculations.
Calculation of F (and eventually IIF) becomes a task of solving for the voltage across the Rc, C
combination as a function of the output voltage, which we have done here using Laplace
transform arithmetic. Note that to simplify the analysis, the Thevenin equivalent concept is
employed making the calculation one of a simple voltage divider, as shown.
Eventually, the IIF function is calculated and its two inflection points are identified in the lower
right-hand comer.
Armed with this information, once the component values are known, the IIF gain Bode plot is
easily constructed. However, this example is not one of analysis, but rather it is a case that
involves synthesis. The information about IIF will be used in the next slide to allow good
engineering judgment in choosing the compensation components for optimum results.
Compensation Example 1
(Component Value Derivation 1)
1
fz = -- ~ lOMHz
211CR,
Rr R".+R...
f--+<n = (1 + -)( 1 ~ ---) =
~F Rl Rc
10k 100k 1M 10M
FREQUENCY (Hz)
dNational
P Semiconductor
Th. Sight & Sound of Information
This is the open-loop gain plot of the LMH6624 with the IIF function superimposed on top of it
for stability analysis.
• In plotting IIF, here are the criteria or requirements applied:
It is desirable to have the IP occur at 100 Ml:I; which is the op amp's second pole to get about
45° of phase margin.
• IIF pole must be at least one decade below IP so that the required 45° phase margin is not
degraded. Recall that if the op amp's second pole at 100 MHz and the IIF zero are less than
one decade apart, they will have some interaction and the phase margin will be less than
45° since the stability improving effect of the llF has not taken full effect by IP.
• IIF low frequency value is fixed by 1+ RF/Rl, which in this case will be 2 VNor 6 dB.
• As derived in the previous slide, IIF will have a lower frequency zero and a higher
frequency pole.
The criteria/conditions above, which are stated mathematically to the right, will result in the IIF
shape shown. You will notice that two cases for IIF are shown. To minimize output noise, case I
is the preferred IIF plot, as it minimizes the op amp's input-noise voltage gain increase due to
the zero in the IIF function. This mayor may not be important for the application, but it is
something to note here. We will assume it to be of importance in this case. In addition, it is
always the best practice to preserve loop gain as much as possible, and case I again does that
better than for example case 2. So, that means we would like to set the IIF zero at exactly one
decade below 100 MHz (or 10 MHz). At this point, we are ready to pick some component values
and derive the other ones to satisfy these requirements.
(Component Value DerivationZ)
fz = _1_ ~ lOMHz Design C Comments
211CR. # 'oF ~\ ~l
k ~+&. 1 100 160 Rp negative because Rc
f-+",~(l+-)(I+--)~ IOV!V is too low
F
~ Rl Rc 2 47 340 360
3 27 590 1.36k
4 10 1.6K 5.4k
10k 100k 1M 10M
FREQUENCY (Hz)
•..'1 National
Ii" Semiconductor
The Sight& Soundoflnform'fion
Many values of C, Rc, and Rp can be picked to satisfy both conditions stated in Equations (I) and
(II) above.
To reduce the effect of shunt capacitance across critical resistors for high-frequency operation,
let's keep the values of RF below 2 kil. Note that RF and R1 are equal for a gain
of -I. IfRF= R1 = 2 kil ~ Req = I kil.
In the table shown, you will see that one way to do this would be to start with a value for
C and then from that, you would be able to determine the Rc that would put the IIF zero at
10 MHz (or Equation I above). With C and Rc known, Equation II dictates the value of Rp to
meet the IP gain requirement.
As you can see, starting with C = 100 pF results in a value for Rc that is too low to result in a
real value for Rp. So, to increase Rc, it is obvious that C would have to decrease. Therefore, you
see that subsequent attempts all result in real values of Rp and are, therefore, all viable. Now the
question is, which of these values to choose? Obviously, Design 2 through 4 will all work.
However, it is best to avoid extreme values. In this case, Design 4 is probably not the best choice
because with C at 10 pF, you start approaching parasitic capacitance levels on the board and
active components. So, both Designs 2 and 3 are viable first choices.
Because compensation almost always requires some sort of "fine tuning" to arrive at the most
optimum results, it is always desirable to have a means for varying it. You will note that varying
C will move IIF pole and zero proportionately. Therefore, replacing C with a trimmer cap will
allow for easy fine-tuning by moving the pole and zero values in tandem while changing the
relative position of IIF zero to the op amp second pole. This will allow the fine-tuning of the
phase margin for best results.
Bench Evaluation and Fine Tuning
Oelilgn
".;, ...n Comments
•
1
fDFI
100 160 R alive because is too low
2 47 340 360 "
3 27 590 1.36k
4 10 Uk 5.4k
Unccmpenstl!ild
Refl +Over VI
56.8 %
~NatiQnal
(ill'Semiconductor
Th,S,gllt&Soundoflnform,tion
Here are the actual results of bench testing with the just-derived component values.
As expected, the top waveform highlights that with no compensation, the step response shows
ringing and almost 50% overshoot. From the previous slide, Design 2 values (highlighted in the
table shown) were then employed with the results showing a reasonably well-behaved step
response in the bottom scope photo. The overshoot is measured to be less than 10%. Note that
the closest 5% resistor values have been used instead of the exact values in the table.
To explore the effect of reducing the value of C, the center scope photo shows that when this
capacitor is reduced to 10 pF, as expected, the overshoot increases and the system will have less
than the originally stated goal of 45° phase margin.
Steps to Stab;l; ;ng a Closed-Loop
Feedbac/c System
• Solve for the component values that allow

the stability criteria to be met
~National
()" Semiconductor
Th. S"hta SoumJoflnfonJl.fJDn
We were able to analyze and design a stable closed-loop system by employing our knowledge on
how the feedback network operates and keeping track of gain and phase around the loop. To do
so, we had to use the published data on the active device in the loop, as well as general circuit
analysis techniques. The graphical method described was a simplification that allowed insight
into the process, which is more than one would get by using computational or hand-calculation
analysis.
Once the forward- and feedback-path gains are known and plotted, the designer would be in a
position to decide on the best placement of the poles and zeroes from the compensation scheme.
Having done so, he can put together expressions that define the constraints placed on the pole
zero placement. At this point, one can evaluate the component values that meet the criteria. And
finally, it is always necessary to evaluate the theoretical calculations by making actual
measurements on the bench.
~National
PSemiconductor
Practical Techniques to Avoid

Op Amp Instability Due to
Capacitive Loading
Driving Capacitive Loads
r
~NatiQnal
li'" Semiconductor
The Sight & Soufldoflnformation
Capacitive loads are not a matter of choice. In most cases, the load capacitance is not from a
capacitor added intentionally, but from things such as PC board traces and coaxial cables. For
example, PC board traces have capacitance approximately equal to 22 pF/foot for a 0.025" trace
using G-lO dielectric of 0.03" over a ground plane (System Application Guide, Analog Devices,
1993), while a coaxial cable will appear capacitive at the rate of 29 pF/foot for R6-58NU, a
commonly used coaxial cable.
Applications such as sample-and-hold amplifiers and peak detectors require the op amp to drive
large capacitive loads, besides the board traces and cables. Some applications may require the
amplifier to drive the input of another active device, such as another amplifier or an ADC.
Most op amps are designed to be unity-gain stable for moderate capacitive loads. The amount of
capacitive load an amplifier can handle varies. For example, the LM6211 is designed to be unity-
gain stable for capacitive load of 100 pF. That is, if connected in a unity-gain, non-inverting
buffer configuration, the LM62 11 will not oscillate if the capacitive load is 100 pF or less.
Oscillations may occur for higher values of capacitance because amplifiers have an open-loop
output resistance Ro. The presence of CL provides an RoCL low-pass filter that introduces phase
lag in the output voltage. This increased phase shift reduces the phase margin of a feedback
circuit. If there is a significant reduction in phase margin, the transient response will suffer
greatly, or the amplifier may be unstable when a large capacitive load is in place.
Amplifiers cannot be designed to be stable for high capacitive loads without either sacrificing
bandwidth or supplying higher output stage bias currents. The LM6211 needs to be externally
compensated to optimize those applications in which a large capacitive load must be handled at
the output of the amplifier.
Amplifier Susceptibility to
Capacitive Loads
50
40
~
z 30
(;
a:
20
~
w
(/l
~ 10
a..
·10
10 100 1000
CLOAn (pF)
d National
(il'Semiconductor
Th. Sight" SoumJ 0' l"rorm,tJOfJ
This graph shows the variation of the phase margin with capacitive load for the LM62111.
The phase margin of an amplifier circuit can be thought of as the amount of additional phase
shift at the unity-gain loop frequency of the amplifier required to make the circuit unstable (i.e.,
phase shift + phase margin = -180°). As the phase margin approaches zero, the loop phase shift
approaches -180° and the amplifier circuit approaches instability. Typically, values of phase
margin much less than 45° can cause problems such as "peaking" in the frequency response and
overshoot or "ringing" in step response. In order to maintain conservative phase margins, the
pole generated by capacitive loading should be at least a decade above the circuit's closed-loop,
unity-gain bandwidth. When it is not, consider the possibility of instability.
Effects of Capacitive Loading
on Amplifiers
o-ct?:n: R2
NOISE GAIN c 1 + R2
R1
GAIN
(dB)
.:JNational
(II" Semiconductor
The $ight& SOlllldoflnformation
Many designers overlook a powerful way to maintain stability in low-frequency applications

which involves increasing the circuit's closed-loop gain (also known as noise gain), thus
reducing the frequency at which the product of open-loop gain and feedback attenuation goes to
unity.
By increasing the noise gain of the circuit, the unstable situation on the left can be changed to the
case on the right, where the intersection of the noise gain plot and open-loop gain happens in the
stable region of -20 dB/decade.
Although stability can always be achieved by this method, the bandwidth available to the signal
is concomitantly reduced.
Compensating by External Resistor
R1SO
VOUT
V1N
Cc
I
.•.'1 National
~ Semiconductor
Th. Sight" Sound of InfomYtJOn
In some applications, it is essential to drive a capacitive load without sacrificing bandwidth. In

such a case, in the loop compensation is not viable. It is possible to use low-phase margin op
amps to drive heavy capacitive loads. A simpler scheme for compensation is shown. A resistor,
R1so, is placed in series between the output of the amplifier and the load capacitance. This
introduces a zero in the circuit-transfer function, which counteracts the effect of the pole formed
by the load capacitance and ensures stability.
The value of R1so to be used should be decided depending on the size of CL and the level of
performance desired. Values ranging from sn to son are usually sufficient to ensure stability. A
larger value of R1so will result in a system with lesser ringing and overshoot, but will also limit
the output swing and the short-circuit current of the circuit.
Dealing with Load Capacitance
(LMV791)
80 100
80
60 60
40
co 40 20 ,
~ w
z 0 (J)
~ <:
I
C> 20 ·20 Q.
·40
0 ·60
·20
1k 10k 100k 1M 10M
FREQUENCY (Hz)
•..
'1
l'" National
Semiconductor
The Sight & SQund of Information
This graph shows how the isolation resistor can improve the performance of an op amp while
driving heavy capacitive load. In this example, the gain and phase margin for the LMV791 was
plotted versus frequency. The solid lines show the gain and phase margin of the LMV791 with a
capacitive load of 500 pF, which leaves the op amp with zero phase margin, meaning that the
device will be unstable. The dotted line shows the plots after inserting an isolation resistor of
soon. Adding the isolation resistor restores the phase margin to 40°, and the op amp is again
---r t::=--
stable. ~ - 1. J
~~ ~ Lt:/ ~O·
~
F
-----------
In The Loop Compensation
Rs::::ROUTR1N
RF
CF= [RF + 2RIN] CLRour

RF2
dNattonal
P Semiconductor
Th, Sight & Sound of 'nform,llfm
This circuit illustrates another compensation technique, known as in the loop compensation. This
technique employs an RC feedback circuit within the feedback loop to stabilize a non-inverting
amplifier configuration.
A small series resistance, Rs, is used to isolate the amplifier output from the load capacitance CL,
and a small capacitance CF is inserted across the feedback resistor to bypass CL at higher
frequencies. The values for Rs and CF are decided by ensuring that the zero attributed to CF lies
at the same frequency as the pole attributed to CL. This ensures that the effect of the second pole
on the transfer function is compensated for by the presence of the zero, and that the ROC is
maintained at 20 dB/decade. For the circuit shown the values of Rs and CF are given by
equations on the right.
Calculating Rs and CF (LM6211)
r~~..,...
~
CL (pF) Rs (In) CF (pF) Phase Margin (0)
250 60 4.5 39.8
300 60 5.4 49.5
500 60 9 53.1
.•.'1 National
~ Semiconductor
The$ight&SQundoflnform/ltion
Although this methodology provides circuit stability for any load capacitance, it does so at
the price of bandwidth. The closed-loop bandwidth of the circuit is now limited by Rs and
CF·
This table shows different values of Rs and CF that need to be used for maintaining stability
with different values of CL> as well as the phase margins to be expected. RF and RTN are
assumed to be 10 kil, RL is taken as 2 kil, while RouT is taken to be 60il.
Stability and Input Capacitance
• • - .....
.........•
I
I
, ,
••
: R2 ••
I
•
+
VOUT
dNational
l'"
Semiconductor
Th,$ight&SoundoflnfOfm,tif1/l
In certain applications, such as I-V conversion, trans impedance photodiode amplification, and
buffering the output of current-output Digital-to-Analog Converters (DACs), capacitive loading
at the input of the amplifier can endanger stability. The capacitance of the source driving the
amplifier, the op amp input capacitance, and the parasitic/wiring capacitance contribute to the
loading of the input. This capacitance, C1N>interacts with the feedback network to introduce a
peaking in the closed-loop gain of the circuit, causing instability.
This peaking can be eliminated by adding a feedback capacitance, CF>as shown. This introduces
a zero in the feedback network, and, hence, a pole in the closed loop response, and thus
maintains stability. A simple approach is to select Cr = (R/R2)ClN for a 90° phase margin. This
approach, however, can limit the bandwidth excessively.
~National
PSemiconductor
Open-Loop, Closed-Loop, and

Programmable Gain Buffers
Defining a Buffer
High input impedance Consider the circuit: +
R,
Unity gain (usually, but not 20kO va= Vs
always)
Low output impedance
• Large current gain
Large output current drive
(usually larger than an op amp's)
Stable when driving large and
varying capacitive loads
High speed/wide bandwidth
Low operating current
Low noise
Low distortion
d National
~ Semiconductor
Th. Siflht & Sound of Inform,tion
In this slide is a list of some of the desirable, and attainable (non-ideal), buffer traits that help to
define a buffer for a given application. Usually, only a few of these parameters are critical for
any given application. No buffer can do all of these things well, and trade-offs will always be
part of the process. That said, there is nearly always one trait that is critical in any application
where a buffer is used and which really defines what we mean by the idea of a buffer. That trait
is the ability to isolate a source from a load. The measure of how well a given buffer can do this
is embodied in its input impedance and output impedance specifications. As can be seen from the
(ideal) circuit specification on the right, a buffer with an input impedance less than infinite would
load the source and attenuate the input signal to one degree or another, while an output resistance
of more than on would reduce the effective output swing, thus providing less than Vs to the
load. The ideal buffer for the example above provides a gain of I with infmite input resistance
(does not require any input current), has zero output resistance (can drive any desired load
resistance without loss of signal voltage, ergo unity gain), and therefore, provides a tremendous
impedance-level transformation while maintaining the level of the signal voltage. How far the
results are from these ideals will depend upon the application and the choice of buffers.
However, the fact that real buffers don't approach these ideals makes them no less useful.
Because many transducers represent high-source impedance, a unity-gain buffer is found in
many sensor and data-acquisition applications.
• For an impedance transformation from a high
impedance source to a low impedance load, such as
driving a coaxial cable (Matching)
• To minimize the influence on a signal source

(oscillator, sensor, sample and hold, filter, etc.), of a
varying load impedance such as that found at the
inputs of l1L and flash ADCs (Isolation)
• To boost the drive capability of an op amp or other

device (Current Gain)
• To distribute stable, clean signals through

transmission lines or on PC boards or to external
equipment (Matching, Isolation, Current Gain)
.:JNattonal
P Semiconductor
Th. Sight a Sound of Inform,don
For a case where a signal source does not have a low enough output impedance to drive a load,
one can increase the output drive capability by using a buffer. For example, an oscillator might
experience an unacceptably high frequency shift or stop working altogether when loaded
heavily. A buffer is called for in that situation so as to isolate the load from the oscillator.
Buffers are very often used to drive (match) passive loads, such as terminated and unterminated
coaxial cables, as well as the metal traces (e.g., strip lines) on PC boards. But they also are called
upon to drive the signal inputs to other active devices (matching, isolation), such as ADCs. The
inputs to many ADCs represent a very large and varying reactive load at their input terminals.
For example, a flash ADC presents a large and non-linear capacitive load that is very signal
dependent. A buffer with a low output impedance and the ability to remain frequency stability
while driving a nanofarad or more is needed here. Pipelined ADCs also present a difficult
challenge to a buffer. These ADCs consist of differential inputs into an analog switch, followed
by a switched capacitor amplifier, and sample and hold. Besides seeing a purely capacitive input
impedance that changes with each clock cycle, the external input buffer must deal with large
voltage spikes that are caused by the large current pulses that occur when the internal sampling
switch opens and closes. The buffer must be able to absorb these spikes without distorting the
signal.
There are times when it is desirable to provide an op amp with more output drive (current gain)
than it can supply by itself. Any buffer can be put inside an op amp feedback loop. In this case,
the buffer solves the load drive problems, while the op amp maintains the low signal level
precision required. The op amp also can provide additional gain to the overall circuit. In
addition, the op amp is not affected by the heat dissipated in the buffer when driving heavy
loads, and thus does not experience any unwelcome thermal feedback problems. However, when
an op amp is placed inside the buffer/op amp loop, an additional phase lag, introduced by the
buffer, must be included in loop stability considerations.
Wider CL range capability
Fast slew rate/wide bandwidth
High output current drive
Simpler/less expensive
Shorter propagation delay
Fast slew rate/wide bandwidth

Lower distortion
Lower gain error/linearity
Better DC specs (VOFFSET, ROUT)
High output current drive

•..'1 National
P Semiconductor
Th, Sight & SDund of InforTn6&otl
By "dedicated," we mean amplifiers that are not a modified "something else." For example, they
are not op amps configured in a gain of I (this is possible, and is done, but can be expensive
and/or non-ideal for the task). But, by and large, unmodified op amps don't have the special
combination of qualities that make the best buffers. Dedicated buffers are components that are
designed expressly to isolate source and load.
Buffers have been around for many years in integrated circuit form, ever since National
Semiconductor introduced the LH0002 many years ago. They can be divided into two broad
classes: Open loop and closed loop. As a decision problem facing the designer, sorting out which
class to use in a given application can sometimes be confusing. Tradeoffs are inevitable.
To begin with, a closed-loop buffer is essentially an op amp that has been optimized for unity-
gain operation. Since it is internally compensated for unity-gain stability, it will, as a class, be
inherently slower than the open-loop variety (although exceptions abound). However, it will
generally have more accurate DC characteristics, display lower distortion, and have better gain
linearity. Still, the open-loop approach commonly allows for wider bandwidth, shorter
propagation delay, and greater stability over a wider range of capacitive loads. Also, their
simpler circuit topologies (basically they are glorified complementary emitter followers) make
open-loop buffers a cheaper alternative. Still, when it comes right down to it, the objectives of
the application circuit will dictate which type to go with.
If our buffer were perfect, it would display zero output impedance at all frequencies of interest,
infinite input impedance (0 input current), infinite bandwidth and slew rate, and a voltage gain of
precisely I (output = input). Failing to attain those lofty goals, to one degree or another, we will
settle for a buffer that has a measurably insignificant effect on the fidelity of the signal and gets
along with its fellows (doesn't load its sources while presenting an essentially low-impedance
voltage source to the load).
LMH6321 LMH6559 LMH6560 LMH6739 LMH6718 LMH6704 LMV115
Parameter Units
Single Single Quad Triple Dual Single Single
DC Output Current
:t300mA ±74 mA ±74 mA t90 mA t170mA :t90mA t205 ~A
ContInuous
Peak Output Current t570 .83 .83 t160 NlA N/A N/A mA
Slew Rate 1800 4580 3100 3300 400 3000 18 V/~s
Bandwidth, 3 dB 110 1750 680 750 110 650 31 MHz
Voltage Gain 0.91 0.996 0.995 Programmable Programmable Programmable 0.998 VN
Input Offset Voltage
Input Bias Current

±3
±2
.3
·3
.2
·5 ..
to.5
1000; non-
to.6
to.6
2
.5
1000; non-
3.5 mV
"A
Input Resistance 250 200 100 380 65 kn

invertin a inDut inverting input
Output Resistance 5 1.3 1.• 0.05 0.28 0.05 61 n
MInimum Load Resistance 50 100 100 100 100 100 50k n
Power Supply Current 15 10 11.51buffer 10.7/butfer 2.4/buffer 11.5 0.3 mA
Open Loop
'" - - - - - - -
-
Closed Loop
'" '" '" '" '" '" '"
•..'1 National
Ii" Semiconductor
TheSighf&SQundQflnfQrmatiQfI
The characteristics of a selection of National's buffers are summarized and contrasted in the
table above. While these particular tests can be considered relevant to buffers in general, only a
few will be considered critical for a given application. The suitability of a particular buffer is
usually determined by, at most, three or four key specifications, and perhaps one or two 'would
love' capabilities as well. For example, the demands on a coaxial cable driver become more
severe the faster the signal becomes. Thus the most vital considerations for the buffer would
probably be output current drive, slew rate, and bandwidth capabilities. These are common
requirements for all such applications. However, in a field of several competing buffers, where
all adequately meet these requirements, the best choice might be the one that has the lowest THD
+ N or the best gain flatness. Some buffers that are designed for specific markets have been
optimized for certain key parameters of that market. For example, the LMH6739 specifies
differential gain and differential phase, two parameters that have not commonly been specified
by buffers, but which nevertheless are of paramount importance in analog video systems, where
this buffer finds use. While most of the buffers presented here are intended for use alone, or in a
closed-loop combination with op amps to drive coaxial cables and capacitive or other moderate
to high-current loads, the one exception is the LMV 115. This buffer is specially designed as an
oscillator buffer to reduce the effects of spurious signals from the baseband chip to oscillator (in
such portable applications as cellular phone, GSM modules, and oscillator modules) and to
isolate the oscillator from the effects of varying load capacitance and resistance. In these portable
applications, low supply current is more important than speed or output current.
Although the term buffer is largely accepted to mean a device that supplies current gain but no
voltage gain, some applications require that the buffer allow for some voltage gain adjustment
(e.g., -1 to +2) while still performing the essential function of isolation. Three of the buffers
(LMH6739; LMH6718; LMH6704) have this gain feature. The rest are configured internally to
provide a gain of one.
"Classical" Open-Loop
Buffer Architecture
Signal path for positive

going signals
Signal path for negative

going signals
~ National
P Semiconductor
Th,Sil1hf&Soundoflnform,Dr)n
The circuit shown above is the classical embodiment of the open-loop buffer, as first developed
in the prior industry standard, the LH0002. Therefore, the LH0002 is a good starting place for
which to understand this class of buffer. The input stage consists of complementary bipolar
emitter-followers, Ql and Q2. The symmetrical class AB amplifier output transistors, Q3 and
Q4, provide current sourcing or sinking and a relatively constant low impedance to the load. Ql
and Q3, along with Q2 and Q4, make up symmetrical compound emitter-followers with a small-
signal current gain of approximately 40,000 (product of first and second stage betas). This
combination of cascaded emitter-followers will produce close to unity-voltage gain.
Input stage operating current is determined by Rl in conjunction with supply and input voltages.
The emitter-base junction of the first and second stages appear in series between input and output
terminals, therefore the output offset voltage for VIN = 0 is the difference in base-emitter junction
voltages of the PNP and the NPN transistor. This is true for both upper and lower halves of the
circuit, so there is no conflict between the two circuit halves. Output stage quiescent current will
equal that of the input stage if the transistors are matched and at equal temperatures. This
establishes a class AB bias in the output stage so there is no class B crossover distortion in the
output. Resistors R3 and R4 inserted in the output emitter circuits minimize the effect of
unmatched upper and lower circuit halves and limit the potential for thermal runaway due to
input and output stage temperature differences.
llC/assica/" Open-Loop
Buffer Architecture
For the basic circuit the operating cu"ent Is determined by R1

In conjunction with supply and Input voltages
Vs - VB" - V/N
le= Rl
Maximum output curr-ent is dependent on the supply voltage,

R1, Q3 current gain, and the output voltage
Vs - VB'" -loR, - Vo
IO{MAX)= Rl / p, (2)
VS-VSE3
=Rl/ p, + R3 +RL
Gain expression written as • function of load resistance and
I
input voltage is:
RL RL
Av" RL+R3+r" - R3+RL(I+ O~~6) Vw>OlV (3)
Vr
where '.:l ""-,;; ,and P3 .. 200
note that O.026V" thermal Yoltage, VT, at 25°C
~National
(II" Semiconductor
Th. Sight & Sound of Inform,bon
Maximum output current is dependent on the supply voltage, RI, Q3 beta, and the output
voltage. Maximum current is available when V IN rises sufficiently above V OUT that QI is cut off.
Under this condition, RI supplies base current to Q3, and maximum output current is given by
Equation 2.
The voltage gain is slightly less than unity and is a function of load. It is dominated by the finite
output resistance of the output stage. Hence, the gain analysis can utilize the hybrid model. Note
that re3 is the emitter dynamic resistance of Q3 and is load-current dependent. The gain
expression written as a function ofload resistance and input voltage is shown in Equation 3.
When it was introduced, the LH0002 represented a quantum step in IC buffer design. However,
it had two major compromises in its design. The first compromise can be understood by referring
back to the previous slide.
Compromise 1: Transistors Q3 and Q4 are made relatively large to provide the desired output
current. Thus, the major frequency limitation is present at the bases of these transistors
(collector-base capacitances of QI - Q4). Q3 and Q4 are turned on by the current flowing in
resistors RI and R2, respectively. Since the resistance values are established by the quiescent
operating current (they are typically about S kn), they will limit the turn-on current to the output
transistors. Turn on would be improved if these resistors were made smaller, but this would
increase quiescent current and input bias current. Thus a speed/power trade-off is created.
Compromise 2: In terms of small signal behavior, the LH0002 could typically attain small signal
bandwidths of about 30 MHz when using a son load and a 100 mV signal. This was possible
because the LH0002 used hybrid (discrete transistor) construction. The PNP transistors used in
monolithic integrated circuits have poor high-frequency performance relative to the NPNs,
because of longer base transit times and lower carrier mobility. Thus discrete, vertical PNP
transistors were used.
The LMH6321: An Improved
High-Speed, Open-Loop Buffer
Key Features (Typical values)

• High slew rate -1800 V/'tJsinto 500
-2900 V/'tJsinto 1 kO
Wide bandwidth: 100 MHz
Continuous output current: ±300 mA
Wide supply voltage range: 5V to ±15V
Programmable current limit
• High capacitive load drive
Thermal shutdown error flag
Packages: PSOP-8 and T0263-7
Applications: line driver, pin driver,
sonar driver, high density buffering
•..'1 Nati 0 n a I
(:;9 Semiconductor
Th, SiQht & SOIJrld of Inform'tiCIn
New buffer: It was desirable to manufacture a fully monolithic version of such a buffer, but with
none of the previously mentioned compromises. It would be possible to eliminate Compromise 2
provided a suitable monolithic PNP device were developed and Compromise 1 eliminated with
design enhancements. With the development of National's patented Vertically Integrated PNP
(VIP) process, anew, improved version of the venerable LH0002 was created. The VIP process,
which includes trench isolation rather than junction isolation, allowed for the creation of
complementary NPN and PNP transistors on the same die with greatly improved transition
frequency (F ) performance. This new buffer is called the LMH6321 (simplified diagram shown
above), with the H in the prefix standing for high speed. The LMH6321 has performance of
• >100 MHz GBW
• 300 mA continuous output current drive capability, 700 mA peak
• Slew rate = 1800 V/flS into a son load
In addition, the LMH6321
• is stable driving any capacitive load
• allows for external programming of maximum output current with just one resistor
• comes equipped with an error flag
• has on-chip thermal shutdown in the event of a sustained short circuit to ground
The LMH6321: An Improved
High-Speed, Open-Loop Buffer
V+
Q3
R3
20
VI VOUT
R4
20
Q4
~ National
P Semiconductor
The Sight& SounrJoflnformetiQn
The input to the driver stage includes active-load devices cross-coupled to the output stage inputs
so that the output stage is bootstrap driven from emitter followers. The circuit is biased by level
shifting means (II> 12, Dl - D4) to operate as a class AB current amplifier. Each of the bases of
the output transistors is returned to its collector supply by way of an active load transistor (Q5,
Q6) that is connected as an emitter-follower to drive the opposite half of the circuit. Thus, the
active load devices have their inputs cross-coupled to the input transistors and effectively
bootstrap the output transistor drive. This means that the output transistor base capacitances are
both charged and discharged through active transistors, and the circuit is thereby sped up in its
signal drive operation. Complementary transistors Q5 and Q6 are connected as the active loads
for transistors Ql and Q2, respectively. They are connected as emitter-followers that are
bootstrap-driven by cross-coupling from the complementary or mirror image of the circuit.
Resistors Rl and R2 have low values selected to determine the circuit quiescent current and
improve stability with capacitive loads. Each of the bases of the output transistors (Q3 and Q4) is
charged and discharged by means of an active transistor that quiescently carries much less
current than the amount needed to drive the output transistors quickly on and off under
conditions of output loading. Thus, the compromises required in the LH0002 are avoided.
When more output current is required from an op amp, a wide band unity-gain buffer can be
included in the feedback loop. This has the added feature of improving an open-loop buffer's DC
performance (i.e. gain linearity, gain error, offset, output impedance, etc.) due to the very large
loop-gain of the combination. In addition, the op amp is not affected by the heat dissipated in the
buffer while driving heavy loads, and thus does not suffer the negative effects of thermal
gradients on its low-level input stage. However, adding a buffer to the feedback loop will add
another pole (phase lag) to the response. If the unity-gain crossing of an op amp is near the GBW
of the buffer, the over all phase lag of the circuit will consume most, if not all, of the available
phase margin, and oscillation will occur. For this reason, it is important to use a buffer with a
GBW significantly larger than that of the op amp, so that loop performance will be determined
solely by the op amp.
Buffered Op Amp Loop
Using the LMH6321
..
C1
~
l lEXT
Isc (output short circuit
I
I
I
<~ Load
~ .• impedance
I
I
I
*""
~Nattonal
P Semiconductor
nt,SiQht'Soundoflnform.t1on
Compared to most general-purpose, precision, and low-power op amps, the bandwidth of these buffers is
so great that the op amp totally controls the loop stability. Ifa wideband op amp is used, the phase margin
and open-loop frequency response can be altered by the additional pole(s) contributed by the buffers, and
this should be taken into consideration. The buffer phase shift is algebraically summed with the op amp
phase shift and may cause a stable op amp loop to become marginally stable (large overshoot, ringing),
depending on the relative positions of the op amp and buffer poles. In the application above, the LM8261
op amp has a GBW of 15 MHz, while the -3 dB bandwidth of the LMH6321 is greater than 100 MHz.
The LMH6321 buffer has two features not found in most buffers of its class, namely a programmable
output current and an Error Flag (EF) pin. The LMH632I provides an open collector output at the EF pin
that produces a low voltage when the thermal shutdown protection is engaged due to a fault condition.
Under normal operation, the EF pin is pulled up to V+ by an external resistor. When a fault occurs, the EF
pin drops to a low voltage and then returns to V+ when the fault disappears. This voltage change can be
used as a diagnostic signal to alert a microprocessor of a system fault condition. Thermal shutdown can
occur due either to improperly heat sinking the buffer or from an extended short circuit condition, or both.
The output current can be programmed by a single external resistor and voltage source for up to 300 rnA
of continuous current. This current is accurate to 5 rnA±5%. The value of the resistor for any program
voltage and output current 1SC' is
REXT = 400V PROGIISC
Keep in mind that the LMH6321, like all high-current buffers, must be attached to a heat sink when
driving heavy loads that can push the junction temperature above the operating range of the device. The
datasheet for this part gives detailed advice on how to do this by using the copper area of the PC board as
a heat sink. Resistor Rl is recommended as a protection for the input stage of the LMH6321 in the event
of an input/output differential voltage of greater than 5V. This can happen with an output short to ground
while driving the inputs to ±15V. Capacitor Cl is a feed-forward cap to compensate for the pole created
by the buffer's input resistance and capacitance. Thus Cl is given by
I Closed Loop I I Open Loop I R, Zo-50nnso
Best suited for -7 50nJ750 750 500
LMH6559 (;;) LMH6321 (;;) RL-Zo

50017'"
LMH6560 (;;) yO'

R, "0-"'017'"
LMH6718 (;;) R,.

•
fil RC
-
"o
50017'"
LMH6704 (;;) •
LMH6739 (;;) • I REO = Rs +RtfN I
•
I Rs = ZOo NR DR
I
CablelTransmission Line Distribution
The 750 termination implies an RGB video
distribution system
.•.'1Natt 0 na 1
~ Semiconductor
T"- S'rlht" Sound of 'nform,fJon
When driving multiple transmission lines, the load presented to the driver is REQ, above, where
(assuming all transmission lines have the same impedance):
REQ = equivalent load seen by the line drive Rs = source terminating resistance
RL = load terminating resistance N = number of transmission lines
The buffers suggested here are single, dual, triple, and quad devices capable of delivering
74 mA to 300 mA continuous and 83 mA to 570 mA peak output current per driver.
Do not ignore the output impedance of the buffer/drivers, even though this impedance is usually
very low. Even in a closed-loop buffer, the output impedance may be significant at high
frequencies, where it tends to increase. The value of the source resistor should follow this
equation:
Rs = Source termination resistor value Zo = Characteristic line impedance

ROR = Effective output resistance of line driver at frequency N = Number of driven lines
Without this consideration, any reflections on one transmission line will effect what is happening
on the other lines. That is, if the load termination resistors are not optimum, the reflections back
to the line driver from one line may couple into the other lines. If the timing of the reflections are
different, signal integrity could be compromised.
The problem here might be in the dividing of the signal. This can be compensated for by
increasing the gain of the buffers that are gain-programmable. This may not be easy, but it is
possible for unity-gain buffers by putting them into an op amp feedback loop and adding the
necessary gain.
LMH6704: Single, Programmable
Gain Buffer
SSBW: 650 MHz (G = +1 VN, 0.5 Vp•p)
LSBW: 400 MHz (G= +2 VN. 2.0 Vp•p)
• Slew rate: 3000 V/us
lout: 90 mA per channel
• Differential gain/phase: 0.02%/0.02°

• Very low distortion:
_2nd/3'd: -62/-78 at 10 MHz
Low input noise voltage: 2.3 nV/-{Hi
Disable
SOT23-6 and SOIC-8 packages

Pin compatible to OPA692
Replacement for HFA1112
~ National
P Semiconductor
Th,SJght&Soundoflnform,tion
The LMH6704 is a current-feedback Programmable Gate Array (PGA) and has been designed to
provide excellent performance with production-quality video signal in a wide variety of formats
such as HDTV and high resolution VGA. NTSC and PAL performance is nearly flawless with
differential gain of 0.02% and differential phase of 0.02°. Most professional video processing
amplifierslbuffers require differential gain and phase to be less than 0.1 % and 0.1°, respectively.
Programmable Gain Buffer ~jV"
~ t1\"'"' -t ~ )
Buffer gain is set

to Av = +1, which
is worst case for
.CO~for Unity Gain Peaking
peaking
4
3
2
1
o
m -1
~ ~2
~ -3
INPUT CONNECTIONS -4
Non-Inverting (Pin 3) Inverting (Pin 4) -5

GainAv
-6
·WN Ground Input Signal
+1VN
-7 VouT=250mVpp
Input Signal NC (Open)
-6
+2VN Input Signal Ground 1 10 100
FREQUENCY (MHz)
~National
P Semiconductor
""'Stght"SoundoflnformatJOn
The LMH6739 and LMH6704 are Programmable Gain Buffers (PGBs) that are very useful in
high-speed video applications. They essentially are very high-speed, closed-loop current
feedback op amps. Their gain setting resistors, the feedback resistor (RF) and input resistor (Ra)
are built on the chip. RF = Ra = 4500, for the LMH6739 and 4650 for the LMH6704. Thus,
they can be configured with Av = +2, Av = +1, or an Av = -I by connecting pins 3 and 4 as
noted in the chart. The gain accuracy for these buffers is accurate and guaranteed over
temperature to within ±I %. The internal gain-setting resistors match very well. The buffers'
architecture takes advantage of the fact that these resistors track each other very well over a wide
range of temperatures and process variation to keep the overall gain constant, despite the fact that
the individual resistors have nominal temperature drifts. Therefore, it is not recommended that
external resistors be put in series with Ra to change the gain, as this can result in poor gain
accuracy over temperature.
With PGBs that use current-feedback architecture, like the LMH6739 and the LMH6704 as well
as the LMH6718, the feedback resistor, RF, is a compromise between the value needed for
stability at unity gain and the optimized value used at a gain of +2. The result of this compromise
is substantial peaking in some cases at unity gain, as you can see here. If this peaking is
undesirable, a simple RC filter at the input of the buffer will smooth the frequency as shown. The
graph to the left shows the results of a simple filter placed on the non-inverting input in the
schematic.
LMH6704: Single,
Programmable Gain Buffer
C3 C4
0.1"Fy •.S"F
~Nattonal
P Semiconductor
n.. SIght & Sound f1f InftJtmltion
Best performance is obtained with back terminated loads. The back termination reduces
reflections from the transmission line and effectively masks transmission line and other parasitic
capacitances from the amplifier output stage.
With the inverting pin grounded, as shown in the typical application circuit, the gain of the
buffer is +2. This accomplishes two things. First, it compensates for the loss of -6 dB caused by
using back termination, and second, it flattens the gain vs frequency characteristics near the roll-
over frequency, as shown in the frequency response curves.
Simplified Buffer Application for
Analog RouterlSwitcher
Crosspoint
Switch
Vc= V.(RdRl + RT) = v.

So, VeN.= -6 dB
dNational
P Semiconductor
The Sight" Sound oIlntorm.f1O(I
The slide shows a typical application for input and output buffering for routing and switching
platforms. Here, un-buffered input/output analog crosspoint switches are buffered by such
suitable devices as National's LMH6704 or LMH6559. These are single devices. Note that we
did not include the quad LMH6560 or the triple LMH6739, although they could also be used
because many designers prefer single buffers in order to minimize crosstalk in the system.
A simplified diagram for the output buffer circuit is shown in the bottom-right of the slide. Note
that a resistance, Rr, has been placed in series between the output of the buffer and the
transmission line. This back-termination, while not always needed, ensures that the input to the
transmission line will be properly loaded with its characteristic impedance in order to eliminate
the possibility of reflections. However, this will reduce the signal level at the load end by 6 dB.
If this loss is unacceptable, then it is recommended that the LMH6704 be used and the gain set to
2x to compensate for the loss.
Maintaining Signal Integrity When Using
High-Frequency Buffers: Some
Transmission Line Considerations
Beyond a critical length, all traces become first order transmission line problems
Terminate all transmission lines in their characteristic impedance,

or you will get
- Phase and amplitude distortion in frequency domain
- Overshootlundershootlringing/oscillation in pulse response
Layout is critical in transmission lines. They can experience impedance

discontinuities when
other lines approach them
- other lines depart from them
- they have through-holes in them
• Use stripline or microstrip when laying out signal lines on PCB
• Distorted signals produce noise, jitter, and timing problems
• Log onto National's website and download

Transmission Line RAPIDESIGNER© Operation and Application
Guide
.:]Nattonal
(iI" Semiconductor
T1I.Sight&Soundof/nfotm,tKHI
With op amp and buffer bandwidths already in the hundreds of MHz and some pushing well into the GHz
region, it is imperative that attention focus more and more on the parasitic-rich neighborhoods in which
these devices find themselves. Neglecting the effect of parasitic capacitance and inductance on signal
integrity is a sure way to compromise the performance of the application.
Too frequently the designer makes simplified and un-justified assumptions, i.e., is the load resistive or is it
capacitive? Further, there is no such thing as a purely capacitive load, or even one that is only resistive.
As the wavelength of the signal gets shorter, a point is reached where the line is crossed from lumped
circuit components to distributed components. At this point, metal trace interconnects and other signal
carrying lines become transmission lines. The reason for this is that at sufficiently high frequencies, all of
the parasitic 3rd and 4th order components associated with these lines-series inductance, parallel
capacitances, equivalent resistances suddenly become first order terms.
All transmission lines must be properly terminated in their characteristic impedance or the signal source
will see a wildly varying impedance and phase at the higher frequencies. This will cause reflections of
some of the frequencies making up the signal and cause distortion. An un-terminated line can look either
capacitive or inductive, depending on the length of the line and the frequency. The input impedance ~N of
a transmission line with a characteristic impedance Zo and length L, terminated in a load ZL is given by:
ZL + jZox tan pL
ZIN't Z0--------
Zo + jZL x tan pL
Where ~ = 2rrJ"A., and A. is the size of one wavelength on the line. The output impedance of a driver is
significant in two ways. First, it is of interest in terms of how it matches the Zo of the transmission line it
is connected to. Second, it is of interest when understanding what the magnitude of the wave it launches
down the transmission line will be. If, for example, the transmission line is a standard RG58CIU coaxial
cable and we terminate the line in 50n, then by the above equation Z = Zo and the cable will look like a
pure 50n resistance over frequency. Assuming both ends of the cJlble are terminated thus, then there
should be no reflections and no distortion. Half of the signal power will have been absorbed by the load
impedance and half by the source impedance.
PCBs should use stripline or microstrip geometries for signal distribution at very high frequencies. A good
place to find a practical and simple guide to do this is on National's website. Here one can download the
Transmission Line RAPIDESIGNER Operation and Applications Guide, for a step-by- step aid to
designing fool-proof board transmission lines.
• Transmission lines should be terminated
• Simple traces need not be terminated
• Trace becomes a transmission line at:
Where tr is the digital signal rise time

tpR is the signal propagation rate
Typical tpR is about 150 ps/inch on board of

FR-4 material
•..'1 National
PSemiconductor
Th, SIght <I Sound of 'nfrmn,fJon
Sometimes we can get away with treating a signal line as a simple trace. However, this begs the
question, "When must a trace be considered a transmission line?" The formula in the slide tells
us that the line length beyond which a trace must be treated as a transmission line is a function of
the signal rise time and the propagation rate of the signal across the board (a function of board
material). When in doubt, always treat the line as a transmission line.
For analog signals, the rise time can be approximated by treating the signal as if it were a
trapezoid with edge rates equal to the maximum slew rate of the signal. For monotonic sine
waves, the rise time is about 30% of the sine wave period.
Question: Is Termination Needed?
The LMH6559 has an output signal rise time of

0.4 ns. The PCB is a typical one of FR-4 material.
? Beyond what line length should the line be

properly terminated?
0.4 X 10-9
Length>
6 x 150 X 10-125 /in
3
Maximum Length = 10 = 0.44 inches
2250
.:]Nattonal
[i9 Semiconductor
Th.SiQht&Sourrdoflnform,tion
As a practical example, let's look at the case of a very fast buffer-in this instance the LMH6559.
This buffer has a published rise time of 400 ps. So, if we want to know what the maximum
allowed signal trace length would be before termination is required, we just plug this rise time
into the previous equation, and discover that less than half an inch of un-terminated line is
allowed. Beyond this length, transmission line effects start to dominate, and we need to terminate
the line. One should subtract about 10% from the calculated length for safety.
•..'1 National
P Semiconductor
RF Detectors
General Block Diagram
The RF detector measures output power and controls

the PA's output to set the desired power level
~NatiQnal
(II" Semiconductor
Th,S,ghl&Soundoflnforffl.flon
In a cell phone it is important to set the output level of the Power Amplifier (PA) precisely. This is
necessary to transmit the correct power level, which is dictated by the base station, and to compensate for
local temperature and other variables that can affect the output power of the PA. A well-established
method to set the power level precisely is to use closed-loop power control. The RF detector measures the
PA output power through an attenuator and that measurement is compared with the desired level in the
baseband signal processing unit. A DAC applies a control signal to the PA in order to set the correct level.
CDMA and WCDMA are examples of applications where such a closed-loop power control can be used.
The response time of the control loop in these applications doesn't have to be very fast, as opposed to
GSM (TDMA), and this allows implementation of the control scheme in the baseband chip.
RF Detector Types
• Logarithmic RF detector
- Measurement based on peak detection
-Accuracy depends on waveform
• Mean-Square RF detector
- Measures VRMS2 = exact implementation of power
definition
- Waveform independent and therefore suitable for
measuring RF signals exhibiting high peak-to-average
ratios used in 3G and UMTS/CDMA applications
~National
p Semiconductor
The Sigh! , SOWfd of Infonn,tJotI
National offers both logarithmic and mean-square detectors as well as power amplifiers. Logarithmic
detectors are based on peak detection, VpEAK, while a mean-square detector measures VRMS2 Peak
detection is less accurate for power-level detection because the relation between peak voltage and average
power depends on the waveform. For a steady state sine wave of VpEAK volts across a In load, the
average power is ('IPEAK)2/2 Watts. A triangular wave form with the same peak amplitude across the
same load will deliver an average power of ('I PEAK)2/3 Watts. With more complex waveforms, such as the
CDMA signal, the measurement error can be in the order of 5 to 6 dB. Therefore, for many wave forms,
especially those with high peak-to-average ratios, peak detection may not be accurate enough. A mean-
square detector would be recommended. On the other hand, when the log detector signal is processed
through a linear input ADC to provide the PA control voltage, the log detector will provide equal
resolution over the power range. A square law detector will have more resolution at higher power levels
than at low power levels.
of _ ..__ .
-!----
!:
i
:
I
:
:
i
Logarithmic detector: Mean-Square detector:

Constant resolution over Reduced resolution in low
entire range power range
l'"
~National
Semiconductor
The Sight &, Sound of Inform,tum
Many baseband signal-processing chips have ADCs with limited resolution, for instance 8-bit or 256
steps. These steps are linearly divided over the converter input-voltage range. It can be seen that the
logarithmic detector has constant resolution over the complete power range, making a logarithmic
transfer preferred. Mean-square detectors with a log-log response have more limited resolution at
lower power levels, as can be seen on the right-hand side. Therefore, mean-square detectors are
normally used in the steep part of the curve.
Logarithmic Detector
3 co
E.
• Power applied to the input translates 2 g
to a DC voltage on the output 1 w
through a linear-in-dB response ~
o ~
E
- Power: X-axis = Logarithmic -1 ~
-2 <3
- VOUT: Y-axis = Linear -3.3
-4
M ~
-50 -40 -30 -20 -10 0 10 20
Rfi""'_(dBm)
~National
P Semiconductor
Th, Sight & Soundoflnform,tion
Power applied to the input of a logarithmic detector translates to a DC voltage on the output through a
linear-in-dB response. The curves above were obtained from an LMV225 and show that over the
temperature range, the output voltage changes linearly for an input power level change from -55 dEm. To
depict how linear the detection curve is, an error curve with respect to a fitted linear curve also is plotted
for the same temperature range.
Typical Application
LMV225, LMV226, and LMV228
Antenna
R1 1kO
Voo
C 100pF
K2
LMV225
RFINlEn K2
Out
A1 62 LMV2261
LMV228
R2 61 Al 62
GND 61
10 kO GND
LMV225 LMV226/28
High Resistive Tap Directional Coupler
d
l'" National
Semiconductor
111. ~ht & Sound of Inform'tKNI
The LMV225 detector is especially suited for power measurement via a high-resistive tap. The constant
input impedance of the LMV225 (SOn) enables the realization of a frequency-independent input
attenuation to adjust the LMV225's range (-30 dBm to 0 dBm) to the power range of the PA. The
attenuation realized is 20 x log (I + RI/50n). Parasitic capacitance of resistor RI can impact the actual
realized attenuation.
The LMV226/28 also have a son input resistance, but are designed to work with directional couplers that
have attenuation. Therefore, the input range for these devices is -15 dBm to + 15 dBm. The typical
attenuation of a directional coupler is 20 dB, and so the LMV226/28 can be directly connected via the
directional coupler to the PA without the need of additional external attenuation.
LMV225, LMV226, and
LMV228 Specifications
• Logarithmic detector
• Log conformance error ±2 dB
• RF frequency range 450 MHz to 2 GHz
• Supply voltage 2.7V to 5.5V
• Temperature range - 40°C to +85°C
Input Range Output Application

(dBm) Buffer
LMV225 -30 to 0 No High Resistive Tap
LMV226 -15 to 15 Yes Directional Coupler
LMV228 -15 to 15 No Directional Coupler
~National
V" Semiconductor
a
Tn, SiQht Sound of Inform,bon
Mean-Square Detector
f 0'
• Power applied to the input ~ 0.01
translates to a DC voltage on the

output through a Logarithmic-in-dB
response
- Power: X-axis = Logarithmic

- VOUT: Y-axis = Logarithmic i 1.0
S 0.5
)00-
'&
e .(1.5 ----r-
.J
+_
S -1.0 -
~ National
P Semiconductor
Th. Sight 4 Sound oflnfofm,tion
The LMV232 is a mean-square detector and therefore has an output voltage (Volts) that relates
logarithmically to the RF input power (dBm). The input referred error, with respect to an ideal linear
mean square detector, is determined as a measure for the accuracy of the detector.
LMV232 Typical Application
Voo
B3
To Baseband Out 3
R1 C1 LMV232
6.2 kll 1.5 nF
FB A2 C1 RF1N2
C2 C3
BS SD
~ National
P Semiconductor
Th.SiglltASfWndoflnform,tion
The LMV232 is especially suited for CDMA and WCDMA applications with two PAs. The output power
of either PA can be measured at any time, depending on the position of the Band-Select (BS) pin. The
measured output voltage of the LMV232 is read by the ADC of the baseband chip, and the gain of the PA
is adjusted if necessary.
The LMV232 conversion gain is configured by resistor RI. A higher resistor value will result in a higher
conversion gain. The maximum dynamic range is achieved when the resistor value is as high as possible:
i.e. the output signal is just below clipping, while the voltage stays within the baseband ADC input range.
The two inputs of the LMV232 also can be used in an application with one PA to measure the transmitted
power and reflected antenna power.
LMV232 Specifications
• Mean-square detector
• Square-law detection range 20 dB
• Error ±1 dB
• RF frequency range 50 MHz to 2 GHz
• Supply voltage 2.5V to 3.3V
• Temperature range -40°C to +85°C
• Two sequentially selectable RF inputs
• Externally configurable gain and LF filter bandwidth
• Optimized for use with 20 dB directional coupler
~Nattonal
(il'Semiconductor
Th, Sight.l Sound of 'nfoml,fJon
•..'1 National
P Semiconductor
Amplifier-to-ADC Interface
Driving the ADC
• What load does the ADC present to the

amplifier?
-Most ADCs have a switched capacitor input
• Amplifier's settling time
• Amplifier's output impedance
-Isolating the amplifier's output from the ADC
input
~ National
(ill'Semiconductor
.",. Sight" Sound of Infoml,tiotI
The amplifier must be able to drive the Analog-to-Digital Converter's (ADC's) input with
minimum error. One challenge for the amplifier is that many ADCs have a switched capacitor on
the input for sampling the amplifier's output. The amplifier must be designed for settling quickly
with this type of load, or it will be necessary to find some way to isolate the ADC's input from
the amplifier's output (see Section 2 on amplifier stabilization).
Amp/ifier-to-ADC Interface
um
32
3.' ,__ ,
Isolating the Amplifier from the ADC:

Rand C values Dependent on Amplifier, ADC and Signal Frequency
~National
P Semiconductor
rM S,~hta Sound of InJorm,tIOtI
The top schematic shows the ADC's input connected directly to the output of the amplifier.
When the sampling capacitor in the ADC is connected to the amplifier's output, a charging
current flows from the amplifier to the ADC, which causes a momentary glitch that can take
some time to settle. One way to minimize this effect is to slow down the sampling rate. This
provides the amplifier with the time necessary to stabilize its output.
A second way to minimize the error caused by the switch capacitor is to have another capacitor
connected to the ADC's input. This capacitor is much larger than the internal sampling capacitor
and provides the charge needed to quickly charge the ADC's sampling capacitor. An isolation
resistor is needed to isolate the additional load capacitance from the amplifier's output. In
addition, the resistor and capacitor will form a low-pass filter and can be designed to provide
noise reduction functions, as well as helping with the anti-alias function.
High-Speed Signal Paths
• Dynamic range adjust 7 level shifting/amplification/AGe
• Single-ended to differential 7 signal immunity to interference
• Impedance matching 7 signal integrity/SNR
• Reducing the effects of capacitive loading 7 buffer/driver
• Remove unwanted signal components 7 filters
• I-V or V-I conversion 7 amplifier circuit topology/device selection
•..'1 National
(iI" Semiconductor
Th,Sighr&Soundoflnform,tJon
Previous signal sources have emphasized the need for precision op amps to provide the interface
to the ADC. When the interface to the converter is required to handle high-speed signal sources,
there are other things to be considered.
As before, the op amp is required to match the dynamic range of the source to the input dynamic
range of the converter. ADCs are normally fixed-gain devices, providing the best performance
when the input signal level is just below, but not above full scale. For many Radio Frequency
(RF) sources Automatic Gain Control (AGC) is needed, and for this purpose, National has
Voltage Controlled Variable Gain Amplifiers (VCVGAs) such as the LMH6502/03/04 series
described next. Some sources, ultrasound transducers for example, require this gain to be time-
variable to compensate for the signal loss incurred by deeper penetrating scans.
Earlier we saw that many sources provide a differential output signal, with op amps performing
the conversion from differential input to single-ended output. Now that many new ADCs have
differential inputs, op amps are used to convert single-ended inputs to differential outputs. This
conversion can be done with conventional op amps, but is more readily accomplished by use of a
fully differential op amp, such as the LMH6550.
• Differential (LMH6502/03) or single-ended
input (LMH6504)
~National
(ill'Semiconductor
1JI,SightclSoundoflnform,prm
Before looking at differential drive to the ADC, we will consider the circumstances where
the amplifier gain has to change dynamically in order to get the best performance out of the
ADC. For broadcast radio applications, the distance between the transmitter and the receiver
can vary greatly, and this means there are dramatic differences in the signal source
amplitude. In ultrasound applications, there are large differences in the level of the reflected
signal depending on the depth of penetration required. In these cases, it is common to use a
Variable Gain Amplifier (VGA) to optimize the dynamic range at the input to the converter.
For a VGA, the output amplitude is a function of the input signal multiplied by the control
voltage V G. A linear change in this control voltage produces a linear change in gain, either
in dB or in VN. Sometimes, the gain control function is used to correct for a known gross
amplitude degradation in order to allow for detection of a small signal (i.e. ultrasound).
As noted in the earlier section on RF detectors, sometimes it is preferable to have an output
that is linear in dB with respect to the input.
LMH6502/03 Block Diagrams
LMH6503
\
.
............ _._ ..-.---_ ...:
··
• r
l'"
~ National
Semiconductor
Th. Sight & SOllndoflnform,tion
As you can see in the LMH6502 block diagram, the differential input to these devices is first
buffered before being applied across an external resistor ~. The current which flows in ~, in
response to the input differential voltage, is then sensed and applied to the tail current of the QI,
Q2 combination. By varying the base voltage of Q I (VG), one can control how much of the tail
current flows through the 5 kQ resistor on Q2 collector. This way, the signal gain can be varied.
Q2 collector voltage is amplified using the CFA (UI) to appear at the output.
National's VGA's use a Gilbert cell to vary the GM of a differential amplifier with V G. This will
allow the signal to be fully attenuated (gain of 0), or fully on (maximum gain). The Gilbert cell
output is then amplified by a Current-Feedback Amplifier (CFA). This achieves a bandwidth that
is nearly independent of the gain setting or the amplitude of the output voltage.
The LMH6503 functions in much the same way with the difference that there is additional
circuitry that converts the logarithmic relationship of the LMH6502 to a linear one.
What is Linear in dB and
Linear in VIV?
• Both have full range of gain (max gain to cutoff)
• Linear in dB (LMH6502 and LMH6504) allows more resolution at
lower gains (e.g. AGe)
• Linear in VN (LMH6503) is for applications where linearity in
gain is more important (e.g. ultrasound)
30 11 30
~ 10 ~
10 9 10
o 8 0
.10 7 ·10
i:O
& -20 s! ~"20
~ -30 5~ ~.30
-<40 4 40
-50 3 -50
~ 2 ~
.70
·70 V'N_OIFF ~ ±O.1V 1
~ o ~
·1.2 o 0.4 0.8 1.2
o 0.2 0.4 0.8 0.8 1 1.2 1.4 1.8 1.8 2
VGM
VoM
.•..'1 National
l'" Semiconductor
fh, Sight &, Sound of Inform,rion
The main difference between the LMH6503 and LMH6502/04 is the gain control relationship.
The LMH6503's gain control is linear in VN and the LMH6502's gain control is linear in dB.
These plots, taken from the LMH6503/04 datasheets will help explain the differences.
The first plot is taken from the LMH6503 datasheet and illustrates gain (VN) vs. V G' As you can
see, the curve is linear over most of the V G range. This is why we refer to the LMH6503 gain
control as linear in VN. The second gain curve plots the gain in dB and is linear over a wide
range of gains. Because of this, the LMH6504 gain control is referred to as "linear in dB."
LMH6503
Typical AGC Circuit
•..'1
l'" National
Semiconductor
111. Sight a Soofld oIlnform.tIOrl
An Automatic Gain Control (AGC) circuit is a typical application for VGAs. A typical AGC
circuit consists of a VGA and a feedback loop that performs integration and rectification to
provide a control voltage V G.
Circuit Description:
The dual amplifier LMH6643 is used to drive the gain control pin of the LMH6502. R1 and Ry
set the gain of the rectifier. Rx, Ry, and C provide a time constant that sets the acquire and hold
times. The adjustable resistor, RADJ, sets the inverting pin of the integrator to the initial condition
of + 1V. When the RMS current of the signal is greater than the negative current of RADJ, the
integrator decreases the gain of the LMH6503. And when the signal drops below the RADJ
current, the LMH6503' s gain is increased.
AGC Loop (1/2 Wave Rectifier
with Offset Correction)
1 k/l pot,
(" offs.t adjust
l'"
~Nattonal
Semiconductor
Th,S,ght&Soundoflnfrmn,fJOn
Here is another way to do the AGe function. In this method, provision for adjusting offset
correction is included. The output is Y, wave rectified.
The gain of the LMH6714 stage eases the requirement on the LMH6502 max gain.
Ultrasound Block Diagram
IMAGE" CO~OR
MOTION DOPPLER
A ramp on the gain PFlQCESSINQ
(BMODEl
PFlQCESSINQ
1"11001'1
control pin of the TGC
will compensate for
signal attenuation caused DISPU'l'
by traveling deeper within
tissue =
6
•..'1 National
PSemiconductor
Th,SightaSoundoflnfomJlItJon
Here the VGA is used in the Time Gain Control (TGC) block shown above. The function of this
block is to compensate for the loss of received signal as a function of the total round-trip time.
The longer this time, the smaller the amplitude and the larger gain is required from the VGA.
There is a direct correlation between the receive delay and the distance to the object. The reason
for this is that longer delays are associated with signals being returned from deeper tissue within
the body. These farthest reflections are attenuated the most and require the highest gain.
This type of TGC amplifier needs linear-in-dB gain control (LMH6502 or LMH6504) and
requires at least a 50 dB adjustment range. In addition, the VGA should have low noise and low
distortion. Both devices mentioned are capable of meeting the requirements.
LMH6502103104
Variable Gain Amplifiers
LMH6504 Variable Gain Amplifier
130 MHz signal bandwidth 150 MHz Signal bandwidth
100 MHz Gain control bandwidth 150 MHz Gain control bandwidth
1,500 V/lJs Slew rate
>70 dB Gain adjustment range
Device-to-device gain matching within to.42 dB
1,800 V/lJs slew rate 11 mA Supply current
Device-to-device gain matching within to.7 dB Gain control is linear in dB
Replacement for CLC5523
t75 mA Linear output current
Available in MSOP-8 and SOIC-8 packaging
5V to 12V Supply voltage
Replacements for CLC520/522
Available in TSSOP-14 and SOIC-14 packaging
Ideal for automatic gain control

applications in test, measurement, and
instrumentation equipment, video
communications, and medical imaging
.•.'1 National
P Semiconductor
The Sight &, Sound of Information
This slide summarizes the main characteristics of the LMH65xx series of VCVGAs. They have
been designed as improved replacements for the CLC520/22 with which some of you may have
been familiar.
~National
PSemiconductor
Differential Input Amplifiers

Differential Amplifier with
Common-Mode Feedback
• Uses three inter-related amplifiers

• Transfer function is:
• VOUT+ = (V1N+ - V1N-) X A1N + VCM
• VOUT- = -(V'N+ - V1N-) x Av + VCM
• VCM = VOCM (input pin) == (VOUT+ + VouT-)/2
• Fully supports single-to-differential conversion because
common-mode amplifier "drives" unused input
• Examples LMH6550, LMH6551
•.'1 National
Ii" Semiconductor
1M SIght & Sound of Infonn.bon
The "driven" input is one key benefit of the cornman-mode amplifier since without the cornmon-
mode amplifier the ADC input suffers a 6 db gain loss. Maybe even more importantly, it loses
6 dB of dynamic range.
For driving an ADC, the other benefit of the cornman-mode amplifier is that it allows the output
cornman-mode of the amplifier to be precisely set to the best value for the driven ADC.
Differential Amplifier with
Common-Mode Amplifier
• Output common mode is now variable and user

defined. Can be fixed or an AC signal
• Most flexible differential amplifier in existence
• Exceptionally well-suited to driving ADCs
• Inputs are virtual short, but NOT virtual ground
• Common mode of input is set by output common mode
and feedback divider effect - can cause problems with
single supply and high gain
• Common mode at output will set up DC currents,
especially in single-supply operation
d National
P Semiconductor
Th.Sighr&Soundoflflform'flon
Basic Application
R C
Ro and Co
will prevent oscillation due to
L
o
Ro will cause a slight

loss in gain. Once
the system is
designed, RF or RG
can be adjusted to
offset the gain lost in
Ro
•..'1 National
PSemiconductor
The Sight & Sound of Informstion
A split supply provides best performance and maximum flexibility. In the above schematic,
power supply and bypassing capacitors are not shown for clarity. Standard ceramic chip
capacitor bypassing is mandatory for all high-speed amplifiers with 0.01 JlF as a good value for
the bypass capacitors
For the typical ADC, CL is around 7 to 12 pF and RL will be from 1 kO to near infinity. Ra is
necessary for most of the ADCs that are suitable for use with this part (LMH6550). Most designs
will include an external capacitor Co to help provide current to charge the sampling capacitance
CL"
Driving an ADC
Additional anti-alias
filtering will be required T
in most applications V
•..
'1Nattonal
P Semiconductor
Th.Sl9hr5Sollndof'nform,tIOII
Ro (5611 resistor) is needed to prevent the amplifier from oscillating with the ADC load. Co
(39 pF) is recommended to help shunt the currents associated with the sample-to-hold transition
from the ADC front end. Since Ro and Co are needed anyway, they can be used to help
implement the anti-alias filter (not shown). They will form a low-pass filter with a cut-off
frequency given by
F cutoff = 1/ (2 x 1TX 5611 x (39 pF + 14 pF»
** Note using 14 pF = double the actual ADC input capacitance - this is due to the differential
circuit.
The V REF output of some CMOS amplifiers cannot drive the V CM input of the LMH6550. An
external reference or a buffer amplifier is required in that case.
Adjusting RG to Compensate for Ro
RF1
5000 Ro
250
CL
VI 10 pF
'\ Vo 4V.-p
2V.-p 15000
250
R
O
Vs = ±5V, VCM = OV
RF = 5000, RG = 2500, Ro = 250 RL = 15000,
CL =10 pF
Av = 500/242 x 1500/1550 = 1.999 VN ~ National
P Semiconductor
TIl. Sight 4 Soundoflnform.tion
The differential amplifier datasheet will specify the minimum value ofRo needed to stabilize the
amplifier output for a given capacitive load. This value can be adjusted slightly if desired to help
form an output filter.
Check the ADC datasheet for the input resistance. Some ADCs will be very high resistance and
will require little or no adjustment of~.
Single-Ended Operation
SET RM = RTllRs
RG
SETRr=__ 1-
(~-~J R,'1~(2' (~+ Roll

•..'1 National
Ii" Semiconductor
Th. Sil1htA SOllnd of Inform,bon
These equations need to be solved iteratively. You first calculate RIN ignoring the effects of Ry
and RM. If RM is large enough, it will change RIN and the equation will need to be solved again.
Given 1% resistors, two iterations should suffice.
Common-Mode Importance
• With single-supply input, common-mode

range does not include ground
• Because of feedback resistors, the output

common mode will influence the input
common mode
• Signal-source common mode also will

influence amplifier input common mode
dNattonal
V'" Semiconductor
-""S,ghtaSolJlldolfnform,tJon
This is one of the biggest design challenges for the differential amplifiers. Using a single-ended
input on single supply requires close attention to the amplifier input-range specifications. The
next few slides will detail two example calculations.
Vo1+Vo2 VQCM
2 1 +A.y
-BY DESIGN WHERE R".« RG
20130111
.•.'1 National
~ Semiconductor
Th,Sight&Soundoflnform,tJofl
If V[ has a common-mode voltage, then by superposition, it will add to the V CM voltage. These
calculations are for VICM = (VII + V[2)/2. This is necessary to make sure that the input common-
mode range of the amplifier is not violated.
Single-Supply Common Mode Example 1
Ro
ENABlE
.•..'1 National
P Semiconductor
Th. Sighr & Sound oflnfotm.tJOn
If V1CM is 1.1V, the input pin is well away from the limit of DAV. This assures good linear
operation and the ability to handle large input signals.
Single-Supply Common Mode Example 2
Given, Vs = +5V, VCM = 2V, RF = 10900, RG = 1090, Rs = 2000

=
Then, R1N 2000 so RT is not needed and RM 00 =
V1CM then = 0.2V - Amplifier is not operational at this V1CM
~ Nattonal
l'" Semiconductor
Tn. Sighr & Soulld of Inform.t1OII
In this case, the amplifier is not operational. Additionally, the amplifier will not achieve
datasheet distortion and swing performance if V'CMis too close to OAV. If the input signal goes
below ground, then the input common mode will be pulled even lower.
Common Mode Example 3
• Use two amplifiers with gains of 3.16
• Raise output common mode and AC couple
•..'1 National
~ Semiconductor
TIw S"ht" Sound of Infann.tIOII
High gain can be supported without any problem on split power supplies. As gain goes up, the
input common mode is driven toward zero volts. On split supplies, a zero volt input common
mode is a valid operating state.
Solution number 2 is based on the fact that as gain goes down, the input common mode is closer
in value to the output common mode. In this case, it is suggested to use the square root of 10 to
split the gain equally between the two amplifiers. This is not strictly necessary, but is a good first
suggestion.
Of course, AC coupling is probably not an option in most cases where a differential amplifier is
used. There are still advantages over a transformer, though. Transformers usually have trouble
coupling below 100 kHz, whereas with AC coupling, it is possible to use large capacitors and get
performance down to tens of kilohertz.
GAIN -Two
Definitions
1. % X RF/RG = Gain
from Point A
(system level)
2. RF/RG = Gain from

Point B (Amplifier
Definition)
~National
(ill'Semiconductor
nt. Sight a Sound Dr Inform,bon
The datasheet specifications were determined with point B as the reference point. This is because
most high-speed signal sources are 50n devices making point A internal to the test equipment
and unavailable for probing. Internal source resistance is also usually calibrated out and again
not available for inspection. Point B marked the evaluation board connector.
Systems designers, on the other hand, are usually interested in overall system performance. So it
is important to realize that with impedance matching, there is a voltage loss between the two
stages. One way around this is to have the source placed very close to the amplifier and to not
use impedance matching. In this case RT and RM can be eliminated and the upper RG can be
reduced so that Rs becomes part of~.
• Smaller RF and RG will

reduce bandwidtl1 and Pollll.B
peaking
• For higher gains use
I~ ~
larger RF• try to keep RG.
between 1000 and 30011
• R1 and RM can be
eliminated if R1N matches
Rs (RG > Rs)
• Not All Rs values can be ~
matched
R'N equation does not include
R1N =( R
F
)
effects of RT and Rs· 1- 2* (R + ~)
F
•..'1 National
(it'Semiconductor
111. Sigh! " Sound uf Inform,bon
The ideal value of ~ is around 300 to soon. At lower gains RF should be kept around soon.
For higher gains RF should be increased, rather than decreasing ~. At higher gains, peaking will
not be as much of a problem.
Input impedance values greater than R1N cannot be matched. This is because the differential
configuration has no high impedance inputs.
Single Supply with
Frequency Compensation
LMH6551
or
LMH6550
For gain of 0.33 RF = 2500,

RG= 7500, Ccomp = -3.3 pF
and R1 = 560
R 1 5 are required to isloate

Amp output from ADC
capacitance. R1 and
C2 can also be tuned to cut down
on amplifier niose .
.•..'1 National
P Semiconductor
Th,Stghl&Soundoflnform,fJlJn
With differential amplifiers, gains of less than I are possible, but may cause unacceptable
peaking of the frequency response. Choosing a value of CCOMPthat has a reactance of around 2x
the resistance of ~ at the frequency where peaking is observed is a good starting point. In this
example CCOMPhas reactance roughly equal to the resistance of ~ at the frequency where
peaking was observed. In this example, the customer was interested in a flat response more than
bandwidth.
Single-Supply Operation AC Coupled
AC coupling allows
higher gain and lower
output common mode Rs
voltages ~
VI "'" T
*V1CM = VOCM
because of ~
capacitive
isolation.
V01 +Vo2 VICM=VOCM
*VCM = 2 VI1 + VI2
*BY DESIGN V1CM= --2-
•..'1 National
(iI" Semiconductor
TII. Sight a Soufldoflnformtltlotl
NOTE!! The equation V1CM = V OCM is valid only because of the capacitors between Rr, ~, RM,
and ground.
Driving an ADC
• Make sure to include ADC input capacitance in

equations for matching circuitl anti-alias filter
• High-bandwidth ADC inputs will digitize amplifier
noise: use filtering to reduce
• Remember that ADC input capacitance will be doubled
due to differential circuit
• ADC internal reference may require buffer to drive
amplifier VCM pin
• ADC reference voltage (and VCM pin voltage) is critical
to ADC operation. Check amplifier common mode
calculations to see if split-supply operation of amplifier
is required
dNational
(II" Semiconductor
The $'lIht & Sound of /nform,tion
Designing Anti-Aliasing Filters with
WEBENCH@Online Tools
dNattonal
(i" Semiconductor
The Sight" $oufld of Infonn,tlon
For many amplifier/ADC interfaces, the op amp is used to implement the anti-alias filter. To help
the design procedure, National has expanded its WEBENCH@ online tool offerings. The Signal
Path Designer tool combines ADC selection with the design of an anti-aliasing filter. In addition,
a simple resistor-capacitor interface circuit is customized for the application.
WEBENCH®Signal Path Designer
Tool Selection Process
1. Set ADC Performance Requirements

- Resolution, supply, sampling rate
- Select ADC from proposed list
2. Design Anti-Aliasing Filter
Enter desired input voltage and signal frequency range
Select signal attenuation and gain flatness (2nd order)
Select from 11 different transfer functions (Bessel, etc.)
Select preferred amplifier from 220 options for amps
3. Review Component Selections, Finish Bill Of Materials and
Simulate Circuit Results
All components recommended by system
- Review calculated system performance
~ National
(il'Semiconductor
Th, Sight & Sound of 'nform,hon
In the WEBENCH® Signal Path Designer tool, requirements for the data sampling are identified,
which leads to selection of an ADC from a list of candidates. The 2nd order anti-aliasing filter is
designed next, based on the input signal characteristics and desired filter response. As in the
Active Filter Designer tool, the ideal filters are evaluated first, then one is selected for
implementation. An amplifier is selected for use in the active filter based on the system
requirements.
The overall circuit, including the selected components, is presented to the user. The user can
review the circuit performance and make adjustments to the ADC's input voltage range and
resistor tolerances. When the operating value calculations look good, the user can electrically
simulate the filter.
Choose Ideal Performance Envelope
For Your Needs
Review filter response across
frequency, phase, group delay,
and step response
Group Performance
Delay Trade offs
Frequency
Response
\
Phase
\ Response
•..'1 National
I)'" Semiconductor
Th,Slght&SoundoflnfQfffl,tlon
In addition to frequency response, it is often helpful to evaluate the filters by their group delay or
step response. Sometimes a filter with a very sharp, near-ideal frequency response will have a
step response with a lot of ringing. This will indicate a filter that may not settle quickly from an
input transient, making it difficult to accurately sample a suddenly-changing input signal.
20,000 iterations Gel.
per filter response Response
filU>r
Refel'tlnce
M ••
Signal
Frequency Frequency
Flatness
Error
up to
Nyquist
FrequencY
Attenuation
Ny:'lst S:~:'le
Selected N;:'i:lst
Sample
present you with (H.) (H.) Fmex
(dB)
(kH.) (dB) (ksps) (~:::)
the best o eessel 5000 2000 0.«26 100 47.98 200 126
o eutterworth 4000 2000 0.25e6 100 56.04 200 80
configurations to o Chebyshev 7000 2000 0.3944 100 48.e8 200 122
1dll
meet system o Chebysh8v 4000 2000 0.4992 100 58.14 200 72
0.5d8
specification o Chebyshe.
0.25dll 3000 2000 0.2501 100 62.68 200 56
o Chebyshev
I 0.ld8
@ Chebyshev
3000 2000 0.4157 100 62.17 200 56
• O.OldB 4000 2000 0.1801 100 56.4'1 200 78
Equlnpple
o 0.50 error.
unear 5000 2000 0.2925 100 50.4 200 110
Phase
Equ1npple
o O,.05~erTOr,
5000 2000 0.3992 100 48.87 200 120
Linear
Phase
tfJ National
Semiconductor
The Sight" SOlJnd of Inform,tJon
For the more analytical designers, a chart is provided that summarizes the numerical aspects of
the ideal filter's performance. In this table, it can be seen that to achieve the same gain flatness
and the same attenuation at Nyquist, the different response approximations need to have different
reference frequencies.
In addition, to support the specified maximum signal frequency, some of the responses have
more attenuation at FN than is necessary. Their sample rates could be reduced and the other
performance requirements would still be met.
Select one filter response from this table to be implemented.
Review Suggested Amplifiers For
Your Anti-Aliasing Filter
Product Fokktr IlIllI $
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~ National
P Semiconductor
The SIght.l Sound of 'n'orm,lJon
The next step in implementation is to choose the op amp to be used in the anti-aliasing active
filter. The op amps in this list are selected to meet the bandwidth, closed-loop gain, and supply-
voltage requirements of the design. Also in general, those with lower input offset voltage, lower
supply current, and gain-bandwidth close to the desired target will be higher on the list.
Although the list initially contains 10 amplifiers, many more may be candidates. If this is the
case, there will be a link at the bottom of the table to display all the candidate amplifiers.
Finalize Design Review and
Component Selections
[JJ Click to 5tort

yoyr .Iectdcal
iImWlItllw
--:;tv.
.. ... -
810s Divider
I
AAF MuttipleFeedback
J~:~
...•....c.
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ItJ
1
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v-
AAF FlrstOrdecRC
Cb 58..Q7 uF Ai LMV342MM
Rb 14.3kOhm 1'" Cl 0.068uF
At 35.7 kOhm 1 ••• C2 0.0082 uF
Rl 1.18kOhm
R2 866 Ohm
R3 3.16kOhm
ACJNattonal
P Semiconductor
Th, Sighr 4 Sound oflnform,1JOn
Now that the ADC is selected and the anti-aliasing filter is designed, the remaining circuit
elements are calculated. Because the anti-aliasing filter is operating from a single (ground-
referred) supply voltage, a bias voltage is needed to bring its output voltage into the ADC's
operating input voltage range. This bias voltage is constructed using the system supply voltage,
divided down with two resistors, Rb and Rt, and filtered with a capacitor Cb.
Also, the ADC input is capacitive, and the capacitance varies as it switches into and out of
sample mode. This would present a changing load to the filter amplifier, potentially reducing its
stability. The simplest interface between amplifier and ADC is a series resistor, parallel
capacitor. These components are automatically calculated to minimize the effect of the changing
ADC input capacitance.
..,1"0
,urOWlgn,
English eq <!,It(1lJ4I<)
HldtControls Oom
step 1 ; Select Sunulation Type

Closed lOop Freq Rtl .•.
Vi_P~
Stale f'8Ol.!
t""'HeIP Print
Next steps:
Start New Simulation
or
Hover over eo", compo",
or
Click on In$ltvm.nt comp,
•..'1 Nati 0 na I
~ Semiconductor
The Sight & Soundoll"torm'DOfl
The electrical simulation is for the filter and R-C interface circuits. Available tests include
frequency response and step response, as well as a sine-wave response, to verify operating
voltages in the circuit.
If you are unfamiliar with this simulation environment, click the "Demo" button to see a brief
tutorial video.
.•..'1 National
P Semiconductor
Data Conversion
Systems
Analog-to-Digital Converters (ADCs) are conceptually simple: give them an analog voltage
(or current) and they give you a digital word. Practical application of ADCs is, however, not
quite so simple.
Most of us are more comfortable using a DAC than using an ADC, but even the DAC does
have areas about which we should be careful.
Here we will discuss concrete ways to get the best performance from these products,
including examples of customer problems and how they were resolved.
~National
(ill'Semiconductor
The Sight & Sound of InformatIOn
Semiconductor
Temperature Sensors
Amplifier-to-ADC Interface
-vum
S.2
,..
~ National
l" Semiconductor
Th. Sight a Soundoflflfonn,tiofI
The top schematic shows the ADC's input connected directly to the output of the amplifier.
When the sampling capacitor in the ADC is connected to the amplifier's output, a charging
current flows from the amplifier to the ADC, which causes a momentary glitch that can take
some time to settle. One way to minimize this effect is to slow down the sampling rate. This
provides the amplifier with the time necessary to stabilize its output.
A second way to minimize the error caused by the switch capacitor is to have another capacitor
connected to the ADC's input. This capacitor is much larger than the internal sampling capacitor
and provides the charge needed to quickly charge the ADC's sampling capacitor. An isolation
resistor is needed to isolate the additional load capacitance from the amplifier's output. In
addition, the resistor and capacitor will form a low-pass filter and can be designed to provide
noise reduction functions, as well as helping with the anti-alias function.
Transfer Function Comparison
LM20 vs. a Thermistor
.:JNational
~ Semiconductor
nt.S/fIht&Soundoflnfotrn.bon
When driving the input of an ADC from the output of a temperature sensor, it is important to
realize that every ADC has a quantization error associated with it. The higher the resolution
of the ADC (the more bits it has), the smaller the quantization error. When digitizing the
output of an analog temperature sensor, this quantization error translates directly into a
temperature-reading error - the higher the quantization error (the lower the ADC
resolution), the higher the temperature-reading error.
The slope of the temperature sensor's transfer function (change in voltage per change
in temperature) determines how severe of an impact the ADC error will have upon the
temperature measurement. Let's say that an 8-bit ADC has a reference of 5V so
that each LSB is equal to about 19.5 mY. The LM20, as an example, has a slope of
-11.69 mV/oC. This is equivalent to -0.085 °C/mV, which means that one LSB of
quantization error would result in a maximum (0.085 °C/mV x 20 mY) = 1.7°C error.
Consider now that the NTC thermistor has a slope of -64.7 mVrC at -35°C. Its temperature
error due to quantization would be 0.30°C error at this cold temperature. However at 120°C,
the thermistor has a slope of -1.39°C/mV. So it would have a digitized temperature error of
27.8°C! The plot above shows that National's LM20 performs better at temperatures above
about 35°C, the point where the thermistor has approximately the same slope as that of the
LM20. Also, National's LM94021 has four possible gains; so, the quantization error can be
managed by simply changing the gain.
LM94022:
Lowest Supply Voltage
• 1.5V to 5.5V Supply
• Next generation following LM20
• 5.4 ~A typ Quiescent current
• ±1.5°C Accuracy
• -50°C to 150°C Operating
temperature
• SC70 Package
,..
• Four selectable gains to optimize
maximum gain for a given supply
outpvt Vok~ lfS T.mp8fawre voltage
•., • Optimized to drive ADC inputs
~ en-l\
~u
50 ~A Output Source Current
a 20 ., - 1100 pF Load Capacitance
~.., without external resistor
au 0$ • ., • Competitor's Supply Voltage
•• .• - Four
Seiko 58110: 2.4V min
·' •••• 23 , 23 " •• 10' '" ." selectable
-""-reI linear gains! Maxim MAX6613: 1.8V min
•..-1 Nati 0n a I
~ Semiconductor
The Sight & Sound Qflnformation
National's LM94022 is a next-generation LM20 temperature sensor. Besides an industry-

leading minimum supply voltage of 1.5V, it has many excellent specifications and comes in
a tiny SC-70 package, making it ideal for small, portable products such as cell phones.
The low 5.4 IlA (typical) supply current preserves battery power.
The LM94022's four selectable temperature-to-voltage gains allow the system designer to
optimize the design to get the highest gain over the system's operating temperature and
supply voltage. Selecting the lowest gain allows the LM94022 to measure temperature in a
low-voltage system such as the 1.8V supplies for 90 nm processes used by many controllers
and ASICs, providing a temperature-analog signal over the full operating range of -50°C to
150°C. For systems with higher supply voltages, all the advantages of a steeper output slope
can be utilized by selecting a higher gain.
The LM94022 has been optimized to drive ADC inputs by providing the ability to output 50 IlA
of current and the capability to drive 1100 pF of load capacitance without the need for
external resistors or buffers.
LM95241 TruTherm™
Remote Diode Temperature Sensor
• TruTherm technology for better accuracy
• 5MBus interface
• Two remote diode capability
• Three address versions available
• Up to 13-bit (O.03125°C) resolution
• Remote temperature measurement to 255°C
• Diode fault detection
•..'1 National
~ Semiconductor
The Sight & Sound of Informetiol1
National's LM95241 is an example of an extremely versatile Remote Diode Temperature

Sensor (RTDS). This device can monitor the temperature of two remote diodes plus its own
temperature. This device is capable of monitoring today's extremely small geometry diodes
with very fine temperature resolution. TruTherm™ technology allows accurate sensing of
integrated thermal diodes, such as those found on processors. With the TruTherm mode
turned off, the LM95241 can measure the temperature of a diode connected transistor such
as the MMBT39D4.
The LM95241 comes in three versions, each with a different Fe compatible 5MBus
address, allowing up to three different devices to co-exist on the same bus.
The 13-bit resolution allows remote diode temperature measurements between -55°C and
+125°C with a 2's complement output, or from DOC to 255.875°C, with unsigned binary
format.
The diode fault-detection circuit reports a fault condition if the D+ pin is shorted to GND, to
D-, to the supply, or is floating.
LM95235 TruTherm™
Remote Diode Temperature Sensor
• TruTherm technology for better accuracy
• 5MBus interface
• Three-level address pin
• Remote temp measurement to 255°C
• Diode fault detection .,,,
-
•..'1 National
PSemiconductor
ThllSight&Soundoflnformlltion
The LM95235 is very similar to the LM95241 except that, rather than using three different
versions for different addresses, a three-level address pin is used to provide the possibility of
three different LM93235s on the same bus. It also can measure the temperature of a single
remote diode in addition to its own die temperature.
Pin 6 is programmed to be an address input or an active low "Over Temperature Shutdown"
output that can be used to shut the system down, interrupt a processor, or any desired
function when temperature exceeds a pre-programmed limit.
The LM95241 and the LM95235 are just two examples of the remote diode temperature
sensors available from National.
Application Consideration:
Driving ADC Inputs
Typical SAR Analog-Io-Digital
Converter Input Stage
,,------------
"
LM94022 Input
Pin
,," ""
,
#fI'
Voo OUT
J C
FlLTER '" ,
rC'N
•...
,------------
• The LM94022 can drive up to 1100 pF of load capacitance and
source 50 JAA of current
• Ideal for driving ADC inputs with filter capacitor of a 1 nF or less
• A series resistor on the output can be used for greater load capacitance
(see datasheet)
•..'1 National
()I'Semiconductor
The Sight a Sound of Inform,tJrJfl
Most analog temperature sensor applications use an ADC to sample the analog temperature-
proportional voltage output. These ADCs may be discrete or may be integrated into a
processor or a microcontroller. The LM94022's output is optimized for driving the input
stage of an ADC and a filter capacitor that is often located at the ADC input. Its high 1100 pF
max load capacitance specification means that a filter capacitor as large as 1 nF ± 10%
can be driven by the LM94022 without requiring any external series resistor to stabilize the
output. Eliminating the extra component saves the customer cost and board space.
Additionally, the robust 50 !-LAof source current is designed to drive demanding ADC
current requirements.
Customer Problem:
InaccurateTemperature
Reading
lM94022 driving microcontrolter ADC Input

Na filter cap on output
,
lJ,64l)21 sDurcmgn1lcrocontrollerADCmput
No filter cap 00 output
.cJNattonal
P Semiconductor
Th9Si{Jht.!Soufldoflnfofma/iofl
A customer complained of inaccurate temperature readings with the LM94022 when driving
the input to a sampling ADC. In a cost-cutting move, he eliminated the capacitor at the
LM94022 output.
These two scope photos demonstrate (1) the transient loads placed on the source when the
ADC's sampling capacitor is charging and (2) the stability achieved by placing a filter
capacitor at the input to the ADC. The capacitor is needed when the sampling rate is too fast
to allow the temperature sensor output (ADC input) to stabilize. When the sensor is a low
power device, as with the LM94022, it may not produce enough output current to settle
before the sample is taken, and the addition of a filter capacitor will improve accuracy. The
size of the capacitor will depend upon the size of the internal ADC sampling capacitor (in
this case, the ADC sampling capacitor was approximately 50 pF) and also upon the
sampling frequency. Generally, the filter capacitor value should be about 10 to 20 times the
ADC sample capacitor value. Care must be taken to ensure that the sample frequency is
matched to the maximum source current of the sensor so that the filter capacitor remains
charged to the appropriate level. As you can see in the first image, the output gets pulled low
as the sample capacitor starts to charge. If the sample rate is faster than the time in which the
capacitor can be recharged, that capacitor would still be charging and not settled when the
next sample time ends. The second image shows the benefit of adding a 1 nF filter capacitor
at the ADC's input. The result is a stable DC voltage which is proportional to temperature.
We generally recommend a series resistor in addition to the capacitor for dynamic
applications, but the capacitor alone can be used if the ADC input is static or a slowly
moving DC and the driving device can tolerate the capacitance.
Note also that the "Measured Temperature" indicated here is the temperature measured with
a separate sensor.
When Should You Use
Ie Temperature Sensors?
• When the sensor's temperature range will
be between -55°C and +250°C
- Electronic systems monitoring
- Environmental controls and measurements
• When design time is critical
• When lookup tables are undesirable
• When space is at a premium
dNa/tonal
P Semiconductor
111, SIght a SDund of Infotm,lJDtI
Designers have numerous options for temperature sensing techniques. Thermistors, RTDs,
thermocouples, and active silicon sensors are among the most common. Each has its own set
of advantages and disadvantages in any given application. IC sensors have major advantages
when the temperatures to be measured fall within the normal operating temperature range of
silicon ICs. Among these advantages are small size and fast design time (because external
signal conditioning circuitry is either minimal or not required). In addition, sensor ICs can
include extensive additional functions, such as built-in trip-point comparators or digital I/O.
And, since they include on-chip linearity correction, there is no need for lookup tables to
correct for linearity errors.
National's Focus Areas in
Temperature Sensors
• Multiple Remote Diode Temperature

Sensors (ROTS)
- LM83, LM95241, LM95235, LM95221, LM95231
• Tiny, accurate temperature sensors for
portable systems
- LM20, LM94022
• Accurate temperature sensors
- LM73, LM76, LM92, LM95071
d National
P Semiconductor
T~SifJhtaSoundoflnform,tJon
National has a wide variety of integrated circuit temperature sensors for many different uses.
Traditionally used in Heating, Ventilation and Air Conditioning (HVAC) control systems,
temperature sensors also can be found in PCs, PC peripherals and in personal
communication devices and other communications equipment, to name just a few places. IC
temperature sensors can measure the temperature of a printed circuit board, ambient air,
chassis case temperature, and the die temperature of a power-hungry ASIC, graphics engine
orCPU.
The latter is where RDTS has found the greatest use. Sensing the case temperature of
power-hungry ICs has always had its mechanical challenges in terms of placement and
mounting of the temperature sensor. If the IC is a surface-mounted device, it usually has
hundreds of pins, making positioning of the external temperature sensor close enough to get
an accurate, low thermal lag measurement a nightmare for PCB layout. National's RDTS
products help solve these kinds of monitoring problems.
With the continued miniaturization of portable systems, National has led in the IC package
miniaturization challenge. We have both analog and digital temperature sensors in micro
SMD (Surface Mount Device) and LLp® (Leadless Leadframe Packages). Our 4-pin micro
SMD package is smaller than many available surface mount resistors.
Applications in modem HVAC and process control systems require great accuracy. Again,
National is the leader with the most accurate digital output temperature sensor available
today.
Hardware Monitor Functions
• Temperature sensing
Local
- Remote diode
dNational
P Semiconductor
The Slghr .I Sound of InfOf1Mf1OfI
Hardware monitors are devices used to monitor the status of a system. As such, they contain
an internal temperature sensor, remote diode temperature sensing capability, and inputs for
other voltages that may come from supply voltages, analog temperature sensors, or any
other type of sensor or voltage source.
LM94 TruTherm™
Hardware Monitor
• 5MBus interface
• Quad remote diode sensing
• Monitors 16 voltages
• -127°C to +125°C temperature reading range
• 2 PWM fan control outputs, 6 temp. zones
• 4 Tachometer inputs
• Diode fault-detection
d National
~ Semiconductor
Th,Sight&Soundoflnform'fJon
The LM94 is our latest hardware monitor and comes with our TruTherm capability for remote
diode sensing which provides greater temperature accuracy with diodes of the newest small
geometry products such as processors, graphics engines, large PLDs, and ASICs. Its ability to
monitor 16 remote diodes, 16 separate voltages and 4 fans, together with its 2 fan-control outputs
make it a very powerful device.
Furthermore, the wide temperature range capability and diode fault-detection capability further
enhance its utility.
LMV227
Pwr
10 kO Detector
Temperature Monitors:
Processor
LM94
Hardware
Monitor
~National
P Semiconductor
Tn. Sight a Sound of Infonn,tKHI
The LM94 is a very powerful hardware monitor, as indicated on the previous page. Here we
see a simplified implementation in an RF transmitter application where remote temperatures
and many voltages may be monitored and fans may be controlled. Communication with the
host processor is through a two-wire 5MBus.
The 30 kO output impedance of the LMV227 may require that it be buffered to drive the
LM94 input.
.•..'1 National
PSemiconductor
Interfacing to the Sampling

ADC Input
The sampling ADC, unless the input is buffered, has analog input current pulses at the ADC
sample rate. Let's take a look at how this affects the sampled signal and what should be
done about it.
ADC Input Glitches - Passive Drive
• ADC input glitches are caused by sampling action
• It is not necessary to eliminate the glitches
• Input needs to settle before sampling switch opens
SARADCClock __
Sample switch closes on rise of clock,

causing input glitches
•..'1Nalional
P Semiconductor
Tha Sight & Soundof/nformariolJ
A look at the sampling ADC input will reveal pulses at the ADC sample rate. These pulses
are caused by the recharging of the ADC sampling capacitor at the start of each conversion
cycle. The user should not attempt to filter out these pulses, which are completely normal.
However, the pulses should settle out before the end of the sampling time, which is
generally specified in the datasheet.
In the case of high-speed ADCs with a sample rate equal to the ADC clock rate, the
sampling time is usually either the clock low time (when the sampling edge is the rise of the
ADC clock) or the clock high time (when the sampling edge is the fall of the ADC clock).
ADCs based on Successive Approximation Register (SAR) usually sampled for more than
one clock period.
ADC Input Glitches - Amplifier
Drive
• ADC input glitches are caused by sampling action
• It is not necessary to eliminate the glitches
Sample switch closes on rise of clock,

causing input glitches
~ National
(.iIf'Semiconductor
The $ight&SQundoflnfQrmation
If a feedback amplifier (operational amplifier) is used to drive the ADC input, there may be
overshoot as the amplifier over-corrects for the pulse. Again, there should be no attempt to
filter out these pulses, but they should settle out before the end of the sampling time.
ADC Sampling Filter
• Sampling filter isolates capacitance from amplifier
while allowing input to settle
VADe =V S1G - Verr

where V C
=..::J x FSR x e-(Ut)
err Cf
t = Ts, 't = R f Cf
Verr < Y:zLSB
Cf ~10XCi
R S_ Ts
f 10x <; x In[10x 2-W]
~Nattonal
P nr,Semiconductor
Sighr " Sourld of Informltion
Standard practice when driving the input of sampling ADCs is to isolate the op amp output
from the ADC input with a small resistor and a capacitor. The reason for this is to allow
faster settling of the ADC input to ensure that it has settled before the ADC sampling switch
opens. Additionally, some SAR ADCs can have a large input capacitance that might bring
instability to the driving amplifier. The resistor between the amplifier output and the ADC
input will isolate the ADC input capacitance from the amplifier output and improve loop
stability of the amplifier.
For dynamic applications with AC signals up to half the sample rate, Ts should generally be
the sampling time of the ADC, which can be found in the ADC datasheet.
Refer to the op amp datasheet for specific information when driving capacitive loads.
ADC Sampling Time from Datasheet
• The ADC12DL080 electrical table and the partial timing diagram tell us the
sample time is the same as the clock low time.
ADC124S101
Timing
v"':e" .....- ~
Converter Electrical Characteristics (ADC12DL080)
Unlessolherwise specItIed. the following specltlcatlons IIPPIy fof AGNO::c OGNO '" OR GND '" av, V.:= Vo = +3.3V, VOR:=
Duty Cycle Stabilizer On. Boldface
v••
+2.SV, PO::c rN, Extemal VR~:E +1.0V,IcUt' '" 80 MHz. IIN:: 40 MHz, CL '" 10 pF/pln, l-
o/t
limits 8pply for TJ • TM1N to TMAX: all oItler limits TJ = 2£j"C (Nolu 7, 8, 9)
Units
(LImits)
CO<
pi'
pi'
.•.'1 National
~ Semiconductor
The Sight & SQund of Informstion
The ADC sampling time can be obtained from the datasheet timing diagram and, sometimes,
from the electrical characteristics table.
The timing diagram of SAR-based ADCs will usually show the sampling, or track, time on
the timing diagram, as indicated here for the ADCI24SlOl, a 12-bit, 4-channel ADC
specified for operation over the 500 kSPS to I MSPS range.
The data sheet electrical table for the ADCI2DL080, a 12-bit, dual low power ADC
specified at 80 MSPS, indicates that the sampling time is the time that that clock input is
low. We know this because the input capacitance is highest during the sampling time. The
timing diagram also indicates that the sampling time is the time that the input clock is low
because the sampling period ends at the rise of the clock.
• Application: "Black Box" cockpit voice
recorder
• Observed spikes at input of ADC121 S101
• Added large capacitor at ADC input
• ADC input signal almost non-existent
• Solution: Do not try to eliminate spikes, but
allow spikes to settle out before sample
switch opens (Use RC with fc as described
earlier)
d National
p Semiconductor
111. Sight a Sound oIlnform.DOfI
This customer problem is a very common one. As mentioned before, the important thing is
to allow the input the settle while the ADC sample switch is closed. The RC time constant
should provide a pole as described on the previous slide.
Customer Problem:
High Pitch 'Whine"
• Application: "Black Box" cockpit voice
recorder
• Using ADC121 S021 at 44 kSPS
• High pitch "whine" in reconstructed
recording
• Cause: Aircraft instrumentation (probably
gyro) vibrated at a rate above the range of
hearing that the microphone picked up and
the ADC aliased
• Solution: Use an anti-aliasing filter
~ National
[iI" Semiconductor
Th.Slghf&SoundoflnfDrm'tJon
This customer problem was solved by adding an anti-aliasing filter. A 30 kHz vibration can not
be heard directly, but when sampled at 44 kSPS, 30 kHz, for example, is aliased back to 14 kHz,
which is audible.
Customer Problem:
Rail-to-Rail Output Issue
• Problem: The output of a "rail-to-rail"
amplifier may get down to 10 mV. With a
2.0V reference and an input range of OV to
2.0V, how many LSB of a 1O-bit ADC is this?
2V/210 = 1.95 mV/LSB
10 mV/1.95 mV = 5.12 LSB
The lowest code, then, that will

be seen at the ADC output is "5".
• Solution: Use a pull-down resistor on the

amplifier output
~ National
(iI" Semiconductor
Th. $lghr& Soundoflflfofm.boII
Rail-to-rail amplifiers are very nice products, but they do have their limitations. Here we see
that, with a unipolar supply, a rail-to-rail output amplifier can not provide a signal swing that
goes low enough to use the entire dynamic input range of the ADC. Of course, we lose more
codes as the ADC resolution goes up.
If the full-scale input of the ADC is at the positive supply rail of the amplifier, we also will
not see the codes near full-scale as well. On top of this, there is more distortion at the output
of the amplifier as that output gets closer to the rails.
The solution for this customer was to use a pull-down resistor (270n) at the amplifier
output. The resistor value will depend upon the type of amplifier used and how much
distortion is allowed.
Input Overdrive
• Driving the ADC input beyond the
supply rails can cause latch-up
• Potential problem when using different
supplies for ADC and driving device
• Potential power-on or power-off problem
• Potential problem with power sequencing
.•..'1 National
P Semiconductor
Th9Sighr&Sollndof'nforfflBtlon
If the input to any device, ADC or otherwise, is driven far enough beyond the supply rails
for that device, the result can be a latch-up of that device. A hard latch-up can be
destructive, but more often there is a soft latch-up whereby the device does not work
properly or may not function at all.
Examples of potential problems include driving a single +5V supply ADC with an amplifier
that is powered from ± 5V, from ± 12V or +12V, or even from a separate +5V supply
source from the ADC's power source.
Protecting the inputs with a resistor and two diodes, as shown here, is an effective way of
protecting most ADC inputs. However, this may not be adequate for some devices,
particularly some older devices.
The on-chip ESD diodes do not have a low enough forward drop to adequately protect
against input overdrive.
~National
P Semiconductor
Noise Considerations
We know that noise is always an issue. Adding more circuitry usually adds more noise. There
are things that can be done, however, to minimize the impact.
• Two different PSRR specifications
- What you expect
- What is on the data sheet
- These two are usually NOT the same!
• DC PSRR - change in a DC parameter with
change of supply voltage
• AC PSRR - How much supply noise gets
through to the output
• Datasheets generally show DC PSRR
dNa/tonal
p Semiconductor
",. Sight 4 Sound oIl"torm6t101l
There are at least two different ways to specify Power Supply Rejection Ratio (PSRR). The
PSRR spec we generally see on semiconductor datasheets is DC PSRR. That is, it tells us how
much a certain parameter, such as offset error or gain, can be expected to change with a given
change in the power supply voltage. For example, an ADC with a 5.5 mV offset error at a power
supply voltage of 4.75V may have a 6.0 mV offset error at a power supply voltage of 5.25V,
giving us a DC PSRR of
PSRR = -20 x 10 (~ offset Voltag~\ = (0.006- 0.0055) = (0.0005) = 60 dB

g ~ supply Voltage! 5.25 - 4.75 0.5
This is not what we generally expect to see in the way of a PSRR spec. A very careful look at the
datasheet is usually required to see that the PSRR specified is what we here call DC PSRR and
has absolutely nothing to do with how power supply noise is rejected from the output.
Calculating AC PSRR
AC PSRR = 20 x LOG ( Analo~ Supply Ripple )

Normalized Output Tone
Convert output noise from dB to Volts: Volts = V10(~n
=
Ripple Vp.p peak-peak power supply ripple
VFS = peak-peak full scale input swing
d National
P Semiconductor
The Sight & Sound of InfQrm/ftiQn
AC PSRR, on the other hand, indicates how much noise on the power supply is rejected from the
output.
To measure AC PSRR we look at the ADC output level of the power-supply noise frequency
with a Frequency Domain (FFT) plot. Because the noise level on the power supply is generally
lower than the full-scale input range of the ADC, we normalize the output noise level to what it
would have been with a power-supply noise level equal to the ADC full-scale input range or
swing. Because the result is a scalar, we convert it to dB. Then we add it (algebraically) to the
(ripple) noise level. We negate that normalized figure and convert it to a voltage. The ratio of
that result to the peak-to-peak ripple voltage is the AC PSRR.
Calculating AC PSRR Example
• Example: applying a 40 MHz, 200 mVp•p signal to the

supply pin of an ACC with a 2.0V reference results
in a 40 MHz tone in the FFT plot at -63 dBFS. What is
the PSRR at this 40 MHz?
• Solution:
- Normalized Tone = -63 dB - 20 x Log(0.2/2.0)
= -63 dB - (-20)dB
= -43 dB
- Tone in Volts =
10A(-43/20) =
0.007079V
=
- AC PSRR 20 x Log(0.2/0.007079V) 29 dB =
••'1 National
~ Semiconductor
Th,S,ght4Soundoflnformllrion
A 10-bit ACC datasheet has a PSRR spec of
72 dB with "gain" listed as a condition. What
does this mean? How much high-frequency
noise can the ACC tolerate on the power
supply?
"Gain" as a condition shows that PSRR indicates the

sensitivity of gain to supply voltage variation
This kind of spec does not indicate the amount of
noise that can be tolerated on the power supply
.•.'1 National
()I'Semiconductor
Th. SIght & Sound of 'nfDrm,fJ(Jn
The condition of "gain" means that the specification is DC PSRR and is an indication of the
effect that a change in the DC power supply voltage affects the ADC gain. This spec tells us
nothing about the amount of noise that can be tolerated on the power supply.
PSRR Question 2
An ADC is being powered from a switching

regulator with about 600 mV of ripple at 1 MHz.
An FFT reveals a -66.4 dBFS spur at 1 MHz.
The input dynamic range is 2V. What is the AC
PSRR of this ADC at 1 MHz?
Since 600 mV is already about 10.5 dB below the

2V full scale range, the AC PSRR at 1 MHz is
10.5 dB worse than the 61 dB below full scale
that we see at the output, or 55.9 dB
•..'1 National
p Semiconductor
Th,$If1htoiSoundof/nfOl'm,tfon
n
V1NX2 )
( SF x VREF
Where V1N is the analog input voltage

VREF is the ADC reference voltage
SF is the reference scale factor
n is the ADC resolution (# of bits)
~ National
P Semiconductor
The Sight& Soundoflnform.tion
The ADC output tells us the ratio of the analog input voltage to the reference voltage. Because
the digital output code is a function of the reference voltage, a change of the reference voltage
will cause a change in the output code, just as does a change in the analog input voltage.
Therefore, any noise or variation in the reference voltage appears at the ADC output.
The Scale Factor (SF) in the formula is something not usually discussed as it is most often unity.
However, it is present and should be taken into consideration because some data converters have
scale (gain) factors that are other than unity. The SF can be any number, whole or fractional.
ADC Output Noise vs Resolution with
0.15% Reference Noise
120
100
iil
tn
=-••
III
80
'0 60
z
:;
,So 40
::>
0 20
0
0 10
ADC Resolution (bits)
•..'1 National
l"" Semiconductor
TheSight&Sovndoflnformalion
This graph indicates the amount of output noise present with 0.15% noise on the reference
voltage. Note that this amount of noise is tolerable at 8 bits and even seems tolerable at
10 bits, but the next page shows the amount of Signal-to-Noise Reduction (SNR) we have at this
reference noise level.
Reference Noise and
SNR Reduction vs Resolution
ADC SNR Reduction vs Resolution with

0.15% Reference Noise
45
40
lil 35
~
c: 30
o
ti 25
-6 20
•• 15
ll::
ll::
z
Vl
10
5
o
10
ADC Resolution (bits)
~NatiQnal
P Semiconductor
111. Sight a SDund of Infonn.Don
The two LSB of peak-to-peak noise at 10 bits does not seem like much until you realize that it
brings a 6 dB reduction in SNR performance. Of course, at higher resolutions the effect is much
more dramatic.
If you calculate the amount of noise tolerable on the reference voltage needed for various
resolutions, you will find that the tolerance is reduced by 50% for every additional bit of
resolution. This means that the 0.1953% tolerance for Y, LSB noise at 8 bits becomes 0.00076%
at 16 bits and 0.00000298% at 24 bits. This points to the increasing importance of a quiet
reference at higher resolutions.
High Capacitance on
ADC Outputs
I
I
I
I
I
1I Driven •Device
d National
P Semiconductor
The $ight & Sound of Inform /In on
Since the well-bypassed supply line is isolated from the die by the bond wire inductance as an ADC
output pin goes from low to high, we can have negative-going spikes on the supply line. We call this "V cc
bounce." If the supply line used for the output driver stage(s) is common with the supply line for other die
areas, these spikes can couple into those areas. In the digital areas it can cause jitter-induced noise. In the
analog areas it can directly add noise to the conversion process.
As the digital output(s) go from high to low, the charge on the bus and driven device input capacitances
passes through the die substrate and the ADC ground pin. The ground bonding inductance isolates the die
common from the nice, clean ground at the device pin and pulses of varying amplitude, depending upon
how many outputs are discharged, occur on the die. We call this "ground bounce." The die common, then,
is not at ground or a steady voltage, but can vary enough to cause the difference between the input signal
and ground to be noisy and we have a noisy conversion.
In the case of a differential input ADC, you would think that the Common Mode Rejection (CMR) of the
differential input would eliminate the problem. However, the CMR of any circuit gets worse as frequency
increases, typically getting rather poor as frequency exceeds a few hundred kilohertz. Since these ground-
bounce pulses occur at rates up to the output data rate and since the fast rise time corresponds to even
higher frequencies, the CMR at the frequencies involved is nearly zero.
The task, then, is to minimize these charge and discharge currents so that the induced noise is minimized.
The first step to minimizing this induced noise is to minimize the capacitive loading on the digital output
pines). This means that a bus should not be directly driven by the ADC (thus the reason for a lack of
newer ADCs having a tri-state output). Lower capacitance means less charge moved and less induced
noise. So, it is important to drive only a single, low-capacitance input pin of a receiving device, which
should be as close as possible to the ADC output pines).
Output to Input Coupling
. Output "talks" to input

- Because of output capacitance
- Through the supply
- Through the substrate
. Limiting output current (with resistors)
can help
10~F~ ~ 10~F
J:1
0.1 ~F QO.1~F
-:- 8 x47
.:]Nattonal
P Semiconductor
Thfl Sight & Sound of Informarion
Sometimes, however, it is not possible to get the output capacitance low enough to eliminate the
induced noise. This is especially true at higher ADC resolutions, low reference and signal levels,
and higher sample rates. In this event it is helpful to use 47 to lOon series resistors at the ADC
output pins, located as close to the ADC output pins as possible. This limits the amount of
current used to charge and discharge the capacitances on the ADC outputs and lowers the on-
chip noise.
If the series resistors are not located very close to the ADC digital output pins, the board
capacitance between the ADC and the resistors can be high enough to produce more noise than
desired. This, again, is especially true at high resolutions, low reference and signal levels, and
higher sample rates.
~National
p" Semiconductor
Offset Considerations
The cumulative offsets that are possible in the signal path is something that is not often
considered. This can cause failures at the product test phase or in the field.
• ADC has zero scale and full-scale gain errors
• Amplifiers have offset (Vos) and gain errors
• These errors are additive
• ADCs have zero scale and gain-error tempcos
• Amplifiers have offset tempco (drift)
• These tempcos are additive
• Most important in DC-coupled applications
• Allowable tolerance depends upon
system requirements
•..'1 Nalio1lal
(II" Semiconductor
Th, SIght a SDund of Infrm'WKNl
Here we see some important considerations regarding offset and gain errors in the ADC and
amplifiers that drive the ADC. How much of these errors can be tolerated is determined by
system requirements.
··············--;:1·;<------------
Actual ADC
Transfer Curve
//~/ 1
//
/;;:<1..1..cI"
/ '~Transfer
ADC
ADC Output
Signal
V / . _~~_':".~ - Unused Swing
\t \~'--ADC Full Scale Error
j ~ ~ "Perfect" Range of
Actual Range ~f : voltages to be digitized
voltages to be ,
digitized ' --__ '
------~ ,,
,
ADC Gain Error =
ADC Input Full Scale Error - Offset Error
Signal
d
l'" Natiotlal
Semiconductor
Th. Slght.t Sound of Inform'lion
Offset and gain errors will affect the output unless we either allow for them or compensate for
them. Of course, any amplifier offset error will add to the offset error of the ADC, as will any
gain error.
Large Vas Drift Reduces FSR
• ADC and amp offset change causes shift in ADC
output code range
• Result is loss of full-scale range if output clipping is
to be avoided
Vas Drift, LSB Shift over -40°C to +85°C (FSR = 2V)

~vrc 10 Bits 12 Bits 16 Bits FSR Loss
1 0.064 0.256 4.096 0.006%
10 0.64 2.56 40.96 0.063%
100 6.4 25.6 409.6 0.625%
dNational
(II" Semiconductor
n. Slfht, Sound of IlIforrgt1Dfl
If we are to avoid clipping of the ADC output, we must reduce the input swing to allow for
worst-case offset and gain errors and their drifts. This means a loss of input dynamic range and a
resulting loss of SNR performance.
Manually Adjusted
Offset and Gain Error Compensation
Serial or Parallel
Data Output
- Top
Bottom
Reference
Full-Scale Reference
Voltage
Adjust Voltage
Bottom Reference may be

ground, in some cases
Offset
Adjust
~National
P Semiconductor
1M Sight a Sound of 1,,(orm,t1OtI
System gain and offset errors can be compensated for by slightly modifying the top and bottom
reference voltages of the ADC. The problem here is that most ADCs have the bottom reference
fixed to ground and cannot be adjusted. Furthermore, manufacturing people do not like manual
adjustments, which are rather costly in production. As if this were not enough, offsets tend to
have time and temperature drift.
Fortunately, there is a better solution for all of these cases.
Manual Offset Adjustment
Without Bottom Reference Access
Serial or Parallel
Data Output
Gain/Full-Scale
Adjust
Offset
Adjust
dNational
P Semiconductor
Th. Sight a Sound of Information
When the bottom reference of the ADC cannot be adjusted, the amplifier offset can be adjusted
to null system offset errors. However, the problem with manual adjustments and drift are still
present. But there is a way to get around this.
Processor Controlled
Serial or Parallel
Data Output
~~
-=- Top
Reference Bottom
Full-Scale Adjust Voltage Reference
D'N Voltage
SYNC
Two DAC0815101s may be used

in place of the dual DAC0825085
d National
PSemiconductor
1M Sight a Sound of Info"".fIOn
This solution has the advantages of processor-controlled adjustment of offset and gain errors
whenever desired. For example, adjustments could be done upon application of power, when
temperature changes by a preset amount (because of temperature drift) and when a preset amount
of time has elapsed (because of time drift) since the last adjustment.
Processor Controlled
Serial or Parallel
Data Output
Reference
Offset
CLOCK Voltage
Adjust
D'N
SYNC .2C
CTRL
dNattonal
P Semiconductor
TheS"",.lSoUfldollnfol"m.DOn
If the bottom reference of the ADC cannot be modified, the offset adjustment can be done
through the amplifier, as we saw with the manual adjustment.
Now, what can be done when the reference voltage is the supply?
Automated Offset and Gain Error
Compensation when Supply is
Reference
Serial or Parallel
Data Output
Offset
~
Voltage
Adjust
D'N
SYNC
.•.'1 National
(;l" Semiconductor
Th. Sight a Sound 01 Inform,fJon
When the reference voltage is the supply voltage, such as is the case with National's
ADC121S101, a DAC can be used to provide an adjustable supply voltage. Since the power
consumption of our general-purpose ADCs is so low, driving the supply with a DAC is a simple
matter.
Manual Offset Adjustment
Differential Input, No Bottom Reference
Access
Top
Reference
Voltage
Gain/Full-Scale
Adjust
Offset
Adjust
d National
~ Semiconductor
nut S"ht a Sound oIlnform.DOn
Here is an example of full-scale and offset adjustment with a differential input ADe when the
bottom reference voltage cannot be adjusted. This circuit shows the LMH6550, a fully
differential amplifier, being used in a single-ended-to-differential conversion circuit.
Processor Controlled Offset and Gain
Error Adjust, Differential Input
Serial or Parallel
Data Output
Reference
Voltage
CLOCK
D'N
SYNC Offset
Adjust
Full-Scale Adjust
.•..
'1 National
Ii" Semiconductor
a
The Sighr Sound of /n/olm.tIon
Again, processor-controlled adjustment of the offset voltage is possible with a DAC in a circuit
having a fully differential amplifier.
DAC Usage Considerations
• Quiet reference voltage or current
- VOUT= VREF X G x D/2" (voltage output DACs)
lOUT= IREF X G x D/2" (current output DACs)
• G = DAC gain factor
• D = Digital input code
• n = DAC resolution in bits
• When reference is supply
• Signal integrity
~ National
l'I'Semiconductor
1M Sight a Sound of IrJform6rifHl
With any device, there often are considerations we do not think about. In the case of the DAC,
we find that the importance of a quiet reference voltage is often overlooked, especially when the
supply is the reference. Remember that since the output depends upon the reference, any noise
on the reference will show up at the output, just as is the case with the ADC. When the reference
voltage is the supply voltage, it is important to ensure that the supply voltage is very quiet. This
often means using a separate regulator or reference source for the DAC supply line.
Of course, signal integrity is important to ensure that the expected information is loaded to the
DAC.
General Purpose DACs
Features
• Guaranteed monotonicity • Reference is supply
• Low-power operation • 2.7V to 5.5V supply
• Small packages
• Rail-to-rail voltage output
• Power down feature
• SPI interface
Resolution
Channels
8-bit 10-bit 12-bit
Drop-In
Replaceable
1 DAC081S101 DAC101S101 DAC121S101
Across
Resolution
2 DAC082S085 DAC102S085 DAC122S085 and Sample
ate
4 DAC084S085 DAC104S085 DAC124S085
National's new DACs are small, rail-to-rail output high performance DACs that address the most
common DAC applications. We believe you will find these DACs to be among the best
available.
Customer Problem:
DAC121S101 Excessive Output Noise
• Problem: Excessive noise on the DAC121S101

output
• Conditions:
DAC uses a 3.3V supply
Reference is the supply
Output reconstruction filter uses an LMV751 with a
5V supply
• Discovered: The 3.3V supply was the same used by
3V logic
• Solution: Use an LP2980 LDO with filtered 5V input
for DAC121 51 01 supply
•..'1 National
P Semiconductor
TheSigllt&SQlIndQflnfQrmar;Qf/
The customer did not think of the results of noise on the supply line when the reference is the
supply. When this was brought to his attention, he immediately realized his error. The LP2980
Low Dropout (LDO) regulator did the job for this customer, but the LM4l40 would provide a
more accurate voltage for the sake of the reference. However, the closest voltages available are
2.5V and 4.096V. The LM4041 adjustable reference would be an excellent choice to obtain
whatever voltage is required. The LM4041 is available with accuracies to 0.5%.
~National
PSemiconductor
Managing Jitter
Modem high-speed, high-resolution Analog-to-Digital Converters (ADCs) have very high

resolutions and can accept and are used with input frequencies as high as hundreds of MHz and
sometimes even beyond 1 GHz. Sensitivity to jitter increases with higher signal frequency and
ADC resolution, so jitter management is an important consideration.
• Jitter - the cycle-to-cycle variation in the
signal edge relative to another edge
•..'1 Noli 0 n 0 I
l'" Semiconductor
& 0'
Th, SIQht Sound Inform,tlon
Jitter is defined as the cycle-to-cycle variation in the edge of a signal and is usually spoken of as
fIllS jitter.
Jitter: cycle-to-cycle variation in timing
Sample amplitude
t
variation due to jitter t
ADC
clock
.•.'1
l'" Na ti 0 n a I
Semiconductor
The Sight & Sound of Informafion
Because jitter in the ADC clock relative to the input signal means that there is a variation in the
time a signal is sampled, there is variation in the sampled signal level. If we try to sample the
same point in a waveform at every cycle of that waveform, but there is jitter present, we may
sample levels between, for example, 1.14V to 1.1V, or a 10 mV spread in this example. This
means there is 10 mV of noise at the output. With 6- or 8-bit resolution, this might not be too
bad. At higher resolutions, this can be significant.
The effect of jitter is more easily seen at higher resolutions (digital word widths) and higher
frequencies.
Signal Jitter
Signal jitter has the same effect as clock jitter
Sample amplitude
variation due to
signal jitter t
d National
P Semiconductor
.,.". Sight" Sound of f"fortrnOOll
When considering jitter in ADC applications, we generally think of clock jitter. However, jitter
that is added by the circuitry to the input signal has the same effect as does jitter in the sample
clock. The clock jitter relative to the signal jitter is where the problem exists.
High-Speed ADC Clock Considerations
• Maximum allowable jitter to prevent

significant noise degradation:
V1N(P_P)
t.max =
J 2(n+1) x V FS x 1t x f.In
• Clock rate has no effect upon

jitter-induced noise
l'"
~ National
Semiconductor
Th,Sighf&SOulldoflnformlltiQ/1
Jitter in the sampling clock or in the input waveform (actually, the jitter between the two) results
in decreased noise performance, as we will see shortly. The maximum allowable jitter, from all
sources, is as shown here if we are to prevent it from affecting performance. Jitter is a prime
source of noise with digitized high-frequency signals. Note that sample rate does not enter this
formula because, by itself, it does not affect sample placement. It is the input signal slew rate,
which does not depend upon clock rate, that determines how much jitter affects the output signal.
Most people use a 2n factor rather than the 2(n+l)shown here, but that would limit the noise to
one Least Significant Bit (LSB). Using a factor of2(n+l) limits the noise to Yz LSB, which means,
for all practical purposes, no jitter-induced noise.
High-Speed ADC Clock Considerations
• When the signal is a full-scale one,

the formula reduces to:
t.max
J
=
.•..
'1 National
~ Semiconductor
The Sight& Souncloflnformerion
• High-speed ADCs can exhibit jitter as low as
0.2 ps (rms). It is difficult to find clock
sources with less jitter than about 1 ps (rms).
For a system with a 12-bit ADC and with ADC
input frequencies up to 25 MHz, is clock jitter
a problem?
Allowed tj = 1/[ 2(n+1) 7tfiN]
= 1/[2137t25x 106]
= 1.55 ps
ADC + External Clock Jitter = 1.2 ps,
which is less than the 1.55 ps allowed.
No problem at 12-bits. 25 MHz.
~ National
P Semiconductor
Th, Sight a Sound of Inform,tion
Knowing how much jitter your ADC can tolerate without affecting its performance is important.
After you know how much can be tolerated, you must find a clock source with sufficiently low
jitter so that this rms jitter, plus the rms jitter added to the signal by the circuitry and the rms
jitter of the ADC itself, added in an RSS manner, is less than the tolerable amount.
• The ADC12L080 is a candidate for a narrow-band 78 MSPS
application with an input frequency of 148 MHz. The data
sheet indicates an rms jitter of 0.7 ps. The ADC required
resolution is just 8 bits (12-bit ADC used for input dynamic
range) and the ADC will be operated with an input signal level
of -24 dBFS. The jitter of the clock source is specified at 2 ps
rms. Will clock jitter be a problem in this application?
8-bit performance required, so "n" = 8

Allowed tj = 1/[ 2(n+1) 1t fiN]
= 1/[ 29 1t 148 x 106 ]
= 4.2 ps
ADC + External clock jitter = 2.7 ps, which
is less than the 4.2 ps allowed
There is no problem for this application
~National
P Semiconductor
ThB Sight & Sound of Information
This example illustrates how we determine if the jitter of a specific ADC is adequate for the
application.
~ National
(ilf'Semiconductor
The 51gl1r a Sound of InftNm.tJDtl
These plots from National's WaveVision2 software show the effects of excessive clock jitter.
The noise on the signal is apparent. Normally, you would never see the noise from clock jitter on
a time domain plot. We had to force enough jitter to demonstrate this much noise.
•..'1 National
P Semiconductor
ThfiSight&SoundoflnfQrmatiQn
All of these wave forms (taken with National's WaveVision4 software) look pretty much the
same, yet they were captured with varying amounts of jitter in the sample clock. We need to look
at a frequency domain plot to see the difference.
The Frequency Domain Plot
and Jitter-Induced Noise
Iifl'lO:l1HI .W)"kll
•.•• Ul't. tHt Jl101
no·" •• J1<l76tt~
tf'Oft'U4' ..01\7.11
"""1' 1'1QIl II ~
~ National
P Semiconductor
Th, Sight & Soufld of l"form'Don
With frequency domain plots, we can easily see the effects of jitter. The top left plot is taken
with no significant clock jitter. The top right plot is taken with 25.9 ps (rms) of jitter, which is,
according to our formula, the maximum allowable jitter. Note that we see about a 2 dB
degradation in Signal-to-Noise Ratio (SNR) and Signal-to-Noise And Distortion (SINAD) with
this amount of jitter. Note also the spectral leakage, or "spreading," of energy around the base of
the fundamental. The reason for the degradation is because we did not allow for the jitter in the
ADC itself or for any jitter in the input signal. If the total jitter in all of these sources were
25.9 ps (rms) or less, we should see very little difference in the top two plots. The other plots
show the effects of higher amounts of jitter.
Maximum Allowable Jitter by Input
Frequency and Resolution
30
lil 25
•..
E
III 20 -+- 8 Bits (ADC08200)
3:
•..
Q) 15
..•... 10 Bits (ADC10080)
...•...12 Bits (ADC12L080)
..,
~
10 ..•... 14 Bits (ADC14L020)
><
III
5
==
0
0
The maximum jitter tolerable without suffering a degradation in SNR is determined by the
resolution of the ADC and the frequency of the input signal, as well as the signal amplitude
relative to full scale. The curves are for a full-scale input signal to the ADC. Again, the sample
rate has no effect upon the maximum allowable jitter to prevent noise degradation.
Maximum Jitter(2)
Maximum Allowable Jitter by Input

Frequency and Resolution
•..E 4
Ul -+- 8 Bits (ADC08200)
33
•..ell ..•.. 10 Bits (ADC10080)
-.-12 Bits (ADC12L080)
..,
E 2
..•.. 14 Bits (ADC14L020)
><
III
::ii:
0
0
•..'1 National
~ Semiconductor
Th. $ight & Sound oflnform,tIon
This is the same as the previous slide with the vertical scale expanded.
It seems that avoiding noise-induced jitter is an impossible task at very high input frequencies or
at high resolutions. Careful selection to the the clock source and how it is presented to the ADC,
as well as proper attention to design and layout, will go a long way toward maximizing circuit
performance.
Jitter Effect Upon SNR
14-bit Limit
80
iil 12-bit Limit

~
0::: 60
Z
en
Full-Scale Sine Wave Input Frequency (MHz)

•..'1 National
l"" Semiconductor
The Sight & Sound of Informs/ion
This graph shows the relationship between ADC input frequency, SNR, and clock jitter. Of
course, SNR will never be better than that indicated by the ADC resolution. Best
SNR = (6.02n + 1.76) dB, where "n" is the ADC resolution. Therefore, the best theoretical SNR
for an 8-bit ADC is about 49.9 dB and the best theoretical SNR for a 16-bit ADC is about 98.1 dB.
The theoretical SNR limit by resolution is shown with the dashed lines here.
Minimizing Jitter
• Decouple ADC input from the driving amplifier

• Minimize effect of output capacitance
• Use controlled impedance signal and ADC clock lines
• Minimize components in the signal and clock paths
• Any logic in clock path needs fast rise time
- A related rule of thumb is that Logic's toggle capability should be at
least 5 times the logic fiN
• Use a low-phase noise clock source (e.g., a crystal-based clock)
• Do NOT use a clock signal from an ASIC, FPGA or microcontroller
• Use a clock divider
• Keep supply of analog input and clock driving circuits as noise-free
as possible
• Avoid overloading clock source
•..
'1Naltonal
[:;9 Semiconductor
Full attention to these guidelines will help minimize noise problems.

Using a controlled impedance clock line implies one source driving a single destination.
Logic components tend to add jitter to the signal unless their toggle capability is significantly
higher than the actual toggle rate.
ASICs, FPGAs, and microcontrollers will generally add phase noise (jitter) to a signal. If the
ADC input frequency is in the MHz range, it is generally better to not supply the ADC clock
from these devices.
Starting with a high-frequency clock and dividing it down (using circuitry capable of toggle rates
much higher than the starting frequency) will reduce clock jitter, if done properly.
If the supply of the circuits used to drive the ADC clock or the ADC analog input is not fairly
free of noise, these circuits can often add significant jitter to the signal.
Overloading a clock source can add a lot of jitter to the clock signal. A high capacitive load on a
crystal-based overtone oscillator can cause it to operate in its fundamental mode rather than its
intended overtone mode.
~National
P Semiconductor
Signal Integrity and PCB

Layout Considerations
Signal integrity has become a popular topic in light of the very high edge rates that have resulted
from today's technology. Working with today's high-speed digital signals has meant that digital
designers must be concerned with signal integrity. Signals associated with modern data
converters are no exception.
Actually, even modern, lower-speed converters can be affected because digital circuitry today,
even with low toggle rates, tends to have very fast edge rates (rise and fall times). It is these edge
rates that require attention to signal integrity, not just the toggle rate.
Layout considerations take us into what might be a whole new world - a "Twilight Zone", if you
will - and are very much concerned with signal integrity. We will try to simplifY these
considerations and give you a couple of examples of typical problems in this area.
Signal Integrity Problem
Source
Rs
r- r - ~
r - ~
I \
I-
I
~Nattonal
(ill'Semiconductor
Th. Sight &: Sound of 'nforfflBtion
All interconnecting lines are transmISSIOn lines. If the transmission-line characteristic

impedance (Zo) is not matched to the signal-source impedance (Rs) or the signal-receiver
input impedance, there will be reflections on the line that can cause distortion and even an
amplitude change (increase or decrease) of the signal. This loss of signal integrity could
cause any number of problems in a system.
In the case of the data converter clock line, this mismatch can result in noise, missing codes,
erratic operation, or even a complete malfunction.
Maintaining Signal Integrity
Source
Rs
l'"
JIIIt..'1National
Semiconductor
"'- SIght a Sound of Inform.tJOn
Adding a series terminating resistor such that its value plus the signal-source impedance equals
the characteristic impedance of the transmission line will usually ensure the integrity of the
signal at the far (receiving) end and prevent problems, even without far-end termination. RT
should be as close as possible to the signal source.
Signal Traces vs Transmission Line
• "Long" lines are not simply traces

• Transmission lines can distort signals
• Distorted digital signals produce:
- Timing uncertainty
- Clock or signal jitter
• Through-hole problem
• Layout can be critical
~National
(ill" Semiconductor
1M S'lIht " Scund of 'nfrKm,tKHI
Here is a brief review of some important points we have covered:

All signal-carrying lines are transmission lines. Beyond a certain length we absolutely must treat
them as such if we are to avoid signal distortion, timing problems, and jitter.
Through-holes in a transmission line create impedance discontinuities and cause reflections with
their attendant distortion and noise problems. A through-hole in a PCB has about I to I Y, nH of
inductance, which can create problems. For example, a 14-bit, 80 MSPS ADC must have pins.
bypass capacitors that are no more than 2 to 3 mm from the bypassed Putting these capacitors on
the opposite side of the boardresults in the capacitors being isolated from the ADC by the 1. to:y..n
(at 80 MHz) of the through-hole inductance plus another 1. n or so in the trace inductance.
Layout is critical for transmission lines, as these can experience impedance discontinuities when
other lines approach them and depart from them. This is true even of the return current paths in
the ground plane.
Maximum Trace Length
All traces are transmission lines, but a trace

length longer than this absolutely must be
treated as a transmission line:
where LMAX is the maximum line length beyond which that line
must be considered a transmission line
tR is the signal rise time
tpD is the signal propagation rate down the board
.:JNattonal
(II" Semiconductor
TheSight'Soon(/oflnfrNm,oon
We have shown that a PCB trace can become a transmission line at a surprisingly short distance.
Digital rise time (NOT repetition rate or frequency) is what we use to determine maximum trace
length before it must be considered a transmission line. For analog signals, we can use 30% of
the period of the highest frequency component, divided by its peak-to-peak amplitude, in place
of rise time.
Recommended ADC
Layout Example
Use a Single, Solid Ground Plane
• Black dots are vias to appropriate PWR or GND plane
DIGITAL
PWRSUP
ANALOG
PWRSUP
~ National
P Semiconductor
ThflSighr&Soundoflnformtltion
This recommended ADC layout will allow the best performance that the ADC can offer. To
summarize the requirements:
Use a solid, unified ground plane. DO NOT split the ground plane. Ifthere are ground planes in
more than one board layer, connect them all together with a grid of through-holes (vias) on a
spacing of about I" or less.
Split the power plane, keeping each power plane in the same board layer. There should be
separate power planes for (1) analog circuitry, (2) digital circuitry, and (3) the ADC digital
output drivers.
Use analog power for the ADC digital core supply, but NOT for the ADC digital output drivers.
The power for the ADC digital output drivers may be the same supply as for the component(s)
driven by the ADC outputs.
Locate all analog components and lines over the analog power plane and all digital components
and lines over the digital power plane.
Use separate power sources for each plane. The ADC digital-output power can come from either
power source, but should be decoupled with a series choke. It is generally best to use a linear
voltage regulator for the ADC analog power source.
If any digital circuitry is powered by the same supply as the ADC output drivers and has signal
lines going to the other digital area of the board, use capacitors between the two power planes.
Locate these capacitors very close to the signal lines. This is discussed in the next few pages.
The ADCl2L080 example shown here is a low-power 12-bit, 80 MSPS ADC intended for
wireless communication applications.
When A Trace Crosses
A Plane Boundary
.:JNattonal
P Semicondttctor
fh, Sight 5 Sound of Inform,bon
The plane in which return current flows is not always the ground plane. Current will follow the
path of least impedance, and the least impedance path is the one where magnetic field fringing is
the least (proximity effect). This, in turn, is where the outgoing and return currents remain as
close to each other as possible. By design, the power delivery system is a low impedance one, so
provides a low impedance path. If the power plane is closer to the outgoing path than is the
ground plane, the return current will flow in the power plane.
If the outgoing current path crosses a boundary between two power planes, then the current must
go around the break and find a path to the other power plane. This may be through the power
supply, which might be a very long distance away. The loop area thus formed is very large and
forms an antenna that can both radiate and pick up energy, possibly requiring shielding that
would otherwise not be necessary.
Another problem occurs when this path deviation causes the return currents to flow coincident
with other AC (return) currents (power planes tend to have a lot of AC currents). This common
current path causes crosstalk that can result in noisy analog signals and can cause timing errors
and jitter in digital signals.
BOTTOM LINE: Avoid having lines cross any plane boundaries whenever possible.
Capacitors Shorten the Return Path
l'"
~ National
Semiconductor
Th, Sl~ht& Sound 0' Informstion
Sometimes it is necessary to have lines cross a plane boundary. When this is the case, add two
capacitors right near the plane boundary to shorten the return current path.
Use of a single capacitor between the two planes is not desired, as this couples noise from one
plane into the other. Less noise is coupled with two individual capacitors to ground.
A careful look at the return current path reveals that, although the path is shorter than it would be
without these capacitors, there is a looping of current than can make up a small inductance,
increasing the impedance of the path in this area.
Proper Via Placement
Lowers Return Path Impedance
If we exchange the via placement such that the two vias nearest the plane boundary go to the
more distant plane, the current path is a shorter one with less impedance.
The reason for not putting a single capacitor between the two power planes is to avoid the noise
on one plane from being coupled to the other plane.
Summary of Layout Rules
• Use a single, unified ground plane
• Split power planes

• Let trace routing control ground currents
• Try to avoid traces crossing plane boundaries
• Use capacitors when crossing plane boundaries is
necessary
• Tie down grounded copper areas
at many points
• Remember: Traces are transmission lines
~ National
(ilt'Semiconductor
",. Sight 4 Soundoflnlorm,tion
Here is a summary of rules for maximizing data converter and mixed-signal performance. While
originally intended for high-speed circuits, we ftnd that these guidelines are just as applicable for
lower-speed circuits because of the fast digital edge rates we have today. It is these edge rates,
not so much frequency, that determine circuit and layout needs.
All signal carrying lines are transmission lines. Beyond a certain length, we absolutely must treat
them as such if we are to avoid signal distortion, timing problems, and jitter.
Through-holes in a transmission line create impedance discontinuities and cause reflections with
the distortion and noise problems that come with reflections. A through-hole in a PCB has about
I to I Y2 nH of inductance, which can create problems.
Layout is critical for transmission lines, since they can experience impedance discontinuities and
reflections when other lines approach them and/or depart from them. This is also true of the
return current paths in the ground plane.
Much of this takes us back to what some of us learned in school but never used.
~National
p Semiconductor
Specific Products and

Application Examples
While this section of the seminar has focused mainly on the successful use of Analog-to-
Digital Converters (ADCs), what follows is a brief summary of the characteristics of some
of our ADC product types and some specific applications.
Highest Performance at the Lowest
Power Consumption
8-/1 O-/12-/14-bit cores
ADCs, DACs
General-purpose family
High-speed family
Gigahertz family
Leading supplier in many applications

Communications
Ultrasound
Digital TV
Instrumentation
Imaging
Portable systems
Control systems
Etc.
~National
P Semiconductor
Th. S,ghr A Sound of/"formltJOfl
We take pride in the high performance of our data converter products and the fact that we
can provide such products, often at lower power. Our product offerings are in resolutions
between 8 and 14 bits and application space includes virtually all commercial areas.
New General-Purpose ADC Family
8-/10-/12-Bit Resolution
SPI Interface, Single-Ended Input
Res Sample Rate Channels

1 2 4 8
50 to 200 kSPS ADC081S021 ADC082S021 ADC084S021 ADC088S022
8 bit 200 to 500 kSPS ADC081S051 ADC082S051 ADC084S051 ADC088S052
Drop-in
500 kSPS to 1 MSPS ADC081S101 ADC082S101 ADC084S101 ADC088S102 Replaceable
Across
50 to 200 kSPS ADC101S021 ADC102S021 ADC104S021 ADC108S022 Resolution
and
10 bit 200 to 500 kSPS ADC101S051 ADC102S051 ADC104S051 ADC108S052 Sample rate
500 kSPS to 1 MSPS ADC101S101 ADC102S101 ADC104S101 ADC108S102
50 to 200 kSPS ADC121S021 ADC122S021 ADC124S021 ADC128S022
12 bit 200 to 500 kSPS ADC121S051 ADC122S051 ADC124S051 ADC128S052
500 kSPS to 1 MSPS ADC121S101 ADC122S101 ADC124S101 ADC128S102
Package SOT·23·.LLp·6 MSOP·8 MSOP·10 TSSOP·16
~ National
P Semiconductor
Thfl Sighf& Sou"d of I"formation
National's first new family of General-Purpose (GP) ADCs are drop-in replaceable across
resolution and sample rate and have the same pinout and input impedance. All of these
ADCs have single-ended inputs, use the supply as a reference, and have an SPI interface.
All of these multi-channel parts have multiplexed inputs.
Applications Using Power-Down
• Sample rates below 50 kSPS
- Operate at desired sample rate using CS
- Example: The ADC121S021 (guaranteed from 50 kSPS to
200 kSPS) can be used in a 5 kSPS application by running clock
to the ADCs at 1 MHz (50 kSPS sample rate) with the ADC in
power-down 90% of the time
• Minimizing power consumption

- Keep the ADC in power-down as long as possible
- Example: Using the ADC121S101 for a 500 kSPS application-
Run clock at 10 MHz (500 kSPS sample rate) without using power-
down and consume rated power
• Run clock at 20 MHz (1 MSPS sample rate) with the ADC put into
power down 50% of the time, reducing the power consumption by
almost 50%
•.'1National
l'" Semiconductor
The Sight a Sourld of fnfonn.1Jon
The power-down mode allows operation at user desired sample rate while the ADC is run at
maximum clock rate, resulting in a reduction of average power consumption.
To determine power consumption, multiply the active power consumption by the percentage
of time in the active mode and add to this the product of the power-down power
consumption and the percentage of time in the power-down mode.
Three Standard Speed Ranges,
Three Resolutions
National Offers Guaranteed Performance
Over a Range of Speeds!
• Speed Ranges:
50 kSPS to 200 kSPS
- 200 kSPS to 500 kSPS
- 500 kSPS to 1 MSPS
• Easy migration across speeds and resolutions from
8- to 12-bits with only one layout saves cost and time
• Wide supply voltage from +2.7 to +5.25 V
• Specified industrial temperature -40°C to +85°C
• Some operating temperatures -40°C to +105°C
dNational
P Semiconductor
Th. SIQht" Sound of I"form,tion
National's family of general-purpose ADCs are guaranteed across a range of speeds. This is
unique in the industry. Conventional ADCs are guaranteed at only one speed, so it can take
five or six competitive devices to cover the same range of speeds National covers with a
single product. Customers who use a variety of conventional general-purpose ADCs can
usually standardize on just a few National ADCs.
ADI, TI, Maxim 12-bit Product
Offering by Sample Rate
(across all channels)
• Competitors need many products to cover GP sample rates
• We cover most sample rates with 3 products
- National GPADCs are interchangeable with other ADCs of the
same package configuration
Number
of
ADCs
Offered
dNational
P Semiconductor
Th,Sighr&Soundoflnform,tion
Competitors need many products to cover general-purpose applications and have brought
out their products over time by making incremental additions to their product line. Each of
their devices is guaranteed at only one sample rate.
National's ADCs are guaranteed over a range of sample rates, which is unique in the
industry. We have a standard pin-out for each channel configuration, and ADCs of the same
package configuration are interchangeable across resolution and sample rates. This also is
unique in the industry and allows our customers to easily migrate to new ADCs as sample
rate and resolutions requirements change.
Guaranteed Performance Over
Resolution, Channels, and Sample
Rate
• Three standard sample rate ranges for each
resolution and sample rate - Performance
Guaranteed
- 500 kSPS to 1 MSPS
- 200 to 500 kSPS
- 50 to 200 kSPS
- < 50 kSPS (use power-down to get any lower sample
rate - see notes)
• Each addresses 2 to 3 times as many
competitive units
** Major Difference from Competitors **
~ National
P Semiconductor
T1rlI Sight &. Sound of Inform'tKHI
National's new ADCs are guaranteed over one of three standard sample rate ranges. This
means that you get guaranteed performance where you actually use the product.
National's ADCs replace several competitive units, and a power-down feature can be used
to address sample rates down to essentially zero and to minimize power consumption.
Typical Competitive Guarantee
(AYlrslon,Y. = 2.7Ylo 5.25Y, ,",,= 20M f = 1 MSP

= 2.35Y fo 5.25Y, f",,=
AD7476 - SPEC IFI CAJI ONslnotld; Sand 8 Y'nlll15'Y.
-
unllss otI1en11S1noted; T, = T•• l11T••• unllss otI1en11S1n
AV...a:_"J BV.rwi_L,' sV •.••• I,J U•• TMtc..diti~DtI
DYNAMIC PERFORMANCE flK=JOOkHzSiacWatt

SipII-to-(NcUe. DiItortion) (SINAD)'
••
70
70
••
70
dB ••••
dB ••••
B Vn"cu" VtJD= 2.4 Vto 5.25V
T.l=2!~
7U dBqop
Siplll-t~NaiIC Ratio (SNR)' 70 71 70 dB •••• B VCniOll, Vm=VI Vto5.:n:V
Taal ...., 12.5 dBqop

HumoaicDutorooo (fHD)l
PeU: HarmaaiI: ar Spriow NoDe (SFDR -82 ....,
-7. -7 •
..•0
dBqop
dBqop
lo.tt:tmoWlation o.orriaD (IM.D)I
Second-Ordcr T QlIlf -7. -7. -71 dB.", fa :;::IO~.' klb, ftl = 113.5 !db
Tbird.ordcrTcnDIi -7. -7. -71 dB.,. fa = 101.5 kJb,fb = 113" kHz
Apcrtun::OtIay
Apc:ttu.rtjitter ,.I. ,.I. I.
'"
a.""
..""
Full POIII'Cf Banchridth '.S '.S '.S """qop @'dB
DC ACCURACY 5, B VCniOIll, VQD= CZ.:J5 Vto 3.6 V).,
=
A Vmion, VDl! (2.7 V to H V)
Rcmlulim a;.
lmcsnl Noalinmity' " 12
±u "
t\.5 l.SBmll:
to.6 !.SB""
" ±O.6
~National
P Semiconductor
rMSI(Jht&$oundoflnform'tJon
This is one of a competitor's leading 12-bit ADCs. It is a fine product with performance
guaranteed over supply voltage and temperature. However, there are three versions, each
with its own advantages and only guaranteed at one sample rate.
National's New GPADC
Specification
ADC121 81 01 Converter Electrical Characteristics

Th9 followingspocifications oppIy for Von = <!l.TV 10 S.2SV,fSClJ(= 10 MHzto 20 MHz,fSAllRE ~PS to 1 MW
10•• oIhorMs9 nollld. Bo~ limits IPPIy for TA • -40'C to +85'C: oil oIhor limitsTA = 25'C, un viliUI wisu I~
Symbol I Pe ••• _ I Cond~ion. I Typic.1 I Lim~. I Un~.
STATIC CONVERTER CHARACTERISTICS(Voo• 2.TV to 3.6V)
R9aoju1ionwilh No Mi•• ing Cod9. -4Q'C ~ TA ~ 12S'C 12 Brt.
-40'C ~ TA ~ 85'C ±0.4 ±1 LSB (max)
INL 1nt9gl8! Non·Lin9arity .1 LSB(min)
TA = 12S'C -1.1 LSB (max)
+05 .1 LSB (max)
-40'C ~TA ~ 85'C
DNL Diffv....m.l Non-lin9111ity -0.3 .(I.g LSB(min)
TA = 12S'C ±1 LSB (max)
Off.", Error -40'C ~ TA S 12S'C ±0.1 :01.2 LSB (max)
V"""
GE Goin Error -4Q'C Sf. ~ 12S'C ±02 ±1.2 LSB (max)
~National
~ Semiconductor
Th. Sighr , Sound of InfOftfYtJOfI
The ADCl21Sl01 is pin compatible with the AD7476 and has better performance and
lower power than all versions of the AD7476, and it is guaranteed over a range of sample
rates. The ADCl2lSl0l will replace any of the AD7476 versions.
Also available are IO-bit and 8-bit pin- and functionally-compatible alternatives for the
AD7477 and the AD7478. These alternatives are also better than the AD7477 and the
AD7478.
Descriptive Part Numbering
ADC 12 2 S 02 1
il n Resolution
n n n
Ref/Supply
12 = 12-bit
I ADC
DAC
or I 10 = 10-bit
08 = 8·bit
Speed Options
r- ~_;_O~_=~_,~~~~~~
~
Number of Supplies. Reference
1 = VA is Reference, single supply
2 = VA is Reference, separate output driver supply
3 = Internal/externall VA is reference, single supply
4 = Internal/external/ VA is reference, dual supply
5 = External reference, single supply
6 = External reference, dual supply
l'"
~ National
Semiconductor
TM SIgh!" Sound of Irtform,tJotl
We have developed a new part numbering scheme which we hope will make our products
easier to specify.
The graphics here show the important aspects of the part number, with the first two numeric
digits indicating the resolution of the ADC. The next indicates the number of input channels.
The next place indicates the interface. This initial offering concentrates on providing an
industry-standard SPI interface compatible with a wide range of industrial microcontroller
products.
The inset clarifies the three speed grades we offer relative to the three resolutions. However,
the last three digits can sometimes seem arbitrary against this stated standard.
Example: ADC122S101
• 12-bit, 2-channel, SPI interface, 1 MSPS, single supply
8-pin MSOP Pkg 3 x 5 mm

No external components needed
VA used as reference
SPI Clock is used as ADC clock
Outstanding performance
ENOB: 11.7 bits (typ)
DNL: +0.9/- 0.6 LSB (typ)
CS 10 SeLl<
VA. 2 DOUT
INL: ±0.64 LSB (typ)
ADC122St01
GND 3 DIN 4.3 mW (typ) at 3V Supply
IN2 4 IN1
•..
'1Nattonal
(iI" Semiconductor
r1N S"ht' Soundo/lntonn.bon
Here is an example of our newer products. All of our newer 12-bit offerings have about the
same performance indicated here, whether 1-,2-,4-, or 8-input channels. Similar products of
different resolutions are pin and functionally compatible with each other.
Midpoint
Recreated Midpoint
Third Harmonic
•..'1 National
(iI" Semiconductor
Th. Sight a Sound 0' Inform_tion
One way to control a brushless DC motor without Hall sensors is to monitor the third
harmonic. This method is detailed in IEEE article, "Indirect sensing for rotor flux position of
permanent magnet AC motors operating over a wide speed range". This method is an
alternative to the zero crossing back EMF method and has numerous benefits such as wider
operating speed range, higher precision, and high acceleration/deceleration rate acceptance.
It also can work with PWM control and without mid-point access.
The method is based on the fact that the voltage between the mid-point and the recreated
mid-point (with the 3 resistors) is the third harmonic of the motor. Each minimum or
maximum of this signal will represent the commutation time for the switcher.
This solution implements two single ADCs in a simultaneous sampling configuration. It also
can be implemented with a differential amplifier when the resistors are perfectly matched,
but this might be more expensive than the use of a second ADC.
General Purpose ADCs Are Also
Used for Peripheral Control
H bridge
control • Monitor
- Current
- Bus voltage
- Temperature
• Of a motor
• Of power transistors
• Low
- Speed
- Resolution
Analog temperature
sensors (e.g., LM94021)
• Multiple inputs
• Example: ADC08xS021
~National
P Semiconductor
Th, SiQht & Sound of InfrNm,tJOn
One common application is the monitoring of a motor's performance: Bus voltage, current
drawn, temperature, speed, and vibration. Small ADCs with an input multiplexer can easily
fit the small form factor of motor drives.
Dual ADCs:
ADC102S051
ADC102S101
ADC122S051
ADC122S101
I Power Management I Keypadl

Input
dNattonal
(II" Semiconductor
Th.Sight3SOUfldoflnfonn,tJon
This patient monitor application has the same precision requirements as does any data
acquisition system. The ADC resolution and sample rate will be determined by the sensors
chosen, but a serial output ADC will limit the number of data lines required, easing the
isolation interface requirements. Using a dual ADC eliminates the multiplexer that would
otherwise be needed.
Customer Problem:
Read and Understand the
Datasheet!
• Problem: Cannot select the channel AIN2 of ADC122S051
• Holding DIN pin low to select AIN1, high to select AIN2
• Solution: DIN must be low during ADD1 time
TABL trOll Reg Istar Bit.
Bft 5 Bit 4 Bft3

ADD2 ADDI AD DO
BII" Symbol, Descl1ptlon

7-6,2-0 DONTe Don't care. The value of th/illl8 bits do not aft8d the devk:e.
3 1<000 Thee. three bits determine wNch Input channel wi! be SIJ1'1)Ied and
4 ADDI conwrted In the next trackIhofd cycfe. The mapping between codea and
5 ADD2 channe" is shown In Tabla 3.
TABLE 3. Input Channel selection
ADD2 ADD1 ADDO Input Channel

o 0 INI (DefaulQ
o
d National
P Semiconductor
TIIeSighr&$oufldoflnfM""DOfI
The datasheet indicates that the DIN line must be low for the ADDI (Bit4) time, If this is
violated, channel IN2 will not be selected,
Digital Still Camera Auto Focus
DACs:
DAC101S101
DAC121S101
Charger ~ Battery ) LCD

Display
•..'1Nattonal
l'" Semiconductor
Th, S'llht a Sound 11' Inform.tlon
The DAC is used here to provide a driving voltage to the auto-focus motor. The DACs
shown here are well-suited for this application. For faster speeds, the DACIOlS051,
DACIOlSlOl, DAC121S051, or the DAC121Sl01 are good candidates.
DC/DC
Boost
I ~
~
~National
(II" Semiconductor
The SiQht & Sound of Inform.t1ofI
The blood glucose monitor is yet another example of a use for a general-purpose ADC. We
show the ADCl2lS021 in this application.
Second New GPADC Family
12-/14-/16-8it Resolution
Res Sample Rate Channels
50 to 200 kSPS
12 bit 200 to 500 kSPS Drop·in

Replaceable
500 kSPS to 1 MSPS Across
Resolution
50 to 200 kSPS
and
14 bit 200 to 500 kSPS sample rate
500 kSPS to 1 MSPS
50 to 200 kSPS
16 bit 200 to 500 kSPS
500 kSPS to 1 MSPS
Package Type
~ National
Ii" Semiconductor
TII,S,gllt&Soundoflnform'tion
National's second family of new ADCs will cover resolutions from 12 to 16 bits. The
ADC121S625 is the first product in this family with a differential input and an external
reference.
We have higher-sample-rate 12- and 14-bit, single-channel ADCs, as well as simultaneous
sampling ADCs in development. These provide two discrete ADC channels and are targeted
at motor-control applications, one of the most common general-purpose ADC applications.
In motor control, customers need to have ADC measurements taken at the same time so that
the phase relationship is known. These devices will also be well-suited to AC power
measurement.
SAR ADC Family Value
Proposition
• Better performance than competition

• Performance guaranteed across sample
rate range
• Very low power and small package size
• Standardized pin out with same input
impedance
• Easy migration across resolution and
sample rate
l'"
~National
Semiconductor
TheS'ght&$oundoflnformation
Our processes and design have allowed us to develop a new family of general-purpose
ADCs with better performance and lower power consumption than competitive products.
Our performance guarantee over a range of clock rates is unique. Our standardized pin out
means one board layout for each channel configuration and that one of National's ADCs
may replace several competitive products. All of this simplifies testing and reduces both
development cost and inventory for customers who use multiple ADCs.
Part Numbering Convention
for High-Speed ADCs
ADC 12 L 080
~ "-APprOXimate Sample Rate Specified (MHz)

1 or 2 Letters as indicated below *
Resolution
"AID Converter"
* D - Dual
T - Triple
Q-Quad
L - Low Voltage (3.3V or less)
B - FIFO Buffer
S - Serial (LVDS/SLVS) Outputs
~ National
l'" Semiconductor
The Sight& SQundoflnformsfion
While there are some exceptions to this method of specifYing our products, this method
generally holds for newer devices. The letters following the resolution may be combined, as
in the cases of the ADCI2DL066, which is a dual, low-voltage, 12-bit, 66 MSPS ADC.
Example Application:
Communications Receiver
National's ADCs for Communications National's Diversitv Chipset:

ADC12L066/ADC11 L066 CLC5903 (GSM projects)
ADC12DL066/ADC11 DL066 CLC5526 • DVGA
ADC12L065/ADC12DL065 CLC5506· GTA
ADC 12L0801 ADC12L080/ADC12DL080
ADC12QS065
CLC5957
d National
V" Semiconductor
The Sighr&Soundoflnform,tion
Our high-speed products provide superior performance in communication systems, as well

as in medical and general instrumentation, radar, and other systems requiring high sample
rates, including those where undersampling is used. These systems are very demanding and
our converters are up to the task.
Shown here is our "diversity receiver chip set," consisting of the CLC6628 Digital Variable
Gain Amplifier (DVGA), any of the ADCs listed here, and the CLC5903 digital tuner. In
this application, there are two identical channels. The diversity is in either polarization,
where one antenna is vertically polarized and the other is horizontally polarized, or in space,
where they are separated from each other. When fading occurs, it usually does not happen in
both channels at once. The strongest signal is the one that is accepted by the digital tuner.
Radar System
ADC10321
ADC10030
ADC10040
ADC12010
ADC12020
ADC08D1500
DAC081S101 System
DAC101S101 Control
DAC121S101
•..'1 National
P Semiconductor
ThoSigh/&Soundofl/lfQrmation
Radar systems vary quite a lot in their architecture, depending upon the exact application.
The ND converter used can be 10 to 12 bits at relatively low sample rates, or can be 8 bits
at a very high sample rate. The ADCs shown here are just some of the choices and include
the following:
lO-bit, 20 MSPS ADC10321
lO-bit, 28 MSPS ADCl0030
lO-bit, 40 MSPS ADCl0040
l2-bit, 10 MSPS ADCl20l0
l2-bit, 20 MSPS ADC12020
Dual 8-bit, 1.5 GSPS ADC08Dl500, which can operate as a single 8-bit 3 GSPS ADC.
The D/A converter is generally a fairly low sample rate and can be 8 to 12 bits, again
depending upon architecture. These are 8-, 10- and l2-bit DACs with conversion rates up to
1.7 MSPS.
ADC12DL066
Dua/12-bit, 66 MSPS ADC
Features
Wide dynamic range

• Resolution 12 bits
IF sampling capability • Conversion Rate 66 MSPS (min)
Full power bandwidth-
450 MHz • ENOB 10.5 Bits (typ)
2Vp_p diff. input range • DNL ±0.4 LSB (typ)
• INL ±0.7 LSB (typ)
On-chip reference buffer
• SNR 64 dB (typ)
Pipeline architecture with • SFDR 78 dB (typ)
digital error correction
• THO -74 dB (typ)
3.3V supply • Supply Voltage +3.3V± 5%
64-pin TQFP package
• Power Consumption
- Normal 686 mW (typ)
- Power Down 75 mW (typ)
~National
Ii" Semiconductor
a
1M Sight Sound Df Infonn.tJOn
The ADCl2DL066 is one of our dual, high-speed, l2-bit ADC offerings. As with those
other products, the ADC12DL066 offers excellent performance at low power consumption
levels, together with a very high (450 MHz), full power bandwidth.
ADC12DL066: 10 MHz and 150 MHz
Input Amplitude SNR and SFDR
U 60
III
~
....,
'"
C 50
~ 40
u
!30
'"
z
., 20
•..'1 No ti 0 n 0 I
(ill'Semiconductor
The SIght 4 500nd of I"torm.rion
The excellent performance of the ADC12DL066 over a wide range of input levels, at both
10 MHz and at 150 MHz input frequencies, can be seen here. Note the near ideal level of
performance.
ADC12DL040lADC12DL065
Dual 12-bit 40/65 MSPS
• Industry's Lowest power • Resolution 12 bits

consumption • Conversion Rate 40/65 MSPS
• Single +3V/3.3V operation
At Nyquist:
• On chip precision reference
• DNL to.3 LSB
• Straight binary or 2's to.8 LSB
complement outputs • INL
• SNR 68.5 dB
• Duty cycle stabilizer
• SFDR 85 dB
• Parallel or Mux'd outputs • THO -83 dB
• 64-pin TQFP package
• Power Consumption
• Pin compatible ADCs: Normal 210/360 mW
- ADC12DL066 - Power down 36 mW
- ADC12D040
~National
~ Semiconductor
TrJ.Slghl&Soundollnfofm.1Jon
This recently introduced dual ADC offers excellent performance with extremely low power
consumption. The 250 MHz full power bandwidth and dual nature of this device, together
with its excellent performance, enables efficient, space-, and cost-saving designs of many
systems, including communications and instrumentation, among others. A single, 5V,
40 MSPS version (ADC12040) is available and is pin-compatible with our other l2-bit
high-speed ADCs.
ADC12DL040/65
Performance Charts
Lowest power conSURlption Rnd lineor power scoling ADCl2DlD4O Excellent dynamic perfoR1lance
with sampling frequency across input frequency
lOa
Ila
f
S
JlO
.i. 2IlG
100
a
a III
2. 40
Clod< h.quo"", IMHll "
~ National
(iI" Semiconductor
Th,S/f1htliSCHJndflflnfotm,tlotI
The low power consumption of the ADC12DL040 and of the ADC12DL065 scales in a
linear manner with sample rate so that there is no excess power consumption when
operating at lower sample rates. Note also the excellent distortion performance, even at very
high input frequencies.
ADC12DLOBO
Industry's Highest IF Sampling Dual
12-bitlBO MSPS ADC
• 600 MHz Bandwidth - best in class ADC12DL08O
Sf DR. SNR. and SINAD YO Input Frequency
• 200 MHz IF sampling capability •
- Allows flexibility in frequency planning
- Helps eliminate down conversion stages
- Reduces system power consumption
- Improves system reliability
.•..'1 National
~ Semiconductor
The SIght" Sound of Inform.tion
The ADCI2DL080 is a dual, low-power, 12-bit, 80 MSPS ADC intended for IF sampling
applications. The 600 MHz bandwidth is the best in the industry with flat dynamic
performance up to 200 MHz, another best in the industry. This makes the ADCI2DL080
very attractive for high IF sampling applications, providing the following system benefits:
I. Flexibility in frequency planning
2. Eliminate a down conversion stage
3. Reduction in power consumption and improving system reliability
ADC12QS065: Quad, 12-bit, 65 MSPS
ADC with Serial LVDS Outputs
ADC12QS065 - Quad, 12-Bit. 65 MSPS ADC with SeriallVDS Outputs

Features
IRIII" SNIt and SINAD vs
• Ouad·channel12-bit, 55 MSPS sampfing rate
h1pat Frequency
• Single 3.31/ supply operation
Inl.
• SeriallVOS outputs enabling reduced
a'"
--......
trece count II.'
• Clock and framelVDS pairs for data capture

• 7lIOMbpsseriai lVDS data rate at 55 MSPS
• Power-down mode consuming 3 mW
-
• IIp·60 package 19 x 9 x 0.8 rml, 0.5 rml
pin pitch}
• Operates over the industrial temperature
range oI-4O"C to +85'C 10
• 1Ii a
-
IWIIIlkl
•. '1National
l'" Semiconductor
TheSIght.lSoundofl"torm.f1OII
The quad, 12-bit, 65 MSPS ADC 12QS065 has serial LVDS outputs and is intended for
applications that require multiple high-speed ADCs, such as a medical ultrasound system.
The serial LVDS outputs reduce the number of output lines and minimize the noise caused
by high capacitances on the digital outputs.
12-/14-bit Family
Full Power
Resolution Speed Power ENOB SINAD SNR SFDR THD Bandwidth
Product ID bits) ICMSPS) mW) bitl dB) dBl dB) dB) MHz) Packaaina
ADC12010 12 10 160 11.3 69 70 83 -79 100 L FP-32
ADC12020 12 20 185 11.3 69 70 86 -83 100 L FP-32
ADC12040 12 40 340 11.2 69 70 84 -80 100 L FP-32
ADC12L063 12 62 354 10.3 65 66 78 -74 170 L FP-32
ADC12L066 12 66 357 10.7 66 66 80 -77 450 L FP-32
ADC12L080 12 80 425 10.7 66 66 80 -77 450 L FP-32
ADC12D040 12-bit dual 40 600 10.9 68 68 80 -78 100 T FP-64
ADC12DL040 12-bit dual 40 210 11.1 69 69 86 -83 250 T FP-64
ADC12DL065 12-bit dual 65 360 11.1 69 69 86 -84 250 T FP-64
ADC12DL066 12-bil dual 66 686 10.7 66 66 81 -78 450 T FP-64
ADC12DL080 12-bit dual 80 447 11 69 69.3 82 -80 600 T FP-64
ADC12 S065 12-bil auad 65 800 11.1 68.3 68.5 85 -83 300 LLP-60
ADC14L020 14 20 150 12 74 74 93 -90 150 L FP-32
ADC14L040 14 40 235 11.9 73 73.3 90 -86 150 L FP-32
• Low-power, pin-compatible family

• ADCl2010/20/40 • High full power bandwidth
• ADCl2L063/66/80 • Power-down feature
• ADC l2DL040/65/80 • Parallel CMOS and Serial LVDS
• ADCl4L020/40b outputs
~ National
(iI" Semiconductor
T1I,Sighr&Soundoflnform'DfJn
National's 12- and 14-bit high-speed ADCs include singles, duals, and a quad with sample
rates up to 80 MSPS and impressive performance for the power consumed.
10-bit Family
Full Power
Speed Power ENOB SINAD SNR SFDR THD Bandwidth
Product 10 MSPS) mW) bit) dB) dB) dB) dB) MHz) Packaging
ADC10321 20 98 9.5 59 60 72 -70 150 LQFP-32
ADClO030 27 125 9.4 58 60 68 -66 150 LQFP-32
ADC10040 40 55.5 9.6 59 59 80 -77 400 TSSOP-28
ADC10065 65 68.4 9.5 59 59 80 -72 400 TSSOP-28
ADC10080 80 78.6 9.5 59 59 79 -75 400 TSSOP-28
ADC10D020 20 150 9.5 59 59 75 -73 140 TQFP-48
ADC10D040 40 257 9.5 59 60 72 -69 140 TQFP-48
• Low power pin compatible family

• ADCI0040/65/S0
• ADCIOD020/40
• Power scales with clock speed (ADCI0040/65/S0)
• Multiplexed or parallel outputs on the duals
• Selectable gain with the ADClO040/65/S0
d National
l" Semiconductor
Th, s/{/ht & Sourrd of Inform,tion
Our 10-bit, high-speed offering currently includes wide input bandwidths with speeds of
20 MSPS to 80 MSPS and quite impressive Effective Number of Bits (ENOBs).
Low-Power, 8-/10-bit Family
Full Power
Resolutton Speed PinlFunction Power ENOS SNR SFDR Bandwidth
Product 10 bits MSPSI Com •••••• mW bit dB dBI MHz 1_
SOIC-24.
ADC1173 15 3 7. 46 5 120 TSSOP-24
SOIC-24,
ADC1175 2 6C 7. 47 510 12 TSSOP·24
LLP-24.
SOIC-24.
ADC1175-50 8 50 12 7.2 4 56 120 TSSOP-24
LLP·24,
ADC08351 8 4 40 6. 44 4 12 TSSOP·20
ADC08060 60 ~ 78 7.6 47 63 200 TSSOP-24
ADC08L060 8 6 39 7.6 48 59 270 TSSOP-24
ADC081QO
ADC08200
8 10
20 ..•.• 130
21
7.5
7.
47
46
60
6
200 TSSOP-24
5{){) TSSOP-24
140,170,
ADCS9888 8-bittriple 205 129 - 44- PQFP-128
5{){)
ADC10321 1 2 9 9 6 7 150 lQFP-32

ADC10030 1 2 12 9.4 15 lQFP-32
ADC10040 1 4 55. 9 59 8C 400 TSSOP-28
ADC10065 1 6 68. 9. 59 80 400 TSSOP-28
ADC1oo80 10 8 78. 9. 59 7 400 TSSOP-28
ADC10D020 Dual10-bit 20 150 9. 59 75 140 TQFP-48
ADC10D040 Oual1Q-bit 40 257 9. 60 7 140 TQFP-48
Power scales with clock speed

• Multiplexed or parallel outputs on 10-bit dual ADCs
• Selectable input swings ~ National
(;9 Semiconductor
T1I.Slghf&S6urnfoflnfotm.tIOll
Our 8-bit, high-speed ADC offering includes specified sample rates from 15 MSPS to 205 MSPS.
Products above these sample rates are our ultra-high-speed products, while our 10-bit high speed
offering currently includes high input bandwidthswith speeds of 20 MSPS to 80 MSPS and quite
impressive ENOB.
Low-Power 12-/14-bit Family
Full Power
Resolution Speed Pin/Function Power ENOS SNR SFDR Bandwidth
Product 10 (bits) (MSPS Compatible (mW) (bol) (dB) (dB) (MHz) Packaging
ADC12010 12 10 160 11.3 70 83 100 LQFP-32
ADC12020 12 20 185 11.3 70 86 100 LQFP-32
ADC12040 12 40 340 11.2 70 84 100 LQFP-32
ADC12L063 12 62 354 10.3 66 78 170 LQFP-32
ADC12L066 12 66 357 10.7 66 80 450 LQFP-32
ADC12LOBO 12 80 425 10.7 66 80 450 LQFP-32
ADC12D040 12·bit dual 40 600 10.9 68 80 100 TQFP-64
ADC12DL040 12-bit dual 40 210 11.1 69 86 250 TQFP-64
ADC120L065 12·bit dual 65 360 11.1 69 86 250 TQFP-64
ADC120L066 12-bit dual 66 686 10.7 66 81 450 TQFP-64
ADC120L080 12-bit dual 80 447 11 69.3 82 600 TQFP-64
ADC12QS06 12-bit quad 65 800 11.1 68.5 85 300 LLP-60
AOC14L020
AOC14L040
14
14
20
40 •• 150
235
12 74
11.9 73.3
93
90
150 LQFP-32
150 LQFP-32
High full power bandwidth

Power scales with clock speed
Parallel CMOS and LVDS outputs
Power-down feature
d National
~ Semiconductor
Th. S'l1ht a Sound of Inform.rian
National's 12- and 14-bit high-speed ADCs include pin-compatible families of singles,
duals, and a quad with sample rates up to 80 MSPS and impressive performance for the
power consumed. Some of these products, like the ADC12L066, ADCI2DL066, and
ADC12DL080, feature high input bandwidths, and our data output formats offered are
parallel CMOS and serial LVDS (ADCI2QS065).
ADCOBD1000
Dual, B-bit 1 GSPS ADC
Features
Single 1.9V power supply
Output data rate
- 1:2 demux: 2 output channels
• Resolution 8 bits
interleaved to provide • Conversion rate: 1 GSPS
500 MSPS/channel (LVDS)
Differential inputs Specifications at FIN = 500 MHz
Internal voltage reference ENOB 7.4 bits
Buffered Internal sample and
DNL ±0.15 LSB
hold
Dual edge sampling INL ±0.30 LSB
(interleaving) SNR 47.1 dB
Double Data Rate support SFDR 55 dB
Synchronization between SINAD 46.3 dB
multiple channels THO -55 dB
Full-scale (gain) and offset Power consumption
adjustment of each ADC (I & Q). - Normal Operation: 1.6W (typ)
12S-pin EP LQFP package Power Down Mode: 20 mW
~National
(il'Semiconductor
Th.Sighr&Souf!doflnform,rion
The ADC08DIOOO is a dual, I GSPS ADC with input channels labeled I and Q.
Both converters on the die have fully differential inputs with a maximum input signal range
of 950 mV p.p. Each converter has a 1:2 demultiplexer that feeds two LVDS buses and
reduces the output data rate on each bus to half the sampling rate. A choice of SDR and
DDR is available and an output data clock eases data capture.
The two converters may be interleaved such that they both sample the input signal at the
user's choice of either input. In this Dual Edge Sampling (DES) mode, the two converters
sample the one signal on opposite edges of the ADC input clock, so that the net sample rate
is twice the input clock frequency. Since the ADC08DIOOO is specified for I GSPS, the
overall sample rate in the DES mode is guaranteed at 2 GSPS. Since the ADC08DIOOO will
typically perform at 1.3 GSPS, the DES mode can provide a 2.6 GSPS conversion rate.
ADCOBD1000
Unparalleled Performancel
Low-Power
~Nattonal
P Semiconductor
ThBS,ghtaSoundoflnrorm,tion
The ADC08DIOOO maintains excellent performance over its full input frequency range and
consumes very little power in doing so. This performance is achieved by incorporating
trimmed input termination resistors at the analog signal inputs, avoiding the stub problems
commonly seen when input termination is done on the printed circuit board.
ADCOBD1500 Frequency Domain
Plot (Normal Mode)
~ National
(II" Semiconductor
Th,Sight&Soundoflnform,rion
Best performance is obtained in the normal mode. Note the excellent performance obtained
at this very high sample rate (1.5 GSPS).
This data was taken with our ADC08DI500 development system, which should represent
what can be realized in an actual circuit. Our evaluation board produces somewhat better
performance than shown here.
Competitive solutions require 10 bits, with the attendant large power consumption, to get an
ENOB of just 7.0!
ADCOBD1500 Frequency Domain
Plot (Dual Edge Sampling Mode)
~ National
P Semiconductor
Th,SightASoundoflnformltJl)n
The performance in the DES mode is very close to what can be achieved in the normal
mode. This excellent performance obtained at a 3.0 GSPS rate with our ADC08Dl500
development system, which should represent what can be realized in an actual circuit. As is
true in the normal mode, our evaluation board produces somewhat better performance than
shown here.
Competitive Stance
500 1000
Input Frequency (MHz)
l.'"
~ National
Semiconductor
TM SJg/lr4 Sound of l"form,t1OfI
This input sweep demonstrates how our ADC08D 1000 performs against our only
competition. Note that the National ADC08DlO00 is consistently about 1 ENOB better.
Also, as the frequency gets higher, the difference between the two devices widens.
Comments on Competitive Product
• Many spurs as the input gets close to 1.5 GHz
• Does not deal well with over-range signals
l'"
~ National
Semiconductor
Th.Sighr.tSovndof'nform,tion
The bandwidth of the competition becomes an issue at 1.5 GHz, but, more importantly,
many spurs show up as the input gets close to 1.5 GHz.
Another problem with the competitive offering is that it does not deal well with over-range
signals. This is important for test equipment applications.
~National
PSemiconductor
Signal Translations
LVDS, LVPECL, and CML
Today, three commonly used interfaces, Low Voltage Differential Signal (LVDS), Low Voltage
Positive Emitter-Coupled Logic (LVPECL), and Current Mode Logic (CML) are commonly
used for data transmission. When designing these systems, we often encounter the problem of
how to connect different ICs with different signaling levels.
To maximize performance, a good understanding of input and output circuit configurations,
biasing, coding, and termination is required.
This presentation provides various methods to properly interface LVDS, LVPECL, and CML
devices.
Differential 110 Comparisons
LVDS (3.3V) LVPECL (3.3V) CML (3.3V)
Offset 1.2V 2V 3.1V
Output Swing (Single Ended) 250 to 450 mV 600 to 900 mV 300 to 500 mV
Input Swing (Single Ended) 50 to 1000 mV 310 to 1000 mV 200 to 600 mV
Output Differential (VOD) 500 to 900 mV 1200 to 1800 mV 600 to 1000 mV
Input Differential (VID) 100 to 2000 mV 620 to 2000 mV 400 to 1200 mV
X~~.3
~L~
LVDS LVDS
.... .._.:~
~
~ National
(iI" Semiconductor
1M Stfhr & Sound oIlnfomr.tnH'l
The figure and table show some typical interface levels for differential transmission
technologies. LVDS, LVPECL, and CML feature different swings and different offset voltages.
LVDS is standardized (ANSI/TIAIEIA-644-A-2001) while LVPECL and CML are not.
To maintain interoperability between devices with different supply and interface levels requires
using either direct current (DC) coupling or alternating current (AC) coupling to be employed.
We will discuss and show the benefits and drawbacks to using either DC or AC coupling in the
following slides.
Unless stated otherwise, all references to signal levels are for single-ended measurements.
8>----==----~
•..'1 National
Ii" Semiconductor
T1I,Sighf&Soundoflnform,fJOn
At the most basic level, there are two methods to interface different logic devices: DC coupling
and AC coupling.
• Capacitor selection (AC coupled applications)
• Data encoding (AC coupled applications)
d National
~ Semiconductor
111. Sight a Sound of Inform,rion
When DC and AC couplings are used to interface LVDS, LVPECL, and CML, the various offset
voltages, common-mode ranges, and required terminations should be considered. In addition, for
AC coupled applications, data encoding should also be addressed.
Some of National's LVDS devices will directly accept different logic signals such as LVPECL.
For more information, please consult device datasheets.
LVDSVO LVDS VI
3 3V
2V
Min = 250 mV
Min = 50 mV
_X- ~V --- -
~ National
PSemiconductor
The Sight & Soundoflnformarion
The next few slides show LVDS drivers and receivers with DC Coupling.
This slide shows typical offset voltages between an LVDS driver and receiver.
I........
~ ~ 1
100n
1
1
1 /
~ ~ I.
/
Optional Internal
GND Termination
•..'1 National
l"" Semiconductor
The Sight a Saund oIlnfortNtIM
Because LVDS drivers and receivers have the same offset voltages, common-mode range
compatibility, and target lOOn termination resistance, LVDS devices can be DC coupled. They
can also be AC coupled. However, for best performance results, some type of data coding or DC
balancing should be implemented. DC balancing in AC coupled applications will be discussed in
this presentation.
Termination resistors can be external or internal. Currently, National's Bus LVDS and Channel
Link products do not offer internal terminations. However, some of National's products do
contain internal terminations. For product specific information, please refer to the datasheet or
contact your local sales office.
LVPECL VO LVPECL VI
3V 3V
.••• '1 National

~ Semiconductor
Th. Sight & Sound Dr Infotm.tJon
Interfacing LVPECL-to-LVPECL logic devices uses the same DC coupling methodology as

LVDS.
Optional on-chip
High-impedance biasing
Ii
~National
PSemiconductor
T/l,S,glll&Soundoflnform,nf",
As shown above, LVPECL output and input structures are different from LVDS.
LVPECL uses two son termination resistors pulled to Vcc2V. As such, the differential outputs
(Output ±) will be at Vcc-1.3V (2V when using a 3.3V power supply), which results in a DC
current flow of 14 mA.
LVPECL devices typically have on-chip high impedance (approximately 1 ill) biasing centered
atVcc-1.3V.
Since LVPECL devices have open emitter outputs, the output emitter followers should operate in
the active region with DC current flowing at all times. This increases switching speeds and
maintains fast turn-off times.
CMLVO CMLVI
3 3V
~Nattonal
(il'Semiconductor
On -chip Common mode
biasing
J).
Yo<
On -chip Common mode

biasing
J).
y"
.:]National
P n..Semiconductor
Slfht & Sound 01 ltlfotm,bon
Figure (a) shows DC coupling for CML interfaces. DC coupling can be used when both the
CML driver and receiver meet the following conditions: 1) same power supply voltage; 2) the
termination resistors of the receiver connect to Vcc internally.
Because CML is not standardized, some receiver input termination resistors may not be tied to
Vcc or to other voltages. Thus, we recommend using AC coupling (Figure b) between all CML
to CML interfaces.
LVDSVO LVPECL VI
3V 3V
Min = 250 mV
1V _X-
•..'1 National
PSemiconductor
Th. Sight& Soundoflnfllml'tNHI
This slide shows the typical offset voltage for an LVDS-to-L VPECL interface. To optimize
performance and because the offset voltage requirements differ, level translations should be
implemented.
LVPECL without on-chip biasing:
-R1N = son
-DC offset (VCM - common mode voltage) of LVPECL = 2V
3.3V
~~":.. -r '-
r.· U-U-
'"'"wl •...
j S.-
.~:
I
J ~:
.
I ~ ::::-.:-
•..'l National
PSemiconductor
The Sight a Sound of Inform.t1(H1
The next two slides describe AC coupling between LVDS and LVPECL.
Figures (a), (b), and (c) show possible termination schemes for an LVPECL receiver that does
not have on-chip biasing.
The resistor network resets the offset voltage to 2V and provides an impedance of 50n for the
LVPECL input.
Figure (a) uses low value resistors to provide a single-ended input impedance of 50n. The next
slide, Figure (b), uses higher-value resistors to reduce power consumption.
L VDS-to-L VPECL Interfaces
AC Coupled (3 of 5)
'R1N = 50n
·DC offset (VCM) of LVPECL = 2V
/ -F- 'T ~""
r.--.........,··,...., . n....r'1··.,
~LJ_J1L;-u~
,=r
! ~;~ I;; t,;':
. - .;.-.::-~,,----, "_&lY:t':'.~
1"#
".J:;;;,,~
~Nattonal
P Semiconductor
Th.Sight&SOlHldoflnfom!.twn
The next two slides describe AC coupling between LVDS and LVPECL.
Figures (a), (b), and (c) show possible termination schemes for an LVPECL receiver that does
not have on-chip biasing.
The resistor network resets the offset voltage to 2V and provides an impedance of 50n for the
LVPECL input.
Figure (a) uses low-value resistors to provide a single-ended input impedance of 50n. The next
slide, Figure (b), uses higher-value resistors to reduce power consumption.
AC Coupled (4 of 5)

-R1N = 50n
-DC offset (VCM) of LVPECL = 2V
r- /
'..--J
-r -'-'
..r~.r..:..~..';:
•••-""':'
r,-_r~'-~
"""- ..J '
J ,:;
r '1#
. F
.;;....---,....:-'::-:"'
dNattonal
P Semiconductor
11» SIgIrt a Sound oIlnform,tion
Figure (c) is the simplest way to reduce the total number of components and also has the lowest
power consumption. Although there is a slight offset from the nominal LVPECL common-mode
voltage, this configuration has the added benefit of failsafe protection. For more information on
failsafe biasing, please see the LVDS Owner's Manual.
LVDS-to-LVPECL Interfaces
AC Coupled (5 of 5)
Resistor
Total Offset Offset Network
Component A B Ice VO@AorB Advantage
Fig. (a) 4 2.044V 2.041V 30.85 mA 320 mV

· Possible speed
advantage
Fig. (b) 5 1.994V 1.995V 1.82 mA 340 mV

· Lower power
consumption
· Fail Safe feature

Minimum external
resistors
Fig. (c) 3 1.988V 1.947V 1.58 mA 320mV

· Lowest power
consumption
~Nattonal
~ Semiconductor
Th. Sight & Sound of 'nform,lion
This provides a summary of the three different termination-resistor networks.

Figure (c) is the simplest way to reduce the total number of components and also has the lowest
power consumption. Although there is a slight offset from the nominal LVPECL common-mode
voltage, this configuration has the added benefit of failsafe protection. For more information on
failsafe biasing, please see the LVDS Owner's Manual.
AC Coupled (1 of 3)
0.1 ~F
Figure (e): with on-chip internal biasing (VBB)
~ National
fill'Semiconductor
1M SIf/1f a SDund of Infoml.tiotI
This slide shows an AC-coupled LVDS to LVPECL interface.

Previously, we stated that some LVPECL devices could have internal biasing at the receiver
inputs.
Figure (d) shows an AC-coupled case when an LVPECL receiver input has on-chip biasing.
Alternatively, Figure (e) shows an AC-coupled case when an LVPECL receiver input provides a
reference voltage (VBB) at 2V. For this case, two son series termination resistors are used.
LVDS-to-LVPECL Interfaces
DC Coupled (2 of 3)
,
I r"",
F--
: I ~~'r ,
r-c::r+c::r-L?""~r::-;
j=
1;:::.-
~ National
(ilt'Semiconductor
nt. Sight a Sound of InfomWNHI
When DC-coupling LVDS and LVPECL interfaces, use the resistor network shown here. The
resistor network shifts the DC from the LVDS offset output (V A = 1.2V) to the LVPECL input
(VB = 2V).
Diagram (b) is the single-ended version of diagram (a). Again, for the best performance, the
following needs to be considered: I) offset, 2) termination, and 3) common-mode range.
Because the LVDS output voltage is referenced to ground and the LVPECL input voltage is
referenced to Vco the resistor network shown is used to make the LVDS output less sensitive to
power supply variations.
The selection of bias resistor values often involves a trade off between power consumption and
speed.
For instance, assuming the LVPECL input parasitic capacitance is small, choosing lower resistor
values for RI, R2, and R3 will allow for higher-speed operation. However, with this type of
configuration, the total power consumption will increase due to higher current flow through the
low-value resistors.
When designing resistor networks, impedance matching (RlN = 50n) and network attenuation
(Gain> 0.6 with a minimum VOD of LVDS = 500 mY, and min VID ofLVPECL = 300 mY)
should be considered.
L VDS to L VPECL Interfaces
DC Coupled (3 of 3)
v,~rc<.( __ RI_)=11V (I) v,~rC<'(~)=I1V (I)

_~1+R2-RJ Rl+.~<-RJ
r: ~y",.(~)=Y",-(.Jr (2) v ~Y<I:'( RJ+R2 )=Ya:-l.:W (2)

• RJ+.~2·R3 • Jfi+.~2-R3
R.=(R3·IR1+R~\fi6m~WQ (I) R =(R3.(R1+R2)\116m~WQ (3)

~ R3+(Jfi+.~2)' !II RJ+(RJ+R2)'
DC Coupled
c;...iJo~~ (4) w=~ (4)
(R2- R3) (R2-RJ)
Pick:
Rl = 3740, R2 = 2200, R3 = 3900
Get:
VA = 1.2V, VB = 2V, RlN = 490,
Gain = 0.62
Measured:
VA = 1.199V, VB = 1.909V
VoatA=340mV, VoatB=200mV
lee of Network = 7 mA
•..
'1National
P Semiconductor
Th, Sight & Sovndofln!orm,tion
When DC coupling LVDS and LVPECL interfaces, use the resistor network shown here. The
resistor network shifts the DC from the LVDS offset output (V A = 1.2V) to the LVPECL input
(VB = 2V).
Diagram (b) is the single-ended version of diagram (a). Again, for the best performance, the
following needs to be considered: 1) offset, 2) termination, 3) common-mode range.
Because the LVDS output voltage is referenced to ground and the LVPECL input voltage is
referenced to Vco the resistor network shown is used to make the LVDS output less sensitive to
power supply variations.
The selection of bias resistor values often involves a trade off between power consumption and
speed.
For instance, assuming the LVPECL input parasitic capacitance is small, choosing lower resistor
values for R1, R2, and R3 will allow for higher-speed operation. However, with this type of
configuration, the total power consumption will increase due to higher current flow through the
low value resistors.
When designing resistor networks, impedance matching (RlN = 50n) and network attenuation
(gain> 0.6 with a minimum VOD of LVDS = 500 mY, and min VID of LVPECL = 300 mY)
should be considered.
LVPECL to LVDS Interfaces
DCIAC Coupled (1 of 4)
•..'1
l'" National
Semiconductor
TIl,Sight&Soundoflnformation
L VPECL-to-L VDS Interfaces
AC Coupled (2 of 4)
.••.'1 National
P Semiconductor
Th, Sight & SO(Jnd of 'nform,tion
LVPECL-to-LVDS Interfaces
DC Coupled (3 of 4)
--d National
...
:::.~
(II" Semiconductor
Th. Sight a Soum! of Inform'tion
This slide shows a DC-coupled LVPECL-to-L VDS interface. This figure assumes the LVDS
device has an internal termination resistor.
LVPECL outputs are optimized for 50n loads biased to Vcc-2V. The resistor network shown
primarily serves as a level shifter and attenuator network which addresses this issue.
LVPECL-to-LVDS Interfaces
DC Coupled (4 of 4)
Select:
_ 7_. R2+R3
VA - Vee - 2J - Vee ----- (1) R1 = 1820, R2 = 47.50, R3 = 47.50
Rl+R2+ R3
Get:
RAe = Rl II(R2 + (R3//50n) =SOQ (2) VA = 1.13V, RAC = 51.50, Roc = 62.40,
Gain = 0.337
Roc = RI II( R2 + R3) "" son
Measured:
VA = 1.977V, VB = 0.995V
Gain = R31150n ~ 0.17
Vo at A = 500 mV , Vo at B = 160 mV
R2 + (R3//50n)
Icc of Resistor Network = 41 mA
d National
l" Semiconductor
The Sight" Sound of Inform.tion
This slide shows a DC-coupled LVPECL-to-L VDS interface. This figure assumes the LVDS
device has an internal termination resistor.
LVPECL outputs are optimized for son loads biased to Vcc-2V. The resistor network shown
primarily serves as a level shifter and attenuator network which addresses this issue.
CML-to-LVDS Interfaces
AC Coupled (1 of 2)
CML VO Min = 300 mV Max = 500 mV

3V
~NatiQnal
(II" Semiconductor
Th,Sight&50undoflnformlltirm
CML-to-L VDS Interfaces
AC Coupled (2 of 2)
3.3V
4.3 kO
.:JNational
~ Semiconductor
Th,Sighr" Sound Clflnfonn,tIOt!
LVDS-to-CML Interfaces
AC Coupled
1---------------,
: Vcc CML Input
I
5on:
o.1,..dL _
.:JNational
(ill" Semiconductor
Th,Sight&Soundoflnform,tioft
Interfacing LVDS to CML interfaces is straightforward.

No external termination and biasing resistors are required because CML inputs typically provide
the self-biased termination resistors.
CML-to-LVPECL Interfaces
AC Coupled (1 of 2)
CML VOMin = 300 mV Max = 500 mV

3V
Max = 1000 mV
r-
•..'1 National
~ Semiconductor
Th,$ight&SQundoflnform8f;Qn
CML-to-L VPECL Interfaces
AC Coupled (2 of 2)
d National
~ Semiconductor
Th. Sight a Sound of Inform,rion
The resistor network shown in Figure (a) provides a bias voltage (common-mode voltage) at 2V
with a lOOn termination. This configuration also provides failsafe biasing. Figure (b) shows the
termination scheme if the LVPECL receiver input is internally biased.
LVPECL-to-CML Interfaces
AC Coupled
CMLVI
3V
~ National
()" Semiconductor
Th, Sight & SOllnd of Inlorm,rion
When AC-coupling LVPECL-to-CML interfaces, designers should use an attenuator network.

The MAX VOD for a LVPECL device will be much larger than the Max VID limit for a CML
device. 25n series resistors can be used to provide an attenuation of 0.67.
LVPECL outputs need to be terminated to 150n to obtain the correct DC biasing.
Level Translation Summary
• For optimum performance with DC- and
AC-coupled applications, the following
should be considered:
- Common-mode range
- Offset voltage
- Termination resistance
• AC coupling provides the simplest
interface methodology with the fewest
number of components. However, the
following needs to be considered for
AC-cou pled appl ications:
- Capacitor value selection
- Data encoding
~ National
(II" Semiconductor
~National
P Semiconductor
A C-Coupling Considerations
AC-Coup/ing Considerations
• AC-coupling provides the simplest
interface method and requires the fewest
amount of external components to
interface different logic levels
, I. ffJ
CML
---11
";~.AXlhl
-iii •
L.",eCL.
..•..
'1 National
Ii" Semiconductor
The Sight & Sound rJf Information
Hardware manufacturers may not control both ends of a transmission linJe AC-coupling allows
them to make few assumptions about the driver or receiver they may be interfacing with.
Data-Dependent Jitter (DDJ)
• DDJ shifts crossing points, resulting in higher
jitter and possible bit errors
.:JNattonal
~ Semiconductor
Th'Sighr&Soundoflnfonn,tion
For AC-coupled applications, long strings of Is or Os cause a voltage droop to occur. This droop
results in low-frequency, Data-Dependent Jitter (DDJ). Therefore, care should be placed on
capacitor value selection.
Selecting Capacitor Values
·c = (7.8 x N x Tb )/R
- Tb = bit period
- R = impedance
- N = the maximum number of consecutive
identical bits
• Example:
- 2.488 Gbps 402 ps (Tb) =
- R = 1000 (for LVDS devices)
- N = 100 consecutive bits
C = (7.8 x 100 x 402 ps)/1000
= 3.12 nF
• Would recommend using a 0.1 f.lF or
0.01 f.lF capacitor •..'1 Nati 0 na 1
~ Semiconductor
TIll Sighr&Soundoflnformllrion
For a 2.488 Gbps receiver, Tb = 402 ps. IfN = 100 bits and R = lOOn, the calculated Cis 3.12 nF.
Using a 0.01 ~F for this scenario would suffice.
The most commonly used capacitor values found in high-speed applications are 0.1 ~F and 0.01 ~F
capacitors. These capacitors are easy to find and have sufficient bandwidth to support most high-
speed data rates.
When using AC-coupling capacitors, the smallest package size should always be chosen. This
minimizes package parasitic effects on signal integrity.
Encoding Data
8-/fO-bit Coding
Value Value lQ-bit Code Alternate Note - all codes are

(Decimal) (Binary) Code not 100% DC
HGF EDCBA atxdei fghj abcdei fghj
balanced, but the
overall transmission
0 0000‫סס‬oo 100111 0100 0110001011
1 000‫סס‬oo1 011011 0100 1000101011 is balanced
2 00000010 1011010100 0100101011
3 00000011 1100011011 1100010100
4 00000100 1101010100 0010101011
5 00000101 1010011011 1010010100
6 00000110 0110011011 0110010100 Running
7 00000111 1110001011 0001110100
Disparity
8 00001000 1110010100 0001101011
9 00001001 1001011011 1001010100 (RDmaxJ = 3
10 00001010 0101011011 0101010100
dNattonal
P Semiconductor
Th, Sight & Sound of Inform,rion
For AC-coupled applications, encoded data should be used. Encoding data that results in an
equal number of I s and Os is commonly referred to as DC-balanced data. Although some AC-
coupled applications may work without DC-balanced data, using encoded data optimizes
performance and is strongly recommended.
One type of encoded data is 8-/1 O-bit coding. As you can see, each 8-bit binary value is
translated into 2 possible 10-bit codes. A running tally is kept of the Running Disparity (RD) and
the appropriate code selected to ensure a maximum RD of three. Run length is a maximum of
five with this scheme, and the bandwidth penalty is 20%, 2 out of every 10 bits.
From a data validation perspective, this type of coding has an added benefit. With 8-/10-bit
encoded data, there are only a certain number of valid codes - invalid codes represent a
transmission error.
Other types of coding such as Manchester exist. However because of the popularity of 8-/1 O-bit
encoded data, it was used for this example.
AC-Coupled Experiment
d National
PSemiconductor
Th, Sight 4 Sound of Inform'Don
An AC-coupled test setup with the lO-bit serializer (DS92LVI021A) and deserialzer
(DS92LVI212A) were used to make some measurements. A Tektronix MBlOO BERT was used
to validate data integrity.
Input Clk Line Data Cable
Freq. Rate Cap Value Length Pattern BERT Result
20 MHz 240 Mbps 1 IJF 0.5m PRBS7 No Errors

20 MHz 240 Mbps 1 IJF 0.5m All D's Bit-Errors
20 MHz 240 Mbps 1 IJF 0.5m A111's Bit-Errors

20 MHz 240 Mbps 10 IJF 0.5m All D's Bit-Errors
8-0's and
20 MHz 240 Mbps 10 IJF 0.5m 2-1's No Errors
20 MHz 240 Mbps 10 IJF 0.5m ~1I1's Bit-Errors
8-1's and
20 MHz 240 Mbps 10 IJF 0.5m 2-()s No Errors
~ National
(II" Semiconductor
Th, S"hf & Sound 0' Infomr,bon
At 20 MHz, a string of all Is or all Os was the only pattern which caused bit errors. In the next
few slides, we will discuss the relationship between coded data and bit errors.
&< 'ualion Summary
• When AC coupling, long strings of consecutive Os
and 1s shift the common-mode voltage and reduce
noise margin
• At 20 MHz with a 0.5m cable and a capacitor value
of 10 J,lF, bit-errors occur for an all 0 or all 1 pattern
• Under the same test conditions, the maximum
number of consecutive identical bits allowed for
error-free operation was 8 bits (8 Os or 8 1s)
• Under the same test conditions and a PRBS
pattern, the link is error-free for both 0.1 and 10 J,lF
capacitor values
NOTE:All consecutive high bits were placed starting from the first
data bit (DINO), and all low bits were placed starting from the last
data bit closest to the CLKO bit
d Nattonal
()I'Semiconductor
"" SIght a Sound of Inform_tJon
Error-Free Differential Signal
Transition rich pattern
Cable Length: 0.5m/20 MHzlPRBS-15/Capacitor Value = 10 IJF

NOTE: measured with a differential probe
Tek Run: 4.00GS/s Sample
r---l--' ,
Centered
~ ~,)O.J
:';;1~::{: ~; -' ~ '
"1""'"
r;:; i.' ~
Offset Voltage ~ : _; ,; I
~,;~;\\tl I
I
J
I
I
I
~ National
P Semiconductor
Th.$Jght.tSourHIofl"form,tion
Failing Differential Signal
Bit Errors Reported - 1 IJF Capacitor
Cable length: O.5m/20 MHz/Ail 0 pattern/Capacitor value = 1 IJF

Shifted offset
voltage =
decreased
Embedded
noise margin
clock bit edge
carries into
adjacent data
bit
Embedded
clock bits (low
to high)
~Nattonal
P Semicondllctor
rn. S'l1ht ! Sound of Inform'tion
Here is an example with our DS90LYI021A and DS90LYI212A start/stop bit SerDes. As
shown above, the data arriving at the Rx is a completely unbalanced long run of consecutive Os.
Because these devices contain embedded clock bits (a single I and 0 representing a clock), every
12 bits transmitted contain 10 databits and two clock bits. Long strings of consecutive Is or Os
will result in the common-mode voltage shifting in a linear fashion, and consequently, the noise
margin will be reduced to a fraction on the nominal. Typically, LVDS receivers call for a ±100 mY
threshold. In this scope shot, there is only approximately 75 mY of noise margin.
Failing Differential Signal
Bit Errors Reported - 10 IJF Capacitor
Cable length: 0.5m/20 MHz/Ail 0 pattern/Capacitor value = 10 IJF

Slightly
I
shifted offset I
I
voltage I
I
,h Embedded
".
: t ~
,.11-:....-..
clock bit edge
I! carries into
-----':, "
I
I
adjacent data
bit
Embedded ,
clock bits (low I
I
to high)
~ National
(iI" Semiconductor
Th,SighfaSoundoflnfofm,bon
With a 10 I!F capacitor, there is only a slight shift in offset voltage. Using the larger capacitor
value provides more noise margin.
Typical Offset Voltage
DC-Coupled Applications
Blue = positive
output (A)
Red = negative
output (B)
Centered offset
voltage
l'"
~Nattonal
Semiconductor
Tn, Sighr 4 SCund of Infonn.borr
The graphic shown above is representative of the embedded clock bits from the DS92LVI021A
transmitter and all Os data bits.
For AC-coupled applications, over time, the DC component of the signal is removed and the
common-mode voltage drifts to OV. This results in a shifted DC offset voltage in the differential
signal and reduces noise margin.
Shifted Offset Voltage
AC-Coupled Applications
Blue = positive
output (A)
Red = negative
output (B)
Differential (A - B)
Shifted offset
voltage
.•.'1
l'" National
Semiconductor
TrN SIflht a Sound of In!onn,tJon
The graphic shown above is representative of the embedded clock bits from the DS92L V I 021A
transmitter and all Os data bits.
For AC-coupled applications, over time, the DC component of the signal is removed and the
common-mode voltage drifts to OV. This results in a shifted DC offset voltage in the differential
signal and reduces noise margin.
Restored Offset Voltage
Increased number of switching bits

restores proper offset voltage
•. '1National
l'" Semiconductor
Th,SilJht!Soundofl"form,tion
Unlike the previous all Os case with embedded clock bits from the DS92LVl02IA, the above
scope shots show that increasing the number of switching bits restores the proper offset voltage.
As more bits begin switching, the DC offset voltage is restored and the signals are less likely to
decay to OV. This results in more differential swing and more noise margin.
AC-coupled advantages:
- Simplest method to interface different technologies
- Fewest number of components required to restore DC offset voltages
- Short-circuit protection for removable interfaces (such as on cards used
in network switches and routers)
- Controls DC offset voltages for long-haul, box-to-box applications
- AC droop in signals can increase jitter
• AC-coupled limitations:
- May need to restore DC offset voltage when internal biasing is not
provided
- Optimum performance requires using DC-balanced data
- May be bandwidth limited for low-frequency data rates
• DC-coupled advantages:
- No droop/best signal integrity for compatible interfaces
- No bandwidth limitations for low-frequency data rates
• DC-coupled limitations:
- May require complex resistor networks when using devices with
different interface technologies
- Possible DC offset voltage drift for long-haul, box-to-box applications
~ National
(II" Semiconductor
Th,S'gh!.!Soundoflnform'tion
By using AC coupling, many different interfaces can be used together. Additionally, using AC-
coupled resistor networks can provide more noise margin than a DC-coupled implementation
when encoded data is used.
~National
PSemiconductor
The Sight & Sound of InformatIOn
Interface WEBENCIf®
Online Tools
~ \ a I i una I •. InnovatIve Products from
["l' \emll'011duclor the lVOS Pioneer and leader
nw ••••• s.o-oI __
Select your LVDS device Whllt'sNew:

Interface Products Selection
Guide for Ql of 2006 (pdt
based on device function, 3.0MB)
data rate, etc
OS25MB200
Dual 2.5 Gb/s 1:2 Mux/Buffer wittl Input
Equalization and Output Pre-EmphasIs
OS90LYOllAH,OS90LT012AH,
DS90LV027AH,DS90lY028AH.
OS90lY049H
High Temperature LVOS Drivers and
Receivers
OS42MB200T
Duat 4.25 Gb/s 1:2 Mux/Buffer with Input
Equalization and Output Pre-Emphasls
OS40MB200
Dual 4 Gb/s 1:2 Mux/Buffer with Input
Click on recommended Equalization and Output Pre-Emphasis
OSlSMB200
Dual 1.5 Gbps LVDS 1:2/2: 1 Mux/Buffer with
parts to see results Pre-emphasis
~National
(lll'Semiconductor
The SJght & Sound of Inform tit,on
One of the many tasks a system engineer must accomplish is to select the correct interface
product based on parameters such as data rates, channel length, and jitter margin. National has
simplified this selection process by providing Web tools like the Interface Product Finder along
with Interface WEBENCH@ online tools.
To begin, go to LVDS.NATIONAL.COM. The task of evaluating signal integrity can be
accomplished in three easy steps.
In the first step, enter in your desired LVDS requirements and click on recommended parts to see
your results.
P ••.••••••••
Device Function MUll-Buffer
Data Rate:>- 2000 Mbps
Input Type All

Number of Inputs 1
OutPut Type All
Number of Outputs
.....
f_=~=~ r_ _
NOTE: An attribute hiQhhghted in RED Indicates that this product IS not a direct match.
p
jl8f"
@ DS2SMB200 0
o OS4QMB200 0
~Nattonal
P Semiconductor
""'SightlSoum!ofl"fo",,,6on
In Step 2, the Interface Product Finder will select several appropriate devices that meet or beat
your stated criteria in Step 1. Select the part that best fit your desired requirements. Proceed by
clicking on "Create a Design" to simulate your selected devices.
t'"
~ National
Semiconductor
11I,$,ghraSoufldoflnform,fJOfI
Once you have selected your part, you can simulate it with a variety of channel types and
simulation inputs. Some available channel types include CAT-5, CAT-6, and FR4 traces.
Simulation inputs will include parameters such as test patterns, test amplitude, and pre-emphasis.
Additionally, pre-emphasis for the device can also be adjusted, if needed. Finally, click the
submit button to see your results.
liAIIl!IBlLLIhillli"'D·'II' ••••
Eye D••••.• m before:your •• ckpfa.e/cabk Type Eye:Diagram after your a.ckp"ne/cabJe Typ Eye Diagram after your DS25MB200a
~National
V'" Semiconductor
Th6Sight&SQundoflnformation
The last step would be the displaying of your results. Here you can see how the eye diagram is
affected by channels and devices you have selected. By looking at the eye diagrams, the engineer
will have a very good indicator of the feasibility and integrity of their simulated system.
~National
PSemiconductor
Using Mux-Buffers
In this section we will discuss National's mux-buffer and signal-conditioning parts, their
applications, the internal architecture, and related parts in the product family.
The first application to cover is "redundancy."
National's Mux-Buffer Signa/-
Conditioning Parts
Network switches, edge aggregation router, and core router applications

The enterprise equipment is mostly chassis based
Mux-buffer can reduce network down time by providing redundancy in the
equipment
•..'1 National
(iI'" Semiconductor
Th. SIght a Sound of Infarm.non
Most of the enterprise network switches, edge aggregation routers, and core routers are chassis
based. With a modular system, redundancy is easily built in using National multiplexer and
buffer (mux-buffer) parts.
The benefit of having redundancy is to reduce network down time.
Examples for Redundancy
Original Signal ~
1 Source to 2 Destinations ~
~ National
()I'Semiconductor
Th. SIght & Sound of 'nform,fJ(Jn
This shows the internal structure of a rnux-buffer. The buffer splits incoming data into two paths,
and the mux (multiplexer) selects which data source to send to the output.
Redundancy in Switch Cards
r--- ----------- ------- ------- ----..,

,, ''
l__ ~~ 5"D..,
d National
P Semiconductor
TMSigfrt"Soundof'nfofm,OOII
In a network switch chassis environment, the mux-buffer can create data-path redundancy.
If one switch card fails, the on-board management controller can switch the data path to a
backup switch card. This redundancy allows minimum network down time.
The diagram shows a passive backplane configuration and the mux-buffer is located on each
of the line cards.
Redundancy in Switch Cards
r --- --------- ---- --------,

I I
I I
I SarDes I
I
r ------------- - - ---------- -------,

I I
I I
I SerDes I
I HT I
I TO
: T_ClK
I
I
I
L __
.:JNational
~ Semiconductor
nt, Sight a Sound of Infoml8tj(m
Typical Mux-Buffer Internal
Architecture
• Bi-directional channels
• EO on each input
• De-emphasis on each output
• Line to switch: 1:2 buffer
• Switch to line: 2:1 mux and

switch side Tx loopback
• Data rate supports XAUI, GbE,

Fiber Channel, and PCle
d
l'" National
Semicollductor
ThaS'llhtaSoundoflnfortNDon
The typical mux-buffer component not only contains a mux and splitters, but it also may contain
signal-conditioning functions on its output and its input.
National's Mux-Buffer Signa/-
Conditioning Parts
Network switches, edge aggregation router, and core router applications
1 G to 3.125 Gbps backplane interface applications and conform to XAUI
jitter tolerance. Many networking backplanes are based on XAUI-like
protocols
Trends: Higher-speed line cards are needed to handle faster wire speeds
(e.g., OC-48, OC-192, 10 GbE) and more complex multi-services. This
means higher backplane speed
~ National
(ilf'Semiconductor
Th,Sight&Soundofln!orm,tion
Why build signal conditioning into the mux-buffer parts? Let's take a look at where signal-
conditioning parts are used.
The enterprise network switches and routers are chassis based. With such a modularized system,
the signal normally travels from one card to another card via a long signal path.
Signal-Conditioning Features
5" to 20" long

transmission
lines
BP Connector
~ National
()" Semiconductor
TII.Sight&Soundoflnform,rion
In this example, the source signal would start from an ASIC or FPGA, then pass through a 1" to
10" circuit board trace, a backplane connector, 5" to 20" backplane cabling, another backplane
connector, and through another 1" to 10" circuit board trace to the final destination.
Because of dielectric loss and skin effect, there will be attenuation to the high-frequency signal
band. This attenuation can create data-dependent jitter and cause data errors at the receiving end.
By applying National signal-conditioning parts near the backplane connector, the signal is
conditioned going out to the backplane and coming in from the backplane, reducing jitter and
reducing error.
Signal-Conditioning Features
BP BP
cori~ecio;CoiiheCior
[SE L2 L3
Line-card I
• Long PCB traces attenuate signals due to skin effect
• Signal conditioning overcomes transmission loss
• Enables up to 4 Gb/s data links over long backplanes
~ National
P Semiconductor
Th6$ighl&SoundQflnformation
Compared to the previous slide, the signal-conditioning part not only recovers signal loss across
the board traces, but also conditions the signal in both transmitting and receiving directions. This
is achieved by equalizing the signal, as shown in the next slide.
Input Equalizer
d National
P Semiconductor
TbeSightaSoundoflnfonn,tlon
On the receiving end, there is an equalizer. The equalizer boosts the high-frequency signals to
compensate for the loss due to skin effect and dielectric.
The center trace shows the jitter in the signal after a 25" board trace. The resulting signal at the
output has restored amplitude and reduced jitter.
Output De-emphasis OFF
TJ ;15 ps p-p TJ; 119ps p-p

BP
BP
Connector \
Connector
/
2" 2"
d National
PSemiconductor
1M Sight of SOlIfId of IntorrrYrion
After equalization, the jitter is reduced. On the transmitting side, after 32" of board trace and two
backplane connectors, the signal amplitude again reduces and the jitter increases.
Output De-emphasis ON
• Driver de-emphasis equalizes long transmission line - reduces jitter and

opens data eye for downstream receiver
TJ = 37 ps pop
/ 2"
BP
Connector
2"
I
OUT+
•..'1 Noli 0 n0 I
~ Semiconductor
Th,$ight"Soundoflnform,tlon
By turning on the de-emphasis at the transmitter output, the low-frequency component of the
signal is attenuated relative to the high-frequency component, and the resulting signal at the end
of transmission line is a low jitter signal. Note that the final signal amplitude is reduced.
How De-emphasis Works
_.~ Click on the

switch
to activate
~National
(iI" Semiconductor
Th,Sighr&Soundaflnform,m,n
Here is another demonstration of the de-emphasis. By clicking on the switch, the de-emphasis
can be turned on/off. The jitter histogram shows reduced jitter.
How De-emphasis Works
I 10 meters, CAT-5 at 1.5 Gbps

x=:x:::::>c>cXX=:IE:lI_.~
I
Cfickon the
switch
to deactivate
d National
P Semiconductor
nt, S,~/It a Sound of Inform.tlon
Lower jitter is achieved through de-emphasis. This demo is using the National cross point
switch.
Adjustable De-emphasis Steps
DE [1:0] VOD (mV) VODDE (mV) VODDE in dB

00 1200 1200 0
01 1200 850 -3
10 1200 600 -6
11 1200 426 -9
.•..
'1 Naito na I
(III" Semiconductor
The Sighr a Sound of InfomNfKHI
On many of the National parts, the de-emphasis level is adjustable. This specific example shows
there are four levels of de-emphasis to match the transmission channel attenuation, i.e., different
PCB trace length or cable length.
Redundancy in SDV
•..'1 National
~ Semiconductor
Th, Sight" Sound of Information
Mux-buffers and cross point switches are similar. A cross point switch output can select any
input and an input can go to multiple outputs.
In addition to enterprise network switch and routers, the mux-buffer and cross point switch can
be used in Serial Digital Video (SDV) applications.
The block diagram illustrates the function of multiplexing and switching.
~ National
P Semiconductor
Cable Driver
Using Mux-Buffer
• PCI express, SATA. XAUI, Infiniband, etc. are used to link between systems and
computers. The bit rate can reach beyond 1 Gbps
• High speed cabling requires signal conditioning to overcome transmission loss
• DS40MB200 is used as an example that can be used to improve signal quality over
cable so that receive can recover transmitted signal
• Applications - Network inter-system connection, storage device attachment, computer-
to-computer connection, board-to-board connection, etc
.•.'1 National
(II" Semiconductor
TIl, Sight" Sound o( 'nform.flon
The ever-increasing communication data rate has created higher demands on signal-conditioning
parts used to drive cables. Standards such as PCI Express, Serial AT A, XAUI, and Infmiband
are used to link communications between the systems.
The applications are Storage Area Network (SAN), digital cable connecting computer to display,
personal computer to personal computer, personal computer to peripheral devices, chassis
systems to chassis systems, etc.
PCI Express Cable Example
2.5 Gbps, T J = 88 ps 1e - 15 (0.22 UI)
/,
d National
(II" Semiconductor
The Sight a Sound of Inform'tJOrt
This slide shows the DS40MB200 is capable of driving 10 meters of PCI Express cable.
With the output de-emphasis turned on, the signal at the destination has less then 0.22 UI of
jitter.
PCI Express Cable Example
AC)National
(il'Semiconductor
TIle Sight a Sound of Inform,tion
With signal conditioning on both sides of the cable, de-emphasis on the transmitting end,
and equalization on the receiving end, the jitter is reduced from 0.22 VI to 0.19 Dr.
The Mux-Buffer and
Signal-Conditioning Family
·DS40MB200-4.00 Gbps; Dual- channel; 1:2 but; 2:1 mux; De-emp; EQ
·DS42MB200 - 4.25 Gbps; Dual- channel; Ind temp; 1:2 but; 2:1 mux; De-emp; EQ
·DS25MB200 - 2.5 Gbps; Dual channel; 1:2 buffer; 2:1 mux; De-emp; EQ;
·DS15MB200 -1.5 Gbps; Dual channel; 1:2 buffer; 2:1 mux; De-emp
·SCAN15MB200 -1.5 Gbps; Dual channel; 1:2 buffer; 2:1 mux; JTAG
·DS90LV004 - 1.5 Gbps; Quad channel; Buffer; Pre-emphasis
·SCAN90004 - 1.5 Gbps; Quad channel; Buffer; Pre-emphasis; JT AG
·DS42BR400 - 4.25 GbpsQ transceiver
·EQ50F100 - 6.25 Gbps; Backplane equalizer
·DS90CP04 - 2.5 Gbps; 4x4 crosspoint switch
·SCAN90CP02 -1.5 Gbps; 2x2 crosspoint switch with Pre-emphasis; JTAG
·DS90CP22 - 0.8 Gbps; 2x2 crosspoint switch
·CLC018 - 1.5 Gbps; 8x8 crosspoint switch
.•..'1 National
(II" Semiconductor
Th,Sight&SOlJndQflnformBtiQn
For detailed information on applications, part selection, and part descriptions, please refer to
the Interface Product Selection Guide and Broadcast Video Selection Guide.
The component information such as datasheet, reference design, evaluation kit, and white
paper is also available at http://lvds.national.com.
~ National
PSemiconductor
Cable Driving
Cable Types
For the highest bandwidth and longest drive distance

Used often in video broadcast equipment
For economical data transfer

CAT-5, CAT-5, CAT-7
Specialty connectors are eliminating RJ45 crosstalk
• Twin-axial
Used for high-density, high-bandwidth applications
Seen as a standard cable for specifications like Infiniband
• Fiber Optic
Used for extreme distance and bandwidth
Intra campus to intercity applications
l'"
~National
Semiconductor
Th,Sighf&Soundoflnform,tion
There are several major types of cable, each with many variations to cover specific conditions or
bandwidth requirements.
Coaxial: This is the highest-bandwidth electrical cable. By definition, it is fully shielded and also
offers high-bandwidth, low-crosstalk connectors to complete the assembly.
Twisted Pair: This common cable type is most often seen in Ethernet applications in CAT-5 or
CAT-5e four pair configurations. The widespread use also makes it a relatively low cost
solution. It can also be found in many other low-to-medium speed applications where signal-to-
signal skew or timing is not critical or the distance is short.
Twin-axial: This type of cable represents a "middle ground" between the low-loss coaxial cable
and the economical twisted pair cable. It is used for high-speed serial specifications like
Infiniband.
Fiber Optics: When signals need to travel very long distances, fiber optics are often used. Fiber
optic cables represent the lowest-loss medium possible for serial communications. It is necessary
to do an electrical-to-optical conversion which adds to the overall cost. This additional cost
limits the adoption of fiber in applications that electrical cables can accomplish with the help of
signal conditioning.
Signal-Conditioning Options
• De-em phasis/pre-em phasis

- Output compensation to adjust for transmission loss
• Fixed/adaptive equalization
- Input compensation to adjust for transmission loss
• Multilevel signaling
Improved utilization of transmission line
bandwidth
l'"
dNattonal
Semiconductor
""'SlQht4Soundoflnlonn_bOtI
There are three options for signal conditioning. The first two are the most common and available
from multiple silicon sources.
De-emphasis/pre-emphasis: Either of these terms can generally be used to define an output
signal-conditioning technique to increase the high-frequency energy of a data signal at the
driving device. This is done in anticipation of the losses that will be found in the transmission
path.
Fixed/adaptive equalization: Input equalization is the use of a high-pass filter that is the
complement to the low-pass characteristic of the cable that you are using. This helps to
compensate for some of the attenuation effects of the cable.
Multilevel signaling: This technique uses four or more signal levels to compress more data into a
lower frequency range. Reducing the maximum frequency of interest allows data to be
transferred longer distances or at higher speeds relative to normal two-state digital data.
• Attenuation and bandwidth
Data Signal Cable
Increasing Cable
Length
~ National
Ii" Semiconductor
Th, Slflht & Sound of Inform,von
Looking at any serial data signal with a spectrum analyzer will give the picture on the left. If the
data rate is 1 Gbps, then the first notch in the pattern will be at 1 GHz. More notches will be
present at multiples of the first notch seen. In this case, theywould be seen at 2 GHz, 3 GHz,
4 GHz, etc.
The cables used for transmission always will show increasing levels of attenuation for longer
lengths.
Cable Driving
D'N
From ROUT
BERT to
Transmitter BERT
Analyzer
~National
(I" Semiconductor
Ths$igfJt&Soundoflnformstion
The cable drive set up includes both a transmitter and receiver. The topology is point to point.
The waveforms are taken at the driver output and the receiver input. The signal quality of the
receiver output is also analyzed to ensure robust reception of the attenuated signal.
Cable Loss Example
CAT-6 Cable loss of 0.4 dB/meter at 400 MHz

- 6 dB or 50% reduction after 15m
.:JNattonal
~ Semiconductor
Th,SiQht&$oundoflnfOfm,tion
These graphics show the same signal, one at the beginning of the cable and the other at the end.
The highest-frequency signal at the end of the cable shows a 6 dB or 50% reduction in
amplitude.
Pre-Emphasis Example
DS15MB200 and DS90LV004
• De-emphasis/pre-emphasis
- Output compensation to adjust for transmission loss
[~
1 UI 1 UI I
•.'1 National
~ Semiconductor
Th, Sight & Sound of Inform,lJorl
The primary signal-conditioning technique used to improve LVDS performance is output pre-
emphasis. Pre-emphasis is controlled amplitude and duration output overdrive used to
compensate for high-frequency losses and extend transmission distance over cables and
backplanes. The simplest and most effective pre-emphasis scheme is full-first-bit pre-emphasis.
The waveforms on the right show the difference between no pre-emphasis and 6 dB of pre-
emphasis. The pre-emphasis boost cleans up the jitter seen at the input of the receiving device,
extending the length of cable that can be driven at a given frequency.
Pre-Emphasis Example
.•..'1 National
~ Semiconductor
Th. SlQht a Sound of InfOl11YfIM
The primary signal-conditioning technique used to improve LVDS performance is output pre-
emphasis. Pre-emphasis is controlled amplitude and duration output overdrive used to
compensate for high-frequency losses and extend transmission distance over cables and
backplanes. The simplest and most effective pre-emphasis scheme is full-first-bit pre-emphasis.
For buffers without an internal clock for timing, the length of this pulse is optimized for the
maximum specified datarate.
The waveforms on the right show the difference between no pre-emphasis and 6 dB of pre-
emphasis. The pre-emphasis boost cleans up the jitter seen at the input of the receiving device,
extending the length of cable that can be driven at a given frequency.
L VDS Cable Driving
2.0
1.8
Ui 1.6
Co
.c 1.4
~
--
Q)
•..
CIl
CIl
CIl
1.2
1.0
0.8
0.6
0
0.4
0.2
0
0
.:]Nattonal
(iIF Semiconductor
Th. S'uht " Sound of Infonn,tlofI
M-L VDS Cable Driving
• At the D891 D 176 output

- Higher VOD than LVDS
- Tighter input threshold
- Wider common-mode range
~ National
PSemiconductor
Th,S;ghr&Soundof!nform,fIQn
While TIA/EIA-485 is better suited for longer-distance applications, M-LVDS provides true
multi-point solutions with less power usage at greater speeds. The lower operating voltages of
M-L VDS are the reason for the lower power consumption, but also the reason for the restriction
to shorter distances where noise coupling and differential attenuation through the interconnect
media are lower.
M-L VDS Cable Driving
250
(i) 200
Co
.c
~ 150
-•..
ell
III
-
III
III
0
100
50
0
0
d National
(.il'Semiconductor
The S,~ht •• Sound of fnform,tJOn
The larger VOD, tighter input thresholds, and wider common-mode range of M-L VDS devices
make them great candidates for driving significant distances over cable. In this example, the
M-L VDS can achieve its full operation data rate across 20 meters of cable. At slower data rates,
similar to RS485, the M-LVDS devices can transmit and receive data at distances of over 100
meters.
Adaptive Equalization
Data Data
Source Destination
Example A: Surveillance camera Security monitors

Example B: Control PC Large outside LED display
(airport, roadside, hotel. .. )
"~
':IV
",
~
Cable Equalizer
.:]Nattonal
(;9 Semiconductor
Th, Sight" Sound of Inform/ltion
National has many SDV products for the broadcast video professional equipment market. These
products go into the studios that produce, edit, and distribute the digital video for broadcasting,
closed circuit TV, and video on demand.
These same parts have applications in the broad market transferring data of any type. For
example, the standard-definition digital TV cable drivers, retimers, and equalizers operate at
155 Mbps, which is the STM-I telecom standard used through out the telecom world. Telecom
OEMs use these SDV products in their equipment for sending the STM-I data over many meters
of cable. The SDV products also will work at the 622 Mbps data rate used in telecom
applications.
Adaptive EQ Waveforms
~National
Ii" Semicollductor
rM Sight a Sound of InfrKrMtIOtI
The CLCOl2 from National has the capability to equalize up to 300 meters of 75n Belden
coaxial cable or 100 meters of common CAT-5e cable. It is important to take extra care when
dealing with Twisted Pair (TP) cable. The high-gain amplifiers in the CLCOl2 will not be able to
discriminate from excessive crosstalk and the small remaining signal from the distant transmitter.
For this reason, it is recommended that shielded TP be used whenever possible and the unused
pairs in the cable be terminated with loon resistors.
It's Not Just Attenuation
Cable Drive Summary
• Crosstalk
- Adjacent signals reduce the signal-to-noise ratio of
the interconnect
- Connectors are the most common culprit
• Impedance discontinuities
Cause reflections and reduce the bandwidth of an
interconnect
Connectors and vias
• Insertion and return loss
- Device inputs and outputs are not ideal
~ National
P Semiconductor
TIll Sight & Sound of Inform,rion
Crosstalk cannot be forgotten and becomes increasingly important as the speeds increase into the
Gbps range. Crosstalk is a concern for multi-conductor or multi-pair cables that do not have a
good isolation between data carrying channels. In addition, connectors can be a significant
source of loss induced by cross talk in a cable assembly. The conducting elements inside a
connector radiate electromagnetic fields, which are coupled to the conductors in the adjacent
pairs of the connector. Similar coupling occurs in the cylindrical vias used by adjacent connector
pairs in a PCB. Consider a bi-directional signal transmission over a multi-channel cable where
the drivers are driving at their full amplitude, and the receivers are receiving weak signals from
their far-end partners, heavily attenuated by the cable's transmission loss. The near-end-crosstalk
from the strong local driver, superimposed onto the weak receive signal, results in a poor signal-
to-noise ratio. Neither driver pre-emphasis nor receiver equalization compensate for crosstalk;
therefore, the designer should minimize crosstalk by selecting individual pair cable shielding and
low crosstalk connectors when multi-channel data transmission is required.
Also, device inputs and outputs do not represent ideal sources or terminations. This non ideality
allows energy from crosstalk and impedance discontinuities to be partially reflected at device
inputs and outputs increasing the jitter on the primary signal.
As data speeds increase to and beyond 2 Gbps it is recommended that designers look to CML
devices that utilize a de-emphasis scheme. This behaves exactly like pre-emphasis only the
signal amplitudes are decreased instead of increased. By decreasing the output amplitude of the
driver, it is possible to reduce the effects of crosstalk on these high speed signals.
~National
PSemiconductor
Clock Distribution
While a lot of attention has been given to the ever-increasing speed of serial data transmission, it
is important to understand that system clocks may not be making the same quantum leaps in
speed, but that levels of accuracy required for system operation have matched the data-path step
for step. With faster and higher-resolution ADC and DAC devices, clock specifications are
critical for optimum system performance.
Clock Distribution Topics
• Using M-L VDS for clock applications

- LVPECL comparison
- ATCA backplane requirements and analysis
~ National
~ Semiconductor
Th, Sight a Sound of Inform,rifHI
Before clocks are multiplied, divided, and cleaned, they must be distributed across the system. In
the case of larger systems with complex backplane configurations this task ideally handled by
devices like the Multipoint Low Voltage Differential Signaling (M-LVDS) family from
National.
PCI Industrial Computer Manufacturing Group (PICMG), is a consortium of more than 600
companies who collaboratively develop open specifications for high-performance
telecommunications and industrial computing applications.
ATCA, Advanced Telecom Computing Architecture (Advanced TCA ®), is the largest
specification effort in PICMG's history, with more than 100 companies participating.
Advanced TCA, the PICMG 3.X family, is a new series of PICMG specifications targeted to
requirements for the next generation of carrier-grade communications equipment.
The sub-standards within PICMG encompass a large cross-section of high-performance, widely
used computing standards in the market now.
PICMG 3.1. Ethernet
PICMG 3.2. InfiniBand
PICMG 3.3 StarFabric
PICMG 3.4 PCI-Express
PICMG 3.5 Rapid IO
PICMG 3.6 PRS (Under Development)
We will use this section of the presentation to compare the ATCA - M-LVDS solution with
traditional LVPECL and LVDS clock distribution methods.
.•..'1 National
PSemicondu.ctor
M-LVDS
Multipoint,
Low-Voltage Differential Signaling
M-LVDS: Multipoint, Low-Voltage Differential Signaling.

This is a key development in National's LVDS technology. These products are specifically
tailored to meet the demands of distributed clocking architectures. They have slow, controlled
edge rates to reduce system EM! and minimize the transmission line effects of a multi-drop
backplane topology.
M-LVDS (TIAIEIA-899)
• Multipoint-LVDS (described in TIAIEIA-899

standard allows up to 32 driver/receivers
• Electrical characteristics include stronger
drive, slower edge rate, and wider common
mode compared to LVDS (TIAIEIA-644A), all
to improve signal quality in a multi-point
applications
• M-LVDS now specified in ATCA standard for
clock distribution, gaining momentum in
other areas
- A TeA is the open standard for future modular
networks
.:JNattonal
(.:;. Semiconductor
Th,S'Qht&Soundoflnform,tion
While the original LVDS standard was widely adopted to various and diverse applications, the
new TIAlEIA-899 M-L VDS standard is targeted to the very specific needs of multi-point load
topologies. This standardization should allow for the widespread adoption of ML VDS into
systems that can take advantage of this open multi-source product offering. System designers
and architects can look to the M-L VDS family to provide distributed clock solutions for future
generations of electronic systems.
Like RS-485, M-L VDS is specified to handle 32 loads. Devices compliant with the M-L VDS
standard do not provide as much noise immunity as RS-485, but these devices can provide
signaling rates that exceed RS-485 capabilities. In addition to the increased signaling rate,
M-L VDS also provides multi-point operation with less power consumption than RS-485.
While TIAlEIA-485 is better suited for longer-distance applications, M-L VDS provides true
multi point solutions with less power usage at greater speeds. The lower operating voltages of
M-L VDS are the reason for the lower power consumption, but also the reason for the restriction
to shorter distances where noise coupling and differential attenuation through the interconnect
media are lower.
Family Spec Comparison
Edge
VOD (mV) Rate Common
Min Max (mln) Mode Rx Threshold
LVOS 250 450 260 ps o to 2.4V -100 to +100 mV
BLVOS 350 600 260 ps o to 2.4V -100 to +100 mV
M-LVOS
480 650 1 ns -1.4V to 3.8V -50 to +50 mV
OS910176
M-LVOS
480 650 1 ns -1.4V to 3.8V +50 to +150 mV
OS91C176
d National
~ Semiconductor
111. Sight a Sound of Inform.Don
In this chart, some of the key differences between standard LVDS and Multipoint-L VDS are
highlighted.
The LVDS devices are designed to drive a point-to-point topology with very low power. This is
accomplished with a small voltage swing into a lOOn termination. Because M-L VDS devices
are designed to drive multipoint double-terminated loads, they must provide significantly higher
voltage and current to maintain acceptable noise margins in the system.
Another huge difference is the output edge rate. LVDS point-to-point topologies can switch at
rates in excess of 1 Gbps. The edge rates need to be sufficiently quick to accommodate this and
transmission line losses at higher frequencies. M-L VDS, on the other hand, lives in a low-
resistance, high-capacitance environment. This slow edge rate will help eliminate the
transmission line effects of stub capacitance.
In addition to the higher VOD, it is important to note that the receiver thresholds have been
improved. This reduction improves the signal-to-noise margin in complex multi-drop
environments.
Device Functionality
0591 C176 (Type 2 Rx)

:~---
0591 C180 (Type 2 Rx)
05910176 (Type 1 Rx) 05910180 (Type 1 Rx)
8-Pin 50IC package 14-pin 50IC package
•..'1 National
(ill" Semiconductor
T1l. Sighra Soundoflnfom!,tIotl
Basic single channel M-L VDS devices - Transceiver - M-L VDS Driver - M-L VDS Receiver:
These are compatible with other vender M-L VDS offerings.
200
150
E
.S- 100
a> 50
en
2
(5 0
>
-50
-100
TYPE 1 TYPE 2
DS91Dxxx DS91Cxxx
Clock and Data Control Functions
~National
P Semiconductor
TMa Sight Sound of Inform,tion
This graphic highlights the differences between a type 1 and type 2 M-LVDS input. Remember
the M-L VDS input thresholds have been tightened by 100 mY; this improves the noise margin in
large multi-point designs.
For control functions, the type 2 receiver has been designed to be offset from OV differential.
This allows for a wired-OR control scheme to be implemented with differential signaling. The
results are similar to the open-drain style outputs used in LVCMOS control systems.
Type 2 Receiver - Wired OR
Type 2 Receivers with offset can provide

Wired-OR function for control signals
~ National
P Semiconductor
Th.Sight&Soufldofl"form.tlon
Wired-logic signaling is a common technique used on multi-point bus interface standards.

Multiple drivers can pull the control signal high, but when they all go into a Tri-State® condition
the type 2 input will respond to the OV differential with a low output. Examples of standards that
incorporate wired-OR logic include the Aontroller Area Network (CAN), Small-Computer Systems
Interface (SCSI), IEEE-488 (GPIB), IEEE-896 (BTL), and others. Often called wired-OR
signaling, it provides the equivalent OR gating of all the outputs on the signal line(s) and
collision detection. Multi-point protocols most often use wired-logic signaling during bus
arbitration, but some also use it during data-transfer phases.
M-LVDS Common Mode Range
5
4 3.8V
3
••
••
'0
2 LVDS
BLVDS
1
> LVDM
0 o.ov
-1 -1.4V
-2
~National
P Semiconductor
Th.Sight&SoundDfln!otm,tJOfI
The M-L VDS standard includes many unique features to address issues of concern when
operating with multi-point communication. The standard allows up to 32 M-L VDS circuits
(driver, receiver, or transceiver) to be connected to the common transmission media. The
common-mode voltage on a multi-point bus is the sum of the driver output and ground offset
voltages. TIA644 and 644-A drivers are required to have an output offset voltage of 1.2V ±O.175V.
Since there are periods when there are no active drivers on a multi-point bus segment, the
M-LVDS driver cannot be used to establish the worst-case common-mode operating point of the
circuit. During this idle-bus state, the common-mode voltage is bounded by the open-circuit
voltages of the attached components. In the case ofTIA/EIA-899 compliant devices, this voltage
is OV to 2AV and is borrowed from its 644 predecessor. The addition of a lAV ground-noise
offset added to this range gives the common-mode voltage range requirements for M-L VDS
circuits of -IAV to 3.8V.
Edge Rate Specifications
550 BLVDS
0.26 nS min I RISEIFALL
450
350
M-LVDS
1.0 ns min IRISEIFALL
~ 250
150
50
-5\.00 2.00
n8ec
d
l'" National
Semiconductor
11l, Sight" Sound of Inform'Ron
The edge rate of M-L VDS devices is significantly slower than other LVDS families. This
significantly improves the signal quality in a multi-point signaling environment.
Actual M-L VDS tR1SE and tFALL
__ tlIII> •••• __ tIol>_
-'''''''''1
M·LVDS M·LVDS
1.56 ns tR1SE 1.62 ns tFALL
d National
P Semiconductor
1M S"ht a Sound oIlnform'rKKI
A final M-L VDS driver provision to address multi-point operation concerns transition time. As
was shown in the table on a previous slide, 644 and 644-A allow driver transition times as fast as
260 ps. Faster transition times lead to higher signaling rates, which is one of the key benefits of
LVDS.
One of the drawbacks of fast transition times is that careful attention needs to be placed on the
design of the interconnect to minimize impedance mismatches from stubs, connectors, and other
parasitic connections to the line. General guidelines suggest that mainline stubs be kept as short
as possible, with specific guidelines recommending that the propagation delay of a stub be less
than 20% of the signal transition time.
Approximate Acceptable
Stub Length vs tRISEltFALL
- 2
-•
en
c 1.5
•• 1
SAFE •
~
SORRY
•m 0.5
" 0
IU
0 1 2 3
•..'1 National
(lll'Semiconductor
Th,Stght&Soufldofln/orm,tion
For clean backplane waveforms, it is necessary to keep the stubs from acting too much like
individual transmission lines. This is achieved by limiting the stub length based on the driver
edge rate. Stubs will lower the effective impedance of the backplane traces. Short stubs will still
lower the effective impedance, but not significantly impact the signal integrity with reflected
energy.
~National
P Semiconductor
Backplane Clocks
Clock Backplane Application
• lVPECl classically used to drive backplane
- High-power consumption
• BlVDS has made inroads
- Good noise margin and much less power than PECl
• Pt-Pt through the backplane still dominates
"low" frequency clock distribution (coupled with clock
cleaning/multiplication on line card) provides the opportunity for
an improved approach
• Multi-point clocking enables:
- Reduced clock module complexity
- Reduced backplane etch runs
- Reduced clock tree power
- Potential cost savings for customers
• M-lVDS helps by slowing down output transitions improving
signal fidelity
• M-lVDS extended common-mode range not required for clock
distribution
d National
l"" Semiconductor
The SIQht & Sound of Infonn,lion
Traditionally, LVPECL has been used to drive backplane clocks. This type of solution has a
relatively high-load current and device power. M-L VDS can be just as effective at distributing
low-speed clocks (up to 100 MHz) with a significant savings in power.
• lee vs frequency
- Single-channel Tx - Rx implementation
Transmitter Receiver
M-LVDS 15 mA 10mA
LVPECL 27mA 15mA
.:]Nattonal
()I'Semiconductor
n..Slght&SoundflffnftXffl'bon
Backplane Clock Application
-Backplane application
- Trend to multi-Gbps serial data
- Usually point-to-point clock
distribution
- Dual clock modules
- Multiple clock module to
line/channel card connections
- Supply voltage reduction
•..'1 National
(lIP Semiconductor
T1I. Sighr 4 Sound oflnform,Oon
With a redundant centralized clocking approach, each line card will have two independent pairs
of incoming clock lines. In a l4-slot backplane, this would mean 28 separate signal pairs to
provide clock signals to every line card.
Point-to-Point Clock Design
Channel Skew
13.0 pS
Dedicated clock driver

designed for minimum
channel skew and jitter
.:)Nattonal
P Semiconductor
Th. Sight & Soundofln!ofm,tion
There are multiple LVDS parts that are ideal candidates for this type of application. In this
graphic, the LVII0 is shown driving multiple copies of a system clock. Each of the outputs is
closely matched to keep channel skew to a very small value. The typical channel skew for LVDS
parts in this family are 50 ps or less.
.:]Nattonal
l'" Semiconductor
1M S'Q/It & Sound of Inform,don
The distributed clocking approach allows for clock distribution with only 10% of the backplane
resources. This helps to keep cost of the implementation low. As a side benefit, the clock can be
driven from one of multiple sources.
For the central approach, the termination would be provided on each line card. For the
distributed approach, the termination is provided at each end of the backplane.
=
• PICMG PCllndustrial Computer
Manufacturers Group
• ATCA = Advanced Telecom Computing
Arch itectu re
PICMG is a consortium of over 600 companies who collaboralively develop open specifications for
high performance telecommunications and industrial computing applications.
ATCA, Advanced Telecom Computing Architecture (AdvancedTCA"'), is the largest specification

effort in PICMG's history, with more than 100 companies participating.
AdvancedTCA, the PICMG 3.X family, is a new series of PICMG specifications, targeted to
requirements for the next generation of carrier grade communications equipment.
PICMG 3.1. Ethernet

PICMG 3.2. InfiniBand
PICMG 3.3 StarFabric
PICMG 3.4 PCI-Express
PICMG 3.5 Rapid 10
PICMG 3.6 PRS (Under Development)
~Nattonal
(ill" Semiconductor
The Sight" Sound of l"ftXm'oOfl
ATCA has incorporated many of today's widely used interface standards and continues to
develop additional specifications.
Clock Requirements
A TCA = PICMG 3.0
• M-LVDS technology shall be used

• Backplane impedance of 1300, terminated with 800
• Boards interfacing to clock bus must support hot
swap
• Clock drivers high impedance unless authorized to
drive bus
• Redundant 8 kHz system clock
• Redundant 19.44 MHz SONET/SDH clock
• Redundant third pair of clock signals
- Network reference signals derived from external inputs
- User-defined
- 100 MHz max frequency
- Reference clock signals can be driven from any slot
• Source of reference clock is application specific and
may change dynamically [Distributed clock
architecture] ~National
(/f'Semiconductor
Th,S,ght&Soundof/nform,tion
The M-LVDS technology is central to the clocking scheme of an ATCA backplane. The entire
electrical path has been defined to ensure good robust clocking across all possible board
permutations.
__ I··
PICMG 3.0 Backplane

Z.-1300
~ National
P Semiconductor
a
Th. Sight Sound of Inform,tJOfl
This block diagram details the clock channels. They are all 1300 differential and doubly
terminated with 800 at either end of the backplane. The parallel combination of 800 resistors
means that the M-L VDS devices will be driving a 400-load termination. The maximum stub
length from the backplane is defined in the ATCA standard as 1" or 2.5 em.
A TCA Clock Requirements
Q) M-LVOS clock drivers (OS910176)
o LVCMOS-MLVDS
M-LVOS clock repeaters
MLVDS-MLVDS OR MLVDS-LVCMOS
CD M-LVOS bidirectional clock drivers
.•..
'1 National
(II" Semiconductor
Th.Sight&Soufldoflnform,tion
Clock driver (LVCMOS to M-L VDS)

Clock repeater (M-L VDS to M-L VDS)
Clock transceiver (Bi-directional LVCMOS / M-L VDS)
~National
P Semiconductor
ATCA Backplane
Performance
M-LVDS devices support 100 MHz operation as required by PICMG 3.0 standard.
Distributed clock architecture is enabled with multi-point LVDS devices.
High impedance - hot plug support.
Key signal integrity characteristics:

1) Backplane-strength drive capability: Maintains VOD even driving 400 load.
2) Slow controlled driver edge rates: Keeps stubs at every line card from affecting the
signal integrity and noise margin of the distributed clock.
3) Provisions for driver contention: For high reliability operation, it is not destructive if
multiple drivers contend with each other on the multi-point bus.
Two SMA connector pairs connect to
liDs of a single MLVDS transceiver for
"device only" evaluation
Additional two SMA connector pairs

for evaluation of the fabric interface
with instrumentation andlor available
high-speed interface device EVKs (Le.
SCAN15MB200EVK)
This M-LVDS line card allows for direct plug into ATCA backplane clock. All six clock lines
are connected with different stub lengths and impedances to identify optimal line card design.
This allows for good observation of clock signals in the real application.
For non-ATCA applications, an additional M-LVDS device is provided with SMA connections
on input and output.
ATCA Backplane Features
• Six multi-drop M-L VDS

clock pairs
~
• Dual Star topology for
high-speed point-to-point
signals
• M-L VDS evaluation line

card plugs directly into
connectors highlighted in
the photo
~ National
Ii'" Semiconductor
The SIght a Sound of Infonn'tJon
The six multi-drop clock lines are connected to the backplane headers that are highlighted by the
red oval.
The data path is configured in a dual star topology. This means that each fabric or switch card in
the center, identified by large connectors, has point-to-point data connections to each line card.
A TeA Stub Length Effects
M-LVOS OS910176
....--a--s· ---
.-
IT
- ~
.~. A
t::"1
~
. 1
~~I-
l
Longer Stub Length •

Reduced NoIM Margin
d
l.'" National
Semiconductor
TIl.Sight&Souf!doflnform,tifHI
For clean backplane waveforms, it is necessary to keep the stubs from acting too much like
individual transmission lines. This is achieved by limiting the stub length based on the driver
edge rate. All the stub lengths will reduce the effective impedance of the backplane clock traces.
Short stubs will not significantly impact the signal integrity with reflected energy. Long stubs
reduce the overall noise margin available in the design.
ATCA Duty Cycle
M-LVDS DS91D176
45
40
-
.•.'1
l'" Naito
Semiconductor
",. Sight
naI
a Sound oIlntonn.t1on
For distributed system clocks, it is critical to maintain a near 50% duty cycle for many
components to work properly. The M-L VDS devices have better then 45/55 duty cycle
performance all the way to 100 MHz in the ATeA system.
Output VOD Control
M-LVD5 D591D176
>'E 600
-
a 550
g 500
•••
i 450
•••
6 400
~ National
P Semiconductor
a
Th, Sight Soufldoflnformation
Even across such diverse loads like the ATCA backplane and RS-485 cabling, the M-LVDS
DS9lD176 maintains a steady VOD to keep system noise margins high.
ATCA Jitter and Phase Noise
M-LVDS DS91D176 at 50 MHz
5,(1) in dB • 10 x log [Sc!1)!,dBcIHz
Definition
Clock jitter analysis with JIT3 advanced software
on TEK6154C (15 GHz Bandwidth)
• RJ = 6.5 ps rms
• Cycle to cycle jitter = 100 psp_p
•..'lNafional
P Semiconductor
The Sight & Soufldoflnformafiofl
In most cases, the distributed clock frequency will be multiplied up to some specific frequency
and cleaned to ensure the lowest possible phase noise in the signal. This is a phase noise plot of
the M-LVDS DS9IDl76 output.
Phase noise is the measurement of phase fluctuations per unit bandwidth. vea phase noise is
best described in the frequency domain where the spectral density is characterized by measuring
the noise sidebands on either side of the output signal center frequency. Single-sideband phase-
noise power is specified in decibels relative to the carrier (dBc/Hz) at a given frequency offset
from the carrier.
M-L VDS Application Areas
Edge rate (low EMI), wide

common-mode
Low-power, edge rate,

common-mode
Type 2 Rx offset for

wired-OR
Although ATCA is a large early adopter ofM-LVDS technology, many other applications are
sure to use and benefit from the I/O characteristics of this LVDS family.
~National
P Semiconductor
Preserving Signal Integrity
Achieving High-Fidelity Signal

Amplification
High-voltage (30V), low-noise «2.7 nV/..JHZ), operational amplifiers are essential when the
primary design criteria is maintaining AC signal fidelity and integrity. We will look at why 30V,
low-noise operational amplifiers are superior to lower voltage amplifiers.
Low Noise Amplification of
Low-Level AC Signals
• Signal sources include:
Microphones
Audio DACs (16 bits to 24 bits)
Tape head
Phonograph cartridges
Low-level instrumentation
• Applications:
Professional audio
Consumer audio
Industrial instrumentation
Sensors
Low-level measurement
Low-level signal amplification
~ National
(II" Semiconductor
Th.S;ght.tSoundoflnformIflOll
These low-level signals have a typical amplitude in the range of 0.2 mV RMS to 5 mV RMS' This
amplitude needs to be increased to something on the order of 1.5 V RMS (with a gain of 77 dB to
50 dB), adding as little additional noise and distortion as possible.
Typical Mixing-Console Signal Path
From JlVto V
A., = :t15dB
Four amplifiers
• Signal path can include 9 or more amplifiers

• Noise floor multiplied 3x
l'"
~National
Semiconductor
T1I,SighraSoundoflnfOfm.tKHI
From input to output, a typical mixing console may have up to nine amplifiers in the signal path
and a total maximum gain of75 dB. These amplifiers are typically implemented with operational
amplifiers. This is the kind of application that demands very low noise and vanishingly low
distortion in each individual amplifier to maintain excellent signal integrity and fidelity.
As shown in the figure above, a typical mixing-console signal path is composed of a microphone
preamplifier, a high-pass filter, equalization that provides low-, middle-, and high-frequency
response adjustments, a summing section for mixing the different signal inputs, and an output
amplifier (single-ended and/or differential). It is possible that the entire signal path can use up to
10 amplifiers. The total amplifier noise in the 9-amplifier signal path shown above can be as
high as three times the noise of a single amplifier.
Typical Mixing-Console Microphone
Preamplifier
• Differential amplifier
• DC blocking capacitor for phantom
microphone power
dNational
P Semiconductor
Tn. Si,ht " Sound of Inform,tion
To the microphone preamplifier, a typical ribbon microphone looks like a source impedance of
300ft The equivalent voltage noise density for this 3000 source impedance is 2.22 nV/...fHZ* or
0.393 flVRMs over a 20 Hz to 20 kHz (noise) bandwidth. This exceedingly small amount of noise is
one strong reason for needing low-noise operational amplifiers. The dominant components of the
preamplifier's output noise are the microphone's and the amplifier's noise voltage over the
bandwidth of interest. Assume the amplifier noise is 1.7 flVRMs' for example. Since the noise sources
are uncorrelated, the total noise is the square root of the sum of the squares of each noise voltage
contribution. The product of the microphone's noise and the amplifier's noise voltage is:
~(1.7 f.1VY + (O.39f.1VY =1.74f.1V

When using the preamplifier's maximum gain of 60 dB, the noise floor voltage could rise to 1.74 mY.
Microphones have a typical dynamic range of 120 dB. This dynamic range results in a maximum
output voltage of 1.95 V RMS'At full output, the microphone preamplifier gain needs to be only 14 dB.
At this gain, the noise floor voltage only rises to 24.5 flY. This is a SNR of 112 dB.
Differential vs. Single-Ended Inputs
-{>-
• Single-ended inputs will amplify any injected
noise (typically 50/60 Hz or RFI)
• Differential inputs amplify the difference
between the two applied signals
• Differential inputs reject noise that is
common to the two inputs
dNational
~ Semiconductor
The Sight a Sound of InfrHm,tion
Single-ended inputs and outputs are susceptible to noise injection such as AC line frequencies
(50/60 Hz and its harmonics). Any signal appearing on the single-ended input will be passed
through to the output and amplified if the closed-loop gain is greater than unity.
A differential input can be as susceptible to receiving the same kind of noise as the single-ended
input, but if the noise on each input is equal in magnitude and in phase (common-mode noise), it
will be rejected by the differential amplifier.
/,()----j
RSOURCE:':':~::
<:~::.
"'o-----j
• To ensure lowest noise floor, minimize source

resistance
• Noise = 0.13 nVNHz (at 25°C)
• 600n is pro audio standard load and source
resistance - but can be even lower
• This load requires high drive current (±25 mA,
minimum) at ±15V output swing
•..'1 National
l"" Semiconductor
111. Sight a Sound of Inform_Don
As was previously mentioned when discussing the typical microphone preamplifier, the source
impedance contributes noise to the signal of interest. The nominal magnitude of the Johnson
noise in a 10 resistor at room temperature is 0.13 nV/JRZ. The nominal voltage noise density of
a 1000 resistor, a 10 kO resistor, and a 1 MO resistor is 1.3 nV/.JHZ, 13 nV/.JHZ, and 130 nV/.JHZ,
respectively.
Professional audio applications typically use 6000 as source and load resistances. The nominal
voltage-noise density of a 6000 resistor is 3.2 nV /.JHZ.
The relatively low 6000 load requires amplifiers with a minimum output current capability of
±25 mA
Higher-voltage operation:
5Vvs ±15V
*=c}-
+5V +15V
·15V
• More swing results in higher SNR

• 5V vs 30V: ~15.6 dB improvement
•..'1 National
PSemiconductor
Th. Sight & Soundofln/omJ,tion
Modem trends in the semiconductor industry mean that there are a great many low-voltage (5V
to l5V) amplifiers available. However, the existence ofhigber-voltage amplifiers with low noise
and distortion will help designers maximize the dynamic range achieved by their designs.
With all else being equal, simply using a ±15V supply amplifier instead of a 5V amplifier
improves SNR by at least 15 dB.
Av = ±15 dB
Four amplifiers
• Multiple amplifiers
• Like noise, want lowest THD+N
• Minimizes increasing THD+N through signal path
.:JNational
P Semiconductor
Th.Stghr&Soundoflnfomllfion
In a multi-amplifier signal processing chain, low amplifier Total Harmonic Distortion (THD) is
necessary to ensure that the overall system linearity and signal integrity is maintained. The
amplifier also will add a noise component (N) to the input noise along with the THD. In a
measurement system it can be difficult to distinguish between these contributions so the term
THD+N is used. The lower THD+N the better because THD+N will increase through the signal
chain. Each amplifier adds to the THD+N that all the previous amplifiers in the signal path have
contributed. Also THD+N sources are assumed to combine as the square root of the sum of the
squares of the individual sources.
THD+N will nominally increase by an order of magnitude for each 20 dB of gain. Therefore, an
amplifier with 0.00 I % unity gain THD+N would measure as 0.1 % THD+N at 40 dB of gain.
Slew Rate and Signal Bandwidth
• Slew Rate (SR): maximum output voltage rate of

change
• Above some frequency/amplitude combination,
slew rate is exceeded
• SR(V/Jls) = 27t x f MAX x Vp
• Min slew rate for 20 kHz, 30 Vp.p signal: 1.88 V/JlS
• Max frequency for 20 V/JlS, 30 Vp_p signal: 212 kHz
d National
(II" Semiconductor
Slew rate is the maximum rate of change that an amplifier's output can sustain and is considered
the large signal performance limit of the amplifier. Reaching and exceeding an amplifier's
maximum slew rate causes the amplifier to cease operating in a small signal mode, and the
output swing no longer accurately represents the input signal. Picture a sine wave morphing into
a triangle waveform. Exceeding an amplifier's slew rate is a function of the combination of input
signal frequency and magnitude. It is a trade-off: To avoid exceeding an amplifier's slew rate, a
high-frequency signal demands lower signal swing, whereas low-frequency signals allow much
high signal swing.
In the first of the two examples above, the minimum slew rate needed to amplify a 20 kHz signal
that swings ±15 Vp•P is 1.88 V/~s. An amplifier with 20 V/~s slew rate can amplify a 212 kHz,
±15 VpoP signal.
Well before the slew rate limit is reached, the amplifier input signal differential voltage is no
longer zero (or very small), and distortion will begin to increase. This is why an audio
operational amplifier needs a slew rate that is well above the minimum needed for the expected
bandwidth and signal swings.
So, What ;s Needed?
.:]Nattonal
(ill'Semiconductor
Th,SiQht&Soundoflnfofm.tiofl
For the example application shown, which shares the same requirements as the vast majority of
other high-accuracy, AC signal processing applications, what are the important capabilities
needed in an operational amplifier?
Low noise, low THD+N, and high slew rate are essential to ensure signal integrity and fidelity.
High power-supply voltage is necessary to maximize signal-to-noise ratio and dynamic range.
The low load impedances used to maintain low-noise operation require an amplifier with high
output-current capability.
Key Overture® LM4562 Parameters
Features
Low noise: 2.7 nV/--IHZ (1.6 pAl'i'RZ at 1 kHz)
Low distortion: 0.00008%
Low ISlAS: 15 nA
Operating voltage: ±2.5V to ±17V
10UTMAX: 28 mA
GBW: 60 MHz
Slew Rate: 20 V/~s
Drives 6000
PSRR and CMRR >110 dB
Channel-to-channel isolation >130 dB'
Applications
Ultra high-quality audio amplification • High-fidelity equalization and crossover
High-fidelity preamplifiers networks
High-fidelity multimedia • High-performance line drivers
State-of-the-art phonograph pre amps High-performance line receivers
HighOperformance professional audio High-fidelity active filters
~National
P Semiconductor
Th6 $ight & Sound QflnformatiQn
The LM4562 is a dual, low-noise, high-voltage, ultra-low distortion operational amplifier

designed to meet the requirements of the applications previouslyshown. It has a typical 2.7nV /..JHZ
voltage noise density, near perfect linearity with a distortionof only 0.00003% (20 Hz to 20 kHz,
VOUT = 3 V RMS)' Its wide ±2.5V to ±17V supply voltage range makes it perfect for professional
and high-end consumer audio applications and the perfect upgrade in applications currently using
5V, l2V, and l5V power supply voltages.
The high 110 dB PSRR and CMRR performance means that external noise, whether coming
through the power supply or injected into the LM4562's inputs, will not degrade the amplifier's
outstanding performance.
Although it is a dual amplifier in an industry-standard eight-pin package, the 130 dB channel-to-
channel isolation ensures that each amplifier will amplify only its intended signal, despite what
the adjacent channel it doing.
Finally, the LM4562 is able to easily drive 600n loads to within 1.2V of the supply rails.
Measuring THD+N
• Limits in resolving THD+N < 0.00050/0
• Amplifier distortion is an input-referred

internal error source
d National
p Semiconductor
Th.Sight4Soundoflnform.rion
The LM4562 is so linear that it is not possible to directly measure the distortion at unity gain.
Even with equipment that can resolve 0.0005% THD+N, the LM4562's actual THD+N is below
the test equipment's resolution and is not revealed.
The LM4562's distortion can be considered an input-referred internal error source. To get a
closer look at the actual THD+N, amplifying the LM4562's error signal is recommended. The
LM4562's closed-loop gain can be left unchanged even while the error signal is amplified. The
addition of a single resistor is used to lower the distortion reducing feedback.
• Signal gain 1 =
• Distortion gain = 1 + 1100
kO (40 dB)
Signal
Test-Signal 600Q Analyzer
Generator
d National
(ill'Semiconductor
1lN SIght a Sound 01 JnforruDtHI
In this THD+N measurement circuit, the signal gain is left at unity, whereas the distortion gain
has been increased by 40 dB. All that is needed is a IOn resistor connected between the
inverting and non-inverting inputs.
With the increased amplitude of the distortion components, the measurement equipment is now
able to easily revolve the error magnitude. If the measurement value is 0.003%, we know that
this is actually 101 (40 dB) times the actual value. How does this translate into an adjusted
THD+N value? It is known that when a number's decimal point is moved either left or right by
one digit, the number's magnitude changes by a factor 10 (20 dB).
• VOUT = 3 VRMS
• At 40 dB and 60 dB - THD+N is 0.003% and
0.03% respectively
d National
~ Semiconductor
ThI1 Siflht a Sound of Inform,tJOfI
The measured LM4562's THD+N is 40 dB higher than actual. This 40 dB (a 100:1 factor)
allows the decimal point to move two digits to the left. Hence, the actual distortion is 0.00003%.
An important reason for using the LM4562 as a microphone preamplifier is its 0.00003%
THD+N. When gains on the order of 40 dB to 60 dB are used in an LM4562-based microphone
preamplifier, the THD+N is increased to as much as 0.03%. Fortunately, the preamplifier's
distortion is still below the typical high-quality microphone which has a THD+N of 0.05%.
Therefore, the LM4562's outstanding THD+N performance preserves the integrity and fidelity
of a microphone's output signal.
"
•
, I III
...
II II I IIII
.,
o. IIIII
..
R
I I IIIII I r+-.LII
=Iil=l
...'1 National
P Semiconductor
The Sighf& Soundoflflform,tion
Here is an actual curve of the LM4562's THD+N versus VIN• This curve was generated with a
distortion signal gain of 101 (40 dB). Shifting the decimal point two places to the left to
compensate for the gain gives a final THD+N value of 0.00003%.
Voltage and Current Noise
Density Curve
¥
.
~
.s •!>
.
!
z
!
10 =
·0
z
i
.3
~
~National
(Il'Semiconductor
nlf Sight a Sound of Inform.rion
The most important LM4562 feature is a very low voltage-noise density. The typical flat-band
voltage noise density is 2.7 nV/~ with a nominal comer frequency of60 Hz. The typical flat-
band current noise density is 1.6 pA/~ with a nominal comer frequency of 30 Hz.
How low is this voltage-noise density? The LM4562 has the same nominal voltage-noise density
as a 4310 resistor.
Calculating Voltage Noise for a
Given Bandwidth
• Starting with the voltage noise density (nVlVHZ)

• The noise for a given bandwidth (20 Hz to 20 kHz,
for example)
• NoiseBW = (nV/.JHz )X(~HZupperLimil - HZLowerLimil )
• The LM4562 has a 2.7 nV/VHZ voltage noise

density
• Noise over 20 Hz-to-20 kHz bandwidth:
0.48 IlVRMS
• SNR: 124.2 dB (referenced to 0.775 VRMS)
~ National
PSemiconductor
TII. Sight a Sound oIlnftK""fJOfI
nBW = (VoltageNoiseDensity)x(~Bandwidth)
For the LM4562, operating over a 20 Hz-to-20 kHz bandwidth, the nominal rms noise
voltage is
nBW = Jij; X .J (20kHz-20Hz)1.57

2.7nV
Hz
Referenced to the voltage that creates I mW dissipation in a 6000 load (0.775 mVRMS)' the
LM4562 has an SNR of 124.2 dB. Referenced to the LM4562's maximum output when
driving a 6000 load (+13.8 Vp.P or 9.76 VRMS)' the LM4562's SNR is 148.2 dB.
LM4562 Audio Operational Amplifier -
Preserving Signal Integrity
• Outstanding performance preserves low-level

signal integrity and fidelity
• 2.7 nV/...JHzvoltage noise density
• 0.000030/0THD+N (RL = 6000, VOUT =3V RMS)
• 6000 load drive
• +13.8V output swing (RL = 6000, V S = +15V)
dNa/tonal
lI" Semiconductor
a
1M Sight Sound of InfonnltJOfI
~National
PSemiconductor
Designing High-Power, High-

Fidelity Audio Amplifiers
Design Challenges
• Requires high voltage and high output current

• Monolithic designs limited to :S100W
• E.g. LM3886, monolithic 68W amplifier (see
application circuit)
e,
.:E v-
-=- ~1 201c4
•.
".
'C;
221AF.:±-
.:]National
(II" Semiconductor
Tfll SiQht a Sound 0/ Inform,Don
The challenge in designing a high-performance, high-power amplifier is that high voltage and
high output current are required. Furthermore, monolithic designs are limited to output power
levels of IOOW or less because of package power dissipation limitations. The LM3886, for
example, has an output power of 68W.
Increasing Output Power by Using a
Different Topology
• Bridged/Parallel
Amplifier (BPA)
topology
• Can use with

LM3886 to get 225W
output power
~National
P Semiconductor
111. SI(Jht " Sound of Inform'lion
Different amplifier topologies can increase the output power beyond what a single monolithic
amplifier can produce. One such topology is the Bridged/Parallel Amplifier (BPA) topology,
which can deliver 225W when implemented with several LM3886 amplifiers.
Discrete Designs
• Con:
• Pro: Size
High power
Cost
- High fidelity
Complexity
Design expertise
~Nattonal
(II" Semiconductor
.",. Sight a Sound of fnform,tion
Another solution is to use a discrete amplifier design. Such a design can use either a MOSFET or
bipolar output stage. The pros of this type of design are that high power and high fidelity are
attainable. The cons of this approach are the complexity of the design, cost of discrete
components, and the need for design expertise.
LM4702 Overture® Stereo High-
Fidelity Power Amp Driver
Features
• Very high voltage operation
• Scalable output power
• Minimum external components
• External compensation
• Thermal shutdown and mute
Key Specifications
Three performance grades available: A, B, C
• Wide operating voltage range** C = ±20 to ±75
B = ±20 to ±100
A = ±20 to ±100**
Grade C Specs
• Output Noise (A-weighted) 90l1V
PSRR (input referred) 110 dB
THO 0.005%
• Slew rate ±15 V/l1S
** In characterization: Target = 200V (±100V)
~ National
(.i" Semiconductor
The Sight& Sound of Information
The LM4702 is a high-fidelity audio power amplifier driver designed for demanding consumer
and pro-audio applications. When used to drive external power transistors, the LM4702 is
capable of delivering in excess of 300W per channel single-ended into an 80 load.
The LM4702 is available in three grades that span a wide range of applications and performance
levels. The LM4702C is targeted at high-volume applications. The LM4702B (in development)
includes a higher voltage rating along with the tighter specifications. Both the LM4702C and
LM4702B come in a TO-220 package. The LM4702A (in development) is the premium part
with the highest voltage rating, fully specified with limits over voltage and temperature, and is
offered in a military 883 compliant TO-3 gold-plated package.
LM4702 Advantages
• Replaces entire
stereo amplifier
front end (see
schematic)
• Reduces circuit
board space,
design time and
cost
• No heatsink
required
d National
P Semiconductor
nr. Sight & Sound of Inform.tkHr
This is a schematic for the front end of a high-power stereo amplifier. The LM4702 replaces this
entire circuit, reducing circuit board space, design time, and cost. The LM4702 itself does not
require a heat sink.
LM4702 100W Stereo
'"
Demo Amplifier (.OO05%THD+N)
jE
'f.~..~
~'~.'l~.".
,... """
,~.
...
~·i
•....'"
THD+N vs POUT Graph
...'1 National
P Semiconductor
Th9 Sight & SoundoflnfQrmafirm
This is a schematic of a complete lOOW stereo amplifier. Notice how few parts are needed for a
complete amplifier that uses the LM4702. It uses far fewer components, and as such, is much
simpler than the schematic shown on the previous slide! As can be seen from the graph, the
THD+N reaches 0.0005%.
In practice, the complete amplifier schematic that is shown in this slide will still need power
supplies and some sort of output protection circuitry or fuses. National's Audio Group has
heatsink modules (used for the power transistors, not the LM4702) with the lOOW complete
amplifier board mounted on them available for evaluation.
LM4702 Simplified Schematic
• Fully complementary implementation

- NPN and PNP have similar IT
• Previous drivers utilized slow lateral PNPs
- Caused instability and reduced bandwidth
• Output of LM4702 operates in Class A mode
.•..'1 National
P Semiconductor
Th, Sight &. Sound of Inform'DOIt
This is a simplified schematic of the internal circuit of the LM4702. As can be seen from the
schematic, it is a fully complementary implementation. In comparison with previous drivers
which used slow lateral PNPs, this implementation is superior because the NPN and PNP
transistors have similar iT's. Another feature is that the output of the LM4702 operates in Class
A mode.
LM4702 Output Power Scaling
M":.
• POUT = 1OOW/ch
into 80 load
'"
to,., "
,.IQ
r
-:- c..,
~~ ,.~
Il,."
• ±40V Supply
~ ..,
• Achievable THD
of 0.0005%
r", ..
• 'O"F "IQ
M":.
~National
(il'Semiconductor
Th, Sight & Soundoflnform/iltion
This is a simplified typical application circuit for the LM4702. With supplies of ±40V, this
amplifier can drive lOOW per channel amplifier into an Sil load with an achievable THD of
0.0005%. The portion of the circuit enclosed in the rectangular box corresponds to the LM4702.
The LM4702 drives an external Class AB output stage, consisting of bias voltage circuitry and
power transistors (Darlingtons shown). If a designer wanted to increase the output power, how
would this be accomplished?
LM4702 Output Power Scaling
..'"~ .v~ • Increase supply to
±60V
~..•
Ce,
~,
",.F .."., • Add output
0 c",
~,.F
...,
,", transistors in
parallel
c.., • POUT = 200W/ch

~,.F
into 80 load
reo ..'"~
",.F
• Current drive limited
to 5 mA
..'"~
t!JNattonal
Semiconductor
"'- Sight & Sound of fnfortNDOII
Amplifier output power may be scaled by changing the supply voltage and number of output
transistors. If a 200W per channel amplifier is desired (see above schematic), the supply voltage
must be increased from ±40V to ±60V in order to get enough voltage swing across the 80 load.
Furthermore, because of power dissipation limitations of the output transistors, one output
transistor must be added in parallel for each existing output transistor - a total of four additional
output transistors. As can be seen from the above schematic, there are now two power transistors
in parallel per side (top and bottom) in both channels. If a 350W per channel amplifier is desired
(not shown), use a ±75 supply and three power transistors in parallel per side in both channels.
Power Supply Requirements
• Maintain voltage level under load to produce

required output power level
• Supply enough current to meet output power

demands
d National
(ilf'Semiconductor
111. SIght a Sound of Inform.rton
Because music and voice programs have a high dynamic, the demands on a power amplifier
supply vary greatly. The power supply needs to maintain the voltage such that the power
amplifier can produce the desired output power while also supplying large output currents. With
the fmite PSRR of the audio amplifier, the power supply should also have acceptable ripple.
Power Supply Options
Power supply design choices:
• Linear regulated supply
• Voltage stays constant
• Expensive, complex, adds power dissipation
• Switching supply
• Good regulation
• More expensive than unregulated, can add switching
noise
• Unregulated supply
• Low cost, acceptable performance for audio power
amplifiers
• Voltage varies significantly
The most common choice is an unregulated supply
~ National
PSemiconductor
TheSil1ht.tSoundoflnform,tiOfl
A well-designed linear regulated supply will have almost as many components as the audio
amplifier portion, and in some cases more. Regulated supplies are more expensive, have higher
part counts and reduced reliability, but the voltage is pretty constant. A switching supply has
very good regulation, but is still more expensive than an unregulated supply and the switching
noise is not something audio designers want in the system. An unregulated supply uses very few
parts, is simple, and lower cost with high reliability, but has the drawback that the supply voltage
varies much more. The most common choice for customers is to use a unregulated supply.
Unregulated Supply Schematic
• Unregulated supply components:
• Transformer
• Diode bridge
• Supply capacitors
Power
Mains
-v
~ National
Ii" Semiconductor
The Sight & SQund of Information
An unregulated supply is very simple and consist of only a few parts. The heart of the supply,
and typically the largest cost, is the transformer. The transformer may be a standard type or a
more expensive, but higher performance toroid. The diode bridge can be discrete diodes or a
complete bridge in a single package. The supply capacitors are typically designed to act as
current reservoirs to stabilize the voltage under high current demands and limit ripple. The
current reservoirs consist of large, electrolytic capacitors of value from 470 flF to 20,000 flF or
several capacitors in parallel for even higher values. Additionally, there will be another group of
capacitors located near the IC(s). Capacitors by each IC for high-frequency noise rejection are
typically ceramic chip type in value from 0.01 flF to 0.47 flF and smaller value electrolytic or
tantalum capacitor of value from I flF to 47 flF used by each IC, as needed.
Unregulated Supply Issues
• Output power
• High line condition on mains (or brown out)
• Rating of transformer used in the design
• Heating of the transformer
• Real example:
• 360 VA Toroid transformer, ±30V, 6A.
• No signal, supply voltage = ±44.5V
• POUT = 2 x 50W/80, supply = ±35V
• POUT = 2 x 60W/80, supply = ±33V
~ National
(II" Semiconductor
ThllSighfASoundoflnformlltion
Unregulated supplies have a significant amount of voltage variations. The voltage will drop as
output current increases. This is called supply droop. A high line condition on the mains will
raise the voltage so the maximum rating of the power supply must take this possible condition
into account. The rating of the transformer also will affect how much voltage variation occurs.
As the transformer heats up, the resistance of the windings will increase, resulting in additional
voltage drop. When there is no signal, the supply voltage will float to a higher level since only
minimal current is being drawn. The example gives some actual numbers from a design. Notice
that the no signal supply voltage rises as high as ±44.5V, while under a full load the supply has
dropped to ±33V.
Unregulated Supply Issues
• The high-line, no-input-signal supply voltage must not

exceed the maximum voltage of the IC
• Large supply capacitors reduce ripple but slow supply

droop increasing Po in the IC. Too much capacitance
increases load on and heating of the transformer
• High line condition may increase maximum voltage by

10% more
d National
P Semiconductor
Th,S,ght&Soundoflnrormatio(l
As shown in the real example in the last slide, the minimum voltage under full-load conditions
results in an unregulated supply that will float up 30% under a no signal condition. If the no
signal voltage is lowered, then the full-load voltage also will decrease and the target output
power specification would no longer be met. Adding additional capacitance on the supply will
help reduce the supply droop, but also slows the rate of supply collapse so that power dissipation
is higher in the amplifier IC. High supply capacitance also will increase the current load from the
transformer, increasing the heating of the transformer. The result, in order to use an unregulated
supply, amplifier ICs must have significant supply head room above the operating supply. This
poses a challenge, since the supply is limited by the fabrication process and by design.
Summary
• Need adequate headroom above full power

supply rating
• Traditional Ie supply ranges limited to 100 to

120V
• LM4702 dramatically raises supply voltage to

200V
~ National
PSemiconductor
Th.Sight&Soundoflnform,tlon
In summary, unregulated supplies should be used because they are less expensive and give
acceptable performance for audio power amplifiers. However, adequate headroom must exist
between the nominal power supply voltage and the maximum supply voltage of the IC in order
to account for extreme conditions (high line, no input signal). Traditionally, IC supply voltages
have been limited to 100 to 120V. The LM4702 is a dramatic improvement with its 200V supply
voltage.
• LM4804 mono 1.8W
BTL amplifier
• Operating supply
range of 3V to 4.2V
• Output power
exceeds 2W (THD+N
= 10%) over power
supply range of 2.9V AlJdioln~
201<
V O.::F Ai
to 4.2V
~National
V'" Semiconductor
The Sight" Sound of InformlltJon
When relatively low-voltage power supply sources are used, it is more difficult to get high
speaker power levels, even with BTL amplifiers. Lower impedance speakers will increase power
levels, but at the cost of increased current levels in the amplifier and in circuit traces. A more
preferable approach may be to use a boosted Boomer® amplifier, represented here by the
LM4S04. This amplifier delivers I.SW to an SO BTL speaker while operating on a battery
voltage of just 4.2V. In addition, it will deliver a minimum of 2W (10% THD+N) to that same
SO BTL speaker over a battery voltage range of2.9V to 4.2V.
Maintaining Signal Integrity
• Differential input versus single-ended
input
Input.
C, R;
r"
COUT
:~
_. iCB
-=-
2VOO
Bias
-=-
1rJ -=-
~Nattonal
Ii" Semiconductor
nr.SightetSfJumirtflnform,tion
Low-voltage power amplifiers in portable applications are often subject to interfering signals
from adjacent digital and RF circuits. Differential input amplifiers are considered excel1ent low
noise and high PSRR amplifiers when compared to similar single-ended amplifiers. But care
must be taken with both to maintain signal integrity on both sides of the amplifier's input.
Typically, differential inputs will provide better SNR than single-ended inputs, but this is only
true as far as the differential amplifier is designed and laid out properly to maintain balance
between the amplifier "halves." Close matching of external components is required to maintain
the excel1ent PSRR and CMRR benefits differential amps provide.
LM4927 Mono, Fully Differential Amplifier
Key Specs
• Differential inputs and outputs
• 1.3W Output power (Voo = 5V,

THD+N =
1%, 80)
• Improved PSRR at 217 Hz (87 dB)
• Low output noise and high SNR
• Requires minimal external

components (CB is optional)
Packages
• LLP
Applications
• Mobile phone
• PDA
• Portable electronic devices
~National
P Semiconductor
TIN Sight a Sound of Inform.Don
The LM4927 is a mono, fully differential audio power amplifier primarily designed for
demanding applications in mobile phones and other portable communication device applications.
It is capable of delivering 1.3W watts of continuous average power to an SO load with less than
1% THD+N from a 5V DC power supply. It has improved PSRR and very low output noise. It
also drives 40 loads with 2.1 W of output power with 5V DC power supply and less than 1%
THD.
LM4928 Stereo, Fully Differential
Amplifier
Key Specs
• National first stereo differential Inputs
and outputs amplifier
• 1.2W OutRut Rower (Voo = 5V,
THD+N = 1%, 80)
Improved PSRR at 217 Hz (90 dB)
Low output noise and high SNR
Requires minimal external
components (ea is optional)
Packages
• LLP
• 16-bumps micro SMD
Applications
Mobile phone
PDA
Portable electronic devices
~Nattonal
Ii" Semiconductor
Th,Si(Jht&Soundoflnfomlarion
The LM4928 is a stereo, fully differential audio power amplifier primarily designed for
demanding applications in mobile phones and other portable communication device applications.
It is capable of delivering 1.2W per channel of continuous average power to an 811 load with less
than 1% THD+N from a 5V DC power supply. It has improved PSRR and very low output
noise.
When supplied in the LLp® package it can also drive 411 loads. Output power = 1.8W per
channel (411, THD+N = 1%).
Class D Advantages
• Efficiency
Longer battery life
• Important for portable devices
• Laptops
• Cell phones
Lower device temperature
• LCD TVs
- Panel thermal distortion
• No heatsinking
- Smaller solution
.••.
'1 National
l'" Semiconductor
TheSight&Soundoflnformlltion
Class D's main advantage versus Class AB is higher efficiency. This extends battery life, which
is critical for portable devices such as laptops and cell phones. Also, the Class D amplifier
operates at a lower device temperature for the same rated output power compared to an AB
amplifier. This is critical in LCD displays, where heat dissipation from an audio amplifier can
cause thermal distortion on the LCD panel itself. Since the Class D amplifier runs at a lower
temperature, smaller size heatsinks or no heats inking at all can be achieved.
Efficiency
• How the Class D is

efficient
100
Output MOSFETs
00
operating in the linear
&:l
region (low resistance
switches) l 70
Output stage requires no ~ 00
bias current ~ ~
(4:
40
• Good Class D amplifiers lb
~
can achieve 11 > 85%
20
10
o
o 0.1 0.2 0.3 0.4 0.5 0.6 0.7
OUTPUT POWER (W)
~ National
PSemiconductor
TIll Sighr a Sourrd 0' I"form.rion
Here is an efficiency comparison for a typical Class D amplifier versus a Class AB amplifier.
Peak efficiency is achieved at a faster rate for Class D. The reason for this is that the Class D's
output MOSFETs operate like very low resistance switches, that are either fully on or fully off.
Also, the output stage for the Class D does not require any bias current.
Efficiency Losses
• Where it loses power

Internal sources
• ROSON
- Determined by MOSFET size
- Biggest contributor to efficiency loss
• Switching losses
Time spent in active region
Higher frequency, more time in active region
Gate current
Larger MOSFETs require more gate current
Designer must create a balance between
switching frequency for best THD+N and
efficiency, and MOSFET size and minimum
gate current
dNattonal
(iI" Semicondtlctor
TIll Sight.l Sound of Information
Theoretically, Class D can achieve an efficiency of 100%. Unfortunately, all MOSFETs have a
non-zero ROSON' The power loss due to ROSON is conduction loss. A voltage divider is formed by
ROSON and the output load, which prevents Class D amplifiers from ever reaching their
theoretical efficiency. ROSON can be minimized by increasing the MOSFET size. The Class D's
gate charge and switching currents also dissipate power, which is considered switching loss.
During switching times, losses occur because the rise and fall times of the FETs are greater than
zero, since the output transistors cannot switch instantaneously. The more time the output FETS
remain in the transition region, the more power is consumed. Also, gate capacitance of the FETs
increase rise and fall times, but as MOSFETS become larger, gate capacitance becomes larger as
well. To ensure fast rise/fall times of the MOSFETs, the gate driver must provide more gate
current to charge and discharge the gate capacitance during the switching interval. Gate currents
also contribute to switching losses as well.
• Simplified PWM modulator
Sawtooth or triangle
waveform used to modulate
audio input
THD+N improves as
switching frequency
increases
Higher switching frequency
leads to decrease in
efficiency
• Noise (EMI)
PWM at a constant
frequency
l'"
~ National
Semiconductor
T1I,SlghfAStJundoflnform.fIOfI
The majority of Class D amplifiers use a PWM (pulse-width modulated) approach. Here is a
simplified view of a PWM modulator. A comparator compares the level of the audio input to a
triangle wave operating at a switching frequency significantly above the audio band. Better
THD+N performance can be achieved with higher switching frequency. However, EMI can be
an issue if the switching frequency is too high. Since traditional Class D amplifiers use a
constant switching frequency, the harmonics of that frequency can radiate, which will make EMI
emissions worse. The resulting PWM comparator output waveform isthen used to drive the
H-bridge output stage.
LM4673 Boomer
2.65W Class D Amplifier
Specs
• Supply voltage = 2.4V to 5.5V
• Improved IOOQ = 2.6 mA (3.75 mA max) at 5V
• Improved PSRR = 78 dB at 217 Hz
• Improved THD+N: 0.02% at 3.6V, 100 mW,
1 kHz into ao
• SNR = 97 dB at 5V, 1W
• Output noise = 23 ~ at 3.6V, A-weighted
• Efficiency = 88% at 3.6V, 400 mW, ao
Extra Features
• PWM architecture
• Fully differential
• Filterless Class D when speakers are
close to outputs
• Output short circuit protection
d National
(.iIf'Semiconductor
The Sight & Sound of Informerion
The LM4673 is a mono PWM class D amplifier with an efficiency rating of 88% for mobile
phones, PDAs, and other portable electronics where battery life is important. This is the world's
smallest Class D audio amplifier in the 4mm pitch micro SMD package.
LM4674 Boomer®-
Stereo 2.5W per Channel Class D Amplifier
Specs
• Supply voltage = 2.4V to 5.5V 1011F +
• Improved PSRR = 74 dB at 217 Hz ~

• Improved THO: 0.07% Typ at 500 mW,
1 kHz into 80 RIGHT
• Efficiency = 85% at 5V, 1W, 80 AUDIO
INPUT
Extra Features
• PWM architecture LEFT
AUDIO
• Fully differential INPUT
• 4 gain selects: 6,12,18,24 dB
• Filterless Class 0
• Independent shutdown control
•..'1 National
(I" n.Semiconductor
a
Slf}ht Sound of Inf~Dotr
The LM4674 is a stereo version of the LM4673 aimed at multimedia phones and PDAs with
stereo speakers.
~National
PSemiconductor
Analog Video Solutions
Video Standards, Formats,

Interfaces, and Signals
Video Groups and Specifications
NTSC: National Television System Committee. The US form of standard definitionTV.

PAL: Phase Alternating Line. The system of standard definitionTV implemented in Europe. etc.
SECAM: Se uential Couleur avec Memoire. The French form of standard definitionTV.
ATSC: Advanced Television Systems Committee. The US form of high definitionTV (HDTV).
VESA: Video Electronics Standards Association. Proposes, pUblishes video standards for Graphics.
ITU: International Telecommunication Union. Proposes/publishes video standards for EU broadcast.
SMPTE: Society of MotionPicture & TV Engineers. Proposes, publishes standards for US broadcast.
.•..'1 National
(;9 Semiconductor
TheSlghtaSourrdofl"tonn.tJon
The top box consists of the analog broadcast TV standards used worldwide.
The middle box consists of the Electronic Industries Alliance (EIA) specifications for YPBPR
analog component video. These EIA 770.X specs do not address YCBCR digital component
video.
• EIA 770.1 is the U.S. specification for enhanced component video, which includes
widescreen signaling (16:9 aspect ratio) for NTSC systems.
• EIA 770.2 is the U.S. specification for Standard-Definition TV (SDTV) analog
component video, which includes 480i and 480p video formats.
• EIA 770.3 is the U.S. specification for High-Definition TV (HDTV) analog component
video, which includes nop and 1080i formats.
The bottom box contains the Society of Motion Picture Television Engineers (SMPTE)
specifications for various video signals, including composite (analog signal only), component
and RGB video (analog and/or digital signals).
Standard-Definition (SDTV)
Formats and Timing
NTSC/480i (Interlaced)
720 (H) x 480 (V) active video resolution (720 x 240 active/field)
858 x 525 total resolution
V refresh rate (frame rate): 29.97 Hz (59.94 Hz field rate)
H scan line rate: 15.734 kHz
PALl576i (Interlaced)
720 x 576 active video resolution (720 x 288 active/field)
V refresh rate (frame rate): 25 Hz (50 Hz field rate)
A lot of variations (PAL I, S, G, H, D, N, M)
•..'1 National
P Semiconductor
TII, Sight & Soundof'nform,tJ()n
In the United States, older conventional televisions were made for displaying NTSC video,
which has an active video resolution of 720 x 480 at 29.97 frames per second or 59.94 fields per
second. In other parts of the world, like Europe, PAL video has an active video resolution of 720
x 576 at 25 frames per seconds or 50 fields per second, and is interlaced as well. In interlaced
scan systems, two fields (referred to as odd and even fields) are required to scan one picture
frame.
Using the PAL format as an example, the odd field, which consists of lines #1 to 312.5, are
scanned first. Then, the even field consisting of lines 312.5 to 525 are scanned next. The odd and
even fields are scanned at 50 fields/see, which equates to 25 frames/sec.
The "active video resolution" is considered to be the portion of the visible picture frame on a
correctly adjusted display. The "total resolution" includes the active video portion plus "non-
active" video portion dedicated to horizontaVvertical sync and blanking, and in the case of
composite video, also color burst information.
Most people often refer to video formats by the active vertical resolution per frame plus the scan
type, "I" for interlaced and "p" for progressive scan. 480i actually has 525 total lines of vertical
resolution (active lines and blanking lines) and has the same timing as NTSC. However, 480i is
transmitted via the analog component interface rather than composite interface. 576i has 625
total lines of vertical resolution and has the same video timing as PAL. 576i is like 480i in that it
is transmitted via analog component interface.
Enhanced Definition (EDTV)
Formats and Timing
480p (Progressive)
720 x 480 active video resolution
V refresh rate: 59.94 Hz
576p (Progressive)
720 x 576 active video resolution
V refresh rate: 50 Hz
.•..'1
National
l'" Semiconductor
Th, Sight a Sound of InformiltJon
Although the EIA 770.2 specification refers to both 480i and 480p as SDTV, 480p is more
commonly referred to as Enhanced Definition TV (EDTV) to distinguish it from its less superior,
interlaced counterpart. In progressive formats, all the scan lines are scanned in one field/frame,
which yields a higher vertical resolution picture per field and reduces visibility of scan lines and
flicker. Therefore, 480p and 576p have the same total resolution as 480i and 576i; however, the
scan rate is twice as fast, resulting in better picture quality and less viewer fatigue. Progressive
scanning is also used in computer monitor displays, but typically at higher resolutions and
frame/refresh rates. This results in better looking static images, such as text and graphics.
High-Definition (HDTV)
Formats and Timing
720p (Progressive)
1280 x 720 active video resolution, "widescreen format" 16:9 (HV) aspect
ratio
V refresh rate: 59.94 Hz
Tri-Ievel sync
1080i at 59.94 Hz* (Interlaced)
1920 x 1080 active video resolution (1920 x 540 active/field),
16:9 aspect ratio
V refresh rate (frame rate): 59.94 Hz (29.97 Hz field rate)
Tri-Ievel sync
'Other refresh rates like 24, 25, 30 Hz, etc. See SMPTE 274M specs.
~Nattonal
[:;9 Semiconductor
Th,Sight.tSOllndoflnfotm.tJon
The U.S. specification for HDTV includes two major HDTV formats: nop is progressive and
I080i is interlaced. These formats have much higher resolution than SDTV and EDTV and come
close to some computer display resolutions. Both nop and I080i have a 16:9 aspect ratio, which
is the ratio of active horizontal-to-vertical resolution, which closely resembles the widescreen
format of cinema. Standard TV formats are closer to a 4:3 aspect ratio.
Another difference between HDTV signals are the handling of its synchronization, or sync
signals, which defines the video format's timing parameters. HDTV signaling uses "tri-Ievel
sync," as opposed to "bi-Ievel" or standard sync found in SDIEDTV signaling. Tri-Ievel sync has
faster rise times because of the increased video timing and high bandwidth of RD, which results
in more accurate timing edges and better jitter performance. These factors are important to meet
the stringent requirements necessary for HDTV sync separation, as we will see later.
Analog Broadcast TV
Standards Worldwide
~National
(ill'Semiconductor
Th,Sight&Soundoflflform,tiOll
NTSC is mainly used in the Americas, Japan, and South Korea.

PAL spans many countries in Europe, Asia, and Africa.
SECAM was developed by French engineers, and is used primarily in France, the Middle East,
Russia, and Africa.
Example: "HD Ready" TV Set
Analog Audio
Broadcast TV, Decoder &
RF Source(s) Amplifiers
Display Display
Electronics e.g., CRT, LCD,
(Display DLP. LCOS.
Dependent) Plasma
The tuner extracts one TV channel at a time from many. then downconverts and
demodulates the signal to "baseband"
The video (or "color") converter separates the colors from the "composite video"
(CVBS) signal and into a "component video" (YPSPR or YCSCR) signal
The deinterlacer and scalar converts the video format to match it to the display
type and applies color space conversion (CSC) from YPSPR to RGB.
The display electronics converts the RGB signal to match that of the display type.
e.g. analog for CRT. LVDS for LCD panel
.•..'1
l'" National
Semiconductor
"'- Sight" Sound of Infomr.tJon
This block diagram demonstrates the various levels of baseband video after the
tuner/demodulator stage. Several stages of video conversion or decoding are necessary before
the video can actually be displayed on-screen. This is a generic example and can vary between
display types, such as CRT, LCD, etc.
Analog Video Interfaces
• Composite Video (CVBS)

- Most widely used interface
• S-Video (Y/C)
• Component Video (YPBPR)
- Found in most "HD ready" TVs
• PC/Graphics (RGB)
RGBHV - 5-channels
RGB~ -4-ch ••
y p, p,
: RGBHV, RGBS
RGsB - 3-ch
~-:'~::,.
A.!JNational
Ii" Semiconductor
1M Sight" Sound oIlnform.tion
Composite, S-video, and component are the most popular video interfaces for consumer video
equipment.
RGB is mostly used for PC/graphic interfaces and comes in three variations, each of which
handles sync signals differently. Above, the signals underlined are the ones that carry the sync
information.
CVBS: Composite Video
· eves combines the luma (brightness), chroma (color),

blanking and sync information into one highly encoded
analog signal
• Includes NTSC, PAL, and SECAM used in analog
broadcast TV transmissions
• Has lowest quality due to bandwidth reduction and artifact
generation in decoding process
• Sync information is embedded in the CVBS signal as a
"composite sync," which combines H and V Sync together
• CVBS acronyms: "Color, Video, Blank, and Sync" or
"Composite Video Baseband Signal"
~National
P Semiconductor
Th. Sight & SOUild of IrJform,bon
Composite video is the most common analog video signal used in consumer video and broadcast
TV. Composite video has been used in analog broadcast TV transmissions since the 1950's
(NTSC) due to its low bandwidth and backward-compatibility with black-and-white TV sets.
Now, digital TV signals make much better use of the broadcast spectrum. Analog TV is now
slowly being replaced due to its inefficient use of the RF spectrum, inferior picture quality, and
as more digital, high-definition content is produced. With analog broadcast TV going out of
favor, composite video will most likely remain for non-broadcast video applications, such as
low-end consumer video.
Implementation of NTSC Color
Block Diagram
• NTSC system (and PAL) was devised to allow chroma information to
be added to the luma signal in a manner transparent to monochrome
TV for backward compatibility
• Basic parameters of the signal (carrier frequencies, bandwidths,
modulation format, etc.) had to remain unchanged
NTSC
Composite
/
Pb and Pr band-
limited by LPFs prior Sync, Setup,
to modulation Burst and Blanking
Generators
d National
(il'Semiconductor
1M SIght a Sound of Inform.rJOn
In the PC/graphics space, RGB signals are used to make color. In the TV/video space, a different
color space was developed to accommodate the need for backward compatibility with
monochrome TV. A color or matrix encoder converts between the RGB and YPBPR color spaces.
The difference signals (PB, PIJ are band-limited using low-pass filters and used to modulate the
amplitude and phase of the 3.58 MHz color subcarrier. This system takes advantage of the
spectral nature of the luminance signal and the fact that the eye is less sensitive to color changes
than luminance changes.
Sync, setup, burst, and blanking generators are added to the combined Y/C signal to produce the
NTSC composite signal.
NTSC Video Signal
(EIA 75% Color Bar Signal)
100
80
75
Amplitude ex Saturation
60 (amount of color)
Phase difference ex Hue

40 (color tint)
Color Burst
Phase;Qo
20
Black
IRE
Level
0 Blank
r Level
H Sync
Pulse
-20
- 40
--
9 cycles
Backporch
H Blank Interval
~National
P Semiconductor
Tll,SightclSQundQflnform,rion
This is a horizontal scan line of color bars. Color information is added on top of the luminance
signal by the subcarrier waveform, with the color (or tint) identified by the phase difference
between the subcarrier and the color-burst reference phase, and the amount of color (or
saturation) conveyed by the amplitude of the subcarrier with respect to the color burst.
The horizontal blanking portion contains the horizontal synchronizing pulse (H sync pulse) as
well as the color reference (color burst) located just after the rising edge of the sync pulse (called
the back porch). The horizontal blanking portion of the signal is positioned in time such that it is
not visible on a correctly adjusted display.
NTSC Video Pattern
(EIA 75% Color Bar Signal)
d National
(III" Semiconductor
The SIght & Soufldoflnf~tJon
This shows the resulting video pattern from the 75% color bar signal. In order from left to
right, the colors are white, yellow, cyan, green, magenta, red, blue, and black. This sequence
runs through all seven possible combinations that use at least one of the three basic color
components of green, red, and blue.
Because green contributes the largest share of luminance, followed by red, then blue, this
sequence of bars thus appears on a waveform monitor in luminance mode as a downward
staircase from left to right.
Color bar patterns are commonly used to assist in the calibration of analog NTSC equipment
in television network facilities.
.}
JExtracted
H Scan Line
of active video
~Nattonal
fiI" Semiconductor
Th,Sighr&SOUfldoflnfQfm,ftOfl
This shows an example of two NTSC fields that comprise one frame. Each field begins with
the vertical blanking interval (about 20 lines) before scanning the active video (viewable
image) area, denoted by vertical and horizontal arrows. Each horizontal scan line begins
with the horizontal sync and color burst signals before the video signal. The waveform
shown at the bottom shows an extracted horizontal scan line of active video.
YPSPR: Analog Component Video
• YCSCR is a family of color spaces used to represent digital component

video and is derived from the RGB color space
- Y is the brightness or luma component
- Cs and CR are the Chroma or color-difference components
• YPSPR is the analog component video form of digital YCSCR
• YCSCR widely used for video and image compression, like MPEG
• RGB signals can be converted to YPSPR signals with a circuit
implementation of the matrix equation:
- Y = KR R + KG G + Ks B
- Ps = 0.5 (B-Y)/(1-Ks)
- PR = 0.5 (R-Y)/(1-KR)
- KR• KG' Ks are luma coefficients and are video format dependent
• YCsCR-to-RGB conversion process by taking inverse matrix
l'"
~ National
Semiconductor
Tn. Sight" Sound of Infonnltion
In YPSPR, RGB is converted into brightness or luma signal (Y) and two color difference or
chroma signals (Ps and PJ. CIE tests noted that human vision has less spatial acuity for color
information than it does for brightness information. If RGB component video is re-coded as a
channel of brightness (Y) and two color difference channels (Ps and Ps), the color difference
data can be spatially reduced without the eye detecting that a change in color has taken place.
Digital YCSCR is used widely in video and image compression schemes, like MPEG, due to its
reduced bandwidth and storage requirements compared to three full-bandwidth channels of
RGB.
Sometimes prime marks (') are associated with YPSPR or RGB (i.e.: Y'PSPR or R'G'B'). The
prime marks refer to video signals that have gamma correction applied to correct for the non-
linearity of phosphor CRT displays. In video systems, gamma correction is applied in the
camera. Refer to the signal source to determine whether gamma correction is applied.
The YPSPR color space is produced by the linear addition and scaling of RGB, as shown in the
matrix equation above.
YPSPR: Analog Component Video
·SDTV Color Space: 480i/p (per EIA-770.2)

-KR= 0.299, ~= 0.587, Ks= 0.114
• HDTV Color Space: 720p/1080i (per EIA-770.3)

-KR = 0.2126, KG = 0.7152, Ks = 0.0722
• Example: 480p matrix equations

- Y = 0.299 R + 0.587 G + 0.114 B
-Ps = (B-Y)/1.772
-PR = (R-Y)/1.402
.•.'1
l'" Nation a I
Semiconductor
The Sight& SQun(JQflnformatiQn
Luma coefficients are shown for SDTV and HDTV analog component color spaces, with the
matrix equations shown for 480p.
YPSPR: Color Space Conversion
~ I GREE
":'~
n n
lOW. nLJnL..AI.YE
~...
"'.:.......I LJ LJ
•..'1 National
Ii" Semicollductor
Th.Sight&SouMoflnform,tHNI
Color is what is perceived by the human brain when the photoreceptors in the eyes are excited
with a visual sensation. These colors can be interpreted or defined by specifications or models
known as color spaces. Color is described using different color spaces, with each space
associated to different applications based on system requirements and needs. RGB is an additive
color system and its color space is defined by three components -red, green, and blue. It stems
from the concept that the human eye is most sensitive to red, green, and blue, and all other
colors are perceived as a combination of the three.
Color space conversion from the YPBPR color space to the RGB color space is shown here by
taking the inverse of the matrix equation from the previous slide. RGB is very common, being
used in virtually every computer system as well as video, etc. RGB is easy to implement, but
non-linear with visual perception, and it is device dependent. Many other color spaces can be
derived by applying linear functions ofRGB. These color spaces separate RGB into luminance
and chrominance information and are useful in compression applications (both digital and
analog). These spaces are device dependent, but are intended foruse under strictly defined
conditions within closed systems. For example, television has adopted the more complex YUV
color space in order to economize bandwidth for transmission andbroadcast of its video signals.
y y
Ref at Bi-Ievel sync Ref at
50% of tF-JOO on Yonly 50% oftR.]OO
•..
'1National
P Semiconductor
rM Sight a Sound of Infomlltion
Bi-Ievel sync is the standard sync signal method for all forms of standard-definition video.
Systems using bi-Ievel sync are typically negative edge-triggered. Bi-level sync, due to its
asymmetry, introduces a DC component into the video signal, which can sometimes be
problematic for sync separation.
Tri-level sync signal has faster rise times because of the increased bandwidth of RD, which
results in more accurate timing edges, improving jitter performance, and sync separation.
Symmetry of the tri-level sync signal eliminates the DC offset found in bi-level sync, which
makes sync processing easier and more robust against noise. Tri-level sync appears on all three
component signals.
The arrows indicate the sync threshold level and reference edge .
• Bi-level sync reference: 50% point on the negative-going edge .
• Tri-levels sync reference: 50% point on the positive-going edge of the tri-Ievel sync, or
a.k.a. positive-zero crossing.
RGB: PC/Graphics Video
• RGB color space represents color as red, green, and blue video
signals
• Very high bandwidth requirements limit its use to short-run video
transmission, like computer and system-level interfaces
• RGB conforms to the VESA standard for graphics, and SMPTE for
analog video interface in TV
• RGB video and sync signal interfaces:
- RGBHV: 5-ch, RGB and separate H and V Sync
• Most common use in PC/Graphics
- RGB~: 4-ch, RGB and separate C Sync (TTL)
- RGsB: 3-ch, RGB with C Sync on Green (SOG)
• Not used very often
• Preferred implementation for TV per SMPTE 253M
~National
[ilf'Semiconductor
Th, Sighr & Sound aflnfrHmltH)n
RGB primary components are the native forms of analog video from a picture source, such as
camera or telecine, or a synthetic RGB video from a PC or graphics generator, or a test signal
generator. RGB's high-bandwidth requirement limits its use to local video transmission, like
PC/graphics and other short-run, system-level video interfaces.
RGBHV has a total of five signals, red, green, blue, H Sync, and V Sync.
RGBS combines H and V sync into a single "composite sync" signal (S), resulting in a total of
four signals.
RGsB or sync on green embeds the composite sync signal onto the green video signal for a total
of three signals.
LMH1251
YPsPR-to-RGBVideo Converter
with Integrated 2:1 Video Switch
• First monolithic analog YPSPR video converter

• Precise YPBPR-to-RGBHV conversion for HOTV and SOTV
• Integrated 2:1 Video Switch
- YPBPR Input Path
• Converts nop, 1080i, 1080p (HO) and
480i, 480p, 576i, 576p (SO)
• Bi-Ievel and tri-Ievel sync plus Macrovision-compatible
- RGBHV Input Path
• Buffers RGBHV inputs up to UXGA (1600 x 1200 at 75 Hz)
• Auto format detection with SO/HO output flag
• Power-save mode
• 24-pin TSSOP package, small footprint, low component count
.••.
'1 National
Ii" Semiconductor
Th~Sjghr&SOllmJQflnforrmltJon
LMH1251 Key Specs
• Wideband Video Amplifiers

- YPBPR Signal Path
• 70 MHz Large-signal (700 mVp_p) bandwidth
• Superior chroma accuracy: Less than 2.5%
differential gain and 1.50 differential phase
- RGB Signal Path
• 400 MHz Large-signal (700 mV p_p) bandwidth
• RGB output tR/tF = 1.55 ns for input tR/tF = 1.5 ns
• 5V supply operation
- Typ. operating lee = 70 mA, 480p YPBPR input
l'"
~ National
Semiconductor
Th,S,ght&Soundof'nfomllJtJon
Based on 1 Vp•p video inputs from a 7Sn analog video source.

The video conversion process is performed by a color-space conversion matrix using analog
technology, rather than multiple stages of digital implementations. The result is a cleaner, crisper
video image.
LMH1251 Connection Diagram
Pin 22 can be
used as an SOtHO
Output Flag when
AUTOIMANUAL in Auto Format
DETECT SELECT
Detect Mode
SOIHOSElEC
~ National
P Semiconductor
Th. Sight & Soundoflnform,rkm
The internal sync separator strips off the sync component from the YPSPR input signal and
generates the H and V sync signals, which are positive polarity logic outputs.
LMH1251 Applications
• Component Video-to-RGB Converter Module

- Higher BW than with discrete solutions and superior
color conversion accuracy
- Smaller footprint, lower power than discrete op amps,
which may need dual supplies
• Analog Front End for LCD/CRT Monitors
- Simple circuit implementation compared to complex,
multi-stage digital ASIC/FPGAs (costly, needs active
filters, A/D-D/A degrades quality)
- Easy to apply into existing RGB path in monitors
.:JNational
P Semiconductor
The Si~ht" Sound of I"form,tion
The LMH1251 is the first and only monolithic fully-analog YPBPR-to-RGB converter available.
Discrete solutions using up to 20 components require design expertise, use more board space,
consume more power and have inferior decoding quality. Digital solutions and FPGAs are more
expensive and typically offer more features than may be needed in a system. Compared to these
alternatives, the analog design of the LMH1251 reduces undesired artifacts and provides a
smaller form factor for easy integration.
LMH1251 Applications
Component Video-to-RGB Converter

Module with VGA Cable Driver
~ National
(iI" Semiconductor
Th8Sight&Soundoflnform8fion
~ National
P Semiconductor
Th.Sight4SoUfldoflfl!orm,tion
The LMH1251 evaluation boards, along with sample parts, are available for order on National's
website.
.•..'1 National
P Semiconductor
Video Sync Separation

What is Sync and Why is it Important?
• Sync is critical to establish proper timing of RGB video

content to its proper pixel locations in the image to generate
a stable image on the display
• Without sync, image display isn't possible
• A display requires both horizontal (H) and vertical (V) sync:
- H Sync regulates the scan line rate within a frame (or field).
- V Sync defines the refresh rate for every frame (or field) of video.
• Different forms of sync signals:
i::r- YPBPR, Y/C, CVBS, RGsB: Composite sync embedded in the
Y component, composite video, or G component in RGsB.
- RGBHV: H and V carried as separate TTL sync signals
- RGBS: H and V combined into a single TTL composite sync (S)
d National
(ilt'Semiconductor
The S,ghr a Sound of Informerron
If two or more video sources are not in sync, a monitor will show rolling, tearing, or incorrect
colors in the picture whenever a transition is made between sources.
Simplified Sync Illustration
HorIlonUlI
------ Rowee
.•..'1 National
P Semiconductor
Th.Sight&Soundoflnformtltion
Critical Sync Output Characteristics
• Negative-going/falling edge = critical sync edge
- Most display systems trigger on negative-going sync
edge
• Jitter = noise in the time domain
- Very low jitter is required to generate clean SD/HD
clocks using H sync as an input reference to PLL
• Sync timing relative to the video (low propagation delay)
-If needed, low prop. delay permits additional circuitry to
further clean-up jitter, which can add prop. delay
• Peak-to-peak sync signal amplitude
- CMOS or TTL level outputs
• Slew rate
- Sync outputs with high slew rate necessary for low jitter
~Nattonal
P Semiconductor
Th,$ighrclSoufldoflnform'tlOfI
LMH1981 Key Features
• Sync separation for all standard analog video signals
- Formats: nop, 1080i (HDTV), 1080p, 480i/p, 576i/p
(SD/EDTV),
NTSC,PAL,SECAM,RGsB
- Signal Interfaces: YPBPR (Component), Y/C (S-Video),
CVBS (Composite), VGA (PC Graphics)
• Tri-Ievel and bi-Ievel sync compatible, Macrovision-compatible
• Precise 50% sync slicing ensures accurate sync separation
• Superior H sync jitter performance
• Automatic format detection and switching
- No external programming via microcontroller, no power cycling
required for video format switching
• Video format output (pin 9) - Binary coded line count o/p
•..'1 Nati on a I
~ Semiconductor
Th6Siqht&Soundoflnrormation
The LMHl98l is a multi-format sync separator with the industry's best jitter performance. It
allows video designers to accurately and precisely extract horizontal and vertical sync signals
without extra filtering and jitter-cleaning stages.
The LMHl98l is compatible with Macrovision video copy protection, in which pseudo sync
pulses are embedded in the vertical blanking interval of the video signal - either recorded onto
VHS tapes or created during playback by a chip on the DVD player. Other sync separators may
mistake Macrovision pseudo sync pulses as true sync pulses, and react by outputting invalid sync
signals.
Precise 50% sync slicing ensures accurate sync separation under varying input amplitude, offset,
and noise conditions.
LMH1981 Key Specs
• 3.3V to 5V supply operation

- 3.3V critical to match FPGA input voltage range
• 0.5 to 2 Vp_p video input range
-Important for double or no 750 input termination conditions
• Typical H sync output jitter on negative-going edge
reference
- < 500 pSp_pfor HDTV (tri-Ievel sync)
- < 1000 pSp_pfor EDTV, RGsB
- < 1500 pSp_pfor SDTV, CVBS
• Typical H sync prop. delay < 50 ns
• V Sync output pulse width = 3H
• 14-pin TSSOP package
l'"
~ National
Semiconductor
Th,Sight,JSrxmduiltdotm.tIon
LMH1981
Pinout and Test Circuit
14-pin TSSOP
Rs
14
~ OEOUT
Odd/Even
Field Output
R,
2 13 Backporcl1
GND BPOUT
Clamp Output
C4
4.7 jJF R,
12 Composite
Vcc Vc<, CSOUT
Sync Output
11
VIN LMH1981 V= Vcc
C3
0.1 J.lF
5 10
GND GND
":"
Rs
9 Video Format
V= VFOUT
Output
R, Rs
Vertical Sync
HSOUT VSOUT
Output
t!JNattonalSemiconductor
TMSightAiSoundoflnform'tKHI
The LMH 1981 has three Vcc and three GND pins, one RElIT pin, and six timing output pins.
Very minimal BOM list: supply bypass caps, AC coupling cap to input, REXT 0.1% precision,
series resistors on outputs for current-limiting during short-circuit conditions.
LMH1981 Verlicallnterval
NTSC - Odd Field
I
I I
BPOUTrtl] :
:------J
H Interval
:
I
VSOUT i ~
I I I
I , I
~_I
I I !
OEOUT I OddField :
I
~ National
P Semiconductor
"" Sight a Sound of Inform'tJon
NTSC employs a total of 525 horizontal lines per frame, with 2 fields per frame of 262.5 lines
each. The odd field begins with a full line of video and ends with a halfline of video.
VIN: NTSC vertical interval odd field shown in the top waveform with equalization and
serration pulses over the first 9 H lines.
Vertical equalization and serration pulses are used to indicate the beginning of a new field for
proper sync separation.
All outputs are in CMOS logic with rail-to-rail output range.
CSOUT: Composite sync output reproduces the input sync pulses with active video portion
stripped off.
HSOUT: Horizontal sync output timing with the leading, falling-edge used as the reference edge.
BPOUT: Burst/back porch clamp output, triggered from the input sync rising edge, can be used
as a timing signal for burst signal stripping and black level clamping (DC restoration).
VSOUT: Vertical sync output timing with V Sync pulse width of 3H's, with leading edge
aligned with the first vertical serration pulse.
OEOUT: Odd/even field is high (or logic 1) for odd fields, edge aligned with V Sync leading
edge.
LMH1981 Vertical Interval
NTSC Even Field
, ,
~ Start of Field 2 :
:. 3H
----~-- 3H
-------3H_____+:
,, ,,
,,
,,
,
l::
I
T VSOUT = 3H --H
I
,, :
I I
I Even Field
,
•..'1 National
(II" Semiconductor
The Sighf .s Sound of Inform.bon
The NTSC even field begins with a halfline of video and ends with a full line.
VIN: NTSC vertical interval even field shown.
OEOUT: Odd/even field is low (or logic 0) for even fields.
LMH1981 Horizontal Interval
Bi-Level Sync
Color burst in • NTSC/PALISECAM (CVBS),

CVBS only
480i/p, 576i/p, RGsB
1 • 50% sync slicing on falling-edge

(Input reference)
• H Sync jitter < 1000 pSp_pon
negative-going reference edge for
-300 mV : Sync Tip Level ! EDTV/RGsB
CSOUT : i - H Sync positive-going edge
",-=fJ- !l'""::::r'''''-
H Sync
reference~
edge
I
:
,
: :
"
: :
I I
:
1
:
not useable as the reference
edge!
• BPOUT width encompasses
CVBS color burst envelope
T:_~lJ
1+----+1 "
I+-T....,.".,-+l
,
- Fixed width for SD/EDTV,
RGsB
~ National
P Semiconductor
Th,Srghf&Soundoflnform'tJOn
Color burst is present only in composite video signals.

The H sync and C sync negative-going edges are triggered from the 50% level of the input sync
negative edge (reference), each with prop delays.
The H sync negative-going edge has very low jitter and must be used as the reference edge for
PLL inputs or display's synchronization systems.
Due to the narrow equalization pulses during the NTSC vertical interval period, the H sync
output positive-going edges are "reconstructed" by the rcs internal timing. Therefore, the H sync
rising edge must not be used as the reference edge.
The back porch output is derived from the input sync trailing edge with a prop delay.
1080i - Field 1 (SMPTE 274)
:.- Start of Field 1
1
I+- H -.. -+I ~ Vertical Sync Serration
VIN
Line
CSOUT
# I 1125
+TD
: ::
HSOUT
1r1rh ,,
,
,,
1
:::
'I 1
BPOUT
~ ;J:1 :
1
H:lnterval
VSOUT
OEOUT
.:JNattonal
l'" Semiconductor
Th.Sight&SOlJlldoffnfonn,bon
I080i employs a total of 1125 horizontal lines per frame, with 2 fields per frame of 562.5 lines
each.
CSOUT: Composite sync output reproduces the input sync pulses below the video blanking level
(0 mY).
OEOUT: Odd/even field is logic high (or logic 1) for field 1.
1080i - Field 2 (SMPTE 274)
VIN
Line# I 563 I 563 I 5M I 565 I 566 I

TTuul I
I
I
I
VSOUT ~
I
T"3OUT = 3H ------l
1
I
OEOUT F_ie_ld_2 _
I
~Nattonal
P Semiconductor
Th,Slght&Sound"ffnfo(m,tton
Horizontal Interval
HDTV Tri-Level Sync
Input
• 720p, 10aOi
reference
~Inpul~ \
• 50% sync slicing at tri-Ievel
O.5V••.••
to2V,..
1V...,.(typ.)
Tri~
•..•••u
50"1.
•..•.
n_ .s"" zero crossing (Input
V Cmulng '>::
: B',""", "'''' reference)
L'~': 50% I
:;:iI _s"" • H Sync jitter < 500 pSp_pon
! ! negative-going edge
CSOUT ----n.
!I-i~-------
-300 mV
reference for HDTV

-ICJ i • CSOUT delay from input
.id:~:;"" leading-edge
HSOU: s-yn-c -~_-.:::;'~!L11-------- . HSOUT delay from tri-Ievel
reference- :0 .
edge
.•••.•
--:
zero crossing
'f+---oII
T_! tJ . SPOUT delay from input

trailing-edge
: I+--+i
T_
~ National
l'" Semiconductor
The SIght a Sound 01 Informet1oll
The timing diagram shows the HD tri-level sync that precedes the active video signaL
The C sync negative-going, leading edge is triggered from the 50% level of the input sync's
negative-going, leading edge with a prop delay.
The H sync negative-going, leading edge has very low jitter and must be used as the reference
edge for PLL inputs or display's synchronization systems.
The H sync leading edge is triggered from the input sync's tri-level zero-crossing (reference).
The back porch output is derived from the input sync's negative-going, trailing edge with a prop
delay.
H Sync Accumulated Jitter Test
Measurement Setup
VM5000 Oscilloscope Setup

o Triggered on 50% reference edge of HSOUT,
with horizontal delay -20 ms to monitor

accumulated jitter on HSOUT leading edge.
o CH1 has a Tek P6245 active probe at the
LMH1981 HSOUT test point on the PCB.

o 4 sec. display persistence
o Pk-Pk jitter obtained by visual inspection,
zoomed into HSOUT falling edge.

-•••
LM1981 Test Board Setup • •:0.•
o Vcc = 5V •
o Video input from Tek TG700 Video Generator
• •
• •
-
• •
• .. .. -
~.
.:JNattonal
(iIF Semiconductor
Th.SiQhtolSoundoflnformlltion
LMH1981 vs competitor at NTSC
H Sync Output Typical Jitter
LMH1981 Competitor
l'"
~Nattonal
Semiconductor
Th,S,ghr&Soundof'nfo(mlllion
This slide shows the LMH1981 versus the closest competitor for jitter on H sync negative-going,
reference edge for NTSC input.
Low jitter is critical for generating SDIHD video reference clocks for AID conversion and SDI
serializers.
LMH1981 vs Competitor at 1080i
H Sync Output Typical Jitter
LMH1981 Competitor
dNational
()" Semiconductor
TIl. Sight" Sound of Inform,tion
Here is the LMH1981 versus its closest competitor for jitter on H sync negative-going, reference
edge for 1080i input.
Video Format Output Feature Example:
480p (525 total lines)
• Counts the # of H sync pulses per field and automatically doubles it
(2 fields/frame) to approximate the total vertical scan line count
• Total vertical line count is output to VFOUT (pin 9) as an 11-bit binary
coded bitstream, clocked out on the 11 consecutive falling edges of
HSOUT after each VSOUT trailing edge
• Current solutions rely on FPGA resources to perform line count processing
VJNLL
line # 7 I 8...
CSOUT ~
HSOUTI r-1 r\
(Clock) U U ,,
VSOUT qp i
~,
,,
o I 0 r+-end
.•..'1 National
l'" Semiconductor
TIl.SightclSoundoflnlorm,tion
II-bit binary data can be loaded into a serial-to-parallel shift registers and used by the FPGA for
video format identification, enabling dynamic adjustment of video system parameters (like color
space or scalar conversion).
Broadcast Video Applications
- Genlock - generator lock to house timing reference
• Video camera, video tape recorder (VTR), time base
controller (TBC), production switcher, frame
synchronizer
-SD/HD clock and sync pulse generation
• Master/slave sync pulse generators (SPG) and clocks
- Video capture or digitization
• AID video converter, video compression (MPEG)
clocks
- Sync stripping - remove 300 mV sync component
• Strip off sync to increase AID converter precision by
30%
-PIP (picture in picture), text/graphics overlay timing
~ National
~ Semiconductor
Th.Sight&Soundoflnfomllfion
Synchronization is one of the most fundamental and critical procedures in a video facility. Every
device in a system must be synchronized in order to successfully create, transmit, and recover
pictures and audio information. The complexities of analog and digital multi-standard and multi-
format environments require the flexibility to achieve and maintain synchronization in facilities
that operate in a mix of video formats. As the broadcast TV industry begins to incorporate more
high-definition programming, there will be a need to bridge the gap between analog and digital
TV formats. The LMH1981 fills that gap by supporting all standard analog SDTV and HDTV
formats.
Sync stripping of -300 mV sync component increases the ADe's dynamic range and hence ADe
precision, by 30%.
LMH1981 Application:
Ana/og-to-SDV Video Converter
• LMH1981 supports the following functions:

- Sync separation for any standard analog video input
- H sync becomes a reference clock input to FPGA PLL
- FPGA generates SD (27 MHz) or HD (74.25 MHz) video clocks
for AID converter and SDV serializer
CVBSfYIGs
Analog Video
Inpul
~ National
P Semiconductor
T1I.$ight4Socmdufl"fomI,fJOfI
Since the LMH1981 jitter is optimized for the H sync negative-going edge and most FPGA PLL
inputs are rising-edge triggered systems, the H sync output must be inverted by the FPGA before
the PLL input.
Example: Analog Video Studio
System Using TG700
~Nattonal
p Semiconductor
Th. Sighr& Sound of Inform,tion
A TV reference signal generator, such as the TG700, provides a "house reference" signal
(composite black burst signal) to synchronize all analog broadcast video equipment, including
cameras, character generators, Video Tape Recorders (VTR), and production switcher. Each piece
of equipment needs to separate the syncs from the black burst signal, in order to extract the Hand
V sync and other timing information for proper sync. The LMH 1981 can be used in various
analog broadcast video equipment.
Multi-format Hybrid Facility
Newer multi-format, multi-standard hybrid video facilities have separate analog and digital video
studio "islands." Video conversion is necessary before video from one island is routed to another
island. For example, in order for analog video to be routed to the digital island, it must be
digitized. The LMHl98l H sync output can be used to generate SD/HD reference clocks used in
the video digitization process (A-D conversion). The LMHl98l also can be used in master sync
pulse generators (SPG) and master clock systems, which are used to synchronize various
broadcast equipment.
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~,f"\IN WM1~

Section 2: Stability Issues

Section 3: Open-Loop, Closed-Loop, and Programmable Buffers

Section 5: Amplifier-to-ADC Interfaces

Section 7: Noise and Offset in Data Converters

Section 8: Managing Jitter

Section 9: Data Converter Products and Applications

Section 10: Signal Translations, LVDS, LVPECL, and CML

Section 11: Using MUX-Buffers

Section 12: Buffering and Cable Driving Solutions

Section 15: High-Fidelity Audio Power Amplifiers

Composite video, S video, Component video, PC/Graphics

Section 17: Video Sync Separation

Broadcast video applications, Analog-to-SDV converter,

Sensors and Sensor

Property SensorlTransducer Output

1- - TC - - .RTD at 1 mA -- RTD at 0.1 mA -+-- LM3s1

--- --- ---

Amplifier With an ADC full scale input range = 2.048V

• Accurately scale the sensor's signal

• Precision sensor interface requirements

• Definition of offset voltage

• Definition of offset voltage drift

• TeVos: Variation of one part over temperature

eid =~ + Vos + (Is )(Rs +)+ (Is -)(Rs _)+

• Major input referred error sources of an op amp

• Precision requires error terms to be small

• AVOL and CMRR are frequency dependent

V COMMON MODE = (V N1 + V N2 )/2

• Common contact temperature sensors

(Plus 2.5V CMV)

Chromel - Alumel thermocouple

Temperature range to measure

Thermocouple output - 0.97 mV

• Expand the circuit to see what

• Replace sources by their equivalent

• Apply circuit analysis techniques

Cases 1 through 7 are variations of "1/F" function

log Axis Frequency Total Phase Total Phase

Case # Condition Comment

Let's put to use what we have already discussed in a real application.

10k 100k 1M 10M

100 MHz pole).

where: R.., ~ (RI)(RF)

F=( l+sCRc )(~)()«.) f,= 1

2. = (1 + RI') ( 1 + sC(R. + R,. + R •• ) )

10k 100k 1M 10M

10k 100k 1M 10M

• Solve for the component values that allow

Practical Techniques to Avoid

Many designers overlook a powerful way to maintain stability in low-frequency applications

In some applications, it is essential to drive a capacitive load without sacrificing bandwidth. In

CF= [RF + 2RIN] CLRour

CL (pF) Rs (In) CF (pF) Phase Margin (0)

250 60 4.5 39.8

300 60 5.4 49.5

Open-Loop, Closed-Loop, and

• To minimize the influence on a signal source

• To boost the drive capability of an op amp or other

• To distribute stable, clean signals through

Fast slew rate/wide bandwidth

High output current drive

Slew Rate 1800 4580 3100 3300 400 3000 18 V/~s

Bandwidth, 3 dB 110 1750 680 750 110 650 31 MHz