a) Write a program and simulate the output waveform of 4:1 Multiplexer using Verilog HDL

b) Design a program code and simulate the output waveform of D-flip flop along with RTL and Technological
view

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a) Write a program and simulate the output waveform of Multiplier using Verilog HDL

b) Design a program code and simulate the output waveform of D-flip flop with reset along with RTL and
Technological view.

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a) Write a program and simulate the output waveform of 8-bit Adder using Verilog HDL

b) Design a Verilog HDL code and simulate the output waveform of Full adder with reset along with RTL and
Technological view.

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a) Write a program and simulate the output waveform of SISO shift registers using Verilog HDL

b) Design a Verilog HDL code and simulate the output waveform of JK flip flop along with RTL and
Technological view.

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a) Write a program and simulate the output waveform of PISO Shift Registers using Verilog HDL

b) Design a Verilog HDL code and simulate the output waveform of Half adders along with RTL and
Technological view.

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a) Write a program and simulate the output waveform of PIPO Shift Registers using Verilog HDL

b) Design a Verilog HDL code and simulate the output waveform of 8:3 priority encoders.

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a) Write a program and simulate the output waveform of Ring counter using Verilog HDL

b) Design a Verilog HDL code and simulate the output waveform of D-flip flop with enable along with RTL and
Technological view.

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a) Write a program and simulate the output waveform of 4-bit Ripple counter using Verilog HDL

b) Design a Verilog HDL code and simulate the output waveform of 4-bit ALU along with RTL and
Technological view.
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Design a Layout, Parasitic Extraction and Simulation of CMOS inverter using DSCH and Microwind

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Write a program to perform Schematic Entry and Spice Simulation Of CMOS NOT Gate (inverter)

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