Report Pstage1

IoT Based Smart Water supply management , monitoring Quality and consumption of water for
Smart City
A
Project Stage-I Report
On
“IoT Based Smart Water supply management , monitoring

Quality and consumption of water for Smart City”
Submitted to
SAVITRIBAI PHULE PUNE UNIVERSITY, PUNE
In the partial fulfillment of the requirement for the degree of
Master of Engineering
in
Electronics & Telecommunication
(VLSI & Embedded Systems)
Submitted by,
MRS. SAPANA D. PAWAR
Under the Guidance of
PROF. SHEIKH S. A
Department of Electronics & Telecommunication

Pravara Rural Engineering College, Loni, 413736
Tal−Rahata, Dist− Ahmednagar, Maharashtra (INDIA)
IoT Based Smart Water supply management , monitoring Quality and consumption of water for
Smart City
Year 2018-2019
Pravara Rural Education Society’s
PRAVARA RURAL ENGINEERING COLLEGE,LONI

Affiliated to Savitribai Phule Pune University, Pune
Certificate
This is to certify that a Project Stage –I report entitled “IoT Based Smart
Water supply management , monitoring Quality and consumption of
water for Smart City”submitted byMrs. Sapana D. Pawae to Savitribai Phule
Pune University, Pune for the partial fulfillment of degree of Master of
Engineering in Electronics &Telecommunication (VLSI & Embedded System) is a
record of bonafide work carried out by him/her under my supervision and guidance
during the academic year 2018-2019.
Prof.Shaikh S.A Prof. Turkane S.S Prof. Turkane S. M

(Guide) (M.E. Co-ordinator) (Head of Dept.)
Dr. Y. R. Kharde
External Examiner (Principal)
i
IoT Based Smart Water supply management , monitoring Quality and
consumption of water for Smart City
STATEMENT OF ORIGINALITY DECLARATION

I hereby declare that I have formed, completed and written the project entitled
“IoT Based Smart Water supply management , monitoring Quality and
consumption of water for Smart City” It has not previously submitted for the
basis of the award of any degree or diploma or any similar title of this for any other
examining University.
Place:- PREC, Loni Name Of Student
Date:- Mrs. Sapana D. Pawar
PREC, M.E. E & TC Page ii

ACKNOWLEDGEMENTS
Every orientation work has imprint of many people and this work is no
different. This work gives me an opportunity to express deep gratitude for the
same. While preparing my project, I received endless help from number of
people.This report would be incomplete if I don’t convey my sincere thanks to all
those who were involved.
First and foremost I would like to thank my respected Guide. Prof.Shaikh

S.A, (Department of Electronics & Telecommunication Engineering) for their
continuous inspiration and moral support throughout this tedious task.
I am also thankful to HOD Prof. Turkane S. M , (Department of

Electronics & Telecommunication Engineering) and M.E Coordinator Prof S. S.
Turkane for giving me an opportunity to present this work and his indispensable
support.
Last but not least I am very much thankful to our Principal Dr.Y.R.Kharde
and the College for cooperation and support in the entire course. I will keep my
improvement curve on the rise and thereby enhance the reputation of my College.
Finally, I wish to thanks my friends and my family for being supportive of

me, without whom this project would not have seen the light of day.
Place: Loni Mrs. Sapana D. Pawar
PREC, M.E. E & TC Page iii

ABSTRACT
In urban areas the water supply to residence and commercial establishments are provided at a
fixed flow rate. There are incidents of excess water drawn by certain customers/users i.e water
will be released unofficially which is considered as water theft. In this project it is proposed to
develop an embedded based remote water monitoring and prevention system by taking the data
of water supply at the consumer/user end.
The overall objective of a distribution system is to deliver wholesome water to the consumer at
particular area and in sufficient quantity and achieve continuity and maximum coverage at
affordable cost. To attain this objective the organization has to evolve operating procedures to
ensure that the system can be operated satisfactorily, function efficiently and continuously as far
as possible at lowest cost.
Here we are using ARDUINO MEGA as our controller and also few sensors are arranged to
detect the presence of water in that particular pipeline. As LEVEL sensors are used to detect the
water level. After that here we used level sensor to detect an level of water in tank if tank is
empty that time through relay solenoid valve will ON. Buzzer will beep.
All the information will be displayed on LCD. Ph sensor for detecting dirty and clean water.
All data will be updated over web server using IOT module(ESP8266)
This project uses regulated 5V, 500mA power supply. 7805 three terminal voltage regulator is
used for voltage regulation. Bridge type full wave rectifier is used to rectify the ac out put of
secondary of 230/12V step down transformer.
PREC, M.E. E & TC Page iv

CONTENTS
SR. NO. TITLE PAGE NO.
CERTIFICATE i
DECLARATION ii
ACKNOWLEDGE iii
ABSTRACT iv
CONTENTS v
LIST OF FIGURES vii
LIST OF TABLES viii

1. INTRODUCTION 1
1.1 Motivation 1
1.2 Gap Identification 6
1.3 Problem Statement 8
1.4 Objective 8
2. LITERATURE SURVEY 9
3. THEORETICAL DETAILS 16
3.1 Device Technologies 16
3.1.1 CMOS 16
3.1.2 FinFET 17
3.1.3 TFET 18
3.2 Interconnect Technologies 23
3.2.1 Copper 23
3.2.2 Carbon Nanotube 26
3.2.3 Graphene Nanoribbons 30
4. SCHEME OF IMPLEMENTATION 33
4.1 Parameters to be Evaluate 33
4.2 Driver Interconnect Load system 34
PREC, M.E. E & TC Page v

4.3 Equivalent RLC model of Interconnects 35

4.3.1 Copper 35
4.3.2 Carbon Nanotube 36
4.3.3 Graphene Nanoribbons 41
5. SIMULATION SOFTWARE 45
6. WORKFLOW 46
7. SUMMARY 47
8. BIBLIOGRAPHY 48
PREC, M.E. E & TC Page vi

LIST OF FIGURES
1.1 (a) Abstract view of FPGA, (b) Basic logic element (BLE). 3
1.2 MPU/ASIC Half Pitch and Gate Length Trends-ITRS 2013 Edition. 5
3.1 Cross section of CMOS Device. 16
3.2 Structure of DG FinFET. 17
3.3 Structure of TFET. 19
3.4 Energy band diagram of On and Off state of TFET. 19
3.5 Dopingless PNPN TFET structure. 21
3.6 Transfer characteristics of the dopingless TFET compared with that
22
of the dopingless PNPN TFET.
3.7 Variation of line resistivities of aluminum and copper (a) with line
24
width and (b) with line thickness.
3.8 Comparative analysis between the thermal conductivity of
24
aluminium and copper as a function of temperature.
3.9 Single walled and multi walled CNT. 28
3.10 CNT types a) armchair b) zig-zag. 28
3.11 (a) Structure of Graphene Nanoribbon (b) armchair, (c) zig-zag. 30
3.12 Single-layer GNR and Multilayer GNR structure.. 31
4.1 Driver Interconnect Load System. 34
4.2 Equivalent RLC model of Copper. 35
4.3 Equivalent RLC model of SWCNT interconnects. 36
4.4 Equivalent RLC model for MWCNT interconnects. 37
4.5 Equivalent RLC model for Mixed CNT bundle interconnects. 39
4.6 Equivalent RLC circuit model for SLGNR interconnects. 41
4.7 Equivalent RLC model of MLGNR interconnects. 42
PREC, M.E. E & TC Page vii

LIST OF TABLE
1.1 Parameter values for Future nodes by ITRS. 6
3.1 Advantages of FinFET. 18
3.2 Parameters for single grain boundary (SGB) PNPN TFET. 21
3.3 Metal interconnects. 23
3.4 Advantages and Disadvantages of Copper. 25
4.1 Combination of Device and Interconnects. 34
PREC, M.E. E & TC Page viii

CHAPTER 1
INTRODUCTION
1.1 Motivation:
Field Programmable Gate Array (FPGA) are pre-fabricated silicon devices that can be
configured to become almost any kind of digital circuits or systems. The “reconfigurable” term
in FPGA indicates an ability to change its functionality even after fabrication. FPGAs are a
popular choice for digital circuit implementation because of their growing density, speed, short
design cycle, and steadily decreasing cost. However power consumption, especially leakage
power, has become a major design hurdle for the semiconductor industry at the nanoscale
regime. FPGA consumes significant amount of static as well as dynamic power due to the
presence of additional logics for providing more flexibility as compared to an Application
Specific Integrated Circuits (ASIC).The flexibility and the versatility of FPGA lie in its
reconfigurability. However, it comes at the cost of extra circuitry resulting more power
dissipation and longer delay. Reconfigurability feature of FPGA is also attractive for the energy
efficient devices. Though ASICs are more power efficient than FPGAs but they are expensive
for lower volume and more difficult to design at a nanoscale. The investment required to produce
a useful ASIC consists of several large items as given below [25]:
1. Deep submicron ASIC CAD tools for synthesis, placement, routing, extraction,
simulation timing, and power analysis are extremely costly.
2. The cost of a mask of a fully-fabricated device is in millions of dollars. This cost can be
reduced if prototyping costs are shared among different smaller ASICs.
3. The high man-power cost to develop a large ASIC.
In addition, the targeted nature of ASIC makes it impossible to reuse it for different portable
applications. Moreover, higher cost and requirement for a proportionally higher return on
investment compels most digital system realization in FPGA despite its higher power
consumption. The following key advantages of FPGAs attract researchers and manufactures to
frequently upgrade the FPGA technology.
1
1. Minimum time to market as compared to ASICs.
2. FPGAs are excellent candidate for low volume production.
3. FPGAs are ideal for prototyping purposes. Hardware testing and verification can also be
quickly performed on the chip.
In recent years, the performance of reconfigurable architectures has been rapidly improving
to bridge the performance gap with ASICs. Previous research work was focused on subthreshold
logic design to enhance the battery life time of mainly application specific portable devices [26,
27]. Therefore, it is also important to investigate the possibility of extending the use of FPGA
even in subthreshold region, so that portable energy efficient systems can utilize the
reconfigurability feature of FPGA [28].
However, FPGA requires approximately 20 to 35 times more area than a standard cell ASIC
and speed performance roughly 3 to 4 times slower than an ASIC and also consumes roughly 10
times higher dynamic power [29]. Therefore, it is important to investigate different techniques
for reducing the power consumption in FPGA, so that it can also be employed in place of ASICs
even in energy constrained applications. It has been well established that interconnect resources
of FPGA consume most of the chip power, area, and determines the overall circuit delay [28,
30]. Though subthreshold operation of FPGA reduces power dissipation by an order of
magnitude but it results in significant delay overhead. Improving the speed of subthreshold
FPGA is a major design challenge at the circuit and device levels so as to widen their application
domain to ULP wireless sensor networks and biomedical applications.
Most of the commercially available FPGA architectures are implemented by the same
functional components: such as an array of configurable logic blocks (CLB) and programmable
interconnect fabrics with surrounded I/O blocks. These components of FPGA are as shown in
Figure 1.1 (a) [31-32]. The majority of FPGAs provides programmable logic using lookup tables
(LUTs). An individual k-input lookup table (LUT) is capable of implementing any k-input
combinational logic function. In order to support sequential logic, flips flops are placed at the
LUT output. This combination is referred as a basic logic element (BLE) and is shown in Figure
1(b). In most of the modern FPGAs, BLEs are grouped together in larger blocks called CLBs and
2
are configured using SRAM memory cells. These reconfigurable blocks allow FPGA to be
programmed after fabrication to realize practically any digital logic function.
CLB
Logic Slice
Cout Block RAM
Interconnect
Switch Matrix
Multiplier
1 2
Local feedback
Fabric
3 4
I/O
5 6
Cin Digital clock
1 : OMUX 2: IMUX 3:
Manager
DOUBLE 4: HEX 5:
LONGH 6: LONGV
(a)
I1 MUX
I2 4-Input
D Flip-flop
I3 LUT
CLK
I4
(b)
Figure.1.1(a) Abstract view of FPGA, (b) Basic logic element (BLE)
Since their inception in 1985, Field Programmable Gate Arrays (FPGAs) have emerged as a
leading choice of technology for the implementation of many digital circuits and systems.
Compared to other programmable devices, an FPGA offers the highest logic density, a good
speed-area trade-off, and a very general architecture suitable for a wide range of applications.
FPGAs are being used in prototyping of designs, communication encoding and filtering, video
communication systems, real time image processing, digital signal processing and the list goes
on. The FPGA consists of logic blocks (a group of CLBs) and programmable interconnect
3
resources. Logic is implemented in FPGAs using many Basic Logic Elements (BLEs). These are
Look-Up-Table and Flip-flops which are connected through fast local interconnects. These BLEs
are grouped into LogicClusters or Logic Blocks.Within a logic block, the BLEs are connected
using a programmable routing structure called an Interconnect Matrix.
Connections between the Logic Blocks are made using fixed wires/tracks. These tracks are
connected to each other and to the logic block inputs and outputs using programmable switches.
These programmable switches are usually implemented using a pass transistor controlled by the
output of a static RAM cell. The CLBs access the interconnect fabric through connection blocks
(CBs), and the inter-CLB wires are interconnected through switch blocks (SBs). These
interconnect resources typically consume approximately 70% of FPGA area and constitute the
major portion of critical path delay and power consumption of most of FPGA design [36].
The role of interconnects is to enable effective passing of clock and other signals in addition
to providing power to various parts of chip. Interconnects are of three types
 Local interconnect
 Intermediate interconnect
 Global interconnect
Local interconnect is used for short distance (5-100µm) communication delay of less than
a clock cycle. Local interconnects are first or lowest level interconnects. Intermediate
interconnect (100 -500µm) is used to connect a device within a block. Global interconnect
(above 500µm) which is used for long distance communication distribute data, clock, power
supply and ground across the chip. They often travel over long distance therefore are always low
resistance material.
The delay of a circuit implemented in an FPGA can be broken down into two major
components: the routing delay and the logic delay. Previous studies have shown that depending
on the architecture, anywhere from 60% to 80% of the circuit delay in an FPGA is due to the
delay in the routing fabric[36]. As integrated circuit manufacturing process geometries shrink
into the deep-submicron region, the resistance and capacitance of wires and switching elements
in an FPGA become increasingly significant, creating routing delays that are an even greater
proportion of the total delay. Thus, minimizing the routing delay through the development of
4
new and faster routing architectures and use of different interconnects materials is an active area
of research and provides the motivation for this work. This project focuses on improvement of
interconnects performance.
The technology roadmap is an ambitious document widely used as a guiding

reference for advanced semiconductor device research and manufacturing purposes. Based on
research from the semiconductor industry and academia, the latest edition of the ITRS
outlines the requirements and identifies the challenges which allow Moore’s law to be
maintained over the next 15 years. In addition to the challenges, it also outlines the possible
solutions to some of the problems that the industry may face and highlights the specific areas that
need urgent research. Overall, the roadmap has three major contributions. The first is to identify
the needs and requirements to be met by technology solutions currently under development. The
second is to recognize the existence of interim solutions for the medium term challenges
and problems and their limitations at the present time. The third important contribution of ITRS
is to identify the areas where there are “no known manufacturing solutions” customarily labeled
as the “Red Brick Wall” - to induce the industry to concentrate on them strategically and
focus research efforts in these areas. One of the important sections expanded significantly in
the 2013ITRS is on the emerging research devices. It was organized with the aim of finding
and building successful new device structures that can replace conventional MOSFETs.
Although some of the listed structures are more of research type, the device structures such
as fully depleted silicon on insulator (FD SOI) and the multiple gates architectures including the
double gate MOSFETs, FinFETs and TunnelFETs are the promising candidates to replace
mainstream device structures. Figure.1.2 shows according to the ITRS that in both the near-term
and the long-term functionality will be increasing by roughly 100% in every technology nodes.
5
Figure.1.2 MPU/ASIC Half Pitch and Gate Length Trends-ITRS 2013 Edition [24]
Table.1.1 Parameter values for Future nodes by ITRS-2013 [24]
Year of production 2013 2014 2015 2016 2017 2018
Logic Node name 16/14 10 7
Vdd(high performance) 0.86 0.85 0.83 0.81 0.80 0.78
MPU-HP physical gate length (nm) 20 18 17 15 14 13
ASIC-LP physical gate length (nm) 23 21 19 17 16 15
Off current, Ioff(µA/µm) 0.1 0.1 0.3 0.3 0.3 0.5
Drive current, Ion (µA/µm) 2050 2110 2400 2590 2650 2710
Although the electronics industry prefers to continue as long as possible with the scaling of
conventional MOSFETs, there is “Red Brick Wall” to this process unless there is a major
technological breakthrough. High channel doping, which degrades the device performance, and
ultra-thin gate oxides, which introduce unacceptable gate leakage, are likely to prompt a
replacement to conventional MOSFETs somewhere beyond the 65nm technology node.
6
Among the replacement candidates are, for example, ultra-thin body SOI and multiple gate
devices complimented by the introduction of strained silicon in the channel region to
enhance the carrier mobility, and high permittivity materials in the gate stack in order to
suppress gate leakage [24].
1.2 Gap Identification:
Scaling of the minimum feature size of transistors andinterconnects has been the driving
factor in exponentiallyimproving the performance of microchips for over four decades.It also
results in tighter packing of the wires on a microprocessor, which increases parasitic capacitance
and signal propagation delay. Consequently, the delay due to the communication between the
parts of a chip becomes comparable to the computation delay itself. This phenomenon, known as
an “interconnect bottleneck”, is becoming a major problem in high-performance computer
systems. While transistor performance improves with scaling, interconnect performance
degrades due to an increase in the resistance per unit length. These results in a significant
degradation in interconnect performance with technology scaling.The historical understanding of
the interconnectproblem in electronics has been that the penalty due to the
performancedegradation of interconnects with technology scaling would be most severe for long
interconnects at the global level. At the nanoscale, however, the nature of the interconnect
problem changes and paves the way for new opportunities. This is because of the fact that the
metal resistivity at small interconnect dimensions drastically increases due to size effects. It is
shown that the historical trend of achieving smaller interconnect latency for short local- and
intermediate-level interconnects will not hold true for future technology nodes.
With the interconnect dimensions scaling below the mean free path of electrons in copper
(40nm), the resistivity of copper rises sharply due to size effects. As a result, the narrow local
interconnects suffer due to a sharp rise in resistance with scaling. In addition to performance and
power challenges, copper interconnect also suffer from reliability issues like electro-
migration.Electro-migration (EM) is diffusion-controlled mass transport, driven by electron
current flow in metal lines. It can be a serious reliability threat when the dimension of Cu
interconnects approaches nanoscale range.Existing copper interconnects technology faces serious
impediments to satisfy delay and speed improvements requirements in the nanoscale regime.
7
Given the long-term scaling problems associated with traditional copper wires, alternative
interconnect technologies and their architecture implication for FPGAs must be explored. Due to
the technology scaling CMOS size is shrinking, performance is improved but new problems
aroused that is short channel length effects which causes more leakage currents and hence more
power dissipation.
To avoid this problem researcher have found new device structure or technology which
are FinFET and Tunnel FET. They both are designed to overcome the short channel length
effects of CMOS. And these devices are now becoming more advanced and better than CMOS.In
Previous studies performance of emerging interconnects was analyzed considering CMOS
driver. Interconnects performance with other device technologies have been carried out by some
researcher. As per the literature survey only one researcher have considered the joint
consideration of interconnects and devices and made a comparison of them. So there is gap
identified that combination of these device technologies and interconnects has to be done to
investigate the performance of interconnects with these devices and to know which interconnect
material is best for each of these devices.
1.3 Problemstatement:
Existing copper interconnects technology faces serious impediments to satisfy delay and
speed improvements requirements in the nanoscale regime. The conductivity of copper steeply
decreases in the deca-nanometer technology nodes due to surface and grain boundary scattering.
Given the long-term scaling problems associated with traditional copper wires, alternative
interconnect technologies and their architecture implication for FPGAs must be explored.
Emerging Interconnect materials are carbon generated interconnects, which are replacing the Cu/
low-k interconnects due to their better performance in terms of power, delay, energy per bit and
signal integrity.
Carbon generated materials are Carbon nanotube (CNT) and GrapheneNanoribbon

(GNR) which has physical properties, such as large mean free path (MFP), extremely high
current carrying capacities, and thermal conductivities. They have strong capabilities to provide
much better performance than that of Cu wires.Due to the technology scaling CMOS size is
shrinking, performance is improved but new problems aroused that is short channel length
8
effects which causes more leakage currents and hence more power dissipation. To avoid this
problem researcher have found new device structure or technology which are FinFET and
TunnelFET. They both are designed to overcome the short channel length effects of CMOS. And
these devices are now becoming more advanced and better than CMOS.
1.4Objective:
As the problem stated in above section of the report, the objective identified as follows:
 To analyse/study emerging interconnects materials CNT and GNR.

 To simulate/optimise Interconnect models in HSPICE software to calculate parameters to
its optimised level.
 To simulate/optimise the PNPN TFET model in TCAD software.
 To simulate/evaluate combination of CMOS/FinFET/ PNPN TFET / Optimised TFET
devices with all interconnect materials to improve the performance of system.
 To make a conclusion specifying which of these interconnect material best suits to which
of the device technology and gives best performance than other combinations.
9
CHAPTER 2
LITERATURE SURVEY
The enhancement in integrated circuit density (Moore’s Law) and performance improvement
have been achieved by evolutionary device scaling and/or increase in chip size. Technology
scaling at each node brings faster and more leaky transistors and worsens the global interconnect
performance. The interconnect becomes the most limiting aspect affecting the functionality of
Ultra Low Power (ULP) circuits due to the increase in resistance at every technology node.
This advancement leads the interconnect technology into a new era where it has to face
certain challenges such as electromigration, higher resistivity due to surface boundary scattering,
skin effect, signal integrity, delay uncertainty, power dissipation, etc. Presently, the devices are
much smaller in dimension and faster in comparison to the Interconnects. The overall
performance of a chip is determined by the Interconnect and not the device or gate delay. The
demand for VLSI circuits with higher speed and component density is also increasing
continuously. During recent past, various IC designers employed only metallic interconnections
(such as Al or Cu) but due to their persistent limitations researchers are forced to look after
several other possibility of using optical, Graphene or organic material based interconnections in
the near future [37].
Hong Li et al. presented electrical and thermal modeling and performance analysis for
various CNT- and GNR-based interconnects and compared with conventional interconnect
materials to provide guidelines for their prospective applications. He showed that single-walled,
double-walled, and multiwalled CNTs can provide better performance than that of Cu. However,
in order to make GNR interconnects comparable with Cu or CNT interconnects, both
intercalation doping and high edge-specularity must be achieved. CNT is promising application
as through silicon vias in 3-D ICs [1].
Ahmet Ceyhan et al.investigated the impact of size effects on the design of a multi-level
interconnection network, and potential power saving offered by individual single-wall nanotube
(SWNT) and mono-layer graphene interconnects and quantified for high-performance and low-
cost designs implemented at future technology nodes. He showed that size effects increase the
10
number of metal levels for a high performance chip by as large as 22.81% and 41.35% at the
21nm and 7.5nm technology nodes, respectively. It has also been demonstrated that individual
metallic SWNT and mono-layer graphene interconnects may be used to reduce the interconnect
power dissipation in both high-performance and low-cost designs [2].
S.D. Pable et al.proposed to improve the performance of subthreshold FPGA in terms of

delay and switching energy by optimizing and operating interconnect drivers in the near
threshold operating region. He explored the possibility of inserting repeaters and the suitability
of CNT as an Interconnect in the subthreshold region. His proposed technique shows 67%,
73.33% and 61.8% increase in speed and 35.72%, 39% and 35.44% reduction in switching
energy for Double, Hex and Long interconnect segments, respectively, over the conventional one
[3].
Ahmet Ceyhanet al. has shown that the historical trend of achieving smaller interconnect
latency for short local- and intermediate-level interconnects will not hold true for future
technology nodes. He demonstrated that individual single-wall carbon nanotube (SWNT)
interconnects can offer significant delay and energy-per-bit improvements in high-performance
circuits at the end of the roadmap [4].Sachin D. Pableet al.investigated and compared the
performance of single-wall carbon nanotube (SWCNT), Cu, and mixed CNT bundle
interconnects for different interconnect lengths and biasing levels under subthreshold conditions.
He proposed that individual SWCNT can be used for short and intermediate length interconnects
at different bias points in the subthreshold region due to less critical interconnect resistance
contrary to superthreshold region. Performance analysis of global interconnect shows that in
moderate subthreshold region, scaled Cu interconnect performs better than individual SWCNT
and mixed CNT bundle, whereas in deep subthreshold region individual SWCNT is still better
[5].
Ahmet Ceyhanet al.investigated trade-offs between the technology parameters of various

interconnect technologies on the basis of their impacts on the circuit performances of emerging
post-CMOS devices. He evaluated the relative performances of all these interconnect
technologies with each type of device. The interconnect technology option that gives the best
performance in terms of circuit delay, energy-per-bit and energy-delay product (EDP) is reported
for each of the device technologies [6].
11
Subthreshold circuits are shown to be the best candidate for satisfying the ultra-low power
demand of battery-operated systems having moderate throughput [7].S.D. Pable et al.presented a
comprehensive analysis of Cu and mixed CNT bundle interconnects and investigates their
performance in terms of delay and energy delay product (EDP) for future subthreshold circuits.
He also carried Crosstalk analysis. Aspect ratio scaling significantly reduces the interconnect
delay and switching energy and at minimum aspect ratio, Cu wire performs better than even an
optimized mixed CNT bundle for global interconnect length under subthreshold conditions [7].
Mrs. P. Murugeswari et al. carried the performance evaluation of both single-walled carbon
nanotube and multi-walled carbon nanotube interconnects delay and compared the results with
that of the copper interconnect. Both the CNTs and copper interconnects are examined
thoroughly with the help of HSPICE simulation using its transmission line model. Comparison
shows that MWCNT is the most promising candidate for local, intermediate and global levels of
interconnects [8].
David Esseniet al. presented the results of a comparative study between the tunnel-FETs
(TFETs) and conventional MOSFETs for ultralow power digital circuits targeting a VDD below
500 mV. He employed numerical TCAD simulations, as well as mixed device-circuit and
lookup-table simulations using either the SENTAURUS or theVerilog-A environment. He
explored the device–circuit interaction in n- and p-type TFETs, and propose a design leading to a
good tradeoff between the currentleakage and transistor imbalance at ultralow VDD, as required
in ultralow voltage systems. He systematically compared the IOFF, ION, effective capacitance,
OFF-state and ON-state stacking factors for TFETs, SOI, and bulk MOSFETs in a wide range of
VDD. He also report simulation results for the sensitivity of the transistors to the variation of
some key device parameters [9].
Brajesh Kumar Kaushik et al. carried research analyses and compared the bandwidth and
absolute frequency response of a Multi-layer Graphene Nanoribbon (MLGNR)and a Multi-
walled Carbon Nanotube (MWCNT) at local, semi-global and global interconnect lengths. The
transfer function of the driver interconnect- load system is obtained by representing the
interconnect line with an equivalent single conductor model of either a MLGNR or a MWCNT.
Using absolute frequency response, it is observed that the bandwidth of the MLGNR is higher by
12
almost ten times and four times in comparison to the MWCNT for local and global interconnect
lengths, respectively [10].
Manoj Kumar Majumderet al.studying, analyzing, and comparing theperformance of CNTs

and GNRs forboth on-chip interconnect and TSV applications. The analysis is carried out using
the electrical equivalent models of interconnects and TSVs.conventional Cu interconnect
materialis approaching its limit and will not beuseful for future interconnect applications. At high
operating frequencies, Cu-based interconnects and TSVs face key challenges in terms of
electromigration, skin effect, coupling noise, and dispersion. CNTs and GNR s are potential
alternative materials to replace Cu. Based on the comparison study, it is observed that MLGNRs
and MWCNT s outperform the Cu interconnects. Moreover, it is observed that MLGNRs and
MWCNTs are also preferred for TSV filler materials [11].
Mixed carbon nanotubes bundles (MCBs) are consideredto be highly potential interconnect
solutions in the current nanoscale regime. Manoj Kumar Majumder et al. proposed different
MCBs with random and spatial arrangements based on the placements of single- and multiwalled
carbon nanotubes (CNTs) (SWNTs and MWNTs) in a bundle. He analyzed Propagation delay
and dynamic crosstalk performances using the modified equivalent single conductor model of
proposed MCB topologies. Encouragingly, a significant reduction in propagation delay and
crosstalk delay is observed for a spatial arrangement of an MCB wherein MWNTs are placed
peripherally to the centrally located SWNTs. Typically, he found the average delay with and
without crosstalk is improved by 82.8% and 80%, respectively, compared to the MCB having
randomly distributed SWNTs and MWNTs [12].
Vobulapuram Ramesh Kumaret al.accurately models the crosstalk effects ina CMOS-gate-
driven coupled RLC interconnect using the nth power law model and finite-difference time-
domain (FDTD) technique. The propagation delay, peak crosstalk voltage, and peak voltage
timing on victim line of coupled-multiple lines are observed and compared to HSPICE
simulation results for the global interconnect length at 32 nm technology node. His proposed
model accurately estimates the performance parameters of driver interconnect load system. An
average error of less than 2% is observed in estimation of peak crosstalk voltage and its timing.
His proposed model can be extended for coupled n lines and useful for the evaluation of signal
integrity, issues of EMI, and EMC of on-chip interconnects [13].
13
Wen-Sheng Zhao et al. performed comparative study on their distributed parameters and
transmission characteristics based on an equivalent single-conductor (ESC) model of Multilayer
Graphene Nanoribbon (MLGNR) interconnects with side contacts. He found that the number of
conducting channels of a metallic MLGNR interconnect is the linear function of its width and
Fermi energy, which can be described by an analytical equation. Its equivalent inductance and
capacitance in the ESC model can also be characterized by a set of closed-form equations.
Furthermore, according to the ITRS projection, transmission performance of the MLGNR
interconnects with different contacts are predicted and compared with their Cu and carbon
nanotube counterparts at different technology nodes. Also proved that MLGNR interconnects
can provide better performance than Cu wires in particular at intermediate level. Even with the
maximum crosstalk impacts considered, the advantage of MLGNR interconnects over Cu wires
can still be kept [14].
Vachan Kumar et al. used Stochastic wiring distribution models topredict the improvement
in energy obtained by replacing a fewor all copper metal levels with Graphene Nanoribbons
(GNRs)in a low-power digital circuit. The models developed by him alsoestimate the
degradation in the performance by replacing a fewor all copper metal levels with GNRs.
Replacing a few localcopper interconnect levels with GNRs is expected to reducethe energy
consumed by local interconnects, without severelydegrading the performance of longer global
interconnects. Thehybrid GNR+copper interconnect is shown to perform worsecompared to the
all GNR interconnect, if the length of the GNRsegment is greater than a critical value. For a
logic circuit with30k gates, it is shown that the hybrid interconnect offers a 30to 40% decrease in
energy and a 4×decrease in maximumfrequency, whereas the all GNR interconnect offers a 50 to
60%decrease in energy and a 7×decrease in maximum frequency [15].
During the recent past, carbon nanotubes (CNTs) have rapidly gained importance in an
intensely growing researched area of interconnects. For various reasons, bundled CNTs are often
preferred over single-walled CNTs (SWCNTs) or multi-walled CNTs (MWCNTs). However,
during fabrication, it is difficult to control the growth of a densely packed bundle having
SWCNTs with uniform diameters or MWCNTs with an identical number of shells. Therefore, a
realistic CNT bundle is in fact a mixed CNT bundle (MCB) that consists of SWCNTs and
MWCNTs. In light of these facts, Manoj Kumar Majumder et al. introduced an analytical model
14
of a MCB that follows the random distribution of CNTs in a bundle. Depending on the
probability of distribution of CNTs having different diameters, he presented a compact multi-
conductor transmission line (MTL) and a simplified equivalent single conductor (ESC) model.
Encouragingly, the simplified ESC model exhibits an average error of only 2.44% at different
interconnect lengths compared with the delay obtained through the MTL approach. Mean
diameter and tube density of the MCB are mapped to the ESC model to analyse the propagation
delay, power dissipation and crosstalk. He observed that irrespective of interconnect lengths; the
performances are significantly improved for higher tube density in a MCB [16].
Massimo Aliotoet al. investigated the potential of tunnel FETs (TFETs) for ultra-low voltage
(ULV)/ultra-low power (ULP) operation at 32-nm node through Verilog-A simulations of
appropriate reference circuits. He analyzed the minimum energy point in a wide range of
conditions, and introduced guidelines for microarchitectural optimization for ultra-low energy.
Voltage scalability of static RAM memories is also analyzed as main limitation to aggressive
voltage scaling of very large scale integration (VLSI) systems, and improved precharge schemes
are introduced to reduce leakage. His investigation permits to understand the potential of TFETs
and their advantages over traditional devices within a unitary framework that is based on fair
design and comparison from device to circuit level, as well as to develop clear design
perspectives in the context of ULV/ULP VLSI digital circuits [17].
Challenges from interconnects in the deep submicronVLSI domain are now a days addressed
through the new innovations. These are the materials based on graphene. Carbon Nanotubes and
Graphene Nanoribbons are the two capable candidates to replace the traditional Cu in VLSI
interconnect. Vangmayee Sharda et al.have reviewed the studies done till date on GNRs and
their performance as interconnect in terms of delay, power dissipation and crosstalk
[18].Chenyun Panet al.analyzed graphene interconnects based onrealistic circuits in terms of
multiple material properties, such as the mean free path, the contact resistance, and the
edgeroughness. The benchmark against conventional copper wires shows that the advantage of
graphene usage occurs only under certain circumstances. The device-level parameters, including
the supply and threshold voltages, and the circuit-level parameters, including the wire length and
width, have large impacts on both the delay and energy-delay product (EDP) comparisons. He
15
investigated two representative circuits, a 32-bit adder and an SRAM. Up to 40% and 70% of the
improvement in delay and EDP are observed for a 32-bit adder.[19].
Mamidala Saketh Ramet al. studied a single grain boundary Dopingless PNPN tunnel field
effect transistor (TFET) onrecrystallized polycrystalline silicon by varying the position of the
grain boundary in the channel. He established theprospect of realizing low-cost thin-film
recrystallized polycrystalline tunnel FETs with:
1) Low OFF-statecurrent and low sub-threshold swing (SS) and
2) AN ON-state current similar to that of a comparable single grain boundary poly-silicon

thin film transistor (TFT). His results indicate that the proposed single grain boundary dopingless
PNPN TFET could be an ideal substitute for the conventional TFTs making it appropriate for
low power display applications as well as the driver circuits [20].
T. Okagakiet al.studied 16nm FinFET logic cellperformance comprehensively with accurate

capacitance extraction. Enlarging the parasitic capacitance with simple layout optimization was
effective to achieve Tpd increase under the same cell area [21]. Moreover, with the modified
delay cell, leakage current could be reduced under same Tpd. The large parasitic capacitance of
FinFET is not only a disadvantage, but beneficial with effective utilization [21].
Mohamed Mohie El-Dinet al. evaluated the performance of FinFET-based FPGA cluster. He
reported the impact of threshold voltage variation, considering die-to-die variations, on the delay,
power, and power-delay product. His analysis showed an increasing trend of the average power
and power-delay product variations with threshold voltage as we go down with technology node
and the delay shows the least percentage of variations with threshold voltage at the most
advanced node of 7nm [22].
Vobulapuram Ramesh Kumar et al. analyzed and compared the power, delay and bandwidth
performance of Cu and doped MLGNR using an equivalent single conductor (ESC) model. The
overall delay and power dissipation of doped MLGNR is substantially smaller by 86.13% and
43.72%, respectively, in comparison to the Cu interconnects. Moreover, MLGNR demonstrates
prominently improved bandwidth and relative stability at global interconnect dimensions. He
also analyzed MLGNR interconnects with different edge roughness conditions [23].
16
CHAPTER 3
THEORETICAL DETAILS
3.1 Device Technologies:
Device technologies considered in the report are
3.1.1 CMOS:
CMOS is a widely used type of semiconductor. CMOS semiconductors use both NMOS
(negative polarity) and PMOS (positive polarity) circuits. Since only one of the circuit types is
on at any given time, CMOS chips require less power than chips using just one type of transistor.
CMOS structure is shown in Figure.3.1
Figure.3.1Cross section of CMOS Device [43].
Two important characteristics of CMOS devices are high noise immunity and low static
power consumption.Since one transistor of the pair is always off, the series combination draws
significant power only momentarily during switching between on and off states. Consequently,
CMOS devices do not produce as much waste heat as other forms of logic. In the project
conventional CMOS model will be used.
17
3.1.2 FinFET:
FinFET technology takes its name from the fact that the FET structure used looks like a set
of fins when viewed.The main characteristic of the FinFET is that it has a conducting channel
wrapped by a thin silicon "fin" from which it gains its name. The thickness of the fin determines
the effective channel length of the device.In terms of its structure, it typically has a vertical fin
on a substrate which runs between a larger drain and source area. This protrudes vertically above
the substrate as a fin.The gate orientation is at right angles to the vertical fin. And to traverse
from one side of the fin to the other it wraps over the fin, enabling it to interface with three side
of the fin or channel.This form of gate structure provides improved electrical control over the
channel conduction and it helps reduce leakage current levels and overcomes some other short-
channel effects.The term FinFET is used somewhat generically. Sometimes it is used to describe
any fin-based, multigate transistor architecture regardless of number of gates.
Figure.3.2 Structure of DG FinFET
Multi-gate MOSFET is a promising device for ultimate CMOS device structure because
the device shows reduced short channel effect (SCE), higher current drivability, nearly ideal
subthreshold swing (SS), and mobility enhancement [35].DG-FinFET transistor is a vertical
18
double-gate emergingdevice having huge potential to substitute bulk devices atnanometer

technology node. The main feature of the FinFET is the electrical coupling between the front and
back gates. Due to this structure, the drain current is controlled by both the front gate (Gf) and
the back gate (Gb) voltages[33].
Advantages of FinFET are:
Table.3.1 Advantages of FinFET
PARAMETER DETAILS
Much lower power consumption allows high integration levels. Early
Power
adopters reported 150% improvements.
FinFETs operate at a lower voltage as a result of their lower threshold
Operating voltage
voltage.
Possible to pass through the 20nm barrier previously thought as an end
Feature sizes
point.
Static leakage
Typically reduced by up to 90%
current
Operating speed Often in excess of 30% faster than the non-FinFET versions.
3.1.3 TunnelFET:
The Tunnel Field Effect Transistor (TFET) wasproposed as a new possible solution to reduce
the powerdissipation. Tunnel transistors are different in their workingprinciple from MOSFETs.
The TFET operates by band-tobandtunneling and, therefore, the subthreshold slope (S) is
notlimited to 60mV/dec as in the case of CMOS[34].In TFETs tunneling of interest is band-to-
band tunneling. For band-to-band tunneling to occur, an electron in the valence band of
semiconductor tunnels across the band gap to the conduction band without the assistance of
traps. The band gap acts as the potential barrier that the particle tunnels across.The tunnel field-
effect transistor (TFET) belongs to the family of so-called steep-slope devices that are currently
being investigated for ultra-low-power electronic applications [2]. A key feature of the TFET,
19
which is critical for low-power switching, is the possibility for an inverse sub threshold slope, S,
below the limit of 60 mV/dec for normal FETs.
The ITRS has signaled out TFETs as the most promising transistors that can reduce the
inverse subthreshold slope (SS) below the 60 mV/decade limit of MOSFETs (at room
temperature), and thus enable an aggressive VDD scaling [9].
Figure.3.3Structure of TFET
20
Figure.3.4Energy band diagram of On and Off state of TFET

The fundamental challenge for realizing commercially competitive TFETs is a limited
on-current level, which is typically addressed by creating higher doping levels and abrupt
dopingprofiles. Figure.3.3 shows a schematic of an n-channel TFET architecture which
incorporates a highly doped p+ source region, a near intrinsic channel region and n+ drain
region.
TFET is simply a gated p-i-n diode, which is operating under reverse bias condition. In a
MOSFET the source of carrier injection mechanism is thermal injection but a TFET utilizes
band-to-band tunneling as a source carrier injection mechanism. Figure.3.4 shows the band
diagrams of the n-channel TFET in the OFF and ON states. In the OFF state, there is a wide
21
potential barrier between the source and the channel; as a result no tunneling is occurring. Only a
very small leakage current exists. But when the gate voltage exceeds the threshold voltage, the
potential barrier between the channel and the source becomes narrow enough to allow a
significant tunneling current, which is called ON state. Because of the different source carrier
injection mechanism in the TFET compare to a MOSFET, it can achieve sub-60-mV/dec S.
TFET is an ambipolar device, it will show p-type behavior with dominant hole
conduction and n-type behavior with dominant electron conduction. But this ambipolarity can be
suppressed by designing an asymmetry in the doping level or profile, or by restricting the
movement of one type of charge carrier using Heterostructures. In principle, because of the
asymmetry TFETs can achieve much higher ION-IOFF ratio over a given gate voltage swing
compared to the MOSFETs, making the TFET architecture an attractive vehicle to implement
low supply voltage (VDD) digital logic circuits. When a TFET is in its off state, the valence
band edge of the channel is located below the conduction band edge of the source, so BTBT is
suppressed, leading to very small TFET off-state currents that are dictated by the reverse-biased
p-i-n diode.
3.1.4 PNPN TunnelFET:

Mamidala Saketh Ram et al. [20]have proposed a single grain boundary dopinglessPNPN
TFET using the charge-plasma concept andhave studied the effect of the single grain boundary
position on its performance. When the singlegrain boundary is present in the channel on the
source side but away from the source-channel junction, the single grain boundary dopingless
PNPN TFET exhibits a high ON-state current as well as a low OFF-state current while
maintaining a sub-60mV/decade average subthreshold swing.
22
Figure.3.5 PNPN TFET structure
A TFET with the source side N+ pocket is called a PNPN TFET and exhibits a
significantly improved ON-state current since the N+ pocket will increase the lateral electric
field, modulate the energy band profile, and reduce the tunneling width. He proposed Dual-
material gate dopingless PNPN TFET by means of charge plasma concept. Using calibrated two-
dimensional simulations, we demonstrate that the proposed dopingless PNPN TFET using a
dual-material gate and a hetero-gate-dielectric exhibit enhanced ON-state current and low
subthreshold swing compared to a conventional dopingless TFET.
Table.3.2 Parameters for single grain boundary (SGB) PNPN TFET [20]
Parameters SGB PNPN TFET

Silicon Film Thickness 10nm
Channel length LS (5nm) + LM(45nm) = 50nm
Gate Oxide thickness 2nm
Gate oxide length LHfo2 + Lsio2 = 25nm
Gate Work function LS = 3.9eV, LM = 4.4eV
Channel Doping NA = 1 × 1017/cm3
Source/Drain Doping --
Grain Boundary Width 4nm
23
Figure.3.6Transfer characteristics of the dopingless TFET compared with that of the dopingless
PNPNTFET [20]
Figure.3.6 Compares the transfer characteristics of the dopingless TFET with that of the
dopingless PNPN TFET. It can be observe that the dopingless PNPN TFET not only exhibits
more than two orders of magnitude (~ 135 times) enhancement in the ON-state current but its
average subthreshold swing (SS), too is significantly smaller (20 mV/decade for LS = 4 nm)
compared to the dopingless TFET [20].
The tunneling current can be expressed as follows [38]
𝐼 = ∫ 𝐹𝑠,𝑉 (𝐸)[1 − 𝐹𝑐,𝐶 (𝐸)]𝑁𝑉 (𝐸)𝑁𝐶 (𝐸)𝑇𝑡𝑢𝑛𝑛𝑒𝑙 𝑑𝐸 (1)
WhereNvand Nc are the effective densities of states in thevalence and the conduction band,
respectively; Fc and Fs are the Fermi–Dirac distribution functions in the channel and the source
region, respectively; and Ttunnel is the tunneling probability.
The parameter used in [20] will be altered and changed to optimize the device. These TFET
model will be simulated and optimized and will be usedin the Project work.
24
3.2Interconnect Technologies:
Interconnect technologies considered in the report are
3.2.1 Copper (Cu):
Copper (Cu) with close to half the resistivity (1.7 μΩ cm) of Al demonstrates ten times better
performance in terms of electromigration. Thus, it emerged as the most appropriate material for
VLSI interconnects in late 90s. Adding to the merit, Cu has higher melting point (1,357 K) than
aluminum (933 K) that provides an advantage over aluminum in terms of stress and
electromigration effects. In comparison with aluminium, copper can withstand about five times
more current density with equal reliability for IC-applications. Due to the advantages that it
offers copper became the preferred interconnect material, especially for submicron and deep
submicron high density, high performance chips. As the aggressive technology scaling continues
a new problem is surfacing. With decrease in cross-section copper interconnect resistivity
increases due to surface roughness and grain boundary scattering, causing increase in
propagation delay, power dissipation and electro-migration.
Table.3.3 Metal interconnects [37].
Metal Bulk resistivity (μΩ cm) Thin-film resistivity (μΩ cm)

Ag 1.6 -
Cu 1.7 2.1
Au 2.4 4.1
Al 2.65 2.7
The advantage of using copper (Cu) as an interconnect in VLSI is mainly due to itslower
bulk resistivity compared to aluminium (Al). Figure.3.7 shows the comparative analyses of the
resistivities of copper and aluminium interconnects with respectto line width and thickness of the
films. Experimental studies reveal that at room temperature, copper interconnect shows almost
35% lower resistivity than Al film having the same length, thickness, and width.
25
Figure.3.7Variation of line resistivities of aluminum and copper (a) with line width and (b
with line thickness [39].
Figure.3.8shows that Cu has higher thermal conductivity than Al, and it is expected that
Cuinterconnectinglines will dissipate more heat than Al-interconnecting lines under the same
conditions
26
Figure.3.8Comparative analysis between the thermal conductivity of aluminium and copper

as a function of temperature [39].
In early 2000, it was realized that even Cu is not able to fulfill the demands of high-speed
interconnects. With the increasing integration density of the CMOSand higher clock frequency,
the requirement of lower resistance and higher bandwidthis the major concern in interconnect
design. Therefore, researchers areforced to find an alternative solution to replace Cu due to the
following reasons:
 The resistivity of Cu interconnects is increasing rapidly under the effects ofenhanced
grain and surface scattering, longer interconnects, and higher frequencyoperation.
 The resistivity of Cu also increases rapidly due to Joule heating. The increasedheating
stimulates electromigration induced hillocks and voids.
 One key constraint in the conventional scaling of silicon VLSI is the highinterconnect
related power dissipation per unit area.
Researchers looked aggressively for replacement of Cu interconnect technologysince its

performance was limited by skin effect, dispersion, signal degradation,power dissipation and
electromagnetic interference that actually pronounced athigher frequency range.
Table.3.4 A comparison shows the reasons for the currently increasing use of Cu-based
metallization in the microelectronics industry
Advantages of Cu Disadvantages of Cu
 Cu is more conductive than Al, thus  Cu diffuses rapidly into Si and SiO2,
allowing finer metallization with lower causing deep-level defects as it
resistive losses (ρCu = 1.67 μΩ cm, contaminates the Si.
ρAl = 1.65 μΩ cm)  The main transport path in Cu is the top
 Atomic migration in Al occurs along grain surface of metallization lines. This results
boundaries and surfaces. There is little or in some electromigration damage. Al-
no bulk transport in Cu. (Bulk self based metallization does not exhibit this,
diffusivity of Al: 1.9×10-12 m2 s-1, as Al forms a protective oxide layer
27
Cu: 1.8×10-16 m2 s-1 at 933 K) preventing surface transport.

 Al is very susceptible to electromigration,  As Cu cannot be dry etched, it was
(get rapid formation of hillocks and voids), necessary to develop an electroplating
whilst Cu is less vulnerable as it has higher process for making copper networks, the
mass and a higher melting point. dual-damascene chemical-mechanical
 Cu is also less likely to fracture under polishing (CMP) process, and an effective
stress. linear material for use as a copper
diffusion barrier and to promote adhesion
Due to the favourable properties of Cu, it is possible for the chip size to be reduced,
whilst increasing the speed and complexity of the device. Cu has proved to be an excellent
metallization material as it has an improved current carrying capability and high electromigration
resistance. The disadvantages have been overcome using new thin-film technology and careful
materials selection. It is therefore possible for component size to be further reduced, increasing
the speed and complexity of the device. This is sufficient for now, though there is a continuing
need to achieve high conductivity and minuscule dielectric constants for future devices.
Therefore, in order for the microelectronics industry to keep up with Moore’s Law and the ever
increasing consumer needs, there needs to be introduction of new materials and processes.
3.2.2 Carbon Nanotube (CNT):

Carbon nanotubes (CNTs) have unique atomic arrangement and band structure that
isresponsible for their outstanding electrical and mechanical properties. These
extraordinaryproperties make CNTs one of the most revered Interconnect materials in current
nanoscale technology. Some of these properties are briefly discussed below:
a) They can conduct large current at smaller cross-sectional area without anysignal
deterioration while simultaneously avoiding electromigration problemsthat are otherwise
prevalent in metallic interconnects.
b) The resistance of the bundled CNT is about three orders of magnitude lower than single
CNT. Thus, it is expected that the CNT bundle would prove to be effective replacement
of copper not only for interconnects but for vias also in future VLSI chips.
28
c) As the feature size reduces, the performance of Cu interconnects severelydegrades due to

the increased surface scattering thereby, drastically reducingthe effective mean free path.
However, in contrast to copper the CNTs supportsballistic flow of electrons with an
electron mean free path of severalmicrometers that strongly motivates researchers to
replace Cu by CNTs.
d) A single-walled CNT (SWNT) results in high contact resistance and
characteristicimpedance. Therefore, a bundle of closely packed parallel CNTs are
preferred. The desired properties of thenanotube bundle includes:
1) Low contact resistance with all nanotubes within a bundle.
2) Distance between the nanotubes within the bundle should be as small aspossible
to have the large nanotube density.
3) Quantum coupling between the nanotubes should be nearly zero.
Carbon nanotubes (CNTs) are tiny tubes about 10,000 times thinner than humanhair and
consist of rolled-up sheets of carbon hexagons. There are mainly twotypes of CNTs that can have
higher structural perfection. Single-walled CNTs(SWNTs) consist of single graphite sheet
seamlessly wrapped into a cylindricaltube. Multi-walled CNTs (MWNTs) comprise an array of
such nanotubes that areconcentrically nested like rings of a tree trunk.Electrical transport in
metallic SWNTs and MWNTs is ballistic that resultsin movement of electrons without scattering
along the nanotube axis. It enablesCNTs a long mean free path in the range of micrometer.
In realisticnanotubeinterconnectswillbeamixedbundleof SWCNT
andMWCNT.MixedCNTbundleisacombinationof SWCNT withdiameter(d)
equalto1nmandMWCNTwith multiple shellswithvariousdiameters ‘d’ where (D1 - Dn) as shown
in Figure.3.9.Contrastingly, theelectrons in Cu can travel only 40–50 nm before scattering.
Interestingly, plasmonsalso propagate easily along the nanotube. Superconductivity has also
beenobserved at low temperatures with transition temperatures of nearly 0.55 K for1.4 nm
diameter SWNTs and nearly 5 K for 0.5 nm SWNTs. The unique electrical properties of CNTs
such as extremely low electricalresistances are observed due to their unique electronic structure
supported by their1D structure. Primarily, the resistance is observed due to the defects in
crystalstructures, impurity atoms, or an atom vibrating about its position in the crystal.
29
Figure.3.9 Single walled, Multi walled CNT and Mixed CNT bundle [16].
Depending on the direction in which CNTs are rolled (chirality), they exhibit either
metallic or semiconducting properties. The graphene sheet can be rolled in many possible ways
such as Armchair, Zigzag are shown in Figure.3.10.
Figure.3.10 CNT types a) armchair b) zig-zag
Due to smaller diameter and higher aspect ratio, the electrons do not scatter muchin
CNTs that results in relatively lower resistance than Cu. The low resistanceensures that the
energy dissipated in CNTs is incredibly small. Thus, the problemof dissipated power density can
30
be properly addressed that otherwise adverselyaffects the performance of silicon circuits. Current
densities of more than 1010A/cm2 have been observed for the metallic CNTs. Since CNTs do not
have anyunused bonds, there is no need to grow a film on the surface in order to tie upthe free
bonds. Moreover, the designer is not restricted to just silicon dioxide as agate insulator, therefore
other superior gate dielectric material can be used that canresult in much faster device.
The metallic CNTs are attractive interconnect materials because of their high thermal and
mechanical stability, thermal conductivity as high as 5800W/mK, ability to carry current in
excess of 1014A/m2 current density even at temperatures higher than 200°C and Fermi velocity
comparable with that of a metal. It is very difficult to make a good contact with a CNT. The
unavoidable contact imperfection increases resistance. CNT resistances in the range 7 KΩ - 100
KΩ have been reported. Such a high resistance is a major disadvantage; if an isolated CNT is
used as interconnect.
3.2.2.1 Advantages of CNTs:

CNTs offer several advantages compared to Cu/low-κ interconnects because of their one
dimensional nature, the peculiar band-structure of graphene, and the strong covalent bonds
among carbon atoms:
1. Higher conductivity:Due to their one-dimensional nature, the phase space for electron
scattering in CNTs is limited, and electron mean free path is in the micron range for high
quality nanotubes, in contrast to 40 nm in bulk copper. The conductivity of densely-
packed CNTs is higher than scaled Cu interconnects for large lengths. Conductivity of
short CNT bundles, however, is limited by their quantum resistance. Metallic SWCNTs
have two conduction channels, and their quantum resistance is 6.5 kΩ.
2. Resistance to Electromigration:The strong sp2 carbon bonds in graphene lead to an
extraordinary mechanical strength and a very large current conduction capacity for
CNTs; 109 A/cm2 in contrast to 106 A/cm2 in Cu. In practice, however, contacts may limit
the maximum current density in CNT interconnects.
3. Thermal conductivity: The longitudinal thermal conductivity of an isolated CNT is
expected to be very high, on the order of 6000 W/mK, as suggested by theoretical models
and extrapolations on measured data from porous bundles. The thermal conduction in
31
CNTs is highly anisotropic, and the transverse conduction is orders of magnitude lower
than the longitudinal conduction.
3.2.3 Graphene Nanoribbon (GNR):
Graphene is a one atom thick sheet of sp2-bonded carbon atoms arranged in a honeycomb
lattice structure, was recently shown to exist in a stable state in nature. It is a semiconductor with
zero bandgap, phonon like 2D confined properties, linear energy dispersion, ambipolar charge
transport, and a very high carrier mobility of 104 cm2/Vs at room temperature. Confinement of
the electrons of graphene in one of the in-plane directions is required and it results in graphene
nanoribbons. These ribbons are strips of graphene with dimension less than 10 nanometers, so
called Graphene Nanoribbons.
Several theoretical studies have been conducted into investigating the electronic
properties of graphene nanoribbons such as tight-binding calculations, density functional theory
(DFT) calculations. GNR can be of two types depending upon their termination style.
Figure.3.11 shows the structures of Armchair and Zigzag GNRs. Width of armchair GNR is
decided by the number of hexagonal carbon rings or generally referred as dimer lines (Na) across
the ribbon. Similarly width of zig-zag GNR is dependent on the number of zig-zag chains (Nz)
across the ribbon.
Figure.3.11 (a) Structure of graphene nanoribbon (b) armchair, (c) zig-zag [18]
32
Figure.3.12 Single-layer GNR and Multilayer GNR structure [14].
The GNR interconnects can be classified as single layer GNR (SLGNR) and multilayer
GNR (MLGNR) depending upon the number of layers as shown in Figure.3.12. SLGNRs have
higher resistance so they don’t fit for the interconnect applications but as MLGNRs have
multiple parallel conduction paths so their resistance decreases by the concept of parallel
resistances and thus they are well suited for the interconnect applications in sub-micron VLSI
circuits. High mean free path of electrons, smaller capacitance, and higher current carrying
capacity make graphene an interesting candidate for replacing copper as the on-chip interconnect
material.
3.2.3.1Advantages Of GNRS:
GNRs offer several advantages compared to Cu/low-κ interconnects:
1. Higher conductivity:Like carbon nanotubes, the mean free path of electrons in pure
high-quality graphene can be quite large. Mean free paths as large as a few hundred
nanometers have been reported in graphene. Substrate-induced disorders are believed to
be the dominant source of electron scattering and high mobilities corresponding to mean
free paths as large as a few micrometers have been reported in the case of suspended
33
graphene. Conductivity of stacks of non-interacting GNRs with smooth edges and Fermi
energies above 0.2 eV has been predicted to outperform those of copper wires, especially
at small cross-sectional dimensions and long lengths.
2. Resistance to electromigration:The strong sp2 carbon bonds in graphene lead to an
extraordinary mechanical strength and a very large current conduction capacity for
GNRs; 109 A/cm2 in contrast to 106 A/cm2 in Cu. In practice, however, contacts may
limit the maximum current density in GNR interconnects.
3. Thermal conductivity: The in-plane thermal conductivity of suspended single layer
graphene sheets has been measured to be 5300 W/mK. This value is comparable to the
highest values reported for SWCNTs bundles.
34
CHAPTER 4
SCHEME OF IMPLEMENTATION
4.1 Parameters to be evaluate:
Interconnect parameters:
 Circuit delay
 Power consumption
 EDP
 PDP
 Propagation delay
 Crosstalk
 Bandwidth
Device parameter:
 Ioff/Ion
 I-V and C-V characteristics
 Power
Technology nodes:
 45nm
 32nm
 22nm
Voltage:
 Subthreshold voltage means Vdd < Vt

 CMOS Subthreshold Vdd=0.4v
 FinFET Subthreshold Vdd=0.4v
35
 TFET Subthreshold vdd=0.1v
Interconnect level:
 Local
 Intermediate
 Global
4.2 Driver Interconnect Load system:
Using Driver Interconnect Load system simulation of interconnects will be performed in

HSPICE software.Equivalent RLC model will be used for each interconnects.Extracted Device
parameter will be used for simulation.
Figure.4.1 Driver Interconnect Load System.
Combination of each device with all interconnects will be done to evaluate the parameters.
Table.4.1 Combination of Device and Interconnects
Driver Interconnects
36
CMOS • Cu
FinFET • SWCNT
• MWCNT
PNPN Tunnel FET
• MCB
Optimized Tunnel FET
• SLGNR
• MLGNR
4.3 Equivalent RLC model of Interconnects:
4.3.1 Copper (Cu):
Equivalent RLC model of Copper interconnect is as shown in Figure.4.2. RLC parameter are
calculated by the equation 4.1 - 4.5 given below.
Figure.4.2Equivalent RLC model of copper [40]
𝜌𝑙
𝑅= (4.1)
𝑤𝑡
3.19 0.76 0.12

𝑤 𝑠 𝑠 𝑡
𝐶 = 𝜀 [ + {2.22 ( ) } + 1.17 ( ) ( ) ] (4.2)
ℎ 𝑠 + 0.7ℎ 𝑠 + 1.51ℎ 𝑡 + 4.53ℎ
37
𝑙
𝑀=𝜇 2𝑙 𝑑
(4.3)
2𝜋 [𝑙𝑛 ( 𝑑 ) − 1 + 𝑙 ]
2𝑙 1 0.22(𝑤 + 𝑡)
𝐿 = 𝜇𝑙/2𝜋 [𝑙𝑛 ( + + )] (4.4)
𝑤+𝑡 2 𝑙
𝜀 = 𝜀𝑟 + 𝜀𝑜 (4.5)
Where R-Resistance, ρ-Resistivity, l-Length ofinterconnect, w-Width, s-Spacing, t-Thickness, d-

distancebetween two layers, εo= 8.8541878176 × 10−12 F/m, εr-Relativedielectric permittivity of
copper, μ –Permeability.
4.3.2Carbon NanoTube (CNT):
4.3.2.1 SWCNT:
Single-walled CNTs(SWNTs) consist of single graphite sheet seamlessly wrapped into a
cylindricaltube. Figure.4.3 shows the equivalent RLC model for a Single walled CNT
interconnect.
Figure.4.3 Equivalent RLC model of SWCNT interconnects [40].
RLC parameter can be calculated by given equation.
38
ℎ
𝑅𝑓 = (4.6)
4𝑒 2
1
𝐶𝐸 = 2𝜋 ∈ 𝑦
(4.7)
𝑙𝑛 (𝑑)
2𝑒 2
𝐶𝑞 = (4.8)
ℎ𝑣𝑓
𝜇 𝑦
𝐿𝑀 = 𝑙𝑛 ( ) (4.9)
2𝜋 𝑑
ℎ
𝐿𝐾 = (4.10)
2𝑒 2 𝑣𝑓
Where Rf-Fundamental Resistance, CE-Electrostaticcapacitance, CQ-Quantum capacitance, LM-

Magneticinductance, LK-Kinetic inductance, h= 6.626 × 10−34 joules (Planck’s constant),ε-
Electric field, y-Distance away from the ground, d-Diameter, e = 1.60217662 × 10-19 coulombs
(Electron charge), vf= 1 × 106m/s (Fermi velocity).
4.3.2.2 MWCNT:
MWCNT consists of several SWCNTs with varying diameter nested concentrically inside
one another. Figure.4.4 shows the equivalent RLC model for a Multiwalled CNT. The number of
channels can be calculated from the formula
𝑁 = 𝑎. 𝐷 + 𝑏; 𝐷 > 3𝑛𝑚 (4.11)
Where constant a = 0.0612 nm-1, constant b = 0.425,
D-diameter of the shell
𝐷𝑖 = 𝐷𝑚𝑎𝑥 − 2𝛿(𝑖 − 1) (4.12)
δ- van der Waals gap, Dmax- Outer shell diameter
The number of channels in ith shell is given by
𝑁 = 𝑎. 𝐷𝑖 + 𝑏 (4.13)
39
Figure.4.4Equivalent RLC model for MWCNT interconnects [42].
RLC parameter can be calculated by given equation.
ℎ ℎ 𝐿
𝑅 = 𝑅𝑞 + 𝑅𝑆 . 𝐿 = 2
+ 2
( ) (4.14)
2𝑁𝑒 2𝑁𝑒 𝜆
𝑅𝑄 = ℎ/4𝑒 2 ≈ 6.45𝐾Ω/𝜇𝑚 (4.15)
𝜇 2𝐻
𝐿𝑀 = ( ) cosh−1 (4.16)
2𝜋 𝐷
ℎ 1
𝐿𝑘/𝐶ℎ𝑎𝑛𝑛𝑒𝑙 = ( ) ( ) = 8 𝑛𝐻/𝜇𝑚 (4.17)
2𝑣𝑓 2
𝐿𝑘/𝑆ℎ𝑒𝑙𝑙 = 𝐿 𝑘 /(𝑎. 𝐷 + 𝑏) (4.18)

𝐶ℎ𝑎𝑛𝑛𝑒𝑙
2𝑒 2
𝐶𝑄/𝐶ℎ𝑒𝑛𝑛𝑒𝑙 = 2 ( ) = 193 𝑎𝐹/𝜇𝑚 (4.19)
ℎ𝑣𝑓
𝐶𝑄/𝑆ℎ𝑒𝑙𝑙 = 𝐶𝑄/𝐶ℎ𝑎𝑛𝑛𝑒𝑙 × (𝑎. 𝐷 + 𝑏) (4.20)
2𝜋𝜀
𝐶𝐸𝑆 = (4.21)
cosh−1 (2𝐻/𝐷)
2𝜋𝜀 2𝜋𝜀
𝐶𝑠 = 𝐷
= 𝐷𝑜𝑢𝑡
(4.22)
𝑙𝑛 ( 𝐷𝑜𝑢𝑡) 𝑙𝑛 [𝐷 ]
𝑖𝑛 𝑜𝑢𝑡 −2𝑑
40
𝐺𝑇 = 𝜎𝜋𝐷 (4.23)
Where RQ-Quantum contact resistance, RS- Scattering induced resistance, L-Length of the shell,
λ-Mean free path (MFP), N-Number of conducting channels, LM- Magnetic inductance, LK-
Kinetic inductance H- Separation between the nanotube center and ground, D- Diameter of each
shell, CQ-Quantum capacitance, CS-Shell to shell capacitance, CE-Electrostatic capacitance, GT-
Tunneling transconductance (negligible).
4.3.2.3 MCB
Mixed CNT bundle consist of two types of tubes i.e. SWCNTs and MWCNTs. A mixed
SWCNT/MWCNT bundle consists of SWCNTs with a diameter d and MWCNTs with various
diameters Dinner ≤ di ≤ Douter. Since MWCNT have two or more SWCNT, thus no. of shells (NS)
present in MWCNT depends on diameter and is given by
𝐷𝑜𝑢𝑡𝑒𝑟 − 𝐷𝑖𝑛𝑛𝑒𝑟
𝑁𝑠 = 1 + (4.24)
2𝛿
Where δ=0.34nm (van der Waals distance) is the spacing between adjacent concentric shells.
Also Douter and Dinnerare the maximum and minimum shell diameters. The approximate number
of conduction channels per shell for an MWCNT is
𝑁𝑐ℎ𝑎𝑛𝑛𝑒𝑙 (𝑑) = (𝑎𝑑 + 𝑏)𝑃𝑚 𝑑 > 6𝑛𝑚 (4.25𝑎)
𝑠ℎ𝑒𝑙𝑙
= 2𝑃𝑚 𝑑 < 6𝑛𝑚 (4.25𝑏)
Where a = 0.1836 nm-1, b = 1.275, d is the shell diameter and Pm i.e. probability of metallic
tube is equal to 1/3 (similar to an SWCNT bundle). A new approach for mixed CNT bundle
equivalent RLC circuit is shown in figure.4.4 which contains equivalent circuit of bundle
SWCNT and bundled MWCNT interconnects.
41
Figure.4.4Equivalent RLC model for Mixed CNT bundle interconnects [41].
Coupling capacitance (CB) that can be expressed as

𝜋𝜀𝑙
𝐶𝐵 = (4.26)
𝑑𝑐−𝑐 𝑑𝑐−𝑐 2
𝑙𝑛 [( ) + √( ) + 1]
2𝑟 2𝑟
Where dc-c is the distance between the center of any two CNTs, l is the length of nanotube and r
is mean radius of two CNTs.
The resistance for a mixed CNT bundle is given by
−1
𝑁(𝐷𝑜𝑢𝑡𝑒𝑟 )𝜕𝐷𝑜𝑢𝑡𝑒𝑟
𝑅𝑚𝑖𝑥 𝑏𝑢𝑛𝑑𝑙𝑒 = (∫ ) (4.27)
𝑅𝑀𝑊𝐶𝑁𝑇 (𝐷𝑜𝑢𝑡𝑒𝑟 𝑙)
Where 𝑅𝑀𝑊𝐶𝑁𝑇 (𝐷𝑜𝑢𝑡𝑒𝑟 𝑙) is total resistance of MWCNT &𝑁(𝐷𝑜𝑢𝑡𝑒𝑟 ) is the tube count for given
Douter ,for Nbundle CNTs in the bundle it is expressed as
42
2
𝑁𝑏𝑢𝑛𝑑𝑙𝑒 1 𝐷𝑜𝑢𝑡𝑒𝑟 − 𝐷𝑜𝑢𝑡𝑒𝑟
𝑁(𝐷𝑜𝑢𝑡𝑒𝑟 ) = 𝑒𝑥𝑝 [− ( ) ] (4.28)
𝜎𝐷𝑜𝑢𝑡𝑒𝑟 √2𝜋 2 𝜎𝐷𝑜𝑢𝑡𝑒𝑟
where𝐷𝑜𝑢𝑡𝑒𝑟 is mean diameter
The inter shell coupling capacitance Cc in an MWCNT and the electrostatic coupling capacitance
CE between two adjacent CNTs are considered along with the electrostatic capacitance of the
outermost shells of the bundle. Thus the total capacitance of the mixed CNT bundle after
including Cint will be given by
1 1 1 1 1
= + + + (4.29)
𝐶𝑏𝑢𝑛𝑑𝑙𝑒 𝐶𝑄𝑆𝑊𝐶𝑁𝑇 𝐶𝐸𝑆𝑊𝐶𝑁𝑇 𝐶𝑀𝑊𝐶𝑁𝑇 𝐶𝑖𝑛𝑡.𝑏𝑢𝑛𝑑𝑙𝑒
where CQSWNT& CESWCNT are quantum and electrostatic capacitance of SWCNT,CMWCNT = total
MWCNT capacitance and Cint.bundle is inter-CNT coupling capacitance and is given by
2𝜋𝜀
𝐶𝑖𝑛𝑡.𝑏𝑢𝑛𝑑𝑙𝑒 = 𝑏
(4.30)
𝑙𝑛 ( )
𝑎
Where ‘a’ is inner CNT radius & ‘b’ is the radius of circle formed by outer CNT.
The inductance of Mixed CNT arises from two source magnetic inductance (LM) of mix
bundle and the kinetic inductance (LK) of mix bundle. The total kinetic inductance of a mixed
bundle is the parallel inductance value of all the conduction channels in the bundle and is given
by
𝐿𝐾 𝑐ℎ𝑎𝑛𝑛𝑒𝑙
𝐿𝑘 𝑚𝑖𝑥 𝑏𝑢𝑛𝑑𝑙𝑒 = (4.31)
𝑁𝑐ℎ𝑎𝑛𝑛𝑒𝑙,𝑏𝑢𝑛𝑑𝑙𝑒
Where
𝑁𝑐ℎ𝑎𝑛𝑛𝑒𝑙,𝑏𝑢𝑛𝑑𝑙𝑒 = ∑ 𝑁(𝐷𝑜𝑢𝑡𝑒𝑟 ) × ∑ 𝑁𝑐ℎ𝑎𝑛𝑛𝑒𝑙 (𝑑) (4.32)

𝑠ℎ𝑒𝑙𝑙
𝐷𝑚𝑎𝑥 𝐷
4.3.3Graphene Nanoribbons (GNR):
4.3.3.1 Single-layer GNR:
43
Single-layer GNR consist of single layer of Graphene sheet. Figure.4.5 shows the equivalent
circuit for a single-layer GNR.
Figure.4.5 Equivalent RLC circuit model for SLGNR interconnect [40]
ℎ
𝑅𝑞 = (4.33)
2𝑒 2 𝑁𝑐ℎ
ℎ 𝑙
𝑟𝑠 = × (4.34)
2𝑒 2 𝑁𝑐ℎ 𝜆
ℎ
𝐿𝑘 = (4.35)
4𝑒 2 𝑣𝑓 𝑁𝑐ℎ
𝜇0 𝑑
𝐿𝑒 = (4.36)
𝑤
4𝑒 2 𝑁𝑐ℎ
𝐶𝑞 = (4.37)
ℎ𝑣𝑓
𝜀𝑤
𝐶𝑒 = (4.38)
𝑑
𝐸𝑖 − 𝐸𝐹 −1 𝐸𝑖 + 𝐸𝐹 −1
𝑁𝑐ℎ = ∑ [1 + 𝑒𝑥𝑝 ( )] + ∑ [1 + 𝑒𝑥𝑝 ( )] (4.39)
𝐾𝐵 𝑇 𝐾𝐵 𝑇
Where Rq- quantum resistance, rs- per unit lengthresistance, Rmc- contact resistance (in this paper
weassumed Rmc-20KΩ), h-plank’s constant, λMFP- mean freepath(mean free path for SLGNR
450w), e-electroniccharge, l-length of the interconnect, d-distance fromground plane, vf -Fermi
velocity, w- interconnect width,μ0- permeability of free space, ε-permittivity, Nch- numberof
44
conducting channels in one layer, EF- Fermienergy, Ei=ΔE|i+β| (β=0 for metallic GNR and β=1/3
forsemiconducting ones) and ΔE=hvf/2w is the band gapbetween subbands in GNRs.
4.3.3.2 Multilayer GNR:

Multilayer GNR consist of two or more layer of graphene sheet placed over one onther.
Figure.4.6 shows the equivalent circuit for a Multilayer GNR.
Figure.4.6 Equivalent RLC model of MLGNR interconnect [23]
Number of conducting channels (Nch) of each layer in MLGNRtakes into account the
effect of spin and sub-lattice degeneracy of carbon atoms and primarily depends on the width,
Fermi energy (Ef), temperature (T) and can be expressed as
𝑛𝐶 −1 𝑛𝑉 −1
(𝐸𝑛 −𝐸𝑓 )⁄ (𝐸𝑛 +𝐸𝑓 )⁄
𝑁𝐶𝐻 = ∑ [𝑒 𝑘𝑇 + 1] +∑ [𝑒 𝑘𝑇 + 1] (4.40)
𝑛=0 𝑛=0
where k, nC and nV represent the Boltzmann constant, number of conduction and valence bands,
respectively. En is the lowest/highest energy of nth sub-band in conduction/valence band.
Depending on the current fabrication process, the imperfect metal-MLGNR contact

resistance (Rmc) has a typical value ranging from 1 kΩ to 20 kΩ. Each layer of MLGNR exhibits
45
lumped quantum resistance (Rq) that is due to the quantum confinement of carriers across the
interconnect width and can be expressed as
𝑗,𝑗 ℎ
𝑅𝑞 = (4.41)
2𝑒 2 . 𝑁𝐶𝐻
For longer interconnects, scattering resistance appears due to the static impurity scattering,
defects, line edge roughness scattering (LER). The primarily depends on the effective MFP of
electrons (λeff) and can be expressed as
ℎ
𝑅 ′𝑗,𝑗 = (4.42)
2𝑒 2 . 𝑁𝐶𝐻 . 𝜆𝑒𝑓𝑓
λeffof each sub-band can be expressed as
1 1 1
= + (4.43)
𝜆𝑒𝑓𝑓 𝜆𝑑 𝜆𝑛
Where λn is the MFP corresponding to scattering effects due to edge roughness and λd is the
overall effective MFP of several scattering mechanisms of electrons in nanotubes, including
acoustic and optical phonon scattering as well as impurity and defect scattering.
′𝑗,𝑗
Each layer in MLGNR comprises of kinetic inductance 𝐿𝑘 and quantum capacitance
′𝑗,𝑗
𝐶𝑞 that represents the mobile charge carrier inertia and the density of electronic states,
respectively.
Kinetic inductance and quantum capacitance:
′𝑗,𝑗 𝐿′𝑘0
𝐿𝑘 = (4.44)
2𝑁𝐶𝐻
ℎ
𝐿′𝑘0 = (4.45)
2𝑒 2 𝑣𝐹
′𝑗,𝑗 ′
𝐶𝑞 = 2𝐶𝑞0 𝑁𝐶𝐻 (4.46)
46
′
2𝑒 2
𝐶𝑞0 = (4.47)
ℎ𝑣𝐹
Where vF≈ 8×105m/s represents the Fermi velocity of carriers in graphene. The electrostatic
capacitance (C'e) is due to the electric field coupling between the bottom most layer of MLGNR
and the ground plane. Therefore, the C'eis primarily dependent on the MLGNR width (w) and the
distance (d) from the ground plane. Apart from this, the magnetic inductance (L'e) of MLGNR is
due to the stored energies of carriers in magnetic field.
Electrostatic capacitance and magnetic inductance:
′𝑗,𝑗 𝜇0 𝜇𝑟 𝑑
𝐿𝑒 = (4.48)
𝑤
𝜀0 𝜀𝑟 𝑤
𝐶𝑒′ = (4.49)
𝑑
The inter-layer mutual inductance (L'm) and capacitance (C'm) are mainly due to the electron
tunnel transport phenomenon in adjacent layers. The L'mand C'mcan be expressed as
Interlayer mutual inductance and capacitance:
′(𝑗−1,𝑗) 𝜇0 𝛿
𝐿𝑚 = (4.50)
𝑤
′(𝑗−1,𝑗) 𝜀0 𝑤
𝐶𝑚 = (4.51)
𝛿
47
CHAPTER 5
SIMULATION SOFTWARE
In the dissertation mainly software tools will be used to simulate and analyze the
performance of interconnects and to design the devices and to calculate the various parameters.
No hardware isdesigned in the dissertation.
 Cogenda Genius TCAD:

 Visual TCAD is a graphical user interface for device simulator Genius.Visual TCAD is
capable of device simulation of 2D and 3D, SPICE circuit simulation and mixed
device/circuit simulation.
 It consists of the following modules
 Device structure drawing tool
 Circuit schematic capturing tool
 GUI simulation controller
 Visualization tool of simulation results
 Spreadsheet
 X-Y plotting tool
 HSPICE:
 SPICE is a general purpose analog electronic circuit simulator. HSPICE is one of SPICE
variations commercialized by a company Meta Software.
 HSPICE is an analog circuit simulator capable of performing transient, steady state, and
frequency domain analyses.
 Like traditional SPICE simulators, HSPICE is faster and has more capabilities than
typical SPICE simulators.
 It accurately simulates, analyzes, and optimizes circuits from DC to microwave
frequencies that are greater than 100 GHz.
48
 It is ideal for cell design and process modeling. It is also the tool of choice for signal-
integrity an transmission-line analysis.
49
CHAPTER 6
WORKFLOW
The Project stage-Iwork accomplished as follows:
 Searching of latest Published papers.

 Selection of papers for project.
 Literature Survey.
 Gap identification.
 Creating problem statement.
 Finalization of Project topic.
 Defining a Methodology.
 Software Platform finalization.
 Collection of resources.
 Documentation of Project.
50
CHAPTER 7
SUMMARY
In this project performance analysis of emerging interconnects and their combination with
the devices beyond CMOS has to be done. As ITRS 2013 states that evaluation of energy
efficiency necessitates joint consideration of switch and interconnects options. Due to technology
scaling, CMOS performance is improved but leakage currents and power consumption is
increased also interconnect performance has been degraded. Hence new devices such as FinFET,
PNPN Tunnel FET and optimized TFET are also considered in this project. Copper interconnects
has been used since many decades until the problem aroused while technology reaches 45nm.
Hence new interconnect material such as Carbon NanoTube (CNT) and Graphene comes into
consideration. Therefore in this project performance ofconventional copper and these emerging
interconnect will be analyzed with the FinFET, PNPN TFET, optimized TFET and including
CMOS to compare which of these interconnect material suits best to which of the device
technology.
51
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IoT Based Smart Water supply management , monitoring Quality and consumption of water for

“IoT Based Smart Water supply management , monitoring

MRS. SAPANA D. PAWAR

Under the Guidance of

Department of Electronics & Telecommunication

PRAVARA RURAL ENGINEERING COLLEGE,LONI

Water supply management , monitoring Quality and consumption of

water for Smart City”submitted byMrs. Sapana D. Pawae to Savitribai Phule

Pune University, Pune for the partial fulfillment of degree of Master of

Engineering in Electronics &Telecommunication (VLSI & Embedded System) is a

during the academic year 2018-2019.

Prof.Shaikh S.A Prof. Turkane S.S Prof. Turkane S. M

STATEMENT OF ORIGINALITY DECLARATION

Place:- PREC, Loni Name Of Student

Date:- Mrs. Sapana D. Pawar

PREC, M.E. E & TC Page ii

First and foremost I would like to thank my respected Guide. Prof.Shaikh

I am also thankful to HOD Prof. Turkane S. M , (Department of

Finally, I wish to thanks my friends and my family for being supportive of

Place: Loni Mrs. Sapana D. Pawar

PREC, M.E. E & TC Page iii

PREC, M.E. E & TC Page iv

LIST OF FIGURES vii

LIST OF TABLES viii

PREC, M.E. E & TC Page v

4.3 Equivalent RLC model of Interconnects 35

PREC, M.E. E & TC Page vi

PREC, M.E. E & TC Page vii

PREC, M.E. E & TC Page viii

3. The high man-power cost to develop a large ASIC.

1. Minimum time to market as compared to ASICs.

2. FPGAs are excellent candidate for low volume production.

Figure.1.1(a) Abstract view of FPGA, (b) Basic logic element (BLE)

The technology roadmap is an ambitious document widely used as a guiding

Table.1.1 Parameter values for Future nodes by ITRS-2013 [24]

Year of production 2013 2014 2015 2016 2017 2018

Logic Node name 16/14 10 7

Vdd(high performance) 0.86 0.85 0.83 0.81 0.80 0.78

MPU-HP physical gate length (nm) 20 18 17 15 14 13

ASIC-LP physical gate length (nm) 23 21 19 17 16 15

Off current, Ioff(µA/µm) 0.1 0.1 0.3 0.3 0.3 0.5

1.2 Gap Identification:

Carbon generated materials are Carbon nanotube (CNT) and GrapheneNanoribbon

 To analyse/study emerging interconnects materials CNT and GNR.

S.D. Pable et al.proposed to improve the performance of subthreshold FPGA in terms of

Ahmet Ceyhanet al.investigated trade-offs between the technology parameters of various

Manoj Kumar Majumderet al.studying, analyzing, and comparing theperformance of CNTs

1) Low OFF-statecurrent and low sub-threshold swing (SS) and

2) AN ON-state current similar to that of a comparable single grain boundary poly-silicon

T. Okagakiet al.studied 16nm FinFET logic cellperformance comprehensively with accurate

3.1 Device Technologies:

Device technologies considered in the report are

Figure.3.1Cross section of CMOS Device [43].

Figure.3.2 Structure of DG FinFET

double-gate emergingdevice having huge potential to substitute bulk devices atnanometer

Advantages of FinFET are:

Table.3.1 Advantages of FinFET

Figure.3.4Energy band diagram of On and Off state of TFET

3.1.4 PNPN TunnelFET:

Figure.3.5 PNPN TFET structure

Parameters SGB PNPN TFET

The tunneling current can be expressed as follows [38]

𝐼 = ∫ 𝐹𝑠,𝑉 (𝐸)[1 − 𝐹𝑐,𝐶 (𝐸)]𝑁𝑉 (𝐸)𝑁𝐶 (𝐸)𝑇𝑡𝑢𝑛𝑛𝑒𝑙 𝑑𝐸 (1)