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VHDL Component Configuration

Component Configuration.
The generate statement. • In order to simulate a VHDL specification, an (entity
declaration / architecture body) pair has to be
associated to component instances.

This binding is called component configuration.

1. Component Configuration

2. Configuration Declaration There are three mechanisms provided in VHDL for

component configuration:
1. Default binding (see Fö. 2, slide 14).
2. Configuration specification (see Fö 2, slide 17).
3. Specification of Regular Structures
3. Configuration declaration.

4. The generate Statement

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Component Configuration Component Configuration (cont’d)

entity XOR_GATE is
Let us consider again the structural specification for the port(X, Y:in BIT; Z:out BIT);
four bit parity generator: end XOR_GATE;

architecture ARCH_XOR_1 of XOR_GATE is

begin
. . . . . . . . .
V(0)
end ARCH_XOR_1;
T1
V V(1) architecture ARCH_XOR_2 of XOR_GATE is
EVEN
T3 begin
V(2) . . . . . . . . .
T2 end ARCH_XOR_2;
V(3)

entity INV is
port(X:in BIT; Z:out BIT);
end INV;

entity PARITY is architecture ARCH_INV_1 of INV is

port(V:in BIT_VECTOR(3 downto 0); begin
. . . . . . . . .
EVEN:out BIT);
end ARCH_INV_1;
end PARITY;
architecture ARCH_INV_2 of INV is
begin
. . . . . . . . .
end ARCH_INV_2;

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Configuration Specification

Configuration Specification (cont’d)

use WORK.all;
architecture PARITY_STRUCTURAL of PARITY is
component XOR_GATE --component declaration
port(X,Y: in BIT; Z: out BIT);
end component; • Component configuration through configuration
component INV --component declaration specification is static.
port(X: in BIT; Z: out BIT);
end component;
-- configuration specifications: The respective architecture body has to be recompiled
for XOR1,XOR2:XOR_GATE use whenever we want to simulate with a new binding.
entity XOR_GATE(ARCH_XOR_1);
for XOR3:XOR_GATE use
entity XOR_GATE(ARCH_XOR_2);
for INV1:INV use
entity INV(ARCH_INV_1);
signal T1, T2, T3: BIT;
begin
-- component instantiation statements:
XOR1: XOR_GATE port map (V(0), V(1), T1);
XOR2: XOR_GATE port map (V(2), V(3), T2);
XOR3: XOR_GATE port map (T1, T2, T3);
INV1: INV port map (T3, EVEN);
end PARITY_STRUCTURAL;

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Configuration Declaration (cont’d)

Configuration Declaration use WORK.all;

architecture PARITY_STRUCTURAL of PARITY is
component XOR_GATE --component declaration
port(X,Y: in BIT; Z: out BIT);
end component;
• Component configuration can be performed outside component INV --component declaration
the architecture body which instantiates a certain port(X: in BIT; Z: out BIT);
component. end component;
signal T1, T2, T3: BIT;
begin
XOR1: XOR_GATE port map (V(0), V(1), T1);
• A configuration declaration is a design unit which can XOR2: XOR_GATE port map (V(2), V(3), T2);
be compiled separately. XOR3: XOR_GATE port map (T1, T2, T3);
In a configuration declaration the binding of all INV1: INV port map (T3, EVEN);
components which are part of a certain entity can be end PARITY_STRUCTURAL;
specified.
use WORK.all;
configuration CONFIG_1 of PARITY is
• The particular architecture body has not to be for PARITY_STRUCTURAL
recompiled when the binding is changed. for XOR1,XOR2:XOR_GATE use
entity XOR_GATE(ARCH_XOR_1);
end for;
for XOR3:XOR_GATE use
entity XOR_GATE(ARCH_XOR_2);
end for;
for INV1:INV use
entity INV(ARCH_INV_1);
end for;
end for;
end CONFIG_1;

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Specification of Regular Structures. The generate Statement (cont’d)

The generate Statement.
Consider a 4-bit shift register

• The generate statement is an efficient way to specify

designs with a regular structure. DFFx(0) DFFx(1) DFFx(2) DFFx(3)
A Z(1) Z(2) Z(3)
D Q D Q D Q D Q B
It provides a mechanism for conditional compilation. Clk
Q
Clk
Q
Clk
Q
Clk
Q

Clk

label_id : generation_scheme generate

concurrent_statements
end generate optional_id; The D flip-flop:

entity DFF is
• The generation_scheme can be for or if. port(D,CLK:in BIT; Q,QB:out BIT);
end Dff;

architecture DFF_BEHAVIORAL of DFF is

begin
process(CLK)
begin
if CLK=’1’ then
Q <= D after 5ns;
QB <= not D after 5ns;
end if;
end process;
end DFF_BEHAVIORAL;

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The generate Statement (cont’d) The generate Statement (cont’d)

The same using a generate statement with a for scheme:

The 4-bit shift register:

use Work.all;
entity SHIFT_4 is architecture SHIFT_GENERATE_1 of SHIFT_4 is
port(A,CLK:in BIT; B:out BIT); component DFF
end SHIFT_4; port(D,CLK:in BIT; Q,QB:out BIT);
end component;
use Work.all; signal Z: array(0 to 4) of BIT;
architecture SHIFT_SIMPLE of SHIFT_4 is begin
component DFF Z(0)<=A;
port(D,CLK:in BIT; Q,QB:out BIT); Q1:for I in 0 to 3 generate
end component; DFFx:DFF port map(Z(I),CLK,Z(I+1),open);
signal Z: array(1 to 3) of BIT; end generate;
begin B<=Z(4);
DFF1:DFF port map(A,CLK,Z(1),open); end SHIFT_GENERATE_1;
DFF2:DFF port map(Z(1),CLK,Z(2),open);
DFF3:DFF port map(Z(2),CLK,Z(3),open);
DFF4:DFF port map(Z(3),CLK,B,open);
end SHIFT_SIMPLE;

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The generate Statement (cont’d) The generate Statement (cont’d)

Irregularities can be handled using a generate statement with A shift register model of configurable length:
an if scheme:
entity SHIFT_N is
generic(LEN:integer);
use Work.all; port(A,CLK:in BIT; B:out BIT);
architecture SHIFT_GENERATE_2 of SHIFT_4 is end SHIFT_4;
component DFF
port(D,CLK:in BIT; Q,QB:out BIT); use Work.all;
end component; architecture SHIFT_N_GENERATE of SHIFT_N is
signal Z: array(1 to 3) of BIT; component DFF
begin port(D,CLK:in BIT; Q,QB:out BIT);
Q1:for I in 0 to 3 generate end component;
Q2:if I=0 generate signal Z: array(1 to LEN-1) of BIT;
DFFfirst:DFF port map(A,CLK,Z(1),open); begin
end generate; Q1:for I in 0 to LEN-1 generate
Q3:if I=3 generate Q2:if I=0 generate
DFFlast:DFF port map(Z(3),CLK,B,open); DFFfirst:DFF port map(A,CLK,Z(1),open);
end generate; end generate;
Q4:if I>0 and I<3 generate Q3:if I=LEN-1 generate
DFFx:DFF port map(Z(I),CLK,Z(I+1),open); DFFlast:DFF port map(Z(LEN-1),CLK,B,open);
end generate; end generate;
end generate; Q4:if I>0 and I<LEN-1 generate
end SHIFT_GENERATE_2; DFFx:DFF port map(Z(I),CLK,Z(I+1),open);
end generate;
end generate;
end SHIFT_N_GENERATE;

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Summary

• Component configuration can be performed in three

ways: default binding, configuration specification, and
configuration declaration.

• Configuration declaration provides the highest degree

of flexibility. Component configuration is performed in a
separate design unit. The units which instantiate the
components have not to be recompiled in order to
change the binding.

• The generate statement is typically used in order to

model designs with a regular structure.
It provides a mechanism for conditional compilation.

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