TN 423: VLSI CIRCUITS

Lecture 7a

MOS TRANSISTOR ANALYSIS

1
 Outline
1. Introduction
2. MOS Transistor
3. MOS Transistor Operation

2
 Introduction
Ω Digital integrated circuits almost exclusively use
the MOS
Ω BJT has application in analog electronics.
Ω Transistors differ from passive components
such as resistor, capacitor, inductor, and diode
in that MOS transistor output current and
voltage characteristics vary with the voltage on
a control terminal.
Ω Transistors have three terminals concerned with
signal transmission while passive elements
have two terminals.
3
 MOS Transistor
The figure shows a MOS Transistor

4
 MOS Transistor
Ω The bottom rectangular block of material is the Silicon
substrate often referred to as the bulk.
Ω There are four electronically active regions that are marked:
✓ gate (G),
✓ source (S), and
✓ drain (D), and
✓ the bulk terminal (B)
Ω The gate, drain, and source voltages are typically referenced
to the terminal B.
Ω The rectangular gate region lies on top of the bulk separated
by a thin Sio2 dielectric with thickness TOX.
Ω Tox electrically isolates the gate terminal from the
semiconductor crystalline structures underneath.
Ω Two other important dimensions are the transistor gate
length and width. 5
 MOS Transistor
Ω The gate oxide is made of oxidized silicon forming a non-
crystalline, amorphous SiO2.
Ω The gate oxide thickness (Tox) typically ranges from near
15 Å to 100 Å (1 Å = 1 Angstrom = 10-10 m).
Ω The region between the drain and source just under the
gate oxide is called the channel, and is where charge
conduction takes place.
Ω The distance from the drain to the source is called the
channel length (L) and the lateral dimension is the
transistor channel width (W)
Ω Transistor length and width are parameters set by the
circuit designer and process engineer.
Ω The width to length ratio (W/L) is linearly related to the
drain current capability of the transistor.
6
 Physical Structure of MOS

• nMOS transistor • pMOS transistor

7
 Physical Structure of MOS
Ω The channel area is where charge conduction
takes place.
Ω Electrons are the channel current in the nMOS
transistor
Ω Holes are the channel current in the pMOS
transistor.
Ω Drain and source dopants are opposite to the
substrate (bulk), they form pn junction diodes
that are either reverse or zero biased in normal
operation

8
 MOS Transistor Operation
Ω The MOS transistors have three regions of
operation:
✓ Cutoff or sub-threshold region.
✓ Linear or Non-saturation region.
✓ Saturation region.

9
 MOS Transistor Operation
Ω Normal bias of nMOS

10
 MOS Transistor Operation
Ω The bulk or substrate of nMOS transistors must always
be connected to the lower voltage that is the reference
terminal.
Ω The bulk is usually connected to ground for an nMOS
Ω Assume that the bulk and source terminals are shorted
to simplify the description.
Ω The positive current convention in an nMOS device is
from the drain to the source and is referred to as IDS or
simply ID since drain and source current are equal.
Ω When a voltage is applied to the drain terminal, the ID
depends on the voltage applied to the gate control
terminal.

11
 MOS Transistor Operation
Ω Normal bias of pMOS

12
 MOS Transistor Operation
Ω The bulk or substrate pMOS transistors must
always be connected to the higher voltage that
is the reference terminal.
Ω The bulk of a pMOS is connected to the power
supply voltage
Ω Assume that the bulk and source terminals are
shorted to simplify the description.
Ω The positive current convention in an pMOS
device is from the source to the drain and is
referred to as I or simply ID since drain and
DS

source current are equal.

13
 MOS Transistor Operation

Case i: OFF state (non-conducting

state)
• If VGS =0 in an nMOS device,
then there are no free charges
between the drain and source
• There is no current when VGS =
0 for nMOS devices
• An applied drain voltage reverse-
biases the drain-bulk diode
• This is the an OFF state of a
transistor

14
 MOS Transistor Operation
Ω The same operation for pMOS transistor
Ω an applied drain voltage reverse-biases the
drain-bulk diode
Ω This is the OFF state of a transistor

15
 MOS Transistor Operation
Case ii: VGS Slightly increased/decreased
Ω When VGS of an nMOS (pMOS) transistor is
slightly increased (decreased) a vertical electric
field exists between the gate and the substrate
across the oxide.
Ω In nMOS (pMOS) transistors, the holes
(electrons) of the p-type (n-type) substrate close
to the SiO2 interface move away from the
interface.

16
 MOS Transistor Operation

• Deplete the nMOS • Deplete the pMOS

channel of holes with channel of electrons with
small positive values of small negative values of
gate-source voltage gate-source voltage.

17
 MOS Transistor Operation
Case iii: Further increase/decrease in VGS
Ω When VGS of the nMOS (pMOS) device is further increased
(decreased), the strong vertical electric field attracts minority
carriers (electrons in the nMOS and holes in the pMOS
device) from the bulk toward the gate.
Ω These minority carriers are attracted to the gate, but the SiO2
insulator stops them, and the electrons (holes) accumulate at
the silicon to oxide dielectric interface.
Ω These carriers form a minority carrier inversion region or
conducting channel that can be viewed as a “short-circuit”
between the drain and source regions
Ω When VD = VS and ID = 0, then the channel carrier distribution
is uniform along the device.
Ω This is called threshold voltage (Vt)
18
 MOS Transistor Operation
Ω The threshold voltage, Vt, for an MOS transistor is the
voltage applied between the gate and the source of a
MOS device below which the drain-to-source current Id ,
effectively drops to zero.
Ω The threshold voltage of an nMOS transistor Vtn is
positive, while Vtp is negative for a pMOS transistor
Ω An nMOS transistor has a conducting channel when the
gate-source voltage is greater than the threshold
voltage, i.e., VGS > Vtn
Ω A pMOS transistor has a conducting channel when the
gate-source voltage is less than the threshold voltage,
VGS < Vtp.

19
 MOS Transistor Operation

• Creating the conducting • Creating the conducting

channel for nMOS channel for pMOS

20
 MOS Transistor Operation
Ω The threshold voltage Vt is a function of a
number of parameters including the following
1. Gate conductor material.
2. Gate insulation material.
3. Gate insulator thickness-channel doping.
4. Impurities at the silicon-insulator interface.
5. Voltage between the source and the substrate, Vsb

21
 MOS Transistor Operation
Linear Region (non-saturated)
Ω If the channel horizontal electric field is of the same
order or smaller than the vertical thin oxide field, then
the inversion channel remains almost uniform along the
device length.
Ω This continuous carrier profile from drain to source puts
the transistor in a bias state that is equivalently called
either the non-saturated, linear, or ohmic bias state
Ω The drain and source are effectively short-circuited.
Ω This happens when
✓ VGS > VDS + Vtn for nMOS transistor
✓ VGS < VDS +Vtp for pMOS transistor
22
 MOS Transistor Operation
Saturation Region
Ω But if the nMOS VD increases beyond the limit
so that VGS < VDS + Vtn, then the horizontal
electric field becomes stronger than the vertical
field at the drain end, creating an asymmetry of
the channel carrier inversion distribution

Ngeze, LV VLSI Circuits 23

 MOS Transistor Operation
Ω If the drain voltage rises while the gate voltage
remains the same, then VGD can go below the
threshold voltage in the drain region.
Ω When this happens the inversion channel is
said to be “pinched-off” and the device is in the
saturation region.

24