SyncE Wander Testing for Marvell™ 88X3340P and

IDT 82P33731 – White Paper

By Leonid Goldin, Sr. Manager Verification Engineering, Timing Division, Integrated Device Technology; and Michael Rupert, Director Product
Marketing, Timing Division, Integrated Device Technology

Introduction
This white paper describes the successful testing of a combination of Marvell™ 88X3340/88X3340P multi-speed Ethernet Transceivers and
IDT 82P33731 Synchronous Equipment Timing Source (SETS) devices versus ITU-T G.8262, wander transfer, and wander tolerance testing.
The Marvell 88X3310/88X3310P and 88X3340/88X3340P devices are a family of one, two, and four port integrated multi-speed Ethernet
Transceivers. The devices support both copper and fiber interfaces. On the copper interface 10GBASE-T, 5GBASE-T, 2.5GBASE-T,
1000BASE-T, 100BASE-TX, and 10BASE-T are supported with Energy Efficient Ethernet (EEE).
The IDT 82P33731/82P33831/82P33931 family of SETS for 10G SyncE devices are used to manage timing references, clock generation, and
timing paths for SyncE based clocks, per ITU-T Recommendation G.8262. The devices output low-jitter clocks that can directly synchronize
40GBASE-R, 10GBASE-R, 10GBASE-W, and lower-rate Ethernet interfaces. The 82P33731 provides SETS functions only, while the 82P33831
and 82P33931 provide SETS and IEEE 1588 functionality. All devices in the family use the same SETS design and the test results presented
in this paper are valid for the three devices.

Synchronous Ethernet
Synchronous Ethernet (SyncE) is an effective method for distributing Primary Reference Clock (PRC) traceable frequency synchronization
within packet switched networks using the Ethernet physical layer. The long-term Fractional Frequency Offset (FFO) of a SyncE signal is the
same as the PRC to which it is traceable, which is less than 1 part in 1e11 per ITU-T Recommendation G.811. SyncE meets the frequency
synchronization needs of wireless technologies such as Universal Mobile Telecommunications System (UMTS) and Global System for Mobiles
(GSM); and of wireline technologies such as Synchronous Digital Hierarchy (SDH) and Time Division Multiplexing (TDM). SyncE based
frequency synchronization can be used to improve the reliability of time synchronization for 5G and 4G basestations that use IEEE 1588 for
time synchronization.
SyncE is defined in Recommendation ITU-T G.8261, which specifies the network limits for jitter and wander at synchronization interfaces.
Compliance with the jitter and wander characteristics in G.8261 ensures interoperability among equipment produced by different manufacturers.
The requirements for synchronous Ethernet Equipment Clocks (EECs) used in SyncE network equipment are outlined in Recommendation ITU-
T G.8262. Requirements such as jitter and wander generation; jitter and wander tolerance; and clock bandwidths, are specified by G.8262.
Two options for SyncE clocks are defined in G.8262: EEC Option 1 and Option 2. The EEC Option 1 clock is defined to allow backward
compatibility with the 2Mbps hierarchy, and the EEC Option 2 clock is defined to allow backward compatibility with the 1544Kbps hierarchy.
Figure 1 shows an example of a G.8261 compliant SyncE network. Every node in the network is equipped with a synchronous Ethernet
Equipment Clock (EEC) compliant with ITU-T Recommendation G.8262. The EEC in Node 1 locks to an external PRC reference and
synchronizes the Ethernet bit streams transmitted by the node. The EEC in Node 2 locks to the reference recovered from the incoming PRC
traceable Ethernet bit stream and synchronizes the Ethernet bit streams transmitted by the node. This process is repeated until the final node
in the network where a PRC traceable reference timing signal can be output on an external port.

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Figure 1. G.8261 Compliant SyncE Network

PRC

Node 1 Node 3
Packet Switched Network

PRC Traceable
Reference Timing Signal
EEC Ethernet Ethernet EEC
Physical Physical
Node 2
Layer Layer

EEC

PRC = Primary Reference Clock EEC Ethernet Switch Supporting

EEC = synchronous Ethernet Equipment Clock per ITU-T G.8262 Synchronous Ethernet

Figure 2 shows an example of the flow of synchronization signals within a typical SyncE node. In this example, port P0 recovers a line clock
from an incoming PRC traceable bit stream and provides that line clock as a network reference to the SyncE DPLL. The SyncE DPLL provides
a filtered and stable reference for the Ethernet PHY transmit PLL. The cut-off frequency of the transmit PLL in the PHY is set well above 10Hz
so that it does not interfere with the SyncE DPLL transfer function.
The SyncE DPLL is responsible for meeting the majority of the G.8262 EEC requirements, but G.8262 compliance is measured at the Ethernet
interface so compliance is at a system level.

Figure 2. Detail of SyncE Synchronization Signal Flow

Incoming Ethernet bit

stream
P0 Ethernet PHY Network
P1 Reference
REC CLK
SyncE Network
P2

P3 XO
Outgoing Ethernet bit
stream - ITU-T G.8262 SyncE Device
compliant
TCXO
DPLL output DPLL

• EEC Option 1 DPLL - loop filter cut-off between 1Hz and 10Hz
• EEC Option 2 DPLL - loop filter cut-off < 0.1Hz

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Marvell Ethernet Transceiver Configuration

The Marvell 88X3310/88X3310P and 88X3340/88X3340P multi-speed Ethernet Transceivers provide two recovered clock outputs, RCLK0 and
RCLK1. These pins can output a 25MHz clock that is derived from the 125MHz, 200MHz, 400MHz, or 800MHz recovered clock from the copper
receive path when linked to 100BASE-TX, 1000BASE-T, 2.5GBASE-T, 5GBASE-T, or 10GBASE-T. The 125MHz recovered clock is internally
divided by 5 with 60% low and 40% high. The 200MHz, 400MHz, or 800MHz recovered clocks are internally divided by 8, 16, 32 respectively,
with a 50% duty cycle. RCLK drives low when the link is down or when the copper receiver is linked to 10BASE-T.
The RCLK0 pin is enabled when register 31.F002.0 is set to 1, and the RCLK1 pin is enabled when register 31.F002.1 is set to 1. Each of these
bits should be set to 1 for only one port. If the same bit is set high for multiple ports then the highest numbered physical port that is enabled is
selected. Synchronous clocking is used so that the entire system runs locked in frequency with no frequency drift. The line clock recovered by
one port is used as the transmit reference clock for all of the ports.
The recovered line clock needs to be filtered by an external jitter attenuating PLL before it can be used as a transmit reference clock for other
ports in the system for a synchronous operation.

ITU-T Recommendation G.8262 Compliance Test Setup

To ensure accurate results, the Calnex Paragon-X measurement equipment was synchronized with GPS. The Paragon-X was used as SyncE
wander source and analyzer.
Prior to testing, the Paragon-X was calibrated according to the equipment test procedure.

Baseline Testing
The first test was done to establish a baseline using a single Marvell 88X3340P evaluation board. The board has four ports capable of running
1G, 2,5G, 5G, and 10G interfaces. The test setup is presented in Figure 3. A standard wander transfer test was done to verify that the SyncE
DPLL provided proper filtering and that the Ethernet transceiver operates correctly when a line clock recovered by the receiver side of the
device is provided as the system clock input of the transceiver.
Ethernet port 2 of the Paragon-X was configured for 1GE operation and as clock master. This test signal was connected to port 0 of the Marvell
88X3340P evaluation board. The 25MHz recovered line clock was connected to the IDT 82P33731 SyncE DPLL, which used a TCXO as its
system clock. The SyncE DPLL filtered the recovered line clock and multiplied it to 156.25MHz, which was connected to the CLKP/CLKN pins
of the PHY.
Ethernet port 1 of the Paragon-X was configured as a clock slave and was connected to port 3 of the Marvell 88X3340P.

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Figure 3. Baseline Test Setup

GPS

GPS Receiver

Paragon-X

Eth2 1GE
Master

Eth1 P0
Slave 88X3340P
P1 25MHz
REC CLK
P2

P3 XO
Outgoing Ethernet bit
stream - ITU-T G.8262
compliant
82P33731
TCXO
156.25MHz DPLL

The baseline testing also verified that the Ethernet transceiver does not impact the wander signal generated by the Paragon-X. This was done
by configuring the SyncE DPLL with a wide bandwidth of 1kHz and measuring wander passed to the Paragon-X Eth1 port. The resulting gain
on the wander signal through the Ethernet transceiver and the SyncE DPLL was 0dB, which is considered a pass for this test.

Multi-speed Testing
After the baseline testing was completed and passed, another test setup was used to verify proper SyncE operation at all of the speeds
supported by the transceiver. The multi-speed test setup used two Marvel Ethernet transceiver evaluation boards as displayed in Figure 4.
The Paragon-X was set up the same way as in the baseline test. Its Ethernet 1 (Eth1) port was connected to the first Marvell Ethernet transceiver
evaluation board, which was used as a rate convertor. The IDT SyncE DPLL connected to board 1 was configured with a wide bandwidth of
1kHz, and was used as a clock multiplier and jitter attenuator.
The output of the multiplying DPLL was connected to CLKP/CLKN of the Ethernet transceiver on board 1. As demonstrated during the baseline
testing, the Paragon-X wander signal passes through the rate converting Ethernet transceiver. Using this approach it was possible to generate
wander signals at any speed supported by the Marvel Ethernet transceivers.
The transmit side of port 2 of the rate converting Ethernet transceiver on board 1 was connected to the receive side of port 0 on the Ethernet
transceiver on board 2. The recovered wandering line clock from the board 2 provided as the reference of the IDT 82P33731 SyncE DPLL.
The SyncE DPLL was configured to filter its reference according to the ITU-T G.8262; both Option 1 (bandwidth = 1Hz) and Option 2
(bandwidth = 0.1Hz) were tested.
The filtered 156.25MHz clock from the SyncE DPLL connected to board 2 was provided as the system clock (CLKP/CLKN) of the Ethernet
transceiver. The transmit side of port 2 on board 2 was configured for 1GE speed, and was connected to Eth1 port of the Paragon-X which
measured the system output wander.
Master/Slave configuration of the PHYs ensured that the SyncE clock propagated properly through the system.

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Figure 4. Multi-speed Test Setup

GPS

1GE
GPS Receiver P0 88X3340P (board 1) Configured as a
P1 25MHz clock multiplier /
REC CLK
Paragon-X
P2
jitter attenuator

Eth2 P3 XO
Master 1GE /
2.5GE / 82P33731
5GE / XO
10GE 156.25MHz DPLL

Eth1 P0
Slave 88X3340P (board 2)
P1 25MHz
REC CLK
P2
Outgoing Ethernet bit
stream - ITU-T G.8262 P3 XO
compliant
82P33731
TCXO
156.25MHz DPLL

Speeds Tested
The compliance tests were run with the Ethernet interface between board 1 and board 2 running at each of 1G, 2.5G, 5G, and 10G. All wander
transfer and wander tolerance tests were passed with the same results as the baseline test.
Wander transfer for Option 1 requires the low pass filter cut-off to be between 1Hz and 10Hz, and gain peaking must not exceed 0.2dB. The
test result is presented in Figure 5.

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Figure 5. Option 1 Wander Transfer

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Wander transfer for Option 2 requires the low pass filter cut-off to be at 0.1Hz or lower; the test is conducted by combining multiple simultaneous
wander frequencies. The result must be below the mask presented in Figure 6.

Figure 6. Option 2 Wander Transfer

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Wander Tolerance Results

During this test a specific noise signal is applied to the input of the system. No errors or alarms should be caused by the wander. Compliance
was verified with the Link status for both active GE links. The Paragon-X indicates failures with the color red. The tester marks the test field as
green only when no errors occur.
Three tests were run – based on table, MTIE for Option 1, and TDEV from Option 2. The results are summarized in Figure 7 to Figure 9.

Figure 7. Wander Tolerance Tested with Values Presented in the Table

Figure 8. Option 1 Wander Tolerance Tested Based on MTIE

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 SyncE Wander Testing for Marvell™ 88X3340P and IDT 82P33731 – White Paper

Figure 9. Option 2 Wander Tolerance Tested Based on TDEV

Conclusion
By using Marvell 88X3310/88X3310P or 88X3340/88X3340P transceivers in conjunction with IDT 82P33731/82P33831/82P33931 SETS timing
devices in accordance with the guidelines in this white paper, system developers can easily implement SyncE-compliant systems that enjoy the
many benefits of frequency synchronization.

References
 Recommendation ITU-T G.811 (1997), Timing characteristics of primary reference clocks
 Recommendation ITU-T G.8261/Y.1361 (2013), Timing and synchronization aspects in packet networks
 Recommendation ITU-T G.8262/Y.1362 (2015), Timing characteristics of a synchronous Ethernet equipment slave clock

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Revision History
Revision Date Description of Change
February 16, 2018 Initial release

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