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Jan Craninckx
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Abstract
▪ High-performance, small form factor millimeter-wave radar systems are
key enablers for the new smart society. Application for automotive
driver assistance and even autonomous cars is obvious, but also many
other systems like vital signs monitoring, gesture recognition, self-guided
drones, etc are envisioned.
▪ The research presented in this talk investigates the use of nanoscale
CMOS technology for 79GHz radar systems, which will be a key
enabler to open up this market for cost-effective high-volume
production, and allows integration of large digital processing in the same
System-on-Chip. A new concept of phase-modulated radar detection is
also introduced that blends perfectly with the integration capabilities of
CMOS.
2
Why mmWave radars?
mmWave Sensors are Extremely Robust
noise &
vibration
fog
snow & rain smoke
dust
lighting dirt
4
heat
mmWave Sensors are Fully Sealed and Invisibly Mounted
discreet monitoring
perfect aesthetics
privacy
5
fixed
Radar
evolution
mobile
yesterday
automotive today
Angle
(improves with larger antenna)
7
10+ radars per car
▪ High-resolution, 360 degree radar coverage
Medium Range Radar
(MRR) up to 80m
10
Waveform Possibilities
Fast chirp
TX PA
VCO/PLL
FMCW Range-
Doppler
Fast-time Slow-time map
HPF LPF ADC
FFT FFT
RX LNA In-phase
(spillover
mixer (RMAX limit) Range Doppler
cancellation, processing processing
RMIN limit)
Bi-phase
mod Binary sequence
TX PA
PMCW LO Range-
Doppler
Correlator Slow-time map
LPF ADC
I,Q bank FFT
RX LNA Quadrature
mixer Range Doppler
11
processing processing
High Level Comparison: PMCW vs FMCW
PMCW FMCW
Ambiguity function, sidelobes +
Sensitivity to phase noise, flicker noise +
ADC resolution +
ADC speed / IF bandwidth +++
PSD +
Sensitivity to interference +/-
TX orthogonality for MIMO +
Communications capability ++
Industrial acceptance +++
easier market entry / limited IP and patents ++
12
PMCW Radar Operating Principle
2 Gbps
Tchip TX
Distance D
m Tchip 79 GHz LO
RX Target
0 ∫
0 ∫
0 ∫
0 ∫ Target at
G*m ∫ D = (4 * Tchip * C) / 2
0 ∫ C = speed of light in air
0 ∫ G = Path Loss
2 Gbps
Tchip TX
m Tchip 79 GHz LO
TX-to-RX
spillover
RX Target
Accumulations
improve SNR
FFTs
determine the frequency
shift of every range bin the
speed of the object found on
that range bin (Doppler)
Also improves SNR
15
System design, Implementation and Verification
System
design
Validation & IC
demonstration design
Module
& antennas
16
System design
Matlab chain
17
PMCW Radar-on-Chip: SISO Block Diagram
antennas
RF TC Range resolution
LC Ambiguous range
M Ambiguous speed
N Speed resolution
PRN code
High-speed digital front-end Reconfigurable digital baseband
ADCs
S
18
antennas
analog front-end
MIMO Block Diagram
PRN code
...
PRN code
High-speed digital front-end Reconfigurable digital baseband
ADCs
S
Integrate Lc Accumulate
ADC N-point DFT
pulses M pulses
PRN code
Peak
...
...
Lc parallel paths Lc parallel MIMO antennas
MIMO -
Beam-
array DoA
forming
synthesis estimation
Integrate Lc Accumulate -
ADC Lc parallel
pulses M pulses Tracking
PRN code
N-point DFT
19
IC – Module - Platform
IC module platform
TRX_CLKO
TRX_SYNC
NOC_CLK
NOC_RST
VDD18dig
TRX1_DO
TRX2_DO
TRX4_DO
TRX3_DO
VSS18dig
NOC_CE
TRX_DA
NOC_DI
NoC MS
NoC SL
VSSRX1dig VSSRX2dig
NoC SL
VDDRX1dig TX
TX TX
TX VDDRX2dig
PLL 2 TX VDDTX1
TX1P
VDDTX2
TX2P
∫
RF
NoC SL
NoC SL
VDDRX1 VDDRX2
Δ RX RX RX RX
MIMO PRF=1/(Tc*Lc) VSSRX1 VSSRX2
VGA ADC Prog.
PN-LEAK ∫ Fc=1/Tc=2Gbps
CANC Buffer VDDPLL VDDLO
1 00 1 111
2 RX
2 GHz CK
VDDBB18
VSSBB18
RX2IP
RX2IM
PLL_Fref
VDDBB18
VSSBB18
RX1QP
RX1QM
RX2QP
RX2QM
RX1IM
RX1IP
PA
ILO Int-N ILO
LNA IQ MX Modulator
(x5) PLL (x5)
LO-PLL PA
2 GHz CK
Prog.
PRN Code
Delay-Line
1 00 1 111
MIMO Prog.
PN-LEAK ∫ VGA ADC
Fc=1/Tc=2Gbps
Buffer
CANC PRF=1/(Tc*Lc)
Δ
∫
23
Inverter Based ILO for 79GHz
VDD
VDD
A=450mV
Tuned amplifier
iout∙e jΘ
A@ω0 iout∙ejΘ
A@ω0 @5ω0 A/3@3ω0 @5ω0
M1 A/5@5ω0 M1
ω0=15.8GHz * 2π
Vb .. Vb
..
Classical approach Inv based approach
20K Qvar=8.5~20
Qind=15
2 2 3 3 VCO+ VCO-
[3:0]
VDC VDC2 VDC
12um 16um
Lmos=35nm
Vinj+ Vinj-
M1 M2
9um 13.5um
M1:M2=5:1
84
82 -4
-90
74
0 5 10 -100 15
Varactor bits
-110 14dB±1dB
-120
-130
-140 4 6 8
10 10 10
26
Offset Frequency (Hz)
PLL and LO Distribution
Tx_ILO Tx_ILO TX
Cartesian combiner
In-Phase
ILOs
Combiner Combiner
I+ I- Q+ Q-
PPF for
Ibias,I Ibias,Q quadrature
phase shifters
2-stage PPF
RX
Div/N
(79)
Div/8 QILOs
CP-PLL To Dig/ADC VCO @
Rx_QILO Integer-N PLL 27
15.8 GHz Rx_QILO
Antenna Path Details
Analog BB and
ADCs
TX-to-RX Spillover
Transmitter side-lobe
cancellation Digital Core
suppression
RX Front-End Transmitter
Sub-harmonic Injection Locked Oscillators
multiply the PLL frequency by 5
28
TX architecture
CMOS IL-VCO Modulator CMOS28
15.8GHz
BUF (x5)
PA
29
79GHz Phase-Modulator
Linear BB Linear LO
X X
Non-linear LO Non-linear BB
1 0 0 1 0 1 .. Lc 79GHz
LO
PRN Code
generator PRN Code
generator
79GHz
79GHz
LO
LO 1 0 0 1 0 1 .. Lc
PRN Code 77 79 81 GHz
generator
1 0 0 1 0 1 .. Lc
77 79 81 GHz
• Lower 79GHz swing
• More power efficient
30
TX Sidelobe Reduction by Harmonic Rejection
1
79GHz
LO Σ
1
Tc=1/Fc
1 0 0 1 0 1 .. Lc
Delay
Tc/3 Δ
77 79 81 GHz
PRN Code
generator Most effective side-lobe
rejection @ lowest cost
31
79GHz Modulator and PA: Schematic Detail
HR3 0
MMX
Mixer 3-stage PA
Gain MPA
180 Tuner Balun
LOp VSMX CnPA
VGPA
VDD 240 VDD
LOm CnPA
BBin Prog. 60 VDD MPA
Delay-Line
Prog. Buffer
BBin
0°
60°
180°
240°
32
Receiver Implementation
Output To IO
I and Q
Buffer Pads
VDD
Gilbert cell Mixer
mixer
ADC
2dB Gain VGA
Buffer
VGA stage
k ≈ 3 → 10.5 dB
VDD
VDD in 7 steps
VDD VB ADC driver
2-stage LNA ≈-2dB gain
18dB Gain VBIAS RL
k Vout Vin
VDD
Vin Vout
RS
VBIAS
k
33
Vin
RX Spillover Cancellation
BB
BB Weighted copy of BB injected at the
VDD mixer outputs to cancel the spillover
Mix
OUT Mixer BB BB BB BB
C
R
WM
WP
LO- LO+ LO-
R C2 C2
BB
C
Correlation
VDD (multiplication with the TX sequence and integration)
LNA OUT
18 29 Out
D<6:0> 7 Data Out
interface
(from ADC) 1+1
CK CK/4
CK/<prog>
I and Q
1
To TX m’[k] CK gen Clock Out
TRX Sync
Data Available
CK (1.975 GHz)
35
Other antenna path
IC Realization
▪ 28nm CMOS
▪ Die size 3 x 2.63mm
▪ Supply 0.9V/1.8V
▪ Flip chip assembly
36
IC Floorplan
▪ 28nm CMOS
▪ Die size 3 x 2.63mm DIG. DIG.
CORE CORE
▪ Supply 0.9V/1.8V TX TX
ADC ADC
RX BB PLL RX BB
RX FE RX FE
37
IC Photograph
▪ 28nm CMOS
▪ Die size 3 x 2.63mm
▪ Supply 0.9V/1.8V
▪ Flip chip assembly
38
PLL Measurements
▪ 25 MHz reference
▪ 16GHz VCO
▪ VCO only Phase Noise
-116 dBc/Hz @ 10 MHz
▪ 2GHz VCO tuning range
corresponding to 78 to
88 GHz at TX output
▪ 79GHz ILO
▪ -107dBc/Hz @ 10 MHz
1 AP
-30
4 GHz BW
VIEW
▪ 4 GHz BW
-40
2 AP
1
CLRWR
-50
-60
EXT
-70
3DB
BPSK
-80
-90
SideLobe Supp
-100
-110
Measured with SAGE E band WR12 horn antenna, R&S FS-Z90 and FSU
Date: 15.DEC.2015 15:19:49
40
Receiver Measurements
Measured with NOISE COM 5112 and R&S FSU on a dedicated module with GSG pads instead of antennas
Base Band Analog output before the ADC measured
41
Indoor Antenna Module and Evaluation Board
2 dies on the
back of the
module
Antennas on the
front
Panasonic MegTron6® 42
PMCW Demonstrator
Matlab
framework
for data analysis
Radar module (2 chips):
• 4 TX antennas in azimuth
• 4 RX antennas in elevation
• MIMO configuration results in 2x2 and 4x4 array
• Targets can be localized in both azimuth and elevation
RCS = 15dBsm
RCS = 10dBsm
45
MIMO 4x4 Measurements
Angle of Arrival:
46
Conclusions
▪ CMOS Radar SoCs area key building block for next-generation (self-
driving) cars
▪ And smart homes, buildings, things, etc.
▪ PMCW radar system is a feasible alternative for current FMCW
architectures
▪ Major advantage for large-scale radar imagers
▪ IMEC PMCW radar SoCs prototypes show functionality
▪ And are used by partner companies in various application experiments
▪ The future is still to come; we haven’t seen the last innovation in radars
yet ☺
47
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