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Proceedings of the 2nd National Level Technical Student Paper Presentation, 14th October 2011.


POWER BUS ARCHITECTURE – An Alternative approach


Electronics and Communication Engineering Department, SJBIT,
BGS Health & Education City,
Kengeri, Bangalore – 560060.
b.s.balaji22@gmail.com, rekha.sjbit@gmail.com.

 particular attention has to be given for driving nodes with

Abstract— The Low power bus architecture consists of large capacitive loads. Two techniques have been mainly
Driver, Receiver and Interconnects in between them inside the proposed for the decrease of the power dissipation in high
Chip. The Low power bus architecture models are classified in capacitive loads. The first one reduces the power consumption
to Symmetric and Asymmetric based on low voltage scaling by reducing the voltage swing on the node, while the second
technique and very simple design principles were utilized to
one by implementing a charge-recycling procedure. A number
construct driver, receiver and interconnects. The proposed
driver has the ability to switch from a low swing to high swing
of different solutions have been presented based on the above
mode. The receiver can be a simple inverter. The proposed bus techniques.
architecture consists of a driver which has an input the nominal Most of the presented solutions are based on the reduced
voltage value level and decreases the voltage swing on the bus voltage swing technique and are addressed on the bus
line (or the output load); and a receiver which regenerates the architectures. In this case, additional Circuitry consisting of a
proper voltage levels in order to ensure the compatibility with driver and a receiver for each line of a bus is required.
the attached circuits. These bus architectures are designed in Although, a high reduction in power consumption can be
conventional CMOS technology and Pseudo NMOS technology. achieved, they meet a number of constraints which reduce
The proposed bus architectures were implemented on 2.0V
their usability. Factors like the power reduction, the
0.25μm CMOS technology using T-Spice, for signal transmission
along a wire-length of 3mm, 6mm, and 10mm and the extra fan-
technology requirements, the Design complexity, the area
out load of 0.12 pF (on the wire). The performance of each of the occupied and the attainable speed have to be considered in
presented circuits is thoroughly examined using simulation on a order to evaluate these solutions. The major disadvantage is
test benchmark interconnect circuit (i) RC─π (N) type (where N high capacitor loads in on chip driver which are not
= 1, 2, 3), (ii) RC−L type. Comparisons of the proposed supported by CMOS devices during fabrication.
architecture with conventional CMOS architecture are This paper is organized as follows. Section II presents the
presented as well, indicating a significant saving in power due to interconnect test bench mark and circuit topology for the
low voltage scaling. The advantages of the proposed previous four representative works with its device parameters
architectures are that they require only one power supply and
in CMOS design and a prototype CMOS design along it we
threshold voltage as well as less area, hence significantly
design the four circuits in Pseudo NMOS design and compare
reducing the design complexity.
these designs with respect to 0.25μm technology. Section III
Index Terms—Pseudo NMOS Logic design, Previous and presents the circuit structure for the proposed Pseudo NMOS
Present Digital CMOS design, 0.25μm technology, Bus design. Comparative measurement results and analysis are
architecture, and Interconnect Length, Low Power and reported in Section IV. Finally, Section V concludes the
Performance tradeoffs. paper.


In today’s world of VLSI Design, the new trends are The Interconnect Test bench mark we use in this paper is
emerging based on the Moore’s Law which states that ―In shown in Figure 1, which is the same used for previous
every two years the number of transistors in Integrated models. All circuits were implemented in 0.25μm technology
Circuits will be double‖. Similarly, the most important from TSMC. We analyzed all the signaling schemes under
Design issue for the current and future VLSI Circuits is the the identical loading condition, power supply Vin = 2.0V,
reduction of power consumption. In CMOS digital Circuits, Vdd = 2.0 V, and Vbus = 1.0 V.
the major part of the power is dissipated during charging and All circuits are simulated with a receiver output load
discharging of the output load capacitance of the gates. Thus, capacitance of 0.12pF. The interconnect is implemented in
metal—N layer, (where N = 1, 2, 3) with its length varies
when N = 1 the range is 0.3mm to 3mm, N = 2 the range is

Department of Electronics & Communication, SJBIT, Bangalroe-60. -1-

Proceedings of the 2nd National Level Technical Student Paper Presentation, 14th October 2011.

0.6mm to 6mm and N = 3 the range is 1mm to 10mm. The power and are very fast. However, the level converters require
interconnect π-wire is modeled by a πN distributed two power supplies; Vddl, (conveniently can be set to Vbus),
resistance–capacitance (RC) model (Rw = 180 Ω/mm and Cw and Vddh. They also require nMOS devices with two
= 0.13 pF/mm). An extra capacitive load CL of 0.12 pF per different threshold voltages, Vtnl (lower threshold voltage)
mm length of wire is distributed along the wire for the fanout. and Vtnh (high threshold voltage). Unfortunately, there is no
reported suitable low complexity circuit design, in the
literature, for the level restorer at the receiver side for the
LHOS signaling schemes. This paper introduces four low
power Pseudo NMOS signaling schemes with high driving
capability at the driver side and suitable matching low power
level restorer at the receiver side. We compare our proposed
schemes with four other related designs. The set of quality
metrics used for the comparative evaluation are delay
performance, power dissipation, area, design complexity, and
noise sensitivity.

Figure 1(a) Interconnect Test Bench Mark.

Figure 2 Circuit structure for the low-high offset symmetric

Figure 1 (b) The π-wire model. (LHOS) CMOS driver-receiver ddc-db with Vdd = 2.0 V.

Fig. 2 (ddc-db), Fig. 3 (asf-lc) Fig. 4 (mj-sib) and Fig. 5

(mj-db) present the circuit topologies for the four previous
works we use as the basis for the comparison. The topology in
Fig. 2 is the LHOS scheme. The topology in Fig. 3 is the
combination of high performance HOA style source follower
driver at the driver end, and the matching level restorer
circuit at the receiver end.
The signaling schemes for the long interconnect lines are
categorized according to the direction of the swing voltage
reduction in the signal. In the high offset asymmetric (HOA) Figure 3 Circuit structure for the HOA CMOS driver-receiver
low-swing voltage scheme, the range of signal level on asf-lc, with Vdd = 2.0 V, Vbus = 1.0 V
interconnect is between 0 and Vbus, where Vbus < Vdd, and
Vdd is the nominal power supply used by the computational
blocks at the driver and receiver sides of the interconnect. In
the low offset asymmetric (LOA) scheme the signaling
voltage range is between Vbus and Vdd, where Vbus > 0. The
LHOS signaling scheme is preferred to the HOA and LOA
schemes as it works well with a simple inverter at the receiver
end, without significant static power dissipation. The circuits
are unlike most alternatives, requires neither extra power
supply nor a multi-threshold process. However, in addition to
low driving capability, its performance is sensitive to Figure 4 Circuit structure for the LHOS CMOS driver-receiver
variations in the power supply, device parameter, and loading (mj-sib), with Vdd = 2.0 V.
condition. The interconnect signaling schemes employing
low-swing bus drivers; require suitable matching level
converters at the receiver end. If the receiver is not designed
properly it results in excessive static power dissipation and
loss of performance. The work proposes a series of level
converters in the HOA signaling schemes that consume low

Department of Electronics & Communication, SJBIT, Bangalroe-60. -2-

Proceedings of the 2nd National Level Technical Student Paper Presentation, 14th October 2011.

Figure 5 Circuit structure for the LHOS CMOS driver-receiver

(mj-db), with Vdd = 2.0 V.

All the four circuit topologies from previous works are driver-receiver (mj-db), with Vdd = 2.0 V

designed in Pseudo NMOS logic design again and it

represented as below in the following figures. IV. COMPARATIVE EVALUATION

A. Power Consumption Evaluation

The Average Power Consumption is measured from all
these circuit structures like (i) Previous work, (ii) CMOS
design and (iii) Pseudo NMOS design using Tanner EDA
tool - 0.25μm technology from TSMC and also with respect
to Interconnect Length.


Average Power Consumption of π1 Short Interconnect

at 0.25µm Technology

Figure 6 Circuit structure for the low-high offset symmetric LENGTH 0.3mm 1.5mm 3mm
(LHOS) Pseudo NMOS driver-receiver ddc-db with Vdd = 2.0 V. PREV 1.76E-07 5.18E-08 4.76E-08

ASFLC CMOS 4.81E-08 1.10E-07 2.94E-07

NMOS 9.82E-08 1.05E-07 3.54E-07

PREV 1.04E-07 4.43E-07 2.24E-08

DDCDB CMOS 1.98E-08 9.84E-09 5.36E-09

NMOS 1.32E-08 9.29E-09 5.10E-09

Figure 7 Circuit structure for the HOA Pseudo NMOS PREV 1.83E-06 4.14E-07 2,52E-07
driver-receiver asf-lc, with Vdd = 2.0 V, Vbus = 1.0 V.
MJSIB CMOS 5.25E-07 3.38E-07 2.28E-07

NMOS 1.04E-06 7.51E-07 3.58E-07

PREV 1.44E-06 2.23E-07 6.35E-08

MJDB CMOS 4.97E-08 9.51E-09 2.66E-09

NMOS 1.04E-06 7.51E-07 3.58E-07


Figure 8 Circuit structure for the LHOS Pseudo NMOS

driver-receiver (mj-sib), with Vdd = 2.0 V. Average Power Consumption of π2 Medium Interconnect
at 0.25 µm Technology

LENGTH 0.6mm 3mm 6mm

ASFLC PREV 7.60E-08 2.02E-08 2.15E-08

Department of Electronics & Communication, SJBIT, Bangalroe-60. -3-

Proceedings of the 2nd National Level Technical Student Paper Presentation, 14th October 2011.

CMOS 1.86E-08 5.93E-08 1.23E-07

NMOS 2.92E-08 4.93E-08 2.07E-07
PREV 3.82E-08 1.42E-08 9.16E-09
DDCDB CMOS 6.19E-09 1.72E-09 7.96E-10
NMOS 1.80E-09 1.45E-09 5.68E-09
PREV 6.19E-07 1.60E-07 1.13E-07
MJSIB CMOS 2.46E-07 1.67E-07 1.14E-07
NMOS 3.45E-07 3.80E-07 2.71E-07
PREV 5.01E-07 7.86E-08 2.28E-08
MJDB CMOS 2.46E-07 1.67E-07 4.23E-10 Figure 11 shows Average Power consumption vs. π2 Interconnect Length
0.6mm to 6mm from Table II. It predicts results such as DDCDB and MJDB
NMOS 7.94E-09 1.76E-09 6.82E-10 circuit [Pseudo NMOS] provide best results for Medium length but ASFLC
circuits provides good result.


Average Power Consumption of π3 Long Interconnect

at 0.25µm Technology

LENGTH 1mm 5mm 10mm

PREV 4.45E-08 2.01E-08 1.83E-08
ASFLC CMOS 2.29E-08 4.58E-08 1.12E-08
NMOS 1.78E-08 3.27E-08 1.16E-07
PREV 2.33E-08 1.92E-08 7.51E-09
DDCDB CMOS 1.13E-09 3.79E-09 1.86E-09
NMOS 5.07E-08 2.89E-09 4.09E-09
Figure 12 shows Average Power consumption vs. π3 Interconnect Length
PREV 3.80E-07 1.40E-07 8.64E-08 1mm to 10mm from Table III. It predicts results such as DDCDB and MJDB
circuit [Pseudo NMOS & CMOS] provide best results for Long length but
MJSIB CMOS 1.61E-07 1.13E-07 7.62E-08 ASFLC circuits provides good result.
NMOS 3.46E-07 1.66E-07 1.17E-07
PREV 2.91E-07 7.53E-08 2.02E-08
MJDB CMOS 2.74E-09 5.44E-10 8.90E-10
This paper presented the previous design of Low power bus
NMOS 2.63E-09 4.30E-09 1.51E-09 architectures. The results showed that how these models
perform for short, medium and long wire-lengths. The
Previous work is designed along with its device parameter in
CMOS & Pseudo NMOS logic design to check in terms of
Average power consumption under 0.25µm technology. The
Previous works require no reference voltages, and multiple
threshold voltage processes and from the results it has been
confirmed. The Previous work has been analyzed with an
interconnect length of 0.3 to 10mm and an additional load of
0.13pF/mm. At 0.25µm technology, 2.0 V power supply,
3mm, 6mm, & 10 mm wire-length, and the receiver output
loading of 0.12pF, on the whole total power consumption is
10% has been reduced, was obtained from CMOS logic
design, when compared with the respective previous work and
Figure 10 shows Average Power consumption vs. π1 Interconnect Length Pseudo NMOS logic design. Further, the CMOS logic design
0.3mm to 3mm from Table I. It predicts results such as DDCDB and MJDB
circuit [CMOS] provide best results for Short length but ASFLC circuits
outperforms previous work and Pseudo NMOS logic design
provides good result. by 10% in terms of Average power consumption. This paper
proposes the low power bus architecture for VLSI busses
which greatly reduce power dissipation on interconnect lines

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Proceedings of the 2nd National Level Technical Student Paper Presentation, 14th October 2011.

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