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Byte by Byte of Memory Chips.

DRAM chips are produced in three forms: DIP [dual in-line package], SOJ
[ small outline J-lead ] and TSOP [ thin ,small outline package ] The DIP
package has leads extending straight down on both sides of the chip and
these are inserted into small holes in the printed circuit board and soldered
into place. The DIP package was originally used to mount system memory
directly onto the main board. But now, they are primarily used for level 2
cache and are interested into sockets rather than soldered.
SOJs are similar to DIPs, but their leads are bent under at the end, thus
giving them the name ‘J-lead’. The TSOP chips are extremely thin [typically,
only a few millimeters thick ] With the leads sort of ‘splayed’ out to the side.
SOJ & TSOP packages are soldered onto the surface of a printed circuit
board [called ‘surface’ mounting]. Some video boards have sockets
specifically designed for SOJ chips to be inserted.
Semiconductor manufacturers produce these chips in large assembly
plants & in huge quantities. When an assembly line first begins to produce
chips, many chips do not perform as expected and must be discarded or
reclassified. As the line ‘matures’, these defects and substandard chips
become fewer and fewer for some time. But eventually, the equipment itself
begins to wear out & so the defect rate begins to rise again. When this
happens, the line must be retooled for a new run.
To ensure that specifications have been met, each chip must be tested for
reliability & speed as it comes off the assembly line. Although a chip may be
marked for a specific speed, it may actually perform faster or slower [ we
will discuss timing numbers for various memory types later ] In such cases,
they are classified again. For example, if tests indicate that a 60ns chips runs
at 61ns or 65ns, it gets marked as a 70ns chip. Chips that pass all reliability
tests are classified as A-grade [ regardless of speed ], while those that have
minor defects are classified as C-grade. Chips with serious defects are
usually destroyed.
A-grade chips are the most reliable. These are also the most expensive
chips because of their desirability for most applications. C-grade chips are
less expensive and are intended to be used primarily for devices that are not
as demanding as today’s computers & which do not have the exacting
requirements, such as calculators & pagers . Some manufacturers have
additional grades and may use different markings to identify them.
The chip manufacturer imprints a ‘code’ on each IC which indicates the
manufacturer, chip configuration, speed rating and date of manufacturer.
This marking is put onto the IC in such a way that is embedded into the
plastic resin coating of the chip. The only way to remove this marking is to
sand or etch it off. After putting the markings on the IC, a protective coating
is placed on the chip, giving it a somewhat stamp small, recessed polished
‘dots’ into the top of the plastic jacket. This is done both to locate specific
pins [such as pin 1] and to help identify non-factory.
Manufacturers usually use a different grade chips. Many manufacturers
use a generic ‘country code’ for their lower grade chips, so you may see
modules with chips that say ‘USA’, ‘Japan’, ‘France’, ‘Korea’ etc. If you do
see these marketing on the chips of a memory module, you can be fairly
certain that the module was made with sub-standard
[ grade C ] material. In addition, manufacturers may have different ‘lots’ of
chips with different prices, depending on how much QA has been performed.
For example, Micron publishes a document, which indicates there are four
different pricing structures for chips. The costliest chips are carefully tested
and guaranteed to have less thana.1% failure rate. The cheapest chips are
untested for reliability or speed. The buyer gets chips ‘as is’ and may
experience a high failure rate.

DRAM operation and timings

DRAM chips come in various sizes such as 1 Megabit [ abbreviated as Mb ],
4Mb, 16Mb & 64Mb. Larger chips are being developed. The chip contains
‘cells’ which are actually very small capacitors, each of which contains one
‘bit’ of data.
The cells in the chip are arranged into one or more two dimensional
‘grids’ which are accessed using a row and column number. Every column
contains a Sense Amplifier, column select and pre-charge circuitry. The
number of cells per grids chip determine the chip configuration.
For example, a 16Mb chip may be configured as 4Mbx4, 2Mbx8 or
1Mbx16, but in all cases the total capacity of the chip is 16Mb. The first
number indicates the total number of cells per grid, and the second number
indicates the number of grids in the chip. Each grid contains an I / O line
[ DQ ] so that the number of grids also indicates how many bits are
transferred for each output operation. Using the examples provided, a 16 Mb
chip could contain 16 grids with 1 million cells each, 8 grids with 2 million
cells each or 4 grids with 4 million cells each. The configuration most
commonly used for system memory is the 4 Mbx4, which would allow for 8
chips to be used on a 16 MB module [16 Mb x 8 chips = 128 Mbits = 16
Mbytes ] .64 Mb Chips used for system memory are usually an 8 Mbx8
configuration for the same reason.
During a read operation, every bit in the selected row is moved to [and
the signal amplified on] the respective Sense Amps. The bits from the
selected column [s] from each grid are then read out onto the corresponding
I / O line. For a write operation, the value to be written is first placed onto
each Sense Amp from the I / O lines, which is then written into the selected
storage cell within each grid. Note that the bits are read or written to the
same ‘location’ within each grid . As far as the CPU is concerned, it knows
only about bytes, not bits. So it is the DRAM itself which must keep track of
which cells are associated with a specific byte [or memory address].
Since the cells in a DRAM chip will lose ‘memory’ fairly quickly, the cell
must be refreshed on a regular process and the frequent basis. This is called
the refresh process and the number of rows that must be refreshed at one
time is called the refresh rate. The two most common refresh rates are 2K &
4K. The chips which have a 4K refresh rate can refresh more cells at a time
than the 2K chips & complete the process faster. This means that chips with
a 2K refresh rate use less power. Also, each read access of a row / column
effectively refreshes that row by writing back the entire row from the
column Sense Amps. This reduces the overhead necessary for refreshing the


Several lines are used to signal when a row or column is to be accessed,

which row or address is being accessed, & when the data is to be sent or
received. These lines are RAS \ and CAS \ [Row and Column Address
Select], Address buffer and DOUT / DIN.RAS \ and CAS \ signal when a
row or column is to be accessed. The address buffer contains the
Row/Column address that is being accessed and the DOUT / DIN line
indicates when the data is to be transferred. The speed of a chip is typically
measured in nanoseconds [ns] for asynchronous DRAM and MHz for
synchronous DRAM. The asynchronous DRAM timing indicates the ‘Read
Cycle Time’. The most common asynchronous DRAM speed today is 60ns,
though 70ns and 50ns speeds also exist. Some asynchronous DRAM SOJ
chips are available at even faster speeds, such as 40ns, but they are typically
used for video cards. Common SDRAM speeds range from 100 MHz to 125
MHz [10ns to 8ns] with even faster chips being developed.
Printed circuit boards
The PCBs used for a memory module comprise ‘layers’. The signal, power
and ground lines are sandwiched between these layers for protection and to
keep the lines separated. The standard PCB has four layers. Some
manufacturers used 6-layer PCBs for a while but the results did not justify
the additional cost, so it is unlikely that you will find these today. The theory
was that the two additional layers provide even better separation of the data
lines and therefore, reduce the possibility of ‘noise’ or signal leakage
between the lines.
What is really most important in a PCB is the design and materials used.
For example, the ‘typical’ four-layer board is designed with two signal layers
on the outside and the power and ground layers between them. This provides
easy access to the signal layers in case of repairs. Unfortunately, this does
not sufficiently protect against signal noise getting in or out. A better design
is to have the two signal layers, thus protecting the signals from outside
noise & preventing any ‘internal’ noise from affecting adjacent modules.
The question is: How do I know where the signal lines are located? There is
no way to know that.


Memory Modules
Most people think that large semiconductor manufacturers like Texas
Instruments, Micron, NEC Samsung, Toshiba, Motorola etc. whose name
appears on the chips, produce the memory modules they buy. While this is
true in some cases, there are also many memory module manufacturers who
do not produce the semiconductors themselves. Instead, they buy the
components to produce the either directly from the manufacturer or from a
third-party supplier. In most cases, the manufacturer will imprint or silk-
screen its name onto the PCB or will place a sticker on the board to identify
themselves. This is true of the major as well as the third-party
manufacturers. A ‘generic’ manufacturers mostly makes those that do not
bear a name.
The large third-party module manufacturers have contracts with the
semiconductor manufacturers to purchase A-grade chips. Usually, the name
of the IC manufacturer remains on the chip but sometimes, through special
arrangements, the IC manufacturer may imprint the name of the module
maker on the chip instead. This is a ‘factory remark’ & does not have any
bearing on the quality of the chip. The various module types that have been
made for micro-computers [PC, Apple, etc] are SIPP [Single In-line Pin
Package], SIMM [Single In-line Memory Module], DIMM [Dual In-line
Memory Module] or SO-DIMM s are used in laptops and notebooks. The
‘leads’ or pins may be either gold-coated or tin, which is generally
determined by the material used in the memory slots with gold connectors,
while tin leads should be matched with tin slots.


SIMMs come in two main varieties: 30-pin or 72-pin, which indicates the
number of lead [or ‘pin’] connections.
The 30-pin SIMMs are nine bits wide [8 data bits & a parity bit], while
72-pin SIMMs are 32 bits wide [non-parity] or 36 bits wide [parity / ECC].
Since the 386 and 486 processor used a 32-bit [4-byte] wide memory bus,
one had to use four 30-pin SIMMs at a time, whereas only one 72-pin SIMM
was enough. Pentium systems have a 64-bit [8-byte] memory bus, so
SIMMs must be used in pairs [Pentium use only 72-pin SIMMs] or a single
DIMM may be used [DIMMs memory modules necessary to ‘fill up’ the bus
is called a ‘bank’ of memory.
Parity checking is a method of ‘adding up’ the 8 data bits at write time
[actually just the zeros or ones, depending on the type of parity checking] &
storing the result [either a 0 or a 1] in the parity bit. At read time, the data
bits are again ‘added up’, and the result compared to the stored parity bit. If
the result matches, the data is assumed to be unchanged-integrity is
Somewhat assured. This type of checking can detect [but not correct] a
single-bit error. However, a two-bit error would go unnoticed and the
generated parity will match what was stored. Even better checking is
available with ECC [error correction checking], which uses 7 or 8 bits as a
parity check [depending on whether the processor has a 4 or 8-byte memory
bus]. This allows a single-bit error to be not only detected but also corrected
and allows 2,3 and 4-bit errors to be detected.
Estimates say that with today’s memory technology, a single-bit data
error occurs once every 10 years [on any given module]. But when they
occur, any number of things may happen. Depending on the nature of the
application, parity / ECC may or may not be considered important. For
applications such as banking, military or any other area where data integrity
is absolutely essential [such as LAN environments where many people are
accessing the same application and / or data], ECC is highly recommended
[parity is considered too primitive by today’s standards].
Would you want to be the one who suffers from that once-in-decade error
in your checking account?