Compression

TestKompressTM Training
Module 2
Compression with EDT
October 2005
Objectives
Upon completion of this module, you will be able to:
♦ Understand the basic ATPG process for scan testing.

Deterministic pattern generation
♦ Understand embedded deterministic testing (EDT).
Pattern generation process
Pattern application process
♦ Understand and identify the primary EDT logic blocks.
Decompressor
Compactor
Bypass logic
♦ Identify the benefits of EDT.
Test time and data reduction
Area overhead
X bounding
2-2 • TestKompressTM Training: Compression with EDT Copyright © 2005 Mentor Graphics Corporation
Embedded Deterministic Test (EDT)
♦ EDT is the technology behind

DD
TestKompress. EE
CC
CC
♦ Based on standard scan with ATPG. OO
O
M
O
M M
M
Deterministic pattern generation. PP
PP
AA
RR
♦ Requires onboard test logic: EE
CC
TT
SS
Decompressor OO
SS
RR
OO
Compactor RR
Bypass (Optional)
♦ Reduces test data volume.
♦ Reduces test application time. Compressed
Compressed
ATE Compacted
Compacted
Stimuli
Stimuli Responses
Responses
Basic Terminology
Core
DD
EE
CC
CC
OO
OO MM
MM PP
PP
AA
RR
CC
EE
TT
SS
OO
SS
RR
OO
Scan Channels RR
(External)
Scan Chains
(Internal)
Data Volume and Test Application Time
Data Volume = L x W x H
H
No. of Scan Channels
W No. of Patterns
L
Length of Longest Scan Chains
Test Cycles = L x W Test Time = (L x W) / Frequency
EDT Reduces Test Data Volume and Application Time
Standard ATPG
H
L
EDT
EDT appears to the tester as

much shorter scan chains.
H
Decompressor Compactor
L
ATPG With Standard Scan
Tester Tester
4. Store stimuli 5. Store response

1. Target faults
2. Generate test cube
3. Pseudorandom fill
ATPG with EDT
4. Pseudorandom fill
DD
EE
CC
CC OO
OO M
M
MM PP
PP
AA
RR CC
EE
3. Calculate SS
TT
OO
5. Calculate
SS
stimuli OO
RR response
RR
1. Target faults
2. Generate test cube
Standard Test Application Process
2. CAPTURE
Scan flops
1. SHIFT IN capture
Stimuli responses
loaded
from ATE
to internal
scan chains
3. SHIFT OUT
Responses
shifted to
ATE
Stimuli
Stimuli ATE Response
Response
EDT Test Application Process
2. CAPTURE
1. SHIFT IN DD Scan flops
EE
Compressed CC
CC capture
OO
stimuli shifted OO
M
M
responses
MM
through PP
PP (20 bits)
AA
decompressor RR CC
EE
(2 bits) SS
TT
SS
OO 3. SHIFT OUT
RR
OO Responses
Random fill RR
added to stimuli compacted
inside during shift
decompressor to ATE
(20 bits) through
Compressed
Compressed Compacted
Compacted compactor
Stimuli
Stimuli
ATE Responses
Responses (2 bits)
NOTE: Data is loaded cycle-by-cycle.

Example Results of EDT
EDT Logic
Test Time Decreases with EDT.
Sharing EDT Pins With Functional Pins
Channel inputs Can be shared.
Channel outputs Should not be shared with core level bidi or tristate
pins. Muxes will be inserted. Top-level bidi and
tristate OK
EDT_Clock Can be shared with non-clock. Must be constrained.
Reduced coverage if shared.
EDT_Update Can be shared with non-clock pin.
Scan enable Can be shared.
EDT_Bypass Can be shared.
NOTE: Functional signal reuse will be discussed later.

EDT Control Signal Behavior
load_unload shift shift capture load_unload shift

scan_enable
Don’t Care
clock
edt_update Don’t Care
edt_clock OFF
edt_bypass
Don’t Care
edt_reset
NOTE: During capture scan_enable and EDT_Update can have any value.
NOTE: During capture EDT_Clk must be off.
The Decompressor
♦ Logic blocks
Ring generator
– Generates pseudorandom patterns R
R
II PP
Phase shifter N HH
N
– Eliminates linear dependencies G AA
G
SS
♦ Data and control signals GG
EE
EE
EDT_Update NN
SS
EE HH
EDT_Clock RR
II
A FF
Scan channel and chain inputs A
TT TT
EE
Masking data (output only) OO
RR
RR
♦ Routing characteristics
Shallow combinational depth
– High operating speed
The Ring Generator
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
x32 + x18 + x14 + x9 + 1
Stimuli Compression
Scan Channel Inputs
0 x x 1 x x x 1 0 x 1 x x x 1 x x
a⊕ b⊕ d=
c⊕ d⊕ h⊕k=
a⊕ b⊕c⊕ d=
h⊕j=
b⊕ d⊕ e⊕h=
e⊕ f⊕ j=
…kigeca
shifter
shifter
generator
Ring generator
1001110011
variables ⊕
=b⊕ e⊕h⊕ i
=e⊕ f⊕i⊕ j
=a⊕ c⊕g
Phase
Phase
Ring
0011011101
=c⊕g
…ljhfdb
EDT_Update x x 1 x x 0 x x x 1 x x 0 x x x x
EDT_Clock
Scan Chain Inputs

1. Generate test cube.
2. Formulate boolean equations.
3. Solve system of linear equations.
4. Store result as stimuli.
NOTE: Lockup cells may be required for proper scan chain shifting.
The Compactor
♦ Logic blocks
XOR tree
– Not MISR based
Masking Logic CC
– No fault masking or aliasing OO
M
M
♦ Data and control signals PP
AA
EDT_Update CC
TT
EDT_Clock OO
RR
Masking data (input only)
Scan chain and channel outputs
♦ Routing and performance
characteristics
Pipeline stages for increased speed
Compactor Logic
Scan Chain Output
scan chain
scan chain
...
...
scan chain
scan chain
Scan Channel Output

EDT_Clock
decoder
EDT_Update
EDT_Mask
Compactor Logic (Cont.)
Decoder
EDT_Update
1 1
D Q D Q
0 Hold 0 Hold
Reg_1 Reg_0
EDT_Mask DQ
D D Q
Shift Shift Useful for debugging
Reg_1 Reg_0
K19 violations
EDT_Clock
Scan Chain Masking
Chain 1
Chain Output
1 0 X 1 X 0 0 0 1
Channel
0 1 X 1 X 1 X X 0 Output
Chain 2
1 1 0 0 X 1 X X 1 Chain Output
♦ An “X” in one scan cell will block observation of

corresponding cells in other scan chains associated with
the same channel.
Scan Chain Masking — Solution
Chain 1
Chain Output
1 0 X 1 X 0 0 0 1
0
Chain 2 Channel
Chain Output Output
1 1 0 0 X 1 X X 1
1
1 1 0 0 X 1 X X 1
♦ A masking mechanism allows automatic selection of individual scan

chains, so that X sources from other scan chains don’t block observation.
♦ Masking is done only when necessary per pattern basis.
Fault Aliasing
Chain 1
Chain Output
1/0
1
Good/Faulty
0/0
Channel
Output
1
1/0
Chain 2
1/0
1 Chain Output
♦ A fault is aliased if it is only observed by an even number of

scan cells that are in the same time slot in chains that are
compacted into one channel.
Fault Aliasing — Solution
Chain 1
1/0
1
Good/Faulty
1
1/0 1 1
1/0
Channel
Output
0
Chain 2
1/0
1
♦ An aliased fault will not be classified as detected for an
unmasked pattern.
♦ All aliased faults will be masked and detected automatically by
masked patterns.
♦ The other side of the masked observed cell will get another
opportunity to be observed.
EDT Compactor
♦ Fault calculation taken at channel output
True fault coverage result
♦ Masking pattern generation
Only when target fault site is disturbed with “X”
Only when aliasing occurs
♦ Masking data from decompressor
Per-pattern masking data
Masking data is embedded in test pattern set
Masking data shifted into masking register during shift cycle
Very High-Speed TestKompress Shifting — Reduced Test
Application Time
♦ Pipelines can be defined DD
between channel I/O and pads. EE

CC
CC
OO
OO
♦ Enables very high speed MM
PP
MM
PP
AA
TestKompress shifting. RR
EE
SS
CC
TT
OO
♦ Allows different channels to SS

OO
RR
RR
block 1
have different numbers of
pipeline stages.
DD
EE CC
CC
OO
OO MM
MM PP
PP
AA
RR
CC
EE
TT
SS
OO
SS RR
OO
RR
block 2
SET EDt Pins {Input_channel | Output_channel} \

-PIpeline_stages #pipeline_stages
Pipeline Stages
♦ Compactor logic:
XOR tree.
Masking logic.
– Decoding and gating logic.
– Masking register.
♦ Compression rate determines combinational depth.
Chain to channel ratio.
More scan chains compacted into fewer scan channels.
♦ Optional pipeline stages reduce effective combinational depth.
Pipelining inserted to satisfy setup and hold time.
– Based on shift frequency.
– Gate delay of 2-input XOR.
Edge triggered flops.
– Latency = No. of pipeline stages.
– May require lockup cell insertion.
NOTE: Most technologies do NOT require pipelining to shift at 50Mhz.

Pipeline Stages Example
scan
D Q
scan
...
...
scan
D Q
scan
EDT_Update
decoder Pipeline Stage
EDT_Mask
EDT_Clock
NOTE: Adding pipelining may require lockup cell insertion for proper shifting.
EDT Bypass Logic (Optional)
Chain4
DD
ee C
cc C
oo Chain3 oo
m m
m
Channel m pp Channel
pp aa
In1 rr cc Out1
ee Chain2 tt
ss oo
ss rr
oo
rr
Chain1
EDT_Bypass
Bypass Mux
NOTE: Scan chain concatenation may require lockup cells for proper shifting.
Lockup Cells
♦ Eliminate clock skew between flops during scan shifting.
♦ Three possible locations:
Between decompressor and scan chain inputs.
Between internal scan chain during bypass mode.
Between scan chain outputs and first compactor pipeline stage.
♦ Edge triggered flip-flops.
Only inserted where needed.
Based on scan chain I/O clock analysis.
Follows rules outlined in documentation.
NOTE: More information on how lockup cells are inserted is inside

the EDT Process Guide, Chapter 7
Lockup Cell Insertion:
Between Decompressor and Scan Chain Inputs
NOTE: More information inside EDT Process Guide, Chapter 7

Between Scan Chain Outputs and Compressor

Between Scan Chains for Bypass
♦ A lockup cell is inserted when a source and destination cell
have the same active edge and are clocked by different clocks.
♦ A lockup cell is inserted when the active edge of the source cell
precedes the active edge of the destination cell.
♦ If multiple lockup cells are inserted, the tool ensures that:
The earliest data capture time of the last lockup cell is not before
the latest time when the destination cell can capture new data. This
makes the first scan cell of every chain a master and prevents D2
DRC violations.
If the earliest time when data is available at the output of the
source is before the earliest data capture time of the first lockup,
the first lockup cell is driven with the same clock that6 drives the
source.
♦ If a lockup latch already exists at the end of a scan chain, the
tool learns its behavior and treats it as the source cell.
Example: Location of Lockup Cells
Decompressor
Compactor
Chain4
Ring Generator
Phase Shifter
Chain3
SO
SI
Chain2
Chain1
Decompressor Lockup Cells Bypass mode Compactor Pipeline Stages

Lockup Cells when first scan Lockup Cells Lockup Cells
element is TE (see table) When all last scan
elements are LE
Example: Location of Lockup Cells (Cont.)
Decompressor
TE Compactor
Chain4
Chain3
SI SO
Chain2
Chain1
Decompressor Lockup Cells Bypass mode Compactor Lockup Pipeline Stages

Lockup Cells when first scan Lockup Cells Cells when one or
element is TE (see table) more of the last scan
chain elements are TE
Advantages of Embedded Deterministic Test (EDT)
♦ No system logic modifications

EDT logic only in scan path
– Scan chain and channel I/O
– Decompressor and compactor
– Bypass logic
– Lockup cells
♦ No performance impact
Selective compactor
– No test points
– No X-bounding
– No fault masking or aliasing
♦ Low area overhead
20-25 gates per scan chain
0.4% in 1Mgate design
Test Application Time and Data Volume Reduction

Advantages of Embedded Deterministic Test (EDT) (Cont.)
♦ High fault coverage

Core
– Deterministic ATPG
EDT logic
– 95%-99.5% during scan chain check
♦ Supports all ATPG fault models
Stuck, IDDQ, toggle
Transition and path delay
♦ Supports all ATPG pattern types
Clock-seq, combinational
RAM-seq and multi-load
♦ Faster serial simulation
Shorter scan chains
Test Application Time and Data Volume Reduction

Summary
This module introduced and explored the application of the
following topics:
♦ Understanding the Basic ATPG Process for Scan Testing.
Deterministic Pattern Generation
♦ Understanding Embedded Deterministic Testing (EDT).
Pattern Generation Process
Pattern Application Process
♦ Understanding and Identifying the Primary EDT Logic Blocks.
Decompressor
Compactor
Bypass Logic
♦ Identifying the Benefits of EDT.
Test Time and Data Reduction
Area Overhead
X bounding

Compression

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Compression

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TestKompressTM Training

Upon completion of this module, you will be able to:

♦ Understand the basic ATPG process for scan testing.

♦ EDT is the technology behind

Length of Longest Scan Chains

Test Cycles = L x W Test Time = (L x W) / Frequency

EDT appears to the tester as

4. Store stimuli 5. Store response

NOTE: Data is loaded cycle-by-cycle.

Test Time Decreases with EDT.

Channel inputs Can be shared.

EDT_Update Can be shared with non-clock pin.

Scan enable Can be shared.

EDT_Bypass Can be shared.

NOTE: Functional signal reuse will be discussed later.

load_unload shift shift capture load_unload shift

edt_update Don’t Care

x32 + x18 + x14 + x9 + 1

Scan Chain Inputs

Scan Channel Output

♦ An “X” in one scan cell will block observation of

♦ A masking mechanism allows automatic selection of individual scan

♦ A fault is aliased if it is only observed by an even number of

between channel I/O and pads. EE

♦ Allows different channels to SS

SET EDt Pins {Input_channel | Output_channel} \

NOTE: Most technologies do NOT require pipelining to shift at 50Mhz.

NOTE: More information on how lockup cells are inserted is inside

NOTE: More information inside EDT Process Guide, Chapter 7

NOTE: More information inside EDT Process Guide, Chapter 7

Decompressor Lockup Cells Bypass mode Compactor Pipeline Stages

Decompressor Lockup Cells Bypass mode Compactor Lockup Pipeline Stages

♦ No system logic modifications

Test Application Time and Data Volume Reduction

♦ High fault coverage

Test Application Time and Data Volume Reduction

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