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# DIGITAL LOGIC DESIGN

UNIT I

## 1. a) The solution to the quadratic equation x2 – 11x + 22 = 0 is x = 3 and x = 6.

What is the base of numbers.
b) Using 10’s complement, subtract
i) 7253210-325010 ii) 325010-7253210. What do you infer from the results.
c) What are the characteristics of 2’s complement numbers?
d) (1331)r1/3= (11)r [GATE EXAM]

## 2. a) What is the advantage of 1’s and 2’s complement in computers. Represent

+45 and -45 in sign-magnitude, sign-1’s complement and sign-2’s
complement representation.
b) Explain about Weighted and non-weighted codes.
c) How are negative numbers represented?
d) Solve bases x and y, when (84)x = (64)y [GATE EXAM]

3. a) The binary numbers listed have a sign bit in the left most position and, if
negative numbers are in 2’s complement form. Perform the arithmetic operations

i) 101011 + 111000 ii) 001110 + 110010 iii) 111001 – 001010 iv) 101011 –
100110.
b) Explain about Weighted and non-weighted codes.
c) What do you mean by end around carry? When does it come into picture?

## 4. a) Explain how 1's complement and 2's complement of a binary number is

obtained? Illustrate by an example.

b) What is gray code? What are the rules to construct gray code? Develop
the 4 bit gray code for the decimal 0 to 15.
c) Why is the binary number system used in digital systems?

5.. a) Perform the following arithmetic operation using l’s complement method

## i) Add (-19)10 and (29) 10 ii) Add (21)10 and (37)10

b) The Hamming code 010110110 is received at the receiving end. Correct
the received data if there is any error.
c) Convert the decimal number 46 to binary number system, also explain the
steps of conversion.

## Dr. N Leelavathy, Professor & Vice-Principal (Academics), GIET, Rajahmundry.

i)126310 + 968710 ii)767210 + 337810
b) Perform the following subtraction:
i) (11010)2 – (10000)2 using 1’s complement ii) (1000100)2 - (1010100)2 using
2’s complement
c) (25.75)10 to binary number

## Dr. N Leelavathy, Professor & Vice-Principal (Academics), GIET, Rajahmundry.

DIGITAL LOGIC DESIGN
UNIT WISE QUESTIONS

UNIT II

## 1. a) Reduce the following function using K-map technique.

f(A,B,C,D) = ∑ (0,1,4,8,9,10)

## b) Realize f(x,y,z) = ∑ (0,1,5,7) using AND , OR and inverter gates.

c) F(A,B,C,D) = ∑(0,1,4,5,16,17,21,25,29)

## d) What are the limitations of K-maps?

2. a) Using K-map method determine the prime implicant and obtain the possible
minimal expression for the following function

## b) What are the basic operations in Boolean algebra?

3. a) List out the Basic Theorems and Properties of Boolean Algebra. Justify with
Proof. What is a prime implicant in K-map?

## b) Using Quine-McCluskey method, obtain minimal expression for the

following Boolean function

## F(A,B,C,D,E) = ∑m(8,12,13,18,19,21,22,24,25,28,30,31) + ∑φ(2,6,9,20,26,29)

4. Define the connective * for the Boolean variables X and Y as: X*Y = XY + X'Y'. Let
Z = X*Y. Consider the following expressions P, Q and R.

P: X=Y*Z

Q: Y=X*Z

## R: X*Y*Z=1. Find which of the expressions are valid. [GATE EXAM]

5. a) Find the prime implicants, essential prime implicants and number of minimal
expressions for the given function using K -map

f(A,B,C,D) = ∑m(1,3,5,7,8,10,12,13)

## b) Realize a two level OR-AND circuit for the following

F = (x+y’).z + (x’.y.z’)

## c) State and prove consensus theorem

6. a) Using Boolean algebra rules simplify the following Boolean expression and
implement in NAND logic f(A,B,C,D) = ∑m(10,11,14,15)

## Dr. N Leelavathy, Professor & Vice-Principal (Academics), GIET, Rajahmundry.

b) Find the minimal expression using K- map for given function F

F(w,x,y,z) = ∑(0,2,3,5,7,9)+∑d(1,6,10,11)

## c) What is a cell of a K-map?

8. a) What is gray code? What are the rules to construct gray code? Develop the 4
bit gray code for the decimal 0 to 15.

## b) State the Duality principle with example

c) The Hamming code 010110110 is received at the receiving end. Correct the
received data if there is any error.

## F(w,x,y,z) = ∑m(1,4,8,9,13,14,15) + ∑φ(2,3,11,12).

b) Realize a two level NAND-NAND circuit for the following F=(w.x.y) +(y.z)

## Dr. N Leelavathy, Professor & Vice-Principal (Academics), GIET, Rajahmundry.

DIGITAL LOGIC DESIGN
UNIT WISE QUESTIONS

UNIT III

## 1.a) Implement the following using 4 to 16 line decoder

F(A,B,C,D) = ∑(0,1,4,7,9,12,14)

b) Design 4X1 MUX using 2X4 decoder and basic logic gates

## c) Implement 1:8 demultiplexer using two 1:4 demultiplexer

2. a) Construct a 4X16 decoder using 2X4 decoder. Show the schematic diagram
neatly.

## 3. a) Design an octal to binary encoder.

b) Design a full subtractor and implement it using NAND gates. Explain its
operation with the help of truth table?

c) Define Demultiplexer.

## 4. Consider the following combinational function block involving four Boolean

variables x, y, a, b where x, a, b are inputs and y is the output.

f(x,y,a,b)

if(x is 1) y=a;

else y=b;

Which digital logic block ( Full Adder, Priority encoder, Multiplexer or Flip-Flop) is
most suitable for implementing this function. [GATE EXAM]

## Dr. N Leelavathy, Professor & Vice-Principal (Academics), GIET, Rajahmundry.

b) A Combinational circuit is defined by the following three Boolean functions

## b) Implement the following Boolean function using 8:1 MUX.

F(P,Q,R,S) = ∑ (0,1,3,4,8,9,15)

## Y1= Σ(0,1,3,6,7), Y2= Π(0,2,4,7), Y3= Π(1,3,6,7)

b) Define Encoder.

## 11. a) Implement the following using a multiplexer

F(w,x,y,z) = ∑m(0,1,2,3,4,9,13,14,15)

b) Draw the logic diagram of 8:1 MUX with active low enable input using NAND
gates

12. a) Design and realize the combinational logic circuit for converting a BCD
number to a seven segment display

b) Design a full adder with two half adders and other logic gates and explain
its operation.

## c) Using Boolean algebra rules simplify the following Boolean expression

and implement in NAND logic f(A,B,C,D) = ∑m(10,11,14,15)

## Dr. N Leelavathy, Professor & Vice-Principal (Academics), GIET, Rajahmundry.

b) Implement the following Boolean function using 8:1 MUX.

F(P,Q,R,S) = ∑ (0,1,3,4,8,9,15)

## Dr. N Leelavathy, Professor & Vice-Principal (Academics), GIET, Rajahmundry.

DIGITAL LOGIC DESIGN
UNIT WISE QUESTIONS

UNIT-IV

1. a) Draw the truth table, logic diagrams of J-K, R-S, D and T type flip flops.

b) Convert a T flip flop to D flip flop and write characteristic equations of T and D
flip flops.

inverter.

## 4. The minimum number of D -FFs needed to design a MOD-258 counter is -------

[GATE EXAM]

5. a) Define the following terms of a flip flop.(i) Hold time (ii) Set up time ; (iii)
Propagation delay time.

b) Draw the circuit diagram of master-slave J-K flip flop and explain its
operation with the help of a truth table. How is it different from edge trigged flip
flop? Explain.

## 6. a) Compare latch and flip flop

b) Realize D-latch using S-R latch. How is it different from D-flip flop? Draw the
circuit using NAND gates and explain.

## c) Explain the difference between racing and toggling.

7. a) Draw the truth table, logic diagrams of J-K, R-S, D and T type flip flops.

b) Convert a T flip flop to D flip flop and write characteristic equations of T and D
flip flops.

## 8. a) Define the following terms related to flip-flops.

i) set-up time ii) hold time iii) propagation delay iv) preset and v) clear.

## Dr. N Leelavathy, Professor & Vice-Principal (Academics), GIET, Rajahmundry.

b) Discuss D-type edge- triggered flip-flop in detail?

## c) How do you convert one type of flip-flop into another?

9. a) Determine how the circuit shown in Fig. 1 functions as a T-type flip-flop. What
problem would there be when T= 1 and how could it be resolved.

b) How could:

## i) a JK flip-flop be used as a D-type? ii) a JK flip-flop be used as a T-type?

iii) a D-type flip-flop be used as a T-type?

## c) What are the various methods used for triggering flip-flops?

11. a) Draw the circuit diagram of J-K flip flop with NAND gates with positive edge
triggering and explain its operation with the help of a truth table.

inverter.

## c) What is meant by race around condition in flip-flops?

14. a) Design Johnson’s counter using a 2 bit shift register. Draw the waveforms.

## b) List the applications of shift registers.

c) How to load data word ABCD = 1101 in the 4-bit bidirectional shift register in
shift left mode.

## 15. a) Draw and explain the operation of 4 bit ring counter.

b) What is the difference between ring counter and Johnson’s counter? Explain.

## Dr. N Leelavathy, Professor & Vice-Principal (Academics), GIET, Rajahmundry.

c) Explain about parallel in serial out shift register. d) What is the basic
difference between a shift register and a counter?

## b) Explain different types of shift registers.

17. Data from a satellite is received in serial form. If the data is coming at 8MHz
rate, how long will it take to serially load a word in 40-bit shift register?

[GATE EXAM]

18. a) Design a resister to perform left shift and right shift for the following data
10110101 ?

## Dr. N Leelavathy, Professor & Vice-Principal (Academics), GIET, Rajahmundry.

DIGITAL LOGIC DESIGN
UNIT WISE QUESTIONS

UNIT-V

1a). Design a circuit using ROM which will perform the squaring operation
for the given 3 bit binary number.

b) i. How many 32K * 8 RAM chips are needed to provide a memory capacity
of 256K bytes?

ii. How many lines of the address must be used to access 256K bytes? How
many of these lines are connected to the address inputs of all chips?

iii. How many lines must be decoded for the chip select inputs? Specify the
size of the decoder.

cache memory

## 3. A computer uses RAM chips of 1024 x 1 capacity

i)how many chips are needed and how should their address lines be
connected to provide a memory capacity of 16k bytes
ii)How many chips are needed to provide a memory capacity of 16 bytes

4. An eight way set associative cache consists of a total of 256 blocks. The
main memory consists of 8192 blocks, each consisting of 128 words[L3]

## i. Calculate the number of bits in main memory address

ii. Calculate the number of bits in TAG, SET and WORD fields.

## Dr. N Leelavathy, Professor & Vice-Principal (Academics), GIET, Rajahmundry.

DIGITAL LOGIC DESIGN

Unit-1

Ans. 8

## 2. The digit F in hexadecimal system has equivalence in digital

system to--------

Ans. 17

system to------

Ans. 240

represents ---

Ans. 20

6. ------

Ans. 17

Ans. 10001000

Ans. 00011001

Ans. 1011

## Dr. N Leelavathy, Professor & Vice-Principal (Academics), GIET, Rajahmundry.

10. -24 is 2’s complement form is ----------

Ans. 1000

Ans. (59382)10

Ans. 1101

Ans. (10010)2

Unit – II

-------

## Dr. N Leelavathy, Professor & Vice-Principal (Academics), GIET, Rajahmundry.

10. Most preceded operator is --------------
11. (a+b+c)'= -------

UNIT-III

## 3. Which of the circuits in figure (a to d) is the sum-of-products

implementation of figure (e)?

4. For the device shown here, let all D inputs be LOW, both S inputs be

## Dr. N Leelavathy, Professor & Vice-Principal (Academics), GIET, Rajahmundry.

HIGH, and the input be LOW. What is the status of the Y output?

5. For the device shown here, let all D inputs be LOW, both S inputs be
HIGH, and the input be HIGH. What is the status of the Y output?

6. How many data select lines are required for selecting eight inputs?

7. How many 1-of-16 decoders are required for decoding a 7-bit binary
number?

8. For the device shown here, assume the D input is LOW, both S inputs are
HIGH, and

## Dr. N Leelavathy, Professor & Vice-Principal (Academics), GIET, Rajahmundry.

10. How many 4-bit parallel adders would be required to add two binary
numbers each representing decimal numbers up through 30010?

UNIT-IV

## 1. A ripple counter's speed is limited by the propagation delay of:--------------

----

A. each flip-flop

-

---------

## 4. A sequence of equally spaced timing pulses may be easily generated by

which type of counter circuit?

## A Loading data in all four flip-flops at the same time

6. What is a shift register that will accept a parallel input and can shift data
left or right called?

## Dr. N Leelavathy, Professor & Vice-Principal (Academics), GIET, Rajahmundry.

A. bidirectional universal

A. 2 inputs

A. q and q'

A. 1

## 10. Inputs of SR latch are-----

A. s and r

UNIT-V

1. How many address bits are needed to select all memory locations in the
2118 16K × 1 RAM?

A. 14

## Random Access Memory; it is the memory used for short-term

A.
temporary data storage within the computer.

A. flip-flop

A. 8 bytes

A.
system operation

memory system?

## Dr. N Leelavathy, Professor & Vice-Principal (Academics), GIET, Rajahmundry.

C. 8

7.How many storage locations are available when a memory device has 12

A. 4096

## A. on the property of locality of reference

9. The algorithm to remove and place new contents into the cache is called
_______.
a) Replacement algorithm

## 10. The method of mapping the consecutive memory blocks to consecutive

cache blocks is called ______.
A. Direct

11. While using the direct mapping technique, in a 16 bit system the higher
order 5 bits is used for ________.
A. Tag

12. In direct mapping the presence of the block in memory is checked with
the help of block field.
A. False

13. In associative mapping, in a 16 bit system the tag field has ______ bits.
A. 12

## 14. The associative mapping is costlier than direct mapping ( State

True/False).
A. True

15. The technique of searching for a block by going through all the tags is
______.
A. Associative search