SWITCH-MODE

POWER SUPPLIES
SPICE Simulations and Practical Designs

Christophe P. Basso

Second Edition

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 contents

Preface   xiii
Acknowledgments   xv
Nomenclature   xvii

Chapter 1.  Introduction to Power Conversion 1

1.1 “Do you really need to simulate?”    /      1

1.2 What you will find in the following pages    /      2
1.3 What you will not find in This book    /      3
1.4 Converting power with resistors    /      3
1.4.1  Associating Resistors    /     3
1.4.2  A Closed-Loop System    /     4
1.4.3  Deriving Useful Equations with the Linear Regulator    /    6
1.4.4  A Practical Working Example    /     10
1.4.5  Building a Simple Generic Linear Regulator    /    13
1.4.6  Conclusion on Linear Regulators    /     15
1.5 Converting power with switches    /      16
1.5.1  A Filter Is Needed    /     17
1.5.2  Current in the Inductance, Continuous or Discontinuous?    /    19
1.5.3  Charge and Flux Balance    /     23
1.5.4  Energy Storage    /     24
1.6 The duty ratio factory    /      25
1.6.1  Voltage-Mode Operation    /     25
1.6.2  Current-Mode Operation    /     26
1.7 The buck converter    /      28
1.7.1  On-Time Event    /     28
1.7.2  Off-Time Event    /     29
1.7.3  Buck Waveforms—CCM    /     29
1.7.4  Buck Waveforms—DCM    /     31
1.7.5  Buck Transition Point DCM–CCM     /     34
1.7.6  Buck CCM Output Ripple Voltage Calculation    /    36
1.7.7  Now with the ESR    /     39
1.7.8  Buck Ripple, the Numerical Application    /     40
1.7.9  Rms Currents in the Buck Converter    /    41
1.8 The boost converter    /      45
1.8.1  On-Time Event    /     46
1.8.2  Off-Time Event    /     47
1.8.3  Boost Waveforms—CCM    /     47
1.8.4  Boost Waveforms—DCM    /     49
1.8.5  Boost Transition Point DCM–CCM     /     53
1.8.6  Boost CCM Output Ripple Voltage Calculations    /    54
1.8.7  Now with the ESR    /     57
1.8.8  Boost Ripple, the Numerical Application    /     58
1.8.9  Rms Currents in the Boost Converter    /    58
1.9 The buck-Boost converter    /      66
1.9.1  On-Time Event    /     67
1.9.2  Off-Time Event    /     68
1.9.3  Buck-Boost Waveforms—CCM    /     68
1.9.4  Buck-Boost Waveforms—DCM    /     70

iii
iv        CONTENTS

1.9.5  Buck-Boost Transition Point DCM–CCM     /     73

1.9.6  Buck-Boost CCM Output Ripple Voltage Calculation    /    75
1.9.7  Now with the ESR    /     76
1.9.8  Buck-Boost Ripple, the Numerical Application    /     76
1.9.9  Rms Currents in the Buck-Boost Converter    /    77
1.10 Input filtering    /      84
1.10.1  The RLC Filter    /     85
1.10.2  A More Comprehensive Representation    /     87
1.10.3  Creating a Simple Closed-Loop Current Source with SPICE    /    88
1.10.4  Understanding Overlapping Impedances    /     90
1.10.5  Damping the Filter    /     93
1.10.6  Calculating the Required Attenuation    /     95
1.10.7  Fundamental Frequency Evaluation    /     97
1.10.8  Selecting the Right Cutoff Frequency    /    100
What I should retain from This Chapter    /      102
References    /      103
Appendix 1A  An RLC transfer function    /      103
Appendix 1B  The capacitor equivalent model    /      107
Appendix 1C  Power Supply Classification by Topologies     /      110
Appendix 1D  Root Mean Square Values of CCM and DCM Switching Waveforms     /      111

Chapter 2.  Small-Signal Modeling 117

2.1 State-Space Averaging    /      119

2.1.1  SSA at Work for the Buck Converter—First Step    /    121
2.1.2  The DC Transformer    /     124
2.1.3  Large-Signal Simulations    /     125
2.1.4  SSA at Work for the Buck Converter, the Linearization—Second Step    /    128
2.1.5  SSA at Work for the Buck Converter, the Small-Signal Model—Final Step    /    130
2.2 The Pwm Switch Model—The Voltage-Mode Case    /      132
2.2.1  Back to the Good Old Bipolars     /    133
2.2.2  An Invariant Internal Architecture    /     134
2.2.3  Waveform Averaging    /     135
2.2.4  Terminal Currents    /     136
2.2.5  Terminal Voltages    /     137
2.2.6  A Transformer Representation    /     137
2.2.7  Large-Signal Simulations    /     138
2.2.8  A More Complex Representation    /     141
2.2.9  A Small-Signal Model    /     143
2.2.10  Helping with Simulation    /     148
 2.2.11  Discontinuous Mode Model    /     149
2.2.12  Deriving the d2 Variable    /     151
2.2.13  Clamping Sources    /     152
2.2.14  Encapsulating the Model    /     153
2.2.15  The PWM Modulator Gain    /     158
2.2.16  Testing the Model    /     164
2.2.17  Mode Transition    /     165
2.3 The Pwm Switch Model—The Current-Mode Case    /      166
2.3.1  Current-Mode Instabilities    /     168
2.3.2  Preventing Instabilities    /     173
2.3.3  The Current-Mode Model in CCM    /    175
2.3.4  Upgrading the Model    /     180
2.3.5  The Current-Mode Model in DCM    /    184
2.3.6  Deriving the Duty Ratios d1 and d2    /     186
2.3.7  Building the DCM Model    /     188
2.3.8  Testing the Model    /     191
2.3.9  Buck DCM, Instability in DC    /    191
2.3.10  Checking the Model in CCM    /    193
 2.3.11  Building Duty Ratio Factories    /     194
2.4 The Pwm Switch Model—Parasitic Elements Effects    /      202
2.4.1  A Variable Resistor    /     205
 CONTENTS        v 

2.4.2  Ohmic Losses, Voltage Drops: The VM Case    /     206

2.4.3  Ohmic Losses, Voltage Drops: The CM Case    /    209
2.4.4  Testing the Lossy Model in Current Mode    /    209
2.4.5  Convergence Issues with the CM Model    /    212
2.5 PWM Switch Model in Borderline Conduction    /      213
2.5.1  Borderline Conduction—The Voltage-Mode Case    /     213
2.5.2  Testing the Voltage-Mode BCM Model    /     217
2.5.3  Borderline Conduction—The Current-Mode Case    /     219
2.5.4  Testing the Current-Mode BCM Model    /    225
2.6 The Pwm Switch Model—A Collection of Circuits    /      229
2.6.1  The Buck    /     229
2.6.2  The Tapped Buck    /     229
2.6.3  The Forward    /     231
2.6.4  The Buck-Boost    /     232
2.6.5  The Flyback    /     233
2.6.6  The Boost    /     234
2.6.7  The Tapped Boost    /     234
2.6.8  The Nonisolated SEPIC    /     235
2.6.9  The Isolated SEPIC    /     236
2.6.10  The Nonisolated Ćuk Converter    /     237
2.6.11  The Isolated Ćuk Converter    /     237
2.7 Other Averaged Models    /      239
2.7.1  Ridley Models    /     239
2.7.2  Small-Signal Current-Mode Models    /     240
2.7.3  Ridley Models at Work    /     240
2.7.4  CoPEC Models    /     241
2.7.5  CoPEC Models at Work    /     244
2.7.6  Ben-Yaakov Models    /     244
What I Should Retain from This Chapter    /      249
References    /      251
Appendix 2A  Basic Transfer Functions for Converters    /      251
2A.1  Buck    /     252
2A.2  Boost    /     255
2A.3  Buck-Boost    /     258
References    /      261
Appendix 2B  Poles, Zeros, and Complex Plane—A Simple Introduction    /      262
References    /      266
Appendix 2C  Small-Signal Analysis of the DCM Boost Converter in Voltage Mode    /      266

Chapter 3.  Feedback and Control Loops 275

3.1 Observation Points    /      277

3.2 Stability Criteria    /      280
3.3 Phase Margin and Transient Response    /      282
3.4 Choosing the Crossover Frequency    /      283
3.5 Shaping the Compensation Loop    /      284
3.5.1  The Passive Pole    /     284
3.5.2  The Passive Zero    /     285
3.5.3  Right Half-Plane Zero    /     287
3.5.4  Type 1 Amplifier—Active Integrator    /     289
3.5.5  Type 2 Amplifier—Zero-Pole Pair    /     291
3.5.6  Type 2a—Origin Pole Plus a Zero    /    293
3.5.7  Type 2b—Proportional Plus a Pole    /    295
3.5.8  Type 3—Origin Pole Plus Two Coincident Zero-Pole Pairs    /    295
3.5.9  Selecting the Right Amplifier Type    /     297
3.6 An Easy Stabilization Tool—The k Factor    /      298
3.6.1  Type 1 Derivation    /     299
3.6.2  Type 2 Derivation    /     300
3.6.3  Type 3 Derivation    /     302
3.6.4  Stabilizing a Voltage-Mode Buck Converter with the k Factor    /     303
3.6.5  Conditional Stability    /     307
vi        CONTENTS

3.6.6  Independent Pole-Zero Placement    /     308

3.6.7  Crossing Over Right at the Selected Frequency    /    310
3.6.8  The k Factor versus Manual Pole-Zero Placement    /    311
3.6.9  Stabilizing a Current-Mode Buck Converter with the k Factor    /     315
3.6.10  The Current-Mode Model and Transient Steps    /    321
3.7 Feedback with the TL431    /      322
3.7.1  A Type 2 Amplifier Design Example with the TL431    /    326
3.7.2  A Type 3 Amplifier with the TL431    /     327
3.7.3  Biasing the TL431    /     333
3.7.4  The Resistive Divider     /     338
3.8   The Optocoupler    /      340
3.8.1  A Simplified Model    /     340
3.8.2  Extracting the Pole    /     342
3.8.3  Accounting for the Pole    /     344
3.9 Operational Transconductance Amplifiers    /      349
3.10 Shunt Regulators    /      354
3.10.1  SPICE Model of the Shunt Regulator    /    354
3.10.2  Quickly Stabilizing a Converter Using the Shunt Regulator    /    355
3.11 Small-Signal Responses with Psim and Simplis    /      357
What I Should Retain from This Chapter    /      363
References    /      363
Appendix 3A   Automated Pole-Zero Placement    /      364
Appendix 3B   A TL431 Spice Model    /      368
3B.1  A Behavioral TL431 Spice Model    /     368
3B.2  Cathode Current versus Cathode Voltage    /     369
3B.3  Output Impedance    /     370
3B.4  Open-Loop Gain    /     370
3B.5  Transient Test    /     371
3B.6  Model Netlist    /     372
Appendix 3C   Type 2 Manual Pole-Zero Placement    /      374
Appendix 3D   Understanding the Virtual Ground in Closed-Loop Systems    /      378
3D.1  Numerical Example    /     379
3D.2  Loop Gain Is Unchanged    /     381

Chapter 4.  Basic Blocks and Generic Switched Models 383

4.1 Generic Models for Faster Simulations    /      383

4.1.1  In-Line Equations    /     383
4.2 Operational Amplifiers    /      385
4.2.1  A More Realistic Model    /     386
4.2.2  A UC384X Error Amplifier    /     387
4.3 Sources with a Given Fan-Out    /      389
4.4 Voltage-Adjustable Passive Elements    /      391
4.4.1  The Resistor    /     392
4.4.2  The Capacitor    /     392
4.4.3  The Inductor    /     393
4.5 A Hysteresis Switch    /      396
4.6 An Undervoltage Lockout Block    /      398
4.7 Leading Edge Blanking    /      399
4.8 Comparator with Hysteresis    /      401
4.9 Logic Gates    /      402
4.10 Transformers    /      405
4.10.1  A Simple Saturable Core Model    /    407
4.10.2  Multioutput Transformers    /     412
4.11 Astable Generator    /      414
4.11.1  A Voltage-Controlled Oscillator    /     415
4.11.2  A Voltage-Controlled Oscillator Featuring Dead Time Control    /    418
4.12 Generic controllers    /      419
4.12.1  Current-Mode Controllers    /     419
4.12.2  Current-Mode Model with a Buck    /    421
4.12.3  Current-Mode Instabilities    /     422
 CONTENTS        vii 

4.12.4  The Voltage-Mode Model    /     424

4.12.5  The Duty Ratio Generation    /     424
4.12.6  A Quick Example with a Forward Converter    /    425
4.13 Dead Time Generation    /      427
4.14 Short-Pulse Generators    /      427
4.15 List of Generic Models    /      431
4.16 Convergence Options    /      431
What I Should Retain from This Chapter    /      432
References    /      432
Appendix 4A   An Incomplete Review of the Terminology Used in Magnetic Designs    /      433
4A.1  Introduction     /     433
4A.2  Field Definition    /     433
4A.3  Permeability    /     434
4A.4  Founding Laws    /     436
4A.5  Inductance    /     437
4A.6  Avoiding Saturation    /     437
Further Reading     /      438
Appendix 4B  Feeding Transformer Models with Physical Values    /      439
4B.1  Understanding the Equivalent Inductor Model    /    439
4B.2  Determining the Physical Values of the Two-Winding T Model    /    440
4B.3  The Three-Winding T Model    /     441
References    /      444

Chapter 5.  Simulations and Practical Designs of Nonisolated Converters 445

5.1 The Buck Converter    /      445

5.1.1  A 12-V, 4-A Voltage-Mode Buck from a 28-V Source    /    445
5.1.2  The ac Analysis    /     448
5.1.3  Transient Analysis    /     451
5.1.4  The Power Switch    /     455
5.1.5  The Diode    /     456
5.1.6  Output Ripple and Transient Response    /     457
5.1.7  Input Ripple    /     459
5.1.8  A 5-V, 10-A Current-Mode Buck from a Car Battery    /    463
5.1.9  The ac Analysis    /     464
5.1.10  Transient Analysis    /     467
5.1.11  A Synchronous Buck Converter    /     471
5.1.12  A Low-Cost Floating Buck Converter    /    472
5.1.13  Component Constraints for the CCM Buck Converter    /    477
5.2 The Boost Converter    /      478
5.2.1  A Voltage-Mode 48-V, 2-A Boost Converter from a Car Battery    /    478
5.2.2  The ac Analysis    /     481
5.2.3  Transient Analysis    /     485
5.2.4  A Current-Mode 5-V, 1-A Boost Converter from a Li-Ion Battery    /    487
5.2.5  The ac Analysis    /     490
5.2.6  Transient Analysis    /     495
5.2.7  Input Filter    /     496
5.2.8  Component Constraints for the Boost Converter    /    501
5.3 The Buck-Boost Converter    /      501
5.3.1  A Voltage-Mode 12-V, 2-A Buck-Boost Converter Powered from a Car Battery    /    502
5.3.2  The ac Analysis    /     505
5.3.3  Transient Analysis    /     508
5.3.4  A Discontinuous Current-Mode 12-V, 2-A Buck-Boost Converter Operating
from a Car Battery    /     511
5.3.5  Ac Analysis    /     515
5.3.6  Transient Analysis    /     518
5.3.7  Component Constraints for the Buck-Boost Converter    /    521
References    /      522
Appendix 5A   The Boost in Discontinuous Mode, Design Equations    /      523
5A.1  Input Current    /     523
5A.2  Output Ripple Voltage    /     525
viii        CONTENTS

Chapter 6.  Simulations and Practical Designs of Off-Line Converters—The Front End 527

6.1 The Rectifier Bridge     /      527

6.1.1  Capacitor Selection    /     528
6.1.2  Diode Conduction Time    /     531
6.1.3  Rms Current in the Capacitor    /    532
6.1.4  Current in the Diodes    /     534
6.1.5  Input Power Factor    /     534
6.1.6  A 100-W Rectifier Operated on Universal Mains    /    535
6.1.7  Hold-Up Time    /     537
6.1.8  Waveforms and Line Impedance    /     538
6.1.9  In-Rush Current    /     542
6.1.10  Voltage Doubler    /     544
6.2 Power Factor Correction     /      546
6.2.1  Definition of Power Factor    /     547
6.2.2  Nonsinusoidal Signals    /     548
6.2.3  A Link to the Distortion    /    549
6.2.4  Why Power Factor Correction?    /     551
6.2.5  Harmonic Limits    /     551
6.2.6  A Need for Storage    /     553
6.2.7  Passive PFC    /     554
6.2.8  Improving the Harmonic Content    /     558
6.2.9  The Valley-Fill Passive Corrector    /     561
6.2.10  Active Power Factor Correction    /     562
6.2.11  Different Techniques    /     562
6.2.12  Constant On-Time Borderline Operation    /     563
6.2.13  Frequency Variations in BCM    /     565
6.2.14  Averaged Modeling of the BCM Boost    /    567
6.2.15  Fixed-Frequency Average Current-Mode Control    /     569
6.2.16  Shaping the Current    /     573
6.2.17  Fixed-Frequency Peak Current-Mode Control    /     575
6.2.18  Compensating the Peak Current-Mode Control PFC    /    577
6.2.19  Average Modeling of the Peak Current-Mode PFC    /    579
6.2.20  Hysteretic Power Factor Correction    /     581
6.2.21  Fixed-Frequency DCM Boost     /     582
6.2.22  Flyback Converter    /     586
6.2.23  Testing the Flyback PFC    /     590
6.3 Designing A Bcm Boost Pfc    /      591
6.3.1  Average Simulations    /     597
6.3.2  Reducing the Simulation Time    /     601
6.3.3  Cycle-by-Cycle Simulation    /     603
6.3.4  The Follow-Boost Technique    /     605
What I Should Retain from This Chapter    /      606
References    /      607
Appendix 6A  Diode and Bulk Capacitor Current Constraints: A Different View    /      608
6A.1  Design Example    /     610
6A.2  Selecting a Normalized Value for the Bulk Capacitor    /    612
Appendix 6B A Small-Signal Model of the BCM Boost Converter Power
Factor Corrector Operated in Voltage- or Current-Mode Control    /      614
6B.1  Current-Mode Control    /     622
References    /      626

Chapter 7.  Simulations and Practical Designs of Flyback Converters 627

7.1 An Isolated Buck-Boost    /      627

7.2 Flyback Waveforms, No Parasitic Elements    /      630
7.3 Flyback Waveforms with Parasitic Elements    /      633
7.4 Flyback Converter Operated in Quasi-Resonance    /      635
7.4.1  Deriving the Switching Frequency    /     637
7.5 Observing the Drain Signal, No Clamping Action    /      640
7.6 Clamping the Drain Excursion    /      642
7.7  Dcm, Looking for Valleys    /      647
 CONTENTS        ix 

7.8 Designing the Clamping Network    /      649

7.8.1  The RCD Configuration    /     650
7.8.2  Selecting kc    /     654
7.8.3  Curing the Leakage Ringing    /     655
7.8.4  Which Diode to Select?    /     659
7.8.5  Beware of Voltage Variations    /     659
7.8.6  TVS Clamp    /     663
7.9 Two-Switch Flyback    /      664
7.10 Active Clamp    /      666
7.10.1  Design Example    /     671
7.10.2  Simulation Circuit    /     673
7.11 Small-Signal Response of the Flyback Topology    /      674
7.11.1  DCM Voltage Mode    /     679
7.11.2  CCM Voltage Mode    /     682
7.11.3  DCM Current Mode    /     683
7.11.4  CCM Current Mode    /     686
7.12 Practical Considerations about the Flyback    /      688
7.12.1  Controller Start-Up    /     688
7.12.2  Start-Up Resistor Design Example    /     690
7.12.3  Half-Wave Connection    /     693
7.12.4  Good Riddance, Start-Up Resistor!    /     695
7.12.5  High-Voltage Current Source    /     695
7.12.6  The Auxiliary Winding    /     697
7.12.7  Short-Circuit Protection    /     698
7.12.8  Observing the Feedback Pin    /     699
7.12.9  Sensing the Secondary-Side Current    /     701
7.12.10  Improving the Drive Capability    /     703
7.12.11  Overvoltage Protection    /     704
7.13 Compensating Over Power    /      706
7.13.1  Transferring Power with a Flyback Converter    /    707
7.13.2  The Propagation Delay Affects the Maximum Output Power Level    /    709
7.13.3  Why Limit Maximum Power?    /     712
7.13.4  How Do We Practically Limit the Maximum Power?    /    712
7.13.5  The Transition from CCM to DCM    /    714
7.13.6  Deriving Variables    /     716
7.13.7  Computing the Transmitted Power    /     719
7.13.8  Over Power Protection in CCM    /    720
7.13.9  Over Power Protection with a QR Flyback Converter    /    721
7.13.10  Reducing the Maximum Current at High Line    /    723
7.13.11  Calculating an OPP Resistance    /     724
7.14 Standby Power of Converters    /      726
7.14.1  What Is Standby Power?    /     726
7.14.2  The Origins of Losses    /     726
7.14.3  Skipping Unwanted Cycles    /     727
7.14.4  Skipping Cycles with a UC384X    /    729
7.14.5  Frequency Foldback    /     730
7.15  A 20 W, Single-Output Power Supply    /      731
7.16  A 90 W, Single-Output Power Supply    /      746
7.17  A 35 W, Multioutput Power Supply    /      763
7.18 Component Constraints for the Flyback Converter    /      783
What I Should Retain from This Chapter    /      783
References    /      784
Appendix 7A  Reading the Waveforms to Extract the Transformer Parameters    /      784
Appendix 7B  The Stress    /      786
7B.1  Voltage    /     786
7B.2  Current    /     788
Appendix 7C  Transformer Design for the 90-W Adapter    /      789
7C.1  Core Selection    /     789
7C.2  Determining the Primary and Secondary Turns    /    790
7C.3  choosing the Primary and Secondary Wire Sizes    /    790
7C.4  Choosing the Material, Based on the Desired Inductance, or Gapping the Core If Necessary    /    791
7C.5  Designs Using Intusoft Magnetic Designer    /    791
Reference    /      794
x        CONTENTS

Appendix 7D  A Small-Signal Model of the Flyback Converter Operated in Quasi-Resonance    /      794
7D.1  A BCM Flyback Converter    /     796
7D.2  Application Example    /     798
7D.3  The Ac Analysis    /     799
7D.4  Numerical Application    /     801
Reference    /      803
Appendix 7E Switching Losses with a nonlinearly Varying Parasitic Capacitor    /      803
Reference    /      805
Appendix 7F  Testing Transformer Core Saturation Level    /      807
Reference    /      808

Chapter 8.  Simulations and Practical Designs of Forward Converters 809

8.1 An Isolated Buck Converter    /      809

8.1.1  Need for a Complete Core Reset    /    813
8.2 Reset Solution 1, a Third Winding    /      815
8.2.1  Leakage Inductance and Overlap    /     821
8.3 Reset Solution 2, a Two-Switch Configuration    /      824
8.3.1  Two-Switch Forward and Half-Bridge Driver    /    825
8.4 Reset Solution 3, the Resonant Demagnetization    /      829
8.5 Reset Solution 4, the Rcd Clamp    /      834
8.6 Reset Solution 5, the Active Clamp    /      844
8.6.1  Average Simulations of the Active Clamp Forward Converter    /    855
8.6.2  Ac Response of the Active Clamp Forward through Cycle-by-Cycle Simulation    /    855
8.7 Synchronous Rectification    /      863
8.8 Multioutput Forward Converters    /      865
8.8.1  Magnetic Amplifiers    /     866
8.8.2  Synchronous Postregulation    /     871
8.8.3  Coupled Inductors    /     874
8.9 Small-Signal Response of the Forward Converter    /      879
8.9.1  Voltage Mode    /     879
8.9.2  Current Mode    /     886
8.9.3  Multioutput Forward    /     889
8.10 A Single-Output 12-V, 250-W Forward Design Example    /      892
8.10.1  MOSFET Selection    /     898
8.10.2  Installing a Snubber    /     899
8.10.3  Diode Selection    /     902
8.10.4  Small-Signal Analysis    /     904
8.10.5  Transient Results    /     905
8.10.6  Short-Circuit Protection    /     911
8.11 Component Constraints for the Forward Converter     /      912
What I Should Retain from This chapter    /      912
References    /      913
Appendix 8A   Half-Bridge Drivers Using the Bootstrap Technique    /      914
Appendix 8B   Impedance Reflections     /      917
Appendix 8C   Transformer and Inductor Designs for the 250-W Adapter    /      920
8C.1  Transformer Variables    /     921
8C.2  Transformer Core Selection     /     921
8C.3  Determining the Primary and Secondary Turns    /    921
8C.4  Choosing the Primary and Secondary Wire Sizes    /    922
8C.5  Gapping the Core    /     923
8C.6  Designs Using Intusoft Magnetic Designer    /    923
8C.7  Inductor Design    /     926
8C.8  Core Selection    /     927
8C.9  Choosing the Wire Size and Checking the dc Resistive Loss    /    928
8C.10  Checking the Core Loss    /     928
8C.11  Estimating the Temperature Rise    /     928
Reference    /      929
 CONTENTS        xi 

Appendix 8D  A Small-Signal Model for the Active Clamp Forward Converter
Operated in Voltage Mode Control    /      929
8D.1  Revealing PWM Switches    /     930
8D.2  Large-Signal Simulations    /     933
8D.3  Small-Signal Modeling    /     934
8D.4  The Magnetizing Current Resonant Circuit    /     938
8D.5  Final Lap: Associating All the Blocks    /     945
8D.6  Testing a Prototype Response in the Bench    /     948
Reference    /      953
Appendix 8E   Web Content    /      953

Conclusion   955
Index   957
ABOUT THE Author
Christophe P. Basso is currently an engineering director at ON Semiconductor
in France, where he has developed numerous popular switching power supply
controllers, for instance, for the notebook adapter business. He is the author of
several books on power electronics, including McGraw-Hill’s Switch-Mode
Power Supply SPICE Cookbook, and, recently, he released a title 100% dedi-
cated to loop control, Designing Control Loops for Linear and Switching Power
Supplies. He regularly teaches professional seminars at IEEE-sponsored Applied
Power Electronics Conferences and often publishes articles in trade magazines
such as PET and the online newsletter How2Power. Mr. Basso graduated from
the Montpellier University in 1985, and he received his M.S.E.E. in power elec-
tronics from the National Polytechnic Institute of Toulouse in 2008. He holds 29
patents in the field of power electronics and he is an IEEE Senior Member.
 Preface

I am glad to introduce the second edition of my 2008 book Switch-Mode Power Supplies: SPICE
Simulations and Practical Designs. I would like to thank all the readers who have contributed to make the
first edition a success. I received numerous warm and supportive messages from all around the world and
it is extremely rewarding. Without you, this new book would not exist. Some of these readers have been
kind enough to report typos and errors they found in the first edition. I compiled them throughout the years
and I used the list to clean equations and figures.
Revising a book is not an easy task, as some readers will object that there is too little renewed content
to make it a new book while others complain that this new edition represents a completely different docu-
ment than the first one they bought! Needless to say, trying to please both parties is a perilous exercise.
Loyal to my original approach, I added topics in which I detailed the mathematical treatment so that you
can follow and learn from the book. In Chap. 1, it is the case for rms constraints concerning the basic
switching cells. In most of the available books, authors give formulas without founding equations and often
limit their analysis to one conduction mode. Here, both conduction modes are explored and detailed, with
clear summary tables at the end. Numerous Mathcad® sheets are provided online at www.mhprofessional
.com/Basso to let you evaluate your own configurations. Small-signal-wise, Chap. 2 has been expanded
with the PWM switch at work in a discontinuous conduction mode boost converter and the derivation of a
feedforward compensator gain. Chapter 3 now includes OTA-based compensators and offers a transistor-
level TL431 model. Chapter 4 includes several revisions on blocks such as the D-flip-flop and the leading
edge blanking timer. Chapter 6 now includes a complete small-signal analysis of the borderline-operated
boost PFC circuit operated in voltage or current mode. Chapter 7 covers in detail all over power phenomena
in fixed-frequency discontinuous or continuous flyback converters, without forgetting quasi-resonance. A
small-signal model of a QR flyback converter is presented in one of the appendices. Finally, Chap. 8
includes a new small-signal model of the active clamp forward converter operated in voltage-mode control.
I hope you will enjoy reading this second edition, in particular the newly added materials. Despite all my
efforts, some typos or mistakes may have escaped my attention and I would be grateful if you would send
your corrections/remarks to cbasso@wanadoo.fr. As usual, I will keep a record of these findings and compile
them in my webpage http://cbasso.pagesperso-orange.fr/Spice.htm for the benefit of the reading community.
I thank you in advance and wish you the best of luck for your designs!

Christophe P. Basso

xiii
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 Acknowledgments

My warmest thanks and love go first of all to my dear family: Anne, my wife, and my two beloved children,
Lucile and Paul. Revising an entire 900-page book cannot be done overnight and I am grateful I could spend
endless hours correcting and writing new paragraphs without affecting family life. Now that it is done, I
will enjoy hiking, cycling, reading, snowshoeing, and spending leisure time with you all again!
The book revision could not have been envisaged without the help and involvement of many people. I
wish to thank Joël Turchi, my friend and colleague at work, who is always available to discuss technical
subjects for hours and review my work. These discussions also took place with the application team with
whom I am lucky to work: Thierry Sutto, Stéphanie Cannenterre, Yann Vaquette, and Dr. José Capilla. They
kindly reviewed this second edition’s materials. Special thanks go to Alain Laprade of ON Semiconductor
in East Greenwich who kindly reviewed several chapters.
I wish to also express my gratitude to my beloved parents, Michele and Paul Basso, who bought me my
first power supply when I was 14 and let me develop my passion for electronic circuits, at the expense of
numerous breaker trips. As we have returned to my youth, “merci” to teachers such as René Vinci and
Bernard Métral from the “Clos-Banet Lycée,” who instilled their passion and knowledge into the restless
student that I was. At the same time, I published my first article in Radio-Plans (1982), thanks to my friends
Claude Ducros and Christian Duchemin, last editors-in-chief of the now-defunct magazine. Finally, Claude
Duchemin from the Montpellier University added the finishing touches and plugged my fingers into the
switching power supply world!
Both the first and second editions of this book incorporate comments and recommendations from pres-
tigious people I have been honored to work with. Their names follow and I wish to thank them warmly for
the amount of time they spent reviewing the first edition’s materials and tracking inaccuracies: Dr. Vatché
Vorpérian (Jet Propulsion Laboratory), Dr. Richard Redl (Elfi), Ed Bloom (e/j BLOOM associates Inc.), Dr.
Raymond Ridley (Ridley Engineering), Dr. Ivo Barbi (Power Electronics Institute of the Federal University
of Santa Catarina), Jeff Hall (ON Semiconductor), Dhaval Dalal (Acptek), and not forgetting Monsieur
Mullett (formerly with ON Semiconductor) for the two appendices kindly contributed on magnetic designs!
Also, Christian Zardini (retired from the ENSEIRB school), Dr. Franki Poon and Dr. S. C. Tan (PowerELab
and the Hong Kong Polytechnic University), Dr. Dylan Lu (Sydney University), Arnaud Obin (formerly
with Lord Engineering), Dr. V. Ramanarayanan (Electrical Engineering Department of the Indian Institute
of Science in Bangalore), Dr. Jean-Paul Ferrieux (Laboratoire d’Electrotechnique de Grenoble), Steve
Sandler (AEi Systems), Dr. Didier Balocco (formerly with Saft Power Systems), and Pierre Aloisi (for-
merly with MOTOROLA).
I would also like to thank the people at Intusoft, Larry and Lise Meares and all their great support team
(George, Farhad, Everett, Tim), who helped me during the testing phase of the numerous book examples. I
want to thank the editors of simulation software who have kindly contributed simulation examples.
Finally, thank you to Mike McCabe, at McGraw-Hill, for giving me the opportunity to publish a new
edition of my original book.

xv
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 NOMENCLATURE

Ae the cross-section area of a magnetic material

BVDSS the MOSFET drain-source breakdown voltage
B the induction flux density in a magnetic medium
BCM borderline conduction mode (same as CrM) or boundary conduction mode
Br the remanent induction flux level when the magnetizing field is zero
Bsat the induction flux density at which mr drops to 1
CCM continuous conduction mode
CL closed loop
Clump the total capacitance seen on a particular point of the circuit
CrM critical conduction mode
CTR current transfer ratio for an optocoupler
D or d the converter duty ratio; also noted d1 in DCM analysis
D′ or d′ the duty ratio off time (d′ = 1 − d )
d2, d3 the duty ratio off times in DCM: 1 = d1 + d2 + d3
DT the dead time between switching events
D0 the converter static duty ratio during a bias-point analysis
ΔIL the peak-to-peak ripple current in the inductor
ESR equivalent series resistance
ESL equivalent series inductance
h the converter efficiency, eta
fc the crossover frequency, where |T(fc)| = 0 dB
Fsw the switching frequency
Fline the mains frequency
G(f) the compensator frequency response
Gfc the gain deficit (or excess) at the selected crossover frequency fc
j the flux in a magnetic medium
jm the phase margin read at the crossover frequency fc
gm the transconductance of an operational transconductance amplifier (OTA)
H the magnetizing force
Hc the coercive field which brings the flux density back to zero
H(f) the converter power stage (the plant) frequency response
Ia, Ip, and Ic the average currents flowing in or out of the PWM switch terminals
IC the current inside a capacitor C
Id the diode current
ID the MOSFET drain current
Iin the input current of a given converter
Iin,rms or Iac the input rms current in a mains powered converter
IL the current in an inductor L
Imag the transformer magnetizing inductor current in a forward converter
Iout the output current of a given converter
xvii
xviii        NOMENCLATURE

Ip the primary current in a transformer-based converter

Ipeak the peak current in a given element
Isec the secondary current in a transformer-based converter
Ivalley the valley current in a given element
kD the derating factor for the MOSFET BVDSS
kd the derating factor for the diode VRRM
l, le, lm the mean magnetic path length
lg the gap length in a transformer
Lp the primary inductor of a transformer (usually in a flyback converter)
LHP left half-plane zero (LHPZ) or pole (LHPP) located in the left portion in an
s-plane plot
Lleak  the transformer total leakage inductance seen from the primary (all outputs
shorted)
Lmag the magnetizing inductance of a transformer (usually in a forward converter)
Lsec the secondary-side inductor of a transformer
M the converter conversion ratio, Vout /Vin
Mc  the slope compensation level in a current-mode converter (per Dr. Ridley’s
definition)
Mr  the external ramp coefficient in current-mode designs (as a percentage of the
off slope)
mr the permeability of a material relative to that of free space
mi  the initial permeability describes the slope of the magnetization curve at the
origin
m0 the permeability of the air
N  the turns ratio of a transformer normalized to its primary winding. For instance,
if Np = 10 and Ns = 3, then N = 0.3
OL open loop; for instance a gain, a phase, or an output impedance
Pcond  the conduction losses of an element implying a resistive path and a rms current
squared
PF power factor
PFC power factor correction
Pout the converter output power
PIV the peak inverse voltage a diode has to sustain
PSW  switching losses of an element implying an overlap area between a current and
voltage
Q the quality coefficient of a filter or the quantity of electricity (coulombs)
Qr  the charge the diode needs to evacuate before recovering its blocking capabilities
Qrr the total diode recovery charge
QG  the amount of coulombs you need to bring to the MOSFET for its full enhancement
rCf the series resistor of the capacitor; also noted the ESR
rLf the series resistor of the inductor; also noted the ESL
RDS(on) the MOSFET drain-source resistance when turned on
rms root mean square
Rsense or Ri 
the sense resistor in a current-mode converter; sometimes called the burden resistor
RHP right half-plane zero (RHPZ) or pole (RHPP) located in the right portion in an
s-plane plot
Sa or Se the external compensation ramp
Son or S1 the inductor slope during the on time
SEPIC single-ended primary inductance converter
 NOMENCLATURE         xix 

SMPS switch-mode power supply

SPICE Simulation Program with Integrated Circuit Emphasis
Soff or S2 the inductor slope during the off time
Sr the externally imposed blocking slope when blocking a diode
tc the rectifying diode conduction time
td the bulk capacitor discharge time
ton the time during which the power switch is turned on
toff the time during which the power switch is turned off
tprop the propagation delay of the logic blocks in a controller
trr the reverse recovery time of a diode
THD the total harmonic distortion
TVS transient voltage suppressor
T(f) the compensated loop gain
Tj the junction temperature
Tsw the switching period
Vac, Vcp the average voltages across the PWM switch terminals
Vbulk the bulk voltage
Vbulk,max or Vpeak the bulk voltage at the highest line (the ripple is neglected in this case)
VC the voltage across a capacitor C
Vce(sat) the saturation voltage of a bipolar transistor
Vclamp the clamping voltage level
VDS the MOSFET drain-source voltage
Vf the diode forward drop
VGS the MOSFET gate-source voltage
Vin the input voltage of the converter
Vin,rms or Vac the mains rms voltage
VL the voltage across an inductor L
Vleak the voltage across the leakage inductance
Vmin or Vbulk,min the bulk valley voltage, low line only
VOS the voltage overshoot on the RCD clamp
Vout the output voltage
Vpeak the peak amplitude of sawtooth ramp in a voltage-mode PWM
Vp the peak undershoot voltage in response to a load step
Vr  the secondary-side voltage reflected on the primary side in a transformer-based
converter
Vsense the voltage developed across the sense resistor in a current-mode converter
Vripple the peak-to-peak ripple voltage
VRRM the diode maximum repetitive reverse voltage
ζ the Greek letter zeta, representative of the damping factor [often mixed up with
ξ (xi)]
This page intentionally left blank
 Chapter 1
Introduction to
Power Conversion

User friendliness is a key factor for the commercial success of any simulation program. The growing com-
plexity of integrated circuits and equipment makes this aspect increasingly important. Despite numerous
publications devoted to the Simulation Program with Integrated Circuit Emphasis (SPICE), it still scares
the novice when its name is mentioned.
Developed in the mid-1970s at the University of California, Berkeley, the SPICE program’s primary aim
was to fulfill the needs of the electronics industry––mainly integrated circuit makers. However, with the sup-
port and funds from private editors, the SPICE program has evolved over a number of years into many practi-
cal and affordable packages, with emphasis on providing both low-priced and friendly access to beginners.
SPICE can significantly help you speed up the design phase of the equipment you are currently working
on, even if SPICE is not able to generate an electronic schematic by itself. SPICE is inherently efficient
because if you start working with an unfamiliar concept, it will quickly enable you to grasp the full mean-
ing of any particular architecture by unveiling its peculiar waveforms. You can thus use the simulator to
gain insight into the circuit you have to build and also ensure all parameters are taken into account before
the breadboard phase.
This book is intended for power supply designers, experts in their fields, as well as for beginners who
would like to understand the secrets of switch-mode power conversion. Manipulating virtual components
on a computer screen, without the hazards of high voltage, offers an interesting and safe way to learn the
technique. Furthermore, the “experience” gained in simulation, and it is also true for experts simulating a
novel concept, will let you feel more comfortable when breadboarding on the bench.

1.1  “Do you really need to simulate?”

How many times have you heard this question when asking for a simulation package or a new computer?
The following statements do not represent an exhaustive list of pros about computer simulation, but they
can certainly be considered a “help list” available during the negotiations:
1. Here is an argument: Simulation can avoid waste of time and money. With its inherent iterative power,
SPICE covers numerous application cases in which you could easily detect any design flaw or product
weakness. The stability of a closed-loop SMPS represents a typical application when some key feedback
elements are moving (i.e., the variable load that affects a pole) or start to degrade with temperature
and aging (as the electrolytic equivalent series resistor). Moreover, design ideas can also be tested or
assessed in a snapshot through a computer and, if they are worth trying, further refined in the lab.
2. You can start to work on a project by downloading components models and becoming familiar with the
key elements, before going to the bench or waiting for the samples to be delivered. Once these samples
arrive, you will have already gained insight by prototyping with the simulator and the practical debug
phase on the bench will clearly take benefit from your first computer-based experiments.
3. Simulate test measurements whenever you do not own the adequate equipment: Bandwidth measure-
ments represent a good example. If you cannot afford a network analyzer, then a proven small-signal
model can help you start to refine your feedback loop. When run on the final prototype, stability assess-
ments will be faster and more efficient.
4. Power libraries are safe: They let you experiment “what if” when amperes and kilovolts are flowing
in the circuit without blowing up in the event of a wrong connection! Also, they let you see how your

1
2 chapter one

design reacts to a short-circuit of the optocoupler or the opening of a resistor. SPICE can begin to give
you the answer.

1.2  What you will find in the following pages

This book thoroughly details the advantages of SPICE to let you understand, simulate, test, and finally
improve the switch-mode power supply (SMPS) you want to design. By providing you with specific
simulation recipes, this work intends to facilitate as much as possible your SMPS design. Unlike other
books, the author strives to balance the theoretical content, necessary to understand and question simula-
tion results, with practical design examples. This is developed throughout the eight chapters of the book.
Chapter 1 explains switch-mode power supply techniques and types of converters, and it introduces
a few important results to help you better understand averaging techniques. This second edition includes
the comprehensive derivation of root mean square (rms) current constraints of the basic switching cells,
buck, boost, and buck-boost operated in continuous or discontinuous conduction modes. As usual, I
have detailed derivation steps so that you can follow and learn the technique in case you encounter a
different switching cell. A new appendix has been added. Chapter 2 explains how average models were
derived, and different types are described. A good comprehension of this chapter is fundamental: It will
help you question certain weird SPICE data resulting from a bad model implementation. If you do not
understand the way the model has been derived, you will obviously face some difficulties in resolving
these issues. In Chap. 2, you will also learn how to wire an average model and run basic simulations.
This second edition adds the description of the feedforward modulator. I added more details to the small-
signal PWM switch. In particular, I show how keeping the same voltage-mode average model to which
you add a “duty ratio factory” turns the model into a simplified version of current mode. An appendix
has been added focusing on the DCM (discontinuous conduction mode) voltage-mode boost small-signal
transfer function. Closing the loop is obviously an important aspect of converter design that is often
overlooked. This is not the case here, and Chap. 3 will guide you through control loop design, again
using practical examples with a TL431 and not op amps only, as often seen in the literature. OTA (opera-
tional transconductance amplifiers) compensators are now part of this chapter, covering types 1 and 2.
A complete transistor-level model of the TL431 has been added to its dedicated appendix. Because not
every integrated circuit always comes with a SPICE model, Chap. 4 describes how the generic switched
models are derived. This chapter will interest those who want to strengthen their knowledge of SPICE
model writing. A more robust D-flip-flop is described and several new circuits have been added. Chapter
5 describes practical designs of the three basic nonisolated topologies, including the front-end filter.
Before analyzing off-line converters, Chap. 6 shows how to design the rectifying section and explains
the various power factor correction techniques. Small-signal response of the popular borderline-operated
power factor correction (PFC) has been added in a dedicated appendix. Chapter 7 is entirely dedicated to
the flyback converter, with specific design examples at the end. A new section on over power has been
added and it covers all operating modes, including QR converters. An appendix gives the small-signal
response of the QR converter. Nonlinear capacitor switching losses are explored in a dedicated appendix.
Finally, the forward converter appears in Chap. 8, again associated with a design example. The coupled-
inductors section has been updated and a complete small-signal model of the active-clamp converter
operated in voltage-mode is presented with experimental results.
Version syntax is a significant issue with SPICE. Most SPICE editors deal with a proprietary syntax,
sometimes SPICE3 conformant, that makes translation from one platform to another a difficult and painful
exercise. To allow the use of different simulators, the standard models presented throughout the pages are
compatible with Intusoft IsSpice (San Pedro, Calif.) and CADENCE’s PSpice (Irvine, Calif.).
To help you quickly copy and paste examples, simulation files have been made available for download
from a McGraw-Hill website. Please check App. 8E for details. Some selected simulation examples are
offered in IsSpice and PSpice syntax, and you can easily load them on your computer if you have one of these
software programs. For students or newcomers to the SPICE world, some demonstration versions will let
you open files and simulate some of them (those demos are size-limited) to give you a taste of what the full
version can do. The McGraw-Hill download page contains PowerPoint® and Mathcad® files to let you key in
your own design parameters and check small-signal response or rms constraints of the basic switching cells.
 Introduction to Power Conversion 3

For professional power supply designers, another library file is separately distributed. This file contains
the design examples presented in the book plus numerous other industrial applications using real control-
lers. Please visit the author’s website for distribution details (http://cbasso.pagesperso-orange.fr/Spice.htm).

1.3  What you will not find in this book

This book does not describe the way SPICE operates, nor does it solve typical electric circuits. It assumes
that the reader is already familiar with the basics of SPICE simulations. Numerous books and papers are
available on the subject as the References section details [1, 2]. Whenever possible, the extended bibliog-
raphy will guide your choice if you wish to strengthen your knowledge in a particular domain, such as
some topologies that you are unfamiliar with. If some theoretical results are sometimes delivered just “as
is,” we strongly encourage the reader to dig further into the appropriate literature and acquire the theory
that precedes the result.
The book focuses only on a system approach. No SPICE description of typical discrete power elements
such as diodes, MOSFETs, etc., is proposed.
Finally, here is the important statement, probably the most interesting one! SPICE does not replace the
breadboard phase, nor does it shield you from writing equations or understanding electronics. It looks like
a simple sentence, but the author has often been confronted by designers showing boards in the trash and
claiming, “But SPICE said it would work!!” Yes, all ideas work on paper until they face the soldering iron
condemnation.… Use SPICE as a design companion, a circuit insider that can reveal waveforms difficult
to observe. But always question the delivered data: Is this the real behavior, have I been misled somewhere,
does a simple calculation more or less confirm what I see?
After this brief introduction, it is time to plunge into the intricacy of SMPS design and simulation with
SPICE.

1.4  Converting power with resistors

In the electronics world, different types of circuitries must cohabit: logic devices, analog circuits, micro-
processors, and so on. Unfortunately for the designer, these circuits do not cope with a single, fixed, power
supply rail: A microprocessor or a digital signal processor (DSP) will need a stable 3.3-V source or less,
a front-end acquisition board will require ±15 V and perhaps some logic glue around a standard 5 V. For
the final board being supplied from a single power point, for example, the mains outlet or a battery, how is
one to adapt and distribute all these different voltages to the appropriate portions? The solution consists of
inserting a so-called converter to adapt the voltage distribution to the circuit needs.

3.30
1.4.1  Associating Resistors R2
132 Rload2 3V3
Figure 1.1 portrays the simplest option a designer can think of: 50 DSP
resistive dividers. If our DSP consumes 66 mA over 3.3 V, then it
can be replaced by a 50-Ω resistor, the same as for our 50 mA, 5-V R1
logic circuit via the 100-Ω resistor. From a 12-V source, we can 12.0
140
then calculate the dropping resistors: 5.00
+
Vin 5V
Rload1
12V logic
12 − 5 100
R1 = = 140 Ω (1.1)
50 m

12 − 3.3 Figure 1.1  The simplest voltage distri-

R2 =
  = 132 Ω (1.2)
66m bution via resistors.
4 chapter one

Before going further, please note that 0.066 A or 0.05 A was, respectively, noted in the calculation as
66m or 50m. This is done to retain the SPICE notation for units, without any space. It adheres to the fol-
lowing rules and will be extensively used in the remaining portions of the book:
p = pico = 10-12
n = nano = 10-9
m = micro = 10-6
m = milli = 10-3
k = kilo = 103
Meg = mega = 106

• Beware not to mix mega and milli, a very common mistake: 10 mΩ = 10m, 1 MΩ = 1Meg.

Unfortunately, these resistors will be the seat of a permanent voltage drop, and power dissipation (in
heat) will occur. The dissipated power for each resistor is

(12 − 5)2
P1 = = 350 mW (1.3)
140

(12 − 3.3)2
P2 = = 573.4 mW (1.4)
132

From these values, we can now evaluate the system efficiency obtained by dividing the delivered output
power Pout by the power taken away from the source Pin:

52 3.32
Pout = + = 250 m + 218m = 468 mW (1.5)
100 50

122 122
Pin = + = 600 m + 791m = 1.39 W (1.6)
100 + 140 50 + 132

The efficiency, represented by the Greek letter h or “eta,” can be computed by dividing Pout by Pin, or

Pout 0.468
η= = × 100 = 33.6% (1.7)
Pin 1.39

which is an extremely poor performance!

The loss, dissipated in heat, is simply the difference between the power delivered by the source and the
power, converted as the real work, Pout.

Pout 1 
Ploss = Pin − Pout = − Pout = Pout  − 1 (1.8)
η η 

In our example, the loss is 1.39 - 0.468 = 922 mW.

1.4.2  A Closed-Loop System

If the load changes, or if the input voltage drifts, what is going to happen? Well, since our input-to-output
transfer ratio, denoted M, is fixed, the output voltage will also vary. Therefore, we need to think of a kind
of regulated system that permanently observes the output power demand and adjusts the series resistor
 Introduction to Power Conversion 5

to maintain a constant output voltage, if the output voltage represents the variable of interest. For a well-
designed system, the converter must also ensure a proper regulation independent of input voltage variations.
To reach this goal, we need to use several specific components such as

• A reference voltage Vref  : This voltage is by definition extremely stable in temperature and precise in
value (e.g., ±1%). A programmable shunt regulator, such as a TL431 adjustable Zener diode, could do
the job.
• An operational amplifier (op amp): This device will observe a portion of the output voltage (aVout) and
compare it to the reference Vref . It will actually “amplify” the error, the difference between aVout and
Vref , to drive a series-pass element. The error monitored by the op amp is usually denoted by the Greek
letter e or “epsilon”: ε = α Vout − Vref .
• A series-pass element: It can be a MOSFET or a bipolar transistor but working in a linear mode, playing
the role of the necessary variable resistor. If it is a MOSFET, the static driving power is null. For a bipo-
lar, there is a need to supply a sufficient amount of base current to deliver the right collector or emitter
current. This is called the bias current.

Figure 1.2 finally shows how our resistive converter could be improved, let’s say for the 5-V section.
The error amplifier is made via a voltage-controlled voltage source (E primitive) and features a gain of
10k or (80 dB), 20 log10 (10 k ). One input receives the voltage reference whereas the other one, the inverting
input, is biased by a portion of the output voltage. This is actually a linear regulator, however, limited in
the input voltage range since Vin shall be above Vout by a Vbe, at least, to guarantee a proper drive for Q1. If
Vout is below the target (5 V in our example), E1 output increases and strengthens Q1 bias current: Vout goes
up. On the other hand, suppose the load has suddenly been reduced, therefore Vout exceeds 5 V. Thanks to
E1, Q1 bias current goes down, reducing the output voltage until regulation is met again.

Q1
2N2222 Vout

Ib Iout
Iin E1 Rupper
10k 10k
+
Vin – Rload
12 + 100
–
+
+V Rlower
ref 10k
2.5

Figure 1.2  The addition of an error amplifier brings regulation to the

circuit: We have built a linear regulator.

The output voltage observation, which delivers aVout (a fraction of the output voltage), is obtained
through a resistive divider made of Rupper and Rlower. Calculating their values is straightforward:

1. Let us fix a current circulating in the divider bridge. Since there is no biasing current for E1 in the
example (this is the case for most MOS-based technologies), we could take Ib = 250 μA, for example.
A lower value is acceptable, but degrades the noise immunity in a noisy environment.
2. Ib equals 250 μA and entirely circulates in Rlower. Thanks to the control loop, 2.5 V is “seen”across
2.5
Rlower . Therefore, Rlower = = 10 kΩ.
250u
Vout − Vref 5 − 2.5
3. The voltage drop across Rupper is Vout - Vref. Thus, Rupper = = = 10 kΩ.
Ib 250u
6 chapter one

90.0
80.0
70.0
60.0

Efficiency (%)
50.0
40.0
30.0
20.0
10.0
0.0
5 7 9 11 13 15 17
Input voltage (V)

Figure 1.3  As soon as M diminishes, the efficiency dramatically drops (Vout = 5 V).

If we neglect the power needed to drive Q1, then all the source current Iin flows into the load as Iout.
Therefore, applying Eq. (1.7), we can derive the efficiency for this linear regulator:

Pout Vout I out Vout

η= = ≈ = M (1.9)
Pin Vin I in Vin

If we now plot the efficiency versus the input voltage, we can see how difficult the situation becomes
in the presence of small M ratios (Fig. 1.3). For these reasons, resistive divider type of converters, that is to
say series-pass regulators, are limited to applications where M does not fall below 0.3. Otherwise the heat
dissipation burden becomes a real handicap. On the other hand, when the user really needs to operate a
regulator to ratios M closer to 1 (Vin very close to Vout), the low-dropout (LDO) regulator made with a PNP
becomes a good choice. The input low limit is now linked to the transistor Vce(sat) (a few hundred millivolts,
or less) rather than its Vbe (around 650 mV at room temperature, 25°C).
To close the study on regulator efficiency, we can take three different output examples with linear regu-
lators, where output and input conditions vary:
5
1. Vin = 14 V Vout = 5 V ∆V = Vin - Vout = 9 V η = 100 = 35.7%
14
12
2. Vin = 14 V Vout = 12 V ∆V = Vin - Vout = 2 V η = 100 = 85.7%
14
3
3. Vin = 5 V Vout = 3 V ∆V = Vin - Vout = 2 V η = 100 = 60%
5
As a result, one can see that a high efficiency can be obtained with a linear regulator if ∆V is small (as
plotted in Fig. 1.3), but also if Vout >> ∆V.

1.4.3 Deriving Useful Equations with the Linear Regulator

Figure 1.2 is interesting because we can use it to derive general statements, pertinent to the closed-loop
world we are going to enter, linear, or switched. Suppose that we remove the error amplifier and replace it
by a fixed voltage source of 5.77 V, our actual op amp output (look at Fig. 1.2 values), as Fig. 1.4 shows.
The regulator becomes a simple emitter-follower circuit, affected by an output impedance and an output
voltage. As such, it can be described with its equivalent Thévenin generator, what Fig. 1.5 suggests. Rs,OL
represents the open-loop output impedance and Vth, the voltage delivered when biased by a control volt-
age Vc, our fixed 5.77 V in the application. Let us now use this representation and redraw our closed-loop
regulator around it, ignoring, for now, the input voltage contribution.
 Introduction to Power Conversion 7

Q1
2N2222 Vout 5.00
12.0

Iin 5.77 Iout

Rs,CL

+V
in Rload
12 100 +
+V Vth = f (Vc)
bias
5.77 Vth

Figure 1.4  If the feedback is suppressed,

there is no output voltage observation to adjust Figure 1.5  A Thévenin generator portrays the
Q1 bias point: We are running open-loop. regulator when run in closed loop.

In Fig. 1.6,Vout(s) is compared to Vref (s) via a resistive divider affected by a transfer ratio of a. H(0) illus-
trates the static or dc relationship between the output voltage and the control voltage Vc, e.g., Vc = 5.77 V to
obtain Vout = 5 V in this example. The theoretical dc voltage (s = 0, but we purposely avoided this subscript
below for the sake of clarity) you would expect from such a configuration is
Vref
Vout = (1.10)
α
Unfortunately, the whole gain chain and various impedances will affect this value. With a few lines of
algebra, we can write the static output voltage definition (again, s = 0) simply by following the meshes:
Vout
Vout = (Vref − α Vout ) HG − Rs ,OL (1.11)
Rload
Vref HG
Vout = (1.12)
R
1 + α HG + s ,OL
Rload

Vout (s)
H(s)
Rs,OL

Vc(s)
Rupper

a Rload
–
G(s) +

Vref (s)
Rlower
dc bias
0

Figure 1.6  When closing the loop, our Thévenin gen-

erator undergoes a transformation in its dynamic behavior.
Here, the input perturbation is purposely omitted.
8 chapter one

The static error on the output, actually the deviation between what we really want and what we finally
obtain, is derived by subtracting the Vout expression Eq. (1.12) from Eq. (1.10):

 
Vref Vref HG  
1 1
Verror = − = Vref  −  (1.13)
α Rs ,OL α 1  Rs ,OL 1  
1 + α HG +  +α +  
Rload  HG  Rload HG  

If we consider Rs,OL << Rload, then Eq. (1.13) simplifies to

 
1 1 
Verror = Vref  − (1.14)
α α+ 1 
 
HG
which equals zero if
1
α =α + (1.15)
HG
From this equation, we can see that increasing the dc gain, G(0), helps diminish the static error which
finally affects our output voltage precision.
Another important parameter influenced by the loop gain is the closed-loop output impedance. The
output impedance of a system can be derived in different manners. As Fig. 1.5 has shown, our closed-loop
generator can now be reduced to its Thévenin equivalent, that is, a voltage source Vth [Vout measured with-
out any load, or Rload = ∞ in Eq. (1.12)], followed by an output impedance Rs,CL, which we actually look
for. One option consists of calculating a resistor RLX which, once wired between the output and ground, will
V
reduce Vout = Vth to Vout = th . When this occurs, RLX simply equals Rs,CL (we have built a simple resistive
2
divider with equal resistors). We can quickly manipulate Eq. (1.12), assuming Rload = ∞ :
Vth
= Vout ( RLX ) or “What value of RLX will divide the Thévenin voltage by 2?”
2
Vref HG Vref HG
= (1.16)
2(1 + α HG ) R
1 + α HG + s ,OL
RLX
If we call α HG the static loop gain T, then the closed-loop output impedance is

Rs ,OL R
RLX = Rs ,CL = = s ,OL (1.17)
1 + α HG 1 + T
Equation (1.17) teaches us different things:

1. If we have a large dc loop gain T(0), then Rs,CL is close to zero.

2. Because we have compensated the feedback return path G(s) for stability purposes, when the loop gain
T(s) reduces as the frequency increases, Rs,CL starts to rise: An impedance whose magnitude grows with
frequency looks like an inductance. We will come back to this result later.
3. When the loop gain T(s) has dropped to zero, the system exhibits an output impedance that is the same
as in the lack of feedback, Rs,OL: The system runs open-loop.

Why do we talk about a static (dc) and a frequency-dependent gain? Well, this is so simply because Figs. 1.5
and 1.6 do not represent genuine regulators. In reality, G(s) is made via a real operational amplifier, impos-
ing a virtual ground on its inverting pin as soon as local feedback exists. In other words, Rlower simply goes
off the picture in the small-signal model, and a no longer plays a role. This is described in App. 3D.
 Introduction to Power Conversion 9

In this example, we purposely did not account for an input voltage perturbation. This assumption is valid
for bipolar transistors as the weak influence of the Early effect makes them good current generators, almost
independent from their Vce variations. However, when Vout and Vin are close to each other, the transistor
becomes a closed switch rather than a current source. Therefore, the input voltage starts to play a role. Let us
redraw the Fig. 1.6 sketch, including the input voltage contribution. As drawn in Fig. 1.7, the term k represents
the open-loop audio susceptibility, denoted As,OL. It represents the input voltage contribution to the output.

+ Vout (s)
H(s)
+ Rs,OL
k
Vc(s) Rupper

Vin
a Rload
–
G(s) +

Vref (s)
dc bias Rlower
0

Figure 1.7  Our previous regulator mode is now upgraded with an

input perturbation kVin.

Let’s now write the mesh equations as we did previously:

Vout
Vout = (Vref − α Vout ) HG + ( kVin ) − Rs ,OL (1.18)
Rload

 R 
Vout 1 + α HG + s ,OL  = Vref HG + kVin (1.19)
 Rload 
Vref HG kVin
Vout = + (1.20)
 Rs ,OL   Rs ,OL 
1 + α HG + 1 + α HG +
Rload   Rload 

Again, if we consider Rs,OL << Rload , then

Vref kVin
Vout = + (1.21)
 1 + α HG )
+ α 
(1
 
HG

As Eq. (1.21) shows, Vout is made of two terms:

1. The theoretical output voltage, similar to what was defined in Eq. (1.12), simplified, gave (Rload = ∞)
k
2. The input voltage contribution whose new term is or, sticking to the previous definition,
(1 + α HG )
As ,OL A
As ,CL = = s ,OL (1.22)
1 + α HG 1 + T
10 chapter one

Again, operating with a large dc gain ensures an excellent rejection of the input voltage ripple (100
or 120 Hz for full-wave rectification). When T(s) reduces in the high-frequency domain, the system runs
open-loop. Please note that we purposely selected a positive polarity for k, but a negative value could also
have been chosen. It actually depends on the topology under study.

1.4.4  A Practical Working Example

Thanks to SPICE, we can simulate a completely theoretical regulator by associating blocks. Fig. 1.8 depicts
the circuit where you will recognize the block discussed above. The operating parameters are the following:
Rs,OL = 1 Ω
As,OL = 50 m
Vin = 15 V
Vout = 5 V (target)
Vref = 2.5 V
a = 0.5
Please ignore, for now, the presence of the compensation network Rf - Cf . Applying our above input
numbers reveals these closed-loop values:

Equation (1.17), Rs,CL = 1.996 mΩ, or in dBΩ: 20 log10 ( Rs ,CL ) = 20 log10 (1.996m) = −54 dBΩ
Equation (1.20), Vout = 4.991318 V
Equation (1.22), As,CL = 99.8u, or in decibels: 20 log10 ( As ,CL ) = 20 log10 (99.8u) = −80 dB

X2
GAIN
Vin k = 0.05 X3
SUM 2
15.0 0.750 RSOL
GAIN K1
5.09 1 4.99
SUM 2 Vout
4.34 K2

Alpha = 0.5
Rupper
10k

+ + Rf Cf
–

Vin G 100 100 nF

15 E2
0.434 Rload ILoad
+ 50 AC = 1
–

10
2.50 for Zout
– sweep
0.434 +
– 2.50
+
+ Rlower
Beta V1
E1 2.5 10k
100

Figure 1.8  Our theoretical linear regulator, including the output impedance and the input voltage perturbation.
 Introduction to Power Conversion 11

Now, let us compare to what the SPICE simulator will give. We have several options. The first one uses
dV (V )
a .TF statement, which performs a out in calculation as well as an output impedance measurement. The
dVin
SPICE code is the following: .TF V(vout)vin. Once it has run, we obtain the results in the .OUT file:
***** SMALL SIGNAL DC TRANSFER FUNCTION

output_impedance_at_V(vout) 1.995928e – 003

vin#Input_impedance 1.000000e + 020
Transfer_function 9.979642e – 005

As one can see, we are very close to our theoretical numbers. The input impedance value does not make
sense here since we do not absorb current from the source. Now, we can transient-step the input and observe
the output. Stepping the input means replacing the fixed Vin source by a pulsewise linear (PWL) statement. This
SPICE function builds the curve you wish by (time, amplitude) couples. It associates linear segments together.
Here, we start for t = 0 at Vin = 15 V and suddenly increase Vin when t = 10 μs with a 1-μs slope to 500 V:
Vin 7 0 PWL 0 15 10u 15 11u 500

Figure 1.9 reveals the output response when the input is suddenly increased from 15 up to 500 V. We
can observe a deviation of 48.4 mV engendered by a 500 - 15 = 485 V input variation. Therefore, the dc
audio susceptibility is 0.0484 / 485 = 99.8u, which matches the closed-loop calculation.

Vout = 5.03V
815 5.03
Vout = 48.4 mV
Vin = 500V
415 5.01
vout in volts
vin in volts

Vout = 4.99V
Plot1

0 4.99
Vin = 15V

–385 4.97

–785 4.95

2.00u 6.00u 10.0u 14.0u 18.0u

Time in seconds

Figure 1.9  The output response to the input step.

By stepping the circuit output with a current source, we will be able to extract the static output imped-
ance. To do so, we remove Rload and connect a current source affected by a PWL statement:
ILoad vout 0 PWL 0 0.1 10u 0.1 11u 1end
∆Vout
Here, the output will be pulsed from 100 mA to 1 A in 1 μs. The output impedance will simply be .
∆Vin
Figure 1.10 displays the simulation results. For the 900-mA step, we can see a deviation of 1.79641 mV. The
dc output resistance is therefore 1.79641m / 900 m = 1.996 mΩ, again exactly what our calculations predicted.
Now, we reconnect the compensation network made of Rf and Cf. This network will make T(s), the total
loop gain, depend on the sweep frequency. By connecting an ac source of 1 A in place of our static load
resistor, we can sweep the ac output resistance/impedance, called Zout, of our converter.

• The current source is connected with its positive terminal to ground and negative terminal to the output.
12 chapter one

4.9912 Vout = 4.99132V

4.9908

vout in volts
Plot1
4.9904

DVout = 1.79641 mV
4.9900 DIin = 900 mA

Vout = 4.98952V
4.9896

2.00u 6.00u 10.0u 14.0u 18.0u

Time in seconds

Figure 1.10  The response to an output step.

Then, using the graphical interface, plotting Vout alone will reveal Zout since Iout = 1 A, as Fig. 1.11
portrays.
On these graphics, we can observe three areas:

1. The dc region, f < 1 Hz: The loop gain T(0) is extremely high, Cf can be considered as open. Therefore,
Zout is defined by Eq. (1.17) and is extremely small.
2. Above 1 Hz, Cf starts to play a role: The loop gain T(s) starts to diminish and the denominator of
Eq. (1.17) goes down. As a result, Zout increases. An impedance growing with frequency reproduces an
inductive behavior. If we take a point, let us select f = 100 Hz, we can calculate the equivalent induc-
63.24 m
tance Leq. From Fig. 1.11, the equivalent inductance Leq is equal to = 100.6 µ H at f = 100 Hz.
2π 100
3. Cf becomes a complete short, and the loop gain is fixed by Rupper and Rf. Now Zout is close to its open-
loop value, which is 0 dBΩ (1 Ω).

If for filtering reasons we connect a 100-μF capacitor on our regulator output, we create an LC filter that
1
is going to resonate. The resonating frequency is defined by , which is approximately 1.586 kHz.
2π LeqC

Zout = –0.822 dBΩ

10.0
Cf = shorted
vdbout in dB(volts)

–10.0
Zout
Plot1

–30.0 10 dBΩ/div

–50.0 Zeq = –23.98 dBΩ

Zeq = 63.24 mΩ
Zout = –54 dBΩ
–70.0 f = 100 Hz

10m 100m 1 10 100 1k 10k 100k

Frequency in hertz

Figure 1.11  The output impedance sweep with a compensation network.