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The document discusses various topics related to computer organization and architecture. It covers the different modes of operation in a computer, metrics for memory access performance, I/O transfer methods, synchronization techniques between processors and I/O devices, cache memory organization, hardware resource contention, call stack implementation, bus connections, and pipelining.
The document discusses various topics related to computer organization and architecture. It covers the different modes of operation in a computer, metrics for memory access performance, I/O transfer methods, synchronization techniques between processors and I/O devices, cache memory organization, hardware resource contention, call stack implementation, bus connections, and pipelining.
The document discusses various topics related to computer organization and architecture. It covers the different modes of operation in a computer, metrics for memory access performance, I/O transfer methods, synchronization techniques between processors and I/O devices, cache memory organization, hardware resource contention, call stack implementation, bus connections, and pipelining.
a) User and System mode b) User and Supervisor mode c) Supervisor and Trace mode d) Supervisor,User and Trace mode 2. The number successful accesses to memory stated as a fraction is called as _____. a) Hit rate b) Miss rate c) Success rate d) Access rate 3. The method which offers higher speeds of I/O transfers is a) Interrupts b) Memory mapping c) Program-controlled I/O d) DMA 4. The method of synchronising the processor with the I/O device in which the device sends a signal when it is ready is a) Exceptions b) Signal handling c) Interrupts d) DMA 5. While using the direct mapping technique, in a 16 bit system the higher order 5 bits is used for ________. a) Tag b) Block c) Word d) Id 6. The fastest data access is provided using _______. a) Caches b) DRAM’s c) SRAM’s d) Registers 7. The contention for the usage of a hardware device is called as ______. a) Structural hazard b) Stalk c) Deadlock d) None of the mentioned 8. The most Flexible way of logging the return addresses of the sub routines is by using _______ . a) Registers b) Stacks c) Memory locations d) FlipFlop 9. The controller is connected to the ____ a) Processor BUS b) System BUS c) External BUS d) memory 10. The fetch and execution cycles are interleaved with the help of ________. a) Modification in processor architecture b) Clock c) Special unit d) Control unit