Design and Simulation of a New Multi-Level Inverter with Reduced Number of Switches.

By
Yahia Hammadieh & Suhib Al-Ayd

Supervised by

Dr. Majd Ghazi Batarseh

Submitted in partial fulfillment of the requirements for the degree of

BACHELOR OF SCIENCE
in
ELECTRICAL ENGINEERING
at
PRINCESS SUMAYA UNIVERSITY FOR TECHNOLOGY
Amman, Jordan
2016/2017
 This is to certify that I have examined
this copy of an engineering documentation by

Yahia Hammadieh & Suhib Al-Ayd

And have found that it is complete and satisfactory in all respect,

And that any and all revisions required by the final Examining Committee have been made

Dr. Majd Ghazi Batarseh

Acknowledgments
Our sincere thanks and deep gratefulness are first and foremost to God, then to our great supervisor
Dr. Majd Batarseh, we appreciate her great efforts for supporting us until the last moment, we are
really thankful to all knowledge and experience that she put in this project in order to make the new
topology possible, and we are honored to be under her supervision.

We are also grateful to Eng.Saddam Ratrout for his time and experience, he was a great supporter in
technical issues, a very meek person and a knowledge lover.

Finally, we would like to thank our families for their encouragement, patience, help and prayers, which
have been a great moral boost for us to continue our work and give our best.
Abstract
A Multilevel Inverter (MLI) is a DC-AC converter which has recently become the main component
in many applications in order to maintain an AC staircase waveform. The stair-like signal is then easily
filtered to generate an AC signal with minimum Total Harmonic Distortion (THD), in which case, the
more the steps and output levels, the reduced the THD. However, this comes on the expense of the
component count where the less the distortion of the output is, the more components are required.
The main challenge in MLI is the large number of components, whether switches or DC sources
required for implementation, in addition to the associated control complexity.

Various topologies and structures implementing a MLI had been proposed in literature, with the main
focus of reduction in components count in terms of cost, size and efficiency or control optimization
in terms of better THD. The goal of such topologies is to maintain a low THD with minimum amount
of complexity.

The benefits sought after in reducing the number of switches are; savings in overall cost and size of
hardware, simplifying the design and reducing number of control signals, in addition to minimizing
losses and improving reliability and efficiency of the system.

The three most common types of MLI are: Cascaded Multilevel Inverter (CMLI), Diode Clamped
(DCMLI) and Flying Capacitors (FCMLI). This documentation introduces a new topology of
multilevel inverter which is referred to as Flipped Ladder Multilevel Inverter (FLMLI), the proposed
merits of which will be compared against the CMLI. The proposed topology focuses mainly on
reducing the number of switches compared to conventional CMLI where only 1 switch will be
required in FLMLI for any added source (2 levels at the output) versus 4 switches in CMLI.

This topology will be verified in simulation on 7 levels, 11 levels and 45 levels on the PSIM platform
(Power Simulation Software), in addition to implementing 11 levels on Proteus as real hardware
emulation software.
Table of Contents
[1.] Introduction ......................................................................................................................................... 1
1.1 Power Inverters ............................................................................................................................... 1
1.1.1 Square Wave Inverters................................................................................................................ 1
1.1.2 Modified Square Wave Inverters .............................................................................................. 4
1.1.3 Pulse width modulation (PWM) Inverters .............................................................................. 7
1.1.4 Multilevel Inverters ..................................................................................................................... 9
1.2 Design Achieved ........................................................................................................................... 11
1.3 Design Requirments and Constraints ......................................................................................... 11
1.4 Work Distribution ......................................................................................................................... 12
[2.] Background/or Literature Review .................................................................................................. 13
2.1 Multilevel Inverter Types:- ........................................................................................................... 13
2.1.1 Cascaded Multilevel Inverter (CMLI): ................................................................................... 14
2.1.2 Diode Clamped Multilevel Inverter (DCMLI): ................................................................ 15
2.1.3 Flying Capacitor Multilevel Inverter (FCMLI): ................................................................ 16
2.2 State of the Art CMLI .............................................................................................................. 19
[3.] Design ................................................................................................................................................. 23
3.1 LMLI Concept ............................................................................................................................... 23
3.2 Energy Balance and Flippled Ladder Concept ......................................................................... 25
3.3 Design Options ......................................................................................................................... 30
3.4 Developped Design ...................................................................................................................... 31
[4.] Results ................................................................................................................................................. 35
4.1 PSIM Simulation Setup..................................................................................................................... 35
4.2 Hardware Setup ................................................................................................................................. 38
4.3 Proteus Hardware Immulation Setup: ............................................................................................ 41
4.4 PSIM Simulation Results .................................................................................................................. 43
4.5 Proteus Hardwrae Immulation Results .......................................................................................... 45
4.6 Hardware/Simulation Results Discussion: .................................................................................... 46
4.7 Validation of requirements/constraints ......................................................................................... 47
[5.] Conclusion and Future Work .......................................................................................................... 48
5.1 Conclusion .................................................................................................................... 48
5.2 Future work .................................................................................................................. 48
List of Figures
Figure 1.1 Power Inverter Input and Output Waveforms ......................................................................... 1
Figure 1.2 Square Wave Inverter input and output .................................................................................... 2
Figure 1.3 a): H-Bridge inverter. (b): The square wave output. ................................................................ 2
Figure 1.4 (a) 48% THD in conventional two-level inverter (b) conventional two-level inverter output
............................................................................................................................................................................ 4
Figure 1.5 The effect of blanking time ......................................................................................................... 5
Figure 1.6 Modified Square Wave Inverter Output .................................................................................... 5
Figure 1.7 Third and fifth harmonics Elimination [1] ................................................................................ 7
Figure 1.8: Unipolar AC output ..................................................................................................................... 7
Figure 1.9: Bipolar AC output........................................................................................................................ 8
Figure 1.10: Multilevel Inverter input and output ....................................................................................... 9
Figure 1.11: (a) three-level waveform, (b) a five-level waveform and (c) seven-level multilevel
waveform........................................................................................................................................................... 9
Figure 1.12: THD 21% for 7 levels multi-level inverters ......................................................................... 10
Figure 1.13: Final topology ........................................................................................................................... 11
Figure 2.1: Multilevel Inverters Family tree [3].......................................................................................... 13
Figure 2.2: (a)7-levels Cascaded Multilevel Inverters (b) waveform [3] ................................................. 14
Figure 2.3: (a) 3 levels DCMLI. (b) 5 levels DCMLI. (c) 7 levels DCMLI. [3] ..................................... 16
Figure 2.4: (a) 3 levels FCMLI. (b) 5 levels FCMLI. (c) 7 levels FCMLI. [3]........................................ 17
Figure 3.1: a) 2 level out b) 3 level out c) n level out ................................................................................ 23
Figure 3.2: (a) 7 level CMLI versus (b) 7 Level LMLI ............................................................................. 24
Figure 3.3: VH possible states ...................................................................................................................... 25
Figure 3.4: a) the output from the top b) the output from the bottom ................................................ 26
Figure 3.5: one V output can be V top or V bottom................................................................................ 27
Figure 3.6: 7 levels FLMLI schematic ......................................................................................................... 28
Figure 3.7: 7 levels FLMLI output voltage ................................................................................................. 29
Figure 3.8: 7 levels FLMLI sources time operation .................................................................................. 29
Figure 3.9 (a) equal gating angles and (b) unequal gating angles............................................................. 31
Figure 3.10: 11 levels FLMLI Schematic .................................................................................................... 32
Figure 3.11: 11 levels FLMLI output voltage ............................................................................................ 33
Figure 3.12: 11 levels FLMLI Harmonics orders ...................................................................................... 33
Figure 4.1: PSIM Simulation Schematic for 11 levels FLMLI ................................................................ 36
Figure 4.2: PSIM Simulation Schematic for 45 levels FLMLI ................................................................ 37
Figure 4.3: Proteus Simulation Schematic for 11 levels FLMLI ............................................................. 41
Figure 4.4: Bidirectional Power MOSFET proteus .................................................................................. 42
Figure 4.5: Gate Drive with bootstrap circuit on Proteus ....................................................................... 42
Figure 4.6: Proteus Simulation Schematic for 11 levels FLMLI ............................................................. 43
Figure 4.7: PSIM 11 levels FLMLI output voltage on 100Ω & 0.1H load............................................ 43
Figure 4.8: PSIM 11 levels FLMLI output current on 100Ω & 0.1H load............................................ 44
Figure 4.9: PSIM 45 levels FLMLI output voltage on 100Ω & 0.1H load............................................ 44
Figure 4.10: PSIM 45 levels FLMLI output current on 100Ω & 0.1H load ......................................... 45
Figure 4.11: Proteus Hardware Emulation of 11 levels FLMLI output voltage................................... 45
List of Tables
Table 1-1: Comparison between 2-level and multi-level inverters ...........................................................10
Table 1-2: List of Constraints ........................................................................................................................12
Table 1-3: Work Distribution .........................................................................................................................12
Table 2-1: Multilevel inverter types comparison .........................................................................................17
Table 2-2: definition of topologies names....................................................................................................19
Table 2-3: comparison number of DC sources to number of levels........................................................20
Table 2-4: comparison number of DC sources to number of levels........................................................20
Table 2-5: comparison number of Conducting Switches During Operation..........................................21
Table 2-6: Equal Average Power ...................................................................................................................22
Table 3-1: VH values for switch position.....................................................................................................24
Table 3-2: VH values for Ladder and Flipped Ladder Topologies ..........................................................26
Table 3-3: 7 level Flipped Ladder MLI output ............................................................................................28
Table 3-4: number of switches needed in CMLI and FLMLI for 7, 11 and 45 levels ...........................30
Table 4-1: Components and IC's to use in 11 levels FLMLI ....................................................................39
Table 4-2: Components Description.............................................................................................................40
Table 4-3: Proteus Hardware Emulation Challenges..................................................................................46
Table 4-4 Validation of Resign Requirements and Constraints ................................................................47
1 Introduction
1.1 Power Inverters
Nowadays Renewable energy is the key of transition from limited energy to unlimited energy.
Currently, Solar Power and Photovoltaic (PV) systems are widely spreading across many countries, so
the need for power conditioning circuits is inevitable. However, the existing grid is AC and the output
of PVs is DC, thus DC-AC power inversion techniques are widely needed as a major component of
the system.

Power Inverter is an electrical device used to convert direct current (DC) into alternating current (AC).
Using few control circuits and switches, one can get a filtered AC at any required voltage and
frequency, figure1.1 shows the basic concept of any inverter where the output is an AC signal with
zero average produced from a DC input.

Figure 1.1 Power Inverter Input and Output Waveforms

Different control schemes produce different AC outputs as described below.

1.1.1 Square Wave Inverters

The simplest unfiltered inverter is the square wave inverter, which generate two output voltage levels,
VDC or -VDC as shown in figure 1.2, and its average voltage is zero.

1
 Figure 1.2 Square Wave Inverter input and output

The expected and most useful inverter output is an AC sine wave, however, the output in figure 1.2
is a square wave signal which can be considered as a highly distorted sinusoidal (not the desired pure
sine wave).
The undesired and abundant harmonic content of the square wave signal makes it unsuitable to power
AC loads or connect to the existing grid.
The conventional two-level square wave inverter of Figure 1.2 can be implemented using the H-bridge
of four switches as illustrated with its output in figure 1.3.

(b)
(a)
Figure 1.3 a): H-Bridge inverter. (b): The square wave output.

When switches S1 and S4 in figure 1.3(a) are ON, the output voltage will be +VDC, and when S2 and
S3 are ON while the other 2 switches are OFF, the output voltage will be –VDC as in figure 1.3(b). S1
and S3 or S2 and S4 cannot be ON at the same time to avoid the shoot through fault.

2
This control scheme can create two different output voltages across the load, +VDC or -VDC. A useful
approach for inverter analysis is to express the output voltage and load current in terms of a Fourier
series, from equation (1.1) to (1.4)[1].
∞

Vo (t) = ∑ Vn sin(nwo t + θn ) … …. (1.1)

n=1
∞

Io (t) = ∑ In sin(nwo t + ∅n ) … … . (1.2)

n=1

Such that,
4VDC
Vn = … … . (1.3)
nπ
and
Vn
In = … … . (1.4)
Zn
Where:
Zn ≜ load impedance at harmonic 𝑛. .

The harmonic content in the output voltage is quantified by the total harmonic distortion (THD), and
is used to describe the quality of the ac output voltage or current as in equations (1.5) where the RMS
value of the fundamental output voltage component is given in (1.6)[1].

2 2 − V2
√∑∞
n=2(Vn,rms )
√Vrms 1,rms
THD = = … … . (1.5)
V1,rms V1,rms
4VDC
V1,rms = … … . (1.6)
√2 × π

According to (1.5), the distortion in the square wave output voltage due to harmonics is 48%, which
greatly exceeds the allowed unfiltered limit of 15% - 25% THD or a filtered output with THD of no
more than 5% as set by IEEE Std519.
The harmonic content of any signal can also be plotted as a Fourier series. Fig 1.4 (a) shows a 100V
square wave signal at 50Hz frequency and its THD in Fig. 1.4 (b).

3
 (a)

(b)
Figure 1.4 (a) 48% THD in conventional two-level inverter (b) conventional two-level inverter output

Figure 1.4 shows the orders of harmonics existing in the conventional two-level square wave inverter
output voltage and also gives a percentage for all these harmonics as a THD.
Since the desired inverter output is a pure sine, then the control scheme of the H-bridge producing a
two-level square wave inverter is not suitable and better control approaches should be considered for
decreased THD. A control scheme introducing blanking time produces a modified square wave
inverter output with lower THD.

1.1.2 Modified Square Wave Inverters

A control pattern with imbedded delays, or blanking times designated as α, produces three level square
wave output with better signal quality, is shown in Fig. 1.5.

4
 Figure 1.5 The effect of blanking time

The effect of adding blanking time produces an output voltage with three values: zero, +VDC, and -
VDC as depicted in Fig. 1.6

Figure 1.6 Modified Square Wave Inverter Output

The output voltage can be controlled by adjusting the blanking interval α on each side of the pulse
which can be achieved, using the H-Bridge inverter, by turning S1 & S2 or S3 & S4 ON at the same
time to short the output voltage and thus, changing the RMS value of the voltage waveform as given
in equation (1.7)[1]

1 π−α 2 2α
Vrms = √ ∫ VDC d(wt) = VDC √1 − … … . (1.7)
π α π

5
Whereas, the Fourier series of the waveform is expressed in equations (1.8) and (1.9)[1]respectively,
and α is the angle of zero voltage on each end of the pulse.

Vo (t) = ∑ Vn sin(nwo t) … … . (1.8)

n odd

wo : Angular frequency
Where:
2 π−α 4VDC
Vn = ∫ VDC sin(nwo t) d(wo t) = cos(nα) … … . (1.9) ,
π α nπ

The amplitude of the fundamental frequency (V1) can be controllable by adjusting α as in equation
(1.10)[1]:

4VDC
V1 = ( ) cos α … … . (1.10)
π

In fact, the amplitude of any frequency component of the output is also a function of α, therefore, the
harmonic content can also be controlled by adjusting α, this is significant because the third harmonic
can be eliminated from the output voltage and current by setting α=30° which guarantees the
elimination of the third harmonic (V3=0). However, the harmonic elimination feature cancels the
fundamental amplitude control.
Multiple harmonic elimination can be satisfied by a control algorithm that chops the square pulse
more frequently in such a way that more than one harmonic can be nulled. Fig. 1.7 shows the
introduction of various delays at calculated angles in order to eliminate the third and fifth harmonics
at the same time.

6
 Figure 0.7 Third and fifth harmonics Elimination [1]

1.1.3 Pulse width modulation (PWM) Inverters

PWM is a technique used to control the power delivered to electronic device by turning power on and
off to generate a square wave signal similar to that shown in figure 1.7, however maintaining amplitude
control and harmonic elimination as two distinct and independent features.
A PWM inverter requires two control signals; a reference signal, which is a sinusoidal at the desired
frequency of the output and a carrier signal, which is a saw tooth at a much higher frequency.
The ratio of the amplitude of the reference signal to the amplitude of the carrier signal is known as
amplitude modulation and this factor controls the amplitude of the fundamental component in the
output voltage. Whereas, the ratio of the frequency of the carrier signal to the frequency of the
reference signal is known as the frequency modulation. The higher the frequency modulation, the
further the harmonics are pushed away from the fundamental, which eases the filter deign to achieve
a reduced THD. However, the higher the frequency modulation, the faster the carrier signal becomes
which increase the switching losses and decreases the efficiency.
PWM control can result in an AC output that is either unipolar or bipolar as shown in Fig 1.8 and 1.9
respectively.

Figure 1.8: Unipolar AC output

7
 Figure 1.9: Bipolar AC output

8
 1.1.4 Multilevel Inverters
This class of inverters, referred to as Multi-Level Inverters (MLI) produces an output voltage with
more than three levels compared to the modified square wave inverter as shown in Fig 1.10.

Figure 1.10: Multilevel Inverter input and output

The concept behind MLI is that several voltage levels are added to each other to create a smoother
𝑑𝑣
stepped waveform as shown in Figure 1.9, with lower and lower harmonic distortions shown in
𝑑𝑡
figure 1.11.

Figure 1.11: (a) three-level waveform, (b) a five-level waveform and (c) seven-level multilevel waveform

The more levels in the output voltage, the closer it becomes to the sine wave and thus the less the
THD. A 7 level output voltage will contain a much reduced distortion compared to the square wave
inverter with only 21% THD as shown in Fig. 1.12

9
 Figure 1.12: THD 21% for 7 levels multi-level inverters

Table 1.1 below summarized the difference between two-level inverter and multi-level inverters;

Table 0-1: Comparison between 2-level and multi-level inverters

Conventional Inverter Multilevel Inverter

Higher THD in output voltage. Low THD in output voltage.
Not applicable for high voltage applications. Applicable for high voltage Applications.
Multiple voltage levels are not produced. Multiple voltage levels are produced.
𝑑𝑣 𝑑𝑣
High and thus high EMI. low and thus low EMI
𝑑𝑡 𝑑𝑡
Higher switching stresses on devices. Reduced switching stresses on Devices.
Control schemes are simple. Control scheme becomes complex as number of
levels increases.
Lower cost relatively. Higher cost relatively

A multilevel inverter has several advantages over the other types of inverters. The attractive features
of multilevel inverter can be briefly summarized as following [2]:
1. Staircase waveform quality: Multilevel inverters not only can generate the output voltages
𝑑𝑣
with very low distortion, but also can reduce the stresses. Therefore, electromagnetic
𝑑𝑡
compatibility (EMC) problems can be reduced.
2. Filtration: reduce the harmonic filtration order than PWM.
3. Switching frequency: Multilevel inverters can operate at both fundamental switching
frequency and high switching frequency PWM. It should be noted that lower switching
frequency usually means:
• lower switching loss
• higher efficiency

10
Multilevel inverters suffer from a main drawback, which is the large number of power semiconductor
switches needed. Each switch requires a gate drive circuit, which may cause the overall system to be
more complex and expensive.

1.2 Design Achieved

This project focuses on multilevel inverters, due to its advantages mentioned above; it includes several
topologies as will be detailed in chapter 2, among which is the cascaded multilevel inverters, which
will be of the focus of this work.
The aim of this project is to come up with a new multilevel topology that requires reduced number of
switches compared to the Cascaded MLI.
Fig. 1.13 illustrates the design to be achieved.

Figure 1.13: Final topology

1.3 Design Requirements and Constraints

The design requirements for this project are the following:

11
 1- Design should comply with the IEEE519 Standard, in achieving 25% of THD on the filtered
voltage.
2- Output voltage of 120Vrms should be achieved in simulation.
There are some constraints to be considered in the design process as listed in table 1-2

Table 0-2: List of Constraints

Nature Constraint
Economical 1. Proposed topology should demonstrate a minimum 30% reduction
in cost compared to the Cascaded MLI.
2. To balance load over all switches to minimize switches rating for
lower switches cost

Safety 1. If this topology tested controller should be isolated from the main
circuit.

1.4 Work Distribution

This project is a cooperative work of two students, Suhib Al-Ayd and Yahya Hammadieh, The tasks
were achieved by working on different stages in the same time as shown in Table 1.3.

Table 0-3: Work Distribution

Team Members Suhib Al-Ayd Yahya Hammadieh

Topology idea
PSIM design simulation
Proteus hardware simulation
Task reading and research of papers
Hardware implementation of 11 level
multilevel inverter
Writing the documentation
Preparing the graduation project seminar presentation

This documentation is organized as follows: Chapter 2 presents the literature reviewed, presenting the
three basic MLI topologies of Cascaded, Diode Clamped and Flying Capacitors and it also covers
some of the multilevel inverter. Chapter 3 thoroughly introduces the new proposed MLI topology, its
concept and verification. It also highlights the advantages this new proposed topology offers
compared the CMLI. Chapter 4 displays results of simulation verification. Lastly, Chapter 5 discusses
the conclusions and suggests recommendations for future work.

12
2 Background and Literature Review
2.1 Multilevel Inverter Types:-

MLI became very popular and more desirable than its counterpart inverters and thus became the focus
of researchers. Many kinds of MLI were presented in literature over the last 3 decades, of which, the
three most common types were the Cascaded MLI, the Flying Capacitor MLI and the Diode Clamped
MLI. Fig. 2.1 illustrates various MLI types, and indicates that the Cascaded MLI is based on the H-
bridge topology, which is the basic unit in the cascaded family of inverters.

Figure 2.14: Multilevel Inverters Family tree [3].

It is worth mentioning that the Cascaded MLI is the most commonly used topology of all due to its
higher efficiency, higher power quality and less electromagnetic interference [6]. It uses less number
of components and thus cheaper and lighter in weight.

13
2.1.1 Cascaded Multilevel Inverter (CMLI):
CMLI cascades the H-bridge cells introduced in the conventional inverter. Each cell contains four
switches and increases the number of levels by two. Three H –bridge cells are connected in series to
produce 7 level output voltage as shown in figure 2.2.

(b)
(a)
Figure 2.2: (a)7-levels Cascaded Multilevel Inverters (b) waveform [3]

The more H-bridges cells cascaded, the higher the number of switches needed nevertheless, the higher
the number of levels of the output and the lower the THD. The number of switches can be determined
from equation 2.1
S = 2(L − 1) … … (2.1)
Where L: is number of levels
For example, for 7 levels output voltage, 12 switches are needed in 3 cascaded H-Bridge cells.
To produce the staircase output waveform, each cell will operate at a different delay angle α introduced
earlier in Chapter 1.

14
There are plenty of proposed topologies for CMLI in literature; some topologies suggest a way to
reduce the number of power switches with a significant increment in the number of output voltage
levels in order to reduce not only the THD but also inverter price and simplify the control. This can
be achieved by either adding extra capacitors and bidirectional switches to reduce stress on switches
[4], or by adding extra coupled-inductor to one cell then making some switches operate at higher
frequency while others at lower frequency [5]. Furthermore, some new topologies changed the overall
basic structure of CMLI but keeping some of its features such as the series connection between cells
in order to maintain the staircase nature of the waveform given the different delays of each cell. [7].
Asymmetric DC sources, which introduce hardware challenges yet can be used to reduce number of
switches to almost half with good reduction in THD [8]. In addition, number of DC sources can be
reduced by replacing them with capacitors using a proper control method [6].
There are four important values in the cascaded multilevel inverter that can determine the quality of
the inverter:
1- Number of sources compared to number of levels:
The main drawback of the cascaded multilevel inverter is the need for a DC source for each
output level, this is why it is important to develop new topologies to minimize number of
sources needed for high output levels.

2- Number of switches:
Reducing the number of switches will simplify the system, because for each added switch, a
single driver is needed with its accompanying resistors and capacitors, in addition to more
control complexity.

3- Number of conducting switches during Operation:

If each switch has 0.5V voltage drop that means the efficiency will be reduced.

4- Balanced sources in terms of average power supplied:

As seen from Fig. 2.2, each H-Bridge cell operates at different α, that means each source will
provide a different average power over one cycle. If the sources are equal, then the power
supplied by each source will not be equal and thus, if those sources are batteries, then they will
discharge at different points in time. For example, in Fig. 2.2 the source V DC3 will discharge
faster than VDC1. Therefore, it is important to maintain balanced sources in terms of the
average power they supply.

2.1.2 Diode Clamped Multilevel Inverter (DCMLI):

Another type of MLI is the Diode Clamped, they are called clamped because each source point is
clamped by two diodes and one capacitor. It has a different structure than cascaded but it uses the
same number of power switches for the same number of levels exactly as equation (1.4).

15
DCMLI uses a single DC source but this source is of higher voltage with higher levels as illustrated in
figure 2.3.

Figure 2.3: (a) 3 levels DCMLI. (b) 5 levels DCMLI. (c) 7 levels DCMLI. [3]

The reason behind increment is that source voltage will be distributed over capacitors, the output
voltage Van is measured between point (a) and neutral point (n), while Va0 is DC voltage equal to
source voltage.

2.1.3 Flying Capacitor Multilevel Inverter (FCML I):

The idea behind Flying Capacitor MLI is very close to Diode Clamped, where the difference is instead
of clamping two diodes, it clamps one capacitor between each two switches, figure 2.4 shows 3, 5 and
7 levels of FCMLI.

16
 Figure 2.4: (a) 3 levels FCMLI. (b) 5 levels FCMLI. (c) 7 levels FCMLI. [3]

Clamped capacitors are charged and discharged based on switches condition, negative sign on
capacitors represents for charging and positive sign represents for discharging.
Each of the above MLI topologies offers some merits which would make one type favorable in some
applications over the other two. Table 2.1 lists the advantages and disadvantages of each type.

Table 0-4: Multilevel inverter types comparison

TYPES ADVANTAGES DISADVANTAGES

CASCADED 1. Number of output levels is 1. Each H-Bridge needs a
17
 MULTILEVEL twice the number of separate DC source,
INVERTER sources or even more. which limits cascaded
2. The series H-Bridge makes applications.
manufacturing quick and
cheap
DIODE CLAMPED 1. High efficiency at 1. The intermediate DC
MULTILEVEL fundamental frequency levels could be
INVERTER 2. Capacitors can be pre- overcharged or
charged together discharged without any
3. Common DC bus shared control which makes
among multiple phases power flow more difficult
which minimizes the for single inverter
capacitance requirement of 2. Number of clamped
inverter diodes is four times the
number of levels
FLYING 3. Phase redundancies 1. Hard to control and
CAPACITOR property for capacitors monitor all voltage levels
MULTILEVEL voltage levels balancing on capacitors
INVERTER 4. Real and reactive power can 2. Low efficiency for real
be controlled power transmission
5. Inverter can ride through 3. More challenging to
short duration outages due implement FCMLI in
to high number of high levels
capacitors 4. The large number of
capacitors makes it more
expensive

18
2.2 State of the Art CMLI
Due to the advantages of the cascaded MLI, many efforts were dedicated into developing new
topologies of CMLI with enhanced performance and minimized number of switches. A number of
CMLI topologies were investigated and presented in this work. Table 2.2 lists six of the state of the
art CMLI.

Table 0-5: definition of topologies names

Topology Topology NAME

Reference

[9] A Modified Cascaded Multilevel Inverter With Reduced Switch Count

Employing Bypass Diodes.
[10] Symmetric and Asymmetric Design and Implementation of New Cascaded
Multilevel Inverter Topology.
[11] A New Cascaded Multilevel Inverter Topology with Minimum Number of
Conducting Switches.
[12] New Multilevel Converter Topology with Minimum Number of Gate Driver
Circuits
[13] Simulation of a 41-level Inverter Built By Cascading Two Symmetric Cascaded
Multilevel Inverter.
[3] Conventional cascaded multilevel Inverter

Each of the above topologies was evaluated based on the four factors listed above, namely:
1- Number of sources compared to number of levels:
2- Number of switches:
3- Number of conducting switches during Operation:
4- Balanced sources in terms of average power supplied:

Table 2.3 compares the six CMLI in terms of the number of sources needed against various number
of output levels (7, 11, 21, 31 and 41 levels).

19
 Table 0-6: comparison number of DC sources to number of levels

Number of DC sources compared to number of levels

Topology [9] [10] [11] [12] [13] [3]

Output voltage
Levels
7-level 3 3 3 3 - 3

11-level 5 5 5 5 - 5

21-level 10 10 10 10 - 10

31-level 15 15 15 15 - 15

41-level 20 20 20 20 8 20

Table 2.3 shows that all six of the studied MLI require large number of DC sources for high output
levels. Authors in [13] succeeded in dramatically minimizing the number of DC sources for 41 level
output voltage.
Table 2.4 compares the six CMLI in terms of the number of switches needed for the same various
number of output levels (7, 11, 21, 31 and 41 levels).
Table 0-7: comparison number of DC sources to number of levels

Number of Switches

Topology [9] [10] [11] [12] [13] [3]

Output voltage
levels
7-level 6 9 8 10 - 12

11-level 8 15 10 14 - 20

21-level 13 30 15 24 - 40

31-level 18 45 20 34 - 60

41-level 23 60 25 44 14 80

20
Again, it is clear that the number of switches increase with the number of levels required at the output.
For 41 level output, cascading two CMLI managed to reduce the number of switches to more than
80% of those needed in the conventional CMLI.
As for the third criterion, the MLI listed above were compared for the number of conducting switches
as detailed in Table 2.5

Table 0-8: comparison number of Conducting Switches During Operation

Number of Conducting Switches During Operation

Topology Reference [9] [10] [11] [12] [13 [3]

Output voltage
levels
7-level 2 to 4 4 3 2 to 5 - 6

11-level 2 to 6 8 3 2 to 7 - 10

21-level 2 to 11 10 3 2 to 12 - 20

31-level 2 to 16 16 3 2 to 17 - 30

41-level 2 to 21 20 3 2 to 22 4 40

The last factor of equalizing average power, Table 2.6 indicates whether the topology implements
energy or power balance among sources

21
 Table 0-9: Equal Average Power

Topology NAME Energy consumption balance?

A Modified Cascaded Multilevel Inverter With No
Reduced Switch Count Employing Bypass
Diodes.
Symmetric and Asymmetric Design and Yes
Implementation of New Cascaded Multilevel
Inverter Topology.
A New Cascaded Multilevel Inverter Topology No
with Minimum Number of Conducting
Switches.
New Multilevel Converter Topology with Yes
Minimum Number of Gate Driver Circuits
Simulation of a 41-level Inverter Built By No
Cascading Two Symmetric Cascaded Multilevel
Inverter.
Conventional cascaded multilevel Inverter Yes

Chapter 3 will introduce the new proposed topology to generate a multi- level output with reduced
number of switches.

22
3 Design
This work presents a new MLI structure. The proposed topology will start with a scheme that will be
referred to as Ladder Multi Level Inverter or LMLI and will be enhanced to the Flipped Ladder Multi
Level Inverter or FLMLI.
This chapter aims at intruding the concept behind this new MLI topology and verifying its
functionality and merits in the following sections:

3.1 LMLI Concept

A two-pole switch can set the voltage at its terminals to either a high or a low value, Va in Fig. 3.1 (a)
is either Vc or 0. Similarly, Va in Fig. 3.1 (b) can be, depending on the switch position, one of the
following values {2Vc, Vc, 0}. As the number of switch positions increases, the voltage levels will also
increase. This is the main concept behind the CMLI in general and the proposed LMLI and FLMLI
in specific.

Figure 3.1: a) 2 level out b) 3 level out c) n level out

To better illustrate the concept behind this proposed LMLI, the 7 level conventional CMLI presented
in Chapter 2 will be compared against the proposed LMLI.
Fig. 3.2 (a) shows the 7 level 12 switch CMLI versus (b) the 7 level 7 switch LMLI. Both circuits will
produce the same output however the LMLI will utilize reduced number of switches which is an
advantage sought in all MLI topologies.

23
 (b)
(a)
Figure 3.2: (a) 7 level CMLI versus (b) 7 Level LMLI

The proposed LMLI consists of the conventional H-bridge fed from a cascaded leg of three equal
voltage sources, each is Vdc in value. The input voltage to the H-bridge denoted as VH will follow
the pattern shown in Table 3-1.

Table 0-10: VH values for switch position

Switch S1 S2 S3 VH VH in value
ON OFF OFF V1 Vdc
OFF ON OFF V1+V2 2Vdc
OFF OFF ON V1+V2+V3 3Vdc
State

OFF OFF OFF 0 0

The resultant VH is as shown in Fig 3.3, where the four different values of VH (0, Vdc, 2Vdc and
3Vdc) are now fed to the H- Bridge. The function of the H-bridge is to generate an AC signal of VH
for half the cycle, when SH1 and SH2 are ON and –VH for the other half when SH3 and SH4 are
ON.
It’s worth noting here that every source in the cascaded leg requires one switch. i.e, for 7 level output,
3 sources and 3 switches will be added in the cascaded leg.

24
 Figure 3.3: VH possible states

Even though, the LMLI reduced the number of switches compared to the CMLI this topology still
suffers from 2 main drawbacks:
1- The power imbalance drawn from the sources. It is clear that V1 is supplying power for all
three voltage levels of {Vdc, 2Vdc and Vdc} which means that V1 is powering the circuit
almost all the time (close to 90%), while V2 supplies power for the 2 levels of {2Vdc and
3Vdc} and V3 supplies power for only one level of 3 Vdc which is for a fraction of the time
compared to V1 (around 25%). If these DC sources are batteries, then V1 will be discharged
faster than V3. This drawback of unequal average power drawn from the sources should be
addressed.
2- In addition, the cascaded leg operates as a ladder where the output voltage levels are built up
on top of each other, i.e, S1 should be ON for V1 (which is the first level of Vdc) but for the
second level of 2Vdc, S2 should be ON and V2 is added to V1 which restricts the control over
V2 alone, i.e, he output cannot be powered by V2 alone.
These two shortcomings will be addressed in the enhanced proposed topology of Flipped Ladder
MLI.

3.2 Energy Balance and Flipped Ladder Concept

In order to guarantee energy balance for all sources, the Flipping of ladder steps should be maintained.
Fig 3.4 illustrates the concept behind the flipping technique.

25
 (a) (b)

Figure 3.4: a) the output from the top b) the output from the bottom

Fig 3.4 (a) shows the cascaded leg with switching technique that utilizes V1 almost full cycle and V3
for a short fraction of the cycle, hence V1 will be discharged faster than V3, whereas Fig 3.4 (b) flipped
the source operation duration such that V3 operating almost all the cycle and V1 is for the small
fraction of the cycle, in this case discharging V3 faster than V1. Table 3.2 shows that the output of
both circuits VHa and VHb produce the same output in voltage values but with different source
utilization and sequence.

Table 0-11: VH values for Ladder and Flipped Ladder Topologies

Switch S1 S2 S3 VHa VHb VHa or VHb

values
ON OFF OFF V1 V3+V2+V1 Vdc
OFF ON OFF V1+V2 V3+V2 2Vdc
OFF OFF ON V1+V2+V3 V3 3Vdc
State

OFF OFF OFF 0 0 0

In order to combine both functionalities in one circuit, a new switching matrix is introduced as shown
in Fig 3.5.
The circuit in Fig 3.5 incorporates 5 switches in order to implement the flipping of operating sources
to guarantee equal average power.

26
 Figure 3.5: one V output can be V top or V bottom

This structure cascades the DC sources on top of each other in a ladder-like manner where each
sources is inserted between 2 switches. The ladder starts with Stop switch at the top pf the ladder and
terminates with Sbot switch at the bottom. These 2 switches (Stop and Sbot) are fixed and the number
of Dc sources with accompanying switches inserted in between determines, to an extent, the number
of voltage levels at the output.
For example, in Fig 3.5, the 7 level inverter requires three sources V1, V2 and V3 with accompanying
switches of S1 and S2 inserted between the top and bottom switches, Stop and Sbot respectively. All
switches are coupled together in one common point as shown in Fig 3.5.
This ladder can be climbed up or down in both directions via either the upper switch Stop+ or the
lower switch Sbot+ which are complementary meaning one of these switches are ON at any point of
time. The proposed structure produces 2 voltages, denoted by VH+ which comprises the output
voltage in the positive half cycle and VH– which is the output voltage in the negative half cycle as
shown in Fig 3.6.

27
 Figure 3.6: 7 levels FLMLI schematic

The output of which are as listed by the switching sequence in Table 3.3.

Table 0-12: 7 level Flipped Ladder MLI output

Switch Stop+ Sbot S1 S2 Sbot Stop VH+ VH– Vo in values

+
ON OFF ON OFF OFF OFF V1 OFF Vdc
ON OFF OFF ON OFF OFF V1+V2 OFF 2Vdc
ON OFF OFF OFF ON OFF V1+V2+V3 OFF 3Vdc
ON OFF OFF OFF OFF ON 0 OFF 0
State

OFF ON OFF ON OFF OFF OFF –V3 –Vdc

OFF ON ON OFF OFF OFF OFF –V2–V3 –2Vdc
OFF ON OFF OFF OFF ON OFF –V1–V2–V3 –3Vdc
OFF ON OFF OFF ON OFF OFF 0 0

28
The output of the 7 level FLMLI is shown in Fig. 3.7

Figure 3.7: 7 levels FLMLI output voltage

This proposed MLI topology guarantees the swapping of DC sources in order to maintain energy
balance and equalize the average power drawn from the sources. Fig. 3.8 better illustrates the
operational time of each source.

Figure 3.8: 7 levels FLMLI sources time operation

Fig 3.8 clearly shows that one switching cycle contains 16 switching transitions and each source
operates for a total of 8 slots per cycle which makes 180⁰ conduction interval per source.

29
This proposed FLMLI generates the same levels in the output voltage of the conventional Cascaded
MLI (CMLI) with a dramatic reduction in the number of switches. For example the 7 level output
requires only 6 switches in the FLMLI whereas the same output of 7 levels would requires 12 switches
which is double the number of switches needed by the FLMLI.
To highlight the merits of this new proposed Flipped Ladder MLI, the number of switches for the
FLMLI will be compared against those needed for the Cascaded Multilevel inverter CMLI as shown
in Table 3.4.

Table 0-13: number of switches needed in CMLI and FLMLI for 7, 11 and 45 levels

Voltage
levels 7 levels 11 levels 45 levels
Topology
CMLI 12 20 66
FLMLI 6 8 25

Table 3.4 clearly shows the huge reduction in the number of switches between CMLI and FLMLI
topologies. The higher the number of levels means better output with reduced THD however for the
45 levels, 66 switches are needed in CMLI versus only 25 switches in FLMLI. A total reduction of 41
switches which is more than 62% savings in the number of switches.
Needless to say that the fewer the switches, not only the smaller the size, but also the cheaper the
topology is and the simpler the control.

3.3 Design Options

There are two schools when it comes to designing gating signals for the switches in any MLI. One
approach is to generate an stair-like signal with equal step width for all levels as shown in Fig 3.9 (a)
while another design option, shown in Fig.3.9 (b), is to generate stair-like output closer to the sine in
terms of unequal step widths where it is narrower at the edges and wider in the middle as the sinusoidal
amplitudes are.

30
 Figure 3.9 (a) equal gating angles and (b) unequal gating angles

The THD of the signal shown in Fig 3.9 b is less than that of Fig. 3.9 (a) and thus the second design
option was adopted in this project.

3.4 Developed Design

Figure 3.10 illustrates the developed design of 11 levels FLMLI schematic, while Figure 3.11 shows
the output voltage for this proposed design.

31
 Figure 3.10: 11 levels FLMLI Schematic

32
 Figure 3.11: 11 levels FLMLI output voltage

THD of the 11 levels output voltage is only 10%

Figure 3.12 shows the number and order of harmonics for 11-level FLMLI, only 3rd harmonics
appeared with decreasing in voltage amplitude and increment in frequency.

Figure 3.12: 11 levels FLMLI Harmonics orders

33
 3.5 Did the Design Meet Requirements and Constraints?

The design presented in Fig 3.10 and 3.11 generates an output voltage with 170V peak (120Vrms)
with 10% THD unfiltered meeting the design requirements set the beginning of this work.
Also, the proposed design of 11 levels FLMLI used only 8 switches compared to 20 needed switches
in the CMLI. That is a total saving of 60% in number of switches which will reflected on cost.
Therefore, this design met the requirements and constraints.
This chapter verified the working principle of the new proposed FLMLI and highlights the advantage
it offers compared to Cascaded MLI in the reduction of needed switches. Chapter 4 tests the topology
in simulation and presents the results.

34
4 Results

The proposed topology referred to as Flipped ladder multilevel inverter (FLMLI) was first simulated
on PSIM, then a hardware emulation software was used to test the topology. Proteus, is one of the
limited programs where Arduino microcontroller is available for simulation, it also guarantees a
practical safe work before real implementation, keeping in mind cost and safety measures as most
components are not cheap and dealing with high voltage levels carry risk in damaging components
and devices and on humans.
An 11 levels FLMLI and 45 levels were simulated on PSIM. Component selection was carried out for
11 levels FLMLI and some preliminary results were attained on Proteus.
This chapter presents all simulation results in PSIM and hardware emulation on Proteus carried out
for the FLMLI topology. In addition to some component suggestions for prototype implementation.

4.1 PSIM Simulation Setup

PSIM as an ideal case simulator was used to verify functionality and operation of the topology. It can
be useful as a starting point, where all non-idealities can be ignored and other losses or any controlling
problem.
The 11 levels and the 45 levels FLMLI were simulated and their schematics are shown in Fig 4.1 and
Fig 4.2 respectively.

35
 Figure 4.1: PSIM Simulation Schematic for 11 levels FLMLI

36
 Figure 4.2: PSIM Simulation Schematic for 45 levels FLMLI

37
 4.2 Hardware Setup

This section investigates in details with proper justification of the components needed for hardware
implantation of the 11 and 45 levels FLMLI.
Following the set constraints of low voltage hardware testing, a scaled down version was chosen for
component selection. A 25V peak output voltage was chosen and designed for when it came to
component selection on a 100Ω & 0.1H load.
Table 4.1 lists all components required for hardware implementation.

38
 Table 0-14: Components and IC's to use in 11 levels FLMLI

Component Model #NUM Image Reason of picking

POWER IRF530N 8 1- Fast switching speed
MOSFET 2- Low on resistance

Gate driver IR2104 8 1- 2 Outputs: high and

low
2- 10V gate drive supply
voltage
Optocoupler LC817 8 1- Arduino output
amplifier
2- Splitting Arduino
ground from circuit

Arduino Mega 2560 1 1- Easy programming

R3 using USB
2- Many digital input
pins
Diode 1n5408 16 Low forwards voltage drop

Diode MR851 8 Fast recovery diode

Capacitor 0.1uF 6 Gate drive bootstrap

capacitor

Capacitor 1uF 2 Gate drive bootstrap

capacitor

Resistor 1k + 10 + 22
470

Source DC 7

39
 Each component is discussed in details as listed in Table 4.2

Table 0-15: Components Description

Component Description
MOSEFT Switches are the main part in any power inverter, thus it is important to select
IRF530N the optimal switch model.
IRF530N is a fast switching transistor with a very low on resistance (RDS
= 0.09 ohm), drain-source voltage up to (VDS = 100V) with drain current
up to (ID = 17A).
where maximum output voltage in the prototype is 50V and 0.5A for current,
this MOSFET is more than enough.
Gate driver The main advantage of gate drive is bootstrapping to insure Vgs on each
IR2104 MOSFET is always within the driver output levels.
Max control signal frequency in our topology is 50Hz and this driver can
operate at more than 100KHz frequency.
This switches has a gate drive supply range of 10-20V which is the amount
of voltage required to turn IRF530N on.
This driver requires an input voltage of 3.3V, 5V or 15V for initial startup.
Optocoupler Most Drivers contain an optocoupler inside them, and the reason behind
using optocoupler is to split Arduino ground from main circuit ground.
The second reason is to amplify Arduino 5V control signal (using common
emitter amplifier) which is not enough to drive the input voltage of gate
driver.
Arduino Arduino used to control switches by generating PWM signal.
Programing Arduino was done by a simple C language code
Digital ports are programmed to turn on and off for a small period of time
Max output voltage on Arduino is 5V so all PWM peak voltage is 5V.
Diode Diodes are used with bidirectional switches and drivers.
Diodes in bidirectional switches cause voltage drops on output, where only
two diodes are ON simultaneously limiting the losses to the worst case of 2V
drop.
1n5408: 1V forward voltage drop.
Can run at 1MHz.
Used with bidirectional switches.
MR851: 1.25V forward voltage drop.
Used with drivers.

40
 4.3 Proteus Hardware Emulation Setup:

Components listed above were used for 11 level FLMLI hardware emulation on Proteus software as
shown in Fig 4.3.

Figure 4.15: Proteus Simulation Schematic for 11 levels FLMLI

A deeper look into the Proteus Schematic is further detailed in Figures 4.4 – 4.6.
Figure 4.4 shows the bidirectional switch used in ladder steps, where each switch is connected to 4
diodes to allow for bidirectional flow of current, as the power MOSFET can only conduct current in
one direction.

41
 Figure 4.4: Bidirectional Power MOSFET proteus

Figure 4.5 shows the Power MOSFET gate driver including the bootstrap circuit

Figure 4.5: Gate Drive with bootstrap circuit on Proteus

Figure 4.6 shows the optocoupler as common emitters that has been used to amplify input voltage
and provides Arduino ground isolation.

42
 Figure 4.6: Proteus Simulation Schematic for 11 levels FLMLI

4.4 PSIM Simulation Results

PSIM results will be presented in this section, it mainly focuses on the staircase output waveform and
the THD.
Figure 4.7 shows the output voltage of the 11-levels FLMLI.

Figure 4.7: PSIM 11 levels FLMLI output voltage on 100Ω & 0.1H load

As clear from Fig 4.7, in order to meet the constraint of maximum 170V peak output, five 34V sources
in series have been used so that the peak output voltage is 170V. Fig 4.7 shows the staircase steps in
the output voltage of 34V each.

Fig 4.8 displays the output current for the 11 levels FLMLI.

43
 Figure 4.8: PSIM 11 levels FLMLI output current on 100Ω & 0.1H load

The output current peak is about 0.24A. Both the output voltage and current are shown pre-
filtering.
The THD on voltage waveform achieved is about 10% before filtering which is within the accepted
the limit set by the THD IEEE Std. 519-1992.
In order to further reduce the THD and to highlight the advantage this FLMLI topology presents, a
45 levels FLMLI was simulated and the output voltage is shown in Figure 4.9. its obvious that the
THD of 45 level output voltage is dramatically reduced.

Figure 4.9: PSIM 45 levels FLMLI output voltage on 100Ω & 0.1H load

44
45 levels FLMLI output current on 100Ω-0.1H load is shown in figure 4.10

Figure 4.10: PSIM 45 levels FLMLI output current on 100Ω & 0.1H load

4.5 Proteus Hardware Emulation Results

The 11 levels FLMLI was also emulated in hardware and the results of the schematic shown in Fig 4.4
is shown in Fig. 4.11

Figure 4.11: Proteus Hardware Emulation of 11 levels FLMLI output voltage.

45
 4.6 Hardware/Simulation Results Discussion:

There were many issues encountered when dealing with the Proteus that are worth mentioning in this
documentation. Table 4.3 lists those issues and the way they were overcome.

Table 0-16: Proteus Hardware Emulation Challenges

Component Problem Solution

Arduino 1. Arduino was not part of Proteus 1. We found an Arduino
library model on the internet
2. Programming Arduino in Proteus then we inserted to
Proteus LIB
2. Arduino need a program
hex file which can be
generated after verifying
code inside Arduino
software
Ground pin 1. Arduino ground should be 1. We used a common
separated from other grounds ground pin for all grounds
according to our topology as 2. Back to figure 4.2, there is
safety measure but the ground pin no ground pin, then we
for arduino was not working realized there must be a
2. A ground pin with switches ground pin connected to
switches
Gate Drive 1. Vs connection may cause some 1. It’s preferred to connect
problems on driver Output High single switch to each
(OH) when connecting both OH driver
and driver Output Low (OL) on 2. Bootstrap capacitor value
the same driver for two different depends on Ton of each
switches PWM control signal and
2. Bootstrap capacitor value the values of the
capacitors must be
designed carefully (Cap.
Value should be low when
Ton is high)
Wiring Missing Connection Sometimes wires in Proteus
appeared connect while they not

46
 4.7 Validation of requirements/constraints

Table 4.4 discuss the requirements and constraints and how they were met.

Table 0-17 Validation of Resign Requirements and Constraints

Requirement Was it met?

120Vrms output Simulation showed a 170V peak which is
120Vrms. Requirement was met
Unfiltered 25% THD An unfiltered of 10% THD was proven which is
within the IEEE 510 Std that should be
followed. Requirement was met
Constraint Was it met?
Economical 1. FLMLI saved 60% on switches needed
competed to CMLI which meets the
constraint of 30% reduction in cost.
Constraint is met.
2. Balancing has been solved by adjusting
controlling signals on drivers.
Safety Optocoupler has been used to isolated controller
form the main circuit and drivers.

In conclusion, the proposed FLMLI met all design requirements and constraints.

47
5 Conclusion and Future Work

5.1 Conclusion
This documentation presented a design and simulation for MLI DC-AC converter, the objective was
to design a new multilevel inverter with 28-40V input to maintain a 120Vrms on output using
minimum number of switches.
The design focused on 4 main multilevel features: cost, number of switches, number of levels and
total harmonic distortion.
The design of the new topology for multilevel inverter (Flipped ladder multilevel inverter) has been
presented in simulation two softwares: PSIM and Proteus for 11 levels and 45 levels. The new topology
has shown a great improvement (62%) in number of switches and cost over conventional cascaded
multilevel inverter (exceeding the 30% improvement in design requirement), and much lower THD
for the same number of switches, THD was 1.7% for 45 levels and a 10% for 11 levels FLMLI before
filtering which is easily filtered to be 5% or lower after according to IEEE STD 519-1992,

5.2 Future work

Implementing simulation for 11 levels FLCMI in Proteus as hardware

48
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49