Institut für Integrierte Systeme

Integrated Systems Laboratory

Department of Information Technology and Electrical Engineering

VLSI II:
Design of Very Large Scale Integration Circuits
227-0147-00L

Exercise 9

Testing
Prof. L. Benini
F. Gürkaynak

Last Changed: 2019-05-07 15:44:13 +0200

1 Introduction
In VLSI I, we have learned to capture circuit architectures using an HDL and to synthesize the code into
gate-level netlists. In VLSI II, we will continue from there and learn how to prepare design data both for
chip manufacturing and for circuit testing. In addition, we will learn to cope with a number of imperfections
associated with physical circuits including
• synchronization failures,
• layout parasitics,
• interconnect delays and clock skew,
• resistive and inductive voltage drops,
• fabrication defects,
• ageing and electrical overstress.
This exercise is concerned with the impact of fabrication defects and with uncovering such defects hidden deep
in a circuit. A good understanding of the basic concepts behind production testing is required, so please begin
by studying Chapter 17 (A Primer on VLSI Testing) from the Top-Down Digital VLSI Design book.

Student Task 0: Parts of the text that have a gray background, like the current paragraph, indicate steps
required to complete the exercise.

While most of the VLSI exercises are rather practical and need access to EDA software packages, a
pocket calculator is all you need for this one. You are invited to prepare your answers before the
actual exercise hours. If you want your exercise to be checked by the assistants, please hand in your
solutions at the end of the exercise session.

2
2 Design for Test
2.1 Test Coverage
The defect level DL is determined by
DL = 1 − yf1−FC
where yf is the fabrication yield and FC is the fault coverage (number of detectable faults per total of possible
faults).

Student Task 1:
1. Starting from the assumption that 10 0000 000 samples of a large commercial IC have been manufac-
tured, find out how many got scrapped, how many got sold, and how many of those sold are actually
defective. Note that the table below provides room for four different situations in terms of yield and
fault coverage. Collect your numerical results there.

Fabr. Fault Defect Defective Chips Chips

yield cover. level chips sold sold scrapped

80% 95%
80% 99%
50% 95%
50% 99%

2. What is the fault coverage required to achieve a defect level of 1 per thousand for our chip with a)
80% yield and with b) 50% yield respectively?

Some companies claim to provide a so-called “6-sigma” or “6σ” quality grade. Quantitatively, this
equals to 3.4 defects per million of units delivered to the customer. What fault coverages are required
to achieve this quality for the same two yields as before?

3. Let us put the fault coverage in numbers. If the total number of faults in the chip is 7830 712, how
many undetected faults can we tolerate a) for a defect level of 1‰ and b) for “6σ” quality? Repeat
the calculation for fabrication yields of 80% and 50% respectively!

Fabr. Defect level Quality grade

yield 1‰ 6σ

80%
50%
4. Comment on how realistic the above numbers are based on the assumption that they relate to the
popular single-stuck-at model.

3
 5. Explain why achieving a high fault coverage is critical?

2.2 Testing an on-chip memory

The classic approach to memory testing is called checkerboard test and it comprises four major phases:
1. Write a checkerboard pattern into the array of storage cells.
2. Read back the entire memory content and check it for errors.
3. Write the complementary pattern into the array of storage cells.
4. Read back the entire memory content and check it for errors.
Clearly, writing and reading both occur one data word at a time. For this exercise, let us consider a synchronous
memory that allows for one access per clock cycle.

Scan_OUT
Scan_EN

Scan_IN

MEMORY
Clk

DI DO
#d #d
Inputs ADD R/W EN Outputs

#a

all registers/FFs connected to ScanPath (total of #ff FFs)

Clk

Reset Standardcell Block

Figure 1: Simplified diagram of ASIC with embedded RAM.

Student Task 2:
1. The block diagram of fig.1 shows an integrated circuit that includes an embedded RAM. Note that
the remainder of the circuit has been abstracted into a collection of flip-flops plus one large block
that includes all combinational logic. Is this IC fully testable?

4
2. If not so, propose minimal modifications to the circuit diagram such as to overcome the limitations
found.

3. Describe the steps required to do a full checkerboard test.

4. Count the clock cycles required in the occurrence of a small and a large RAM, assuming that the
existing scan chain has a length of 4000.
a) Small: 1 kibit, #a = 6, #d = 16.
b) Large: 256 kibit, #a = 15, #d = 8.
Estimate the lapse of time required to complete the checkerboard test on a tester that runs at
100 MHz and comment on the viability for volume fabrication.

5. Think of how to reduce the number of clock cycles required.

6. Core frequency is often much higher than I/O frequency and long scan chains slow down to test
several memory blocks, what could be done?

You are done with this exercise. Present your results to an assistant in order
E to get a sample solution. Then, start with Exercise 10. E