EMBEDDED PROCESSOR ARCHITECTURE
Devanshi Sinha
Dept. of Electronics and
Communication, Institute of
Technology
Nirma University
Ahmedabad, India
16bec033@nirmauni.ac.in
Abstract- Embedded processors are a special
type of processors which are designed for a
special purpose. Embedded systems consist of
these processors which help them to process the
particular task defined to the system. An
embedded system is very efficient as it focuses to
deliver the assigned task to it in a most efficient
way, with minimum power consumption.
Today’s era of IOT has a great demand of these
embedded processors to fulfil the desires of the
human community, so every processor needs to
be designed in a special way fulfilling the
expected results, hence we require different
architectures for different hardware designs.
The architectural design decides the properties
and functions of that processor.
This paper is about the different
architectures which are present and used in
these embedded processors.
Keywords: processors, embedded systems, IOT.
I .INTRODUCTION
Embedded processors can be divided into two
types: 1. Microprocessors and 2. Microcontrollers.
Embedded processors are basically used where we
require a specific task unlike the utility devices like
laptops, and computers.Different processors have
different architectures. Architecture helps us to
know about the interaction process between a
hardware and softwareof the system. It is similar to
a body skeleton which gives us the outlining and
functionality of our whole body. Just by learning
the architecture of a given processor we can know
our processor and its working easily. It can be
categorized in two basic categories: 1. Von
Neumann 2. Harvard architecture.
Sarthak Seth
Dept. of Electronics and
Communication, Institute of
Technology
Nirma University
Ahmedabad, India
16bec034@nirmauni.ac.in
Further it can be divided on the basis of:
1. Number of instructions executed per clock
2. Connection between memory and
processor.
II .VON NEUMANN ARCHITECTURE
Von Neumann architecture is after the name of the
great mathematician John Von Neumann who
thought of a processor whose memory can store
both data and instruction. Von Neumann
architecture is one of the most common
architectures that are used in today’s era.
It is an architecture which is based on a
 Single processor
 Same memory for both instruction and
data.
 Single instruction execution at a time.
The von Neumann architecture consist of three
different entities: 1. Processing unit 2.storage unit
(IAS) and 3. Input output unit, which are connected
over buses.
Processing unit- it can be divided into ALU,
control unit, registers, clock.
1. Arithmetic and logic unit is a part of the
processing unit performs all the arithmetic as
well as logical operations.
2. Control unit fetches each instruction that is to
be executed and also decodes it for the
hardware.
3. Registers are the memory circuits which hold
the address of the instruction as well as the
present instruction that is being executed .It
 also has the information about the
accumulators, status register and interrupt
registers.
4. Clock defines the sped that is faster the clock,
more number of instructions per second and
faster the processor.
Immediate access store- it is a memory which
consist of both program and data and also known as
RAM. Before von Neumann the memory was
divided into program and data memory which was
really complex, but von Neumann proposed that
there is no such difference in them and designed a
single memory.
Input and output unit – any system requires an
input and an output port to send and receive data. A
port is basically a gateway which allows us to
control the i/o mechanism. As a user we don’t want
to redesign input and output ports hence we use
different i/o controllers which acts as an interface .
Fig 1. Von Neumann Model
III .VON NEUMANN BOTTLENECK
Von Neumann bottleneck is the limitations caused
by this particular architectural design. The term is
on the name of the John Neumann who proposed to
use a same memory for data and instructions. At
the beginning everyone saw the brighter side of it
being simpler and easier to use also it required less
physical space but the era we live in is behind more
and more speed and it is where this architecture
lacked behind. We increased the speed of our
processing unit but the speed of data bus lacked
behind resulting in idle sits of the processor. Many
a times the shared memory leads to crashing of the
system as the defective programs fail to release
memory.
Von Neumann bottleneck is a big problem which
can be overcome by some significant changes in
the processor:
 Caching-some part of instructions that are
used regularly are stored in separate
memory locations so that they can be
accessed easily
 Pre-fetching – it is a technique in which
the next instructions are fed into cache
while the present instructions are being
processed.
 Multithreading – it is a technique of
managing different requests at the same
time.
 Advanced RAM – RAM’s like DDR and
SDR can be used which activates both on
rising and falling edge hence doubling the
speed.
Another architecture was developed to overcome
these problems which were possessed by Von
Neumann, known as Harvard architecture.
IV .HARVARD ARCHITECTURE
Harvard architecture is a design which has two
separate memories for instruction and data.
Harvard architecture got its name from Harvard
Mark 1. In Harvard architecture consist of both
read-only and read-write memory, as the
instructions are only allowed to read whereas the
data can be modified too. As the data and
instruction memory are different their address size
also differs, whereas the instruction address is
wider than data address. Harvard architecture
provide us speed but it comes at the cost expensive
processor, more power requirement and
complexity.
Fig 2. Harvard Model
 V .VON NEUMANN VS HARVARD
Von Neumann is a theoretical design based on the
stored program computer concept which uses same
memory for data and instructions whereas the
Harvard architecture is based on Harvard Mark 1
relay based computer model. It also uses separate
memory for data and instruction. Von Neumann is
slow as compared to Harvard architecture as it
takes one cycle to complete an instruction whereas
von Neumann takes two clock cycles. On the other
hand Harvard based processors are really costly as
compared to Von Neumann, also it is quite easy
and simple to understand. Harvard architecture
comes with a great speed because in this
architecture data transfer and instructions are
fetched at the same time hence it is used in
microcontrollers and signal processing.
VI .MULTI PROCESSOR ARCHITECTURE
Uni-processors cannot provide the performance and
efficiency which is required for the future
applications. Let us think of our cell phones which
are multi functional and provides us multi
windows, working on a single processor. The cell
phone will crash immediately with the old set of
architectural design, hence to overcome this we use
multi processor architecture. This has become
possible with the growing VLSI technology, which
allows us to integrate multi processors on a single
chip.
There are a lot of issues which can be easily solved
with the multiprocessor design, whereas embedding
them on a single chip to form a System-On-Chip
also comes with great challenges such as physical
and logic design, also we need an architecture
which is efficient enough for making an
interconnection between processor and peripherals.
VII .CISC
CISC is a processor architecture based on read only
memory and are designed such that it provides
required capabilities in most effective ways. During
the development years of computers, coding of
applications was done through assembly code. Idea
of high level languages didn't exist at that time.
Writing assembly codes was a tiresome process.
For making programming quick the computers
started supporting huge number of instructions. The
Fig 3. CISC Architecture
instructions were able to support complexity of
operations. Writing lesser codes that is lesser
number of instructions made programming easier
for the programmer. Memory cost was one more
factor for the advancement of complex instruction
set. As the cost of memory was high the designers
wanted to decrease the requirement of memory so
that cost could be reduced.
VIII .RISC
In CISC processor the complex instructions take
large number of processor cycles for execution.
The slowest operation performed decides the
overall speed of the processor in pipelined
technology processors. Thus complex instructions
reduce the execution speed of even simple
instructions. As the compiler technology developed
the programmers started to use higher level
languages. The compiler's work was to convert
high level codes into machine language codes.
Combination of simple instructions was used for
achieving complex operations in compilers. It was
seen that writing combination of simple
instructions rather than one complex instruction
was much more efficient. Hence compiler
generated programs mostly used simple
instructions. Compilers didn't use most of the
addressing modes offered by CISC processor. The
main aim of product designers became reduction in
size and complexity of instruction sets and making
simpler and smaller instruction sets that could be
helpful in 2 ways. First, the speed of pipelining
could be increased due to simpler instructions and
hence the performance could be improved. Second,
the cost could be reduced as simple instruction set
requires less computer hardwares. Hence the design
goal was to attain faster execution due to basic
simple instructions. Compilers used these simple
instructions for construction of complex operations.
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This paper has been guided by Prof. Ami Vora. We
are grateful to our teachers for their guidance,
valuable time and relevant sites and materials. We
are obliged to Prof.AmiVora for enhancing our
skills and improving our knowledge about the
topic.