LF15Ai User Guide V0 5 0

PDK_LF15Ai_V0_5_0
User Guide
iPDK for Cadence & Synopsys
rev. 0.5.0
December 2014
RY
N A
M I
L I
R E
P
There for You, Any Time, Every Time CONFIDENTIAL
Contents
1. LFoundry Profile 1
2. LF15A Technology description 2
3. Introduction 3
3.1. General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2. LF15A PDK Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.3. EDA Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4. PDK setup 8
4.1. Naming convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2. Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.3. Available Add-Ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.4. PDK Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.4.1. Installing the PDK . . . .
4.4.2. Creating User Workareas
4.4.3. Defining Environment . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
RY.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
10
10
11
A
4.4.4. PDK usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5. Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5.1. Installation . . . . . . . .
4.5.2. Design . . . . . . . . . . .
.
.
.
.
.
.
.
.
.
.
I N
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
13
14
M
5. Libraries 15
I
5.1. Primitive Library cmos150 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.1. MOS Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
EL
5.1.2. Bipolar Transistor . . . . . . . . . . . . . . . . . . . . .
5.1.3. Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.4. MOS Capacitors . . . . . . . . . . . . . . . . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
18
19
20
R
5.1.5. Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.6. Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
P
5.2. Primitive Library Modeling . . . . . . . . . . . . . . . . . . . .
5.2.1. Model Usage . . . . . . . . . . . . . . . . . . . . . . . .
5.3. HV Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.1. LDMOS Transistor . . . . . . . . . . . . . . . . . . . . .
5.4. HV Library Modeling . . . . . . . . . . . . . . . . . . . . . . .
5.4.1. Model Usage . . . . . . . . . . . . . . . . . . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
25
25
28
28
29
29
5.4.2. LDMOS Transistor Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.5. Digital Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.5.1. Standard Cell Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.5.2. Synopsys Milkyway Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.6. SealRing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.7. I/O Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.7.1. Pins, Settings and Characteristics for 1.8 V GPIO Cells . . . . . . . . . . . . . 40
5.7.4. Cell Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PDK_LF15Ai_V0_5_0 / UG LFoundry GmbH — http://www.lfoundry.com II

5.7.5. Power Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6. Process Specification 52
6.1. Available Process Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.2. Layer List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.3. General Process Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.3.1. Cross Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.3.2. Resistances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.3.3. Basic Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.3.4. Current Density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.3.5. Interconnect Capacitance Table . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.4. Process Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.4.1. Judgement Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.4.2. Information Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.4.3. Wafer Reject Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7. Process Control Parameters 60

7.1. Parametric Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7.1.1. Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7.1.2. Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8. Physical Verification 64
Y
8.1. DRC: Design Rule Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
8.1.1. Annotations on MIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
8.1.2. Annotations on Resistors .
8.1.3. Annotations on Area Rules
8.2. LVS: Layout Versus Schematic . .
8.2.1. Stamp Check for Diffusion .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
A
.
.
R .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
64
64
64
64
9. ESD Information
9.1. ESD Specification . . . . . . . . . . . . . .
I N
. . . . . . . . . . . . . . . . . . . . . . . . .
66
66
9.2. ESD Rules . . . . . . . . . . . . .
L I
9.2.1. ESD Design Requirements
9.2.2. Protection Devices . . . .
.
.
.
.
.
.
.
.
.
.
.
.
M
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
66
66
66
E
10.Technology and Reliability Qualification 68
10.1. Planned JP001 Level 1 qualification test items for LF15A . . . . . . . . . . . . . . . . 68
Appendix
A. Abbreviations
PR
10.2. Planned JP001 Level 2 qualification test items for LF15A . . . . . . . . . . . . . . . . 69
ii
B. PCM parameter description iv
C. iPDK supported devices vi
D. List of Figures viii
E. Document History ix
PDK_LF15Ai_V0_5_0 / UG LFoundry GmbH — http://www.lfoundry.com III

1. LFoundry Profile
LFoundry is the foundry of choice because it:
• leads analog, digital and mixed signals CMOS process technology by engaging a continuous
process improvement for its own 0.15um technology node.
• promotes specialized manufacturing technologies and a world-class engineering organization.
• supplies a monthly capacity of more than 40k, on 200mm, wafers.
• is fully compliant to and is certified under the TS16949 automotive standards. It is working
towards fully satisfying the ISO15408 smartcard compliance and certification.
• guarantees security and protection of customers own designs and Intellectual Property.
RY
• supports a fairly extensive portfolio of IP that includes RF, HV, embedded memories other than
radiation-hardness capabilities for aerospace applications.
requests from its customers.
N A
• guarantees process efficiency and flexibility and is able to respond to specific capacity and service
• is reliable and flexible.
M I
L I
R E
P
PDK_LF15Ai_V0_5_0 / UG LFoundry GmbH — http://www.lfoundry.com 1

2. LF15A Technology description
The wide range of possibilities offered by the LF15A PDK technology depends from the adopted
process solutions and optimization put in place at any process step.
The major process features include:
• STI (Shallow Trench Isolation) formation to meet low power compliance and high speed perfor-
mances;
• n/p-well formation and channel enhancement;
• a triple option for the gate oxide thickness (28A, 70A and 160A);
• un-doped poly-Si deposition (250 nm) with a dual gate material option (n+ and p+ doped
poly-Si gate);
• gate patterning;
RY
A
• lightly doped drain (LDD) junction formation by ion implantation and spacer formation;
N
• n/p source and drain junction ion implantation;
• CoSi2 formation;
M I
L I
• Si3N4 capping layer deposition and BPSG for poly-to-metal dielectric with chemical mechanical
polishing (CMP) planarization,
R E
• Contact and four/six levels of metal interconnections with TEOS inter-metal dielectrics and
CMP planarization.
P
• Optionally a MIM capacitor and a polyimide passivation (inductors flow).

3. Introduction
3.1. General information
This user guide is a controlled, comprehensive collection of information on LF15A PDK setup and
usage. Additional information can be gathered by visiting our web page at www.lfoundry.com. For
further assistance, contact us at PDKsupport@lfoundry.com.
In order to receive the appropriate support and response, please specify the following:
• PDK name and version
• Work Station operating system (LF15A is designed for LINUX, e.g. RHEL)
• EDA tool version (please check for the supported EDA version in section 3.3)
RY
3.2. LF15A PDK Introduction
N A
This user guide introduces the LF15A PDK.
M I
I
The PDK is OpenAccess based, contains python-based parameterized cells (pycells) and is qualified
for both Cadence and Synopsys environments. The design kit includes analog, digital and IO libraries
EL
to enable LFoundry customers full Mixed-Signal design flow.
The LF15A PDK is modular CMOS process based on 0.15um technology node. The kit includes
R
three metallization flavors: 4-metal, 5-metal and 6-metal with an optional thick metal (2um-6um
thickness) and supports three voltage domains: 1.8V, 3.3V and 5.0V. The LF15A provides optionally
P
MIM capacitor as well as polyimide passivation process (for better inductor performances).
Once your design is ready for Tape Out, please refer to the Customer Manufacturing Guide. It is part
of this PDK and can be found in the directory tools/designupload. You will also find this document
as well as the upload tool itself on the LFoundry SFTP server. Please note that the version on the
SFTP server may be more recent.
Note: All information in this document is subject to change without further notice. Please take care
to use always the most recent version of this document.
Note: The company and product names used in this document are for identification purposes only.
All trademarks and registered trademarks are the property of their respective owners.

3.3. EDA Environment
This PDK is checked to work with the following EDA environment:
Stream Release Tool Usage

Si2
22.04.054 OpenAccess Database, included in Cadence or
Synopsys installation
Cadence
IC 6.1.5 DFII , Virtuoso Schematic Capture, Layout Edi-
tor, Simulator UI
MMSIM 12.10.418 Spectre, Ultrasim Circuit Simulation
Assura 4.12 (6.1.5) Assura DRC, LVS
EXT 12.1.0-s442 Assura QRC Parasitic Extraction
SOC 8.10 SoC Encounter Place&Route
IUS 8.10 NCSIM , Incisive Simulator Suite Digital Simulation
RC 8.10 RTL Compiler RTL Synthesis
Synopsys
2013.12-sp2-2 Custom Designer Schematic Capture, Layout Edi-
tor, Simulator UI
Mentor Graphics
Calibre v2013.1_27.15 Calibre
RY
DRC, LVS, xRC
Note: Please note that other tools and lower versions of tools of the reported ones are not officially
supported and will probably not work with this PDK.
N A
I
Figure 3.1 shows a general overview of the EDA vendors supported by LFoundry, figures 3.2 shows
the supported design flow and EDA tools for Cadence.
L I M
R E
P

RY
N A
M I
L I
R E
P Figure 3.1.: EDA tool vendors

Analog Mixed-Signal Digital
n
sig Virtuoso Netlist
De ry Schematic Editor Editor
t
En
n Spectre Virtuoso Incisive

latio Spectre RF AMS Enterprise
u
Sim Ultrasim Designer Simulator
sis Encounter
nthe RTL
Sy Compiler
t Virtuoso Encounter
you Layout Digital
La
Y
Suite L/XL Implementation
LV
S Assura
LVS
A R
ic
sit n
I N
M
r a QRC
Pa actio Extraction
Ex
tr
L I
DR
C
R E Assura
DRC
Calibre
nmDRC
P Tapeout
b -In dups
Fa
Figure 3.2.: LF15A Cadence Mixed-Signal design flow

Analog Mixed-Signal Digital
n
sig Custom Designer Netlist
De ry Schematic Editor Editor
t
En
n HSpice
latio NanoSim XA VCS
u
Sim HSim
sis Design
nthe Compiler
Sy
t Custom Designer ICC-CD IC

you
La Layout Editor Compiler
Y
Co Design
LV
S Hercules
LVS
A R
ic
sit n
I N
M
r a StarRC
Pa actio Extraction
Ex
tr
L I
DR
C
R E Hercules
DRC
Calibre
nmDRC
P Tapeout
b -In dups
Fa
Figure 3.3.: LF15A Synopsys Mixed-Signal design flow

4. PDK setup
4.1. Naming convention
The next table describes PDK_LF15Ai_V0_5_0 naming convention: PDK_xy_Va_b_c (e.g. PDK_-
LF15Ai_V0_5_0)
x LF15A Process
y i PDK option (i: iPDK (Cadence, Synopsys, . . . ), T: Tanner)
a 0 Main release
b 5 Sub release
c 0 Patchlevel
4.2. Basics
RY
Grid resolution: 0.01 µm
N A
4.3. Available Add-Ons
M I
L I
Sonnet Verification Kit
Available add-ons
E
Please contact the PDK support (PDKsupport@lfoundry.com) for an overview of all available add-ons.
R
P
4.4. PDK Installation
The LF15A design kit is delivered to our customer like a tarball (*.tgz). PDK directory structure is
shown on the figure 4.1 on the page 9. The PDK package has to be installed once on the customers
system. After that, every user is requested to create their own work area.
The 4metal, 5metal and 6metal options are available within the PDK structure. The users MUST set
up the $LF15A_OPTION UNIX variable to define the metal option. The automatic configuration script
workarea.PDK_LF15Ai_V0_5_0 will prompt you to choose the metal option you need to use in your
personal work area. It is strongly recommended that different work areas be created for designs with
different metal options. Changing the metal option for a given design results in DRC and LVS errors
other than database inconsistency. The PDK directory structure is presented on the picture below:
To use the PDK with Virtuoso or Custom Designer environment, please follow the instructions in the
chapter 4.4.1 below.

PDK_LF15Ai_V0_5_0
analog
libraries
4metal cmos150, I/O libs)
cmos150
cmos150pIO1v8hvt
cmos150pIO3v3hvt
cmos150pIO5v0hvt
5metal cmos150, I/O libs)
cmos150
cmos150pIO1v8hvt
cmos150pIO3v3hvt
cmos150pIO5v0hvt
6metal 6 metal OA libs (cmos150, I/O libs)
cmos150
cmos150pIO1v8hvt
cmos150pIO3v3hvt
cmos150pIO5v0hvt
common Common OA data (cmos150_common, digital libs)
cmos150_common
lf15adhvt9s
lf15adlvt9s
models Models
hspice Model files for HSpice
spectre Model files for Spectre
digital Digital and IO libs data
captables Capacitance tables
cmos150pIO1v8hvt Digital data of I/O library (pad limited, 1.8 V, low leak)
gds
lef
liberty
spice
spice_for_lvs
verilog
gds
lef
liberty
spice
verilog
gds
lef
liberty
Y
spice
verilog
lf15adhvt9s Standard cell library (low leak, 9 track)
R
databook
Databook
lf15adhvt9s_best_best
lf15adhvt9s_typical_conditional
A
lf15adhvt9s_worst_worst
gds
lef
liberty
N
spice
I
verilog
lf15adlvt9s Standard cell library (high spead, 9 track)
databook
Databook
lf15adlvt9s_best_best
M
lf15adlvt9s_typical_conditional
lf15adlvt9s_worst_worst
I
gds
lef
liberty
L
spice
verilog
techfiles Tech files for Place&Route
E
lef
doc Documentation
pv Physical verification data
assura PV data for Assura (DRC, LVS, QRC)
R
4metal
drc
lvs
qrc
P
5metal
drc
lvs
qrc
6metal
drc
lvs
qrc
common
drc
lvs
qrc
calibre Calibre data na
hercules Hercules data NA
starrc PV data for StarRC (LPE)
4metal
4metal_mt
5metal
5metal_mt
6metal
6metal_mt
common
techfiles Tech files
tools PDK Tools
plugins Bundles like the Ciranova plug-in
setup Setup files (reference)
user Setup files (for user work area)
Figure 4.1.: File structure of PDK

4.4.1. Installing the PDK
In order to install both the LF15A PDK and the user Work Area you need the following files:
File name Description

PDK_LF15Ai_V0_5_0.tgz LF15A tarball
install.PDK_LF15Ai_V0_5_0 PDK installation script
workarea.PDK_LF15Ai_V0_5_0 Work Area installation script
Note: The PDK installation script (install.PDK_LF15Ai_V0_5_0) and the WorkArea installation
script (workarea.PDK_LF15Ai_V0_5_0) require perl and gtar available on the Customer’s system.
This should be the case for the majority of UNIX systems.
Note: The PDK installation script (install.PDK_LF15Ai_V0_5_0) once the PDK installation step
has been completed, proposes to continue with the user WorkArea preparation. The customer can
accept and proceed with the user WorkArea setup step or can exit from the script and run at a
convenient time the user WorkArea installation script (workarea.PDK_LF15Ai_V0_5_0).
Please invoke the installation script and follow its instructions. It will first require an absolute path
to the PDK tarball folder. Then you have to specify an absolute path to the installation target folder.
Alternatively, you can extract the PDK archive manually:
$ cd ~/PDK (presuming ~/PDK is the directory you store your PDKs in)
RY
A
$ tar xfz ~/PDK_LF15Ai_V0_5_0.tgz (data will be below new directory PDK_LF15Ai_V0_5_0)
N
4.4.2. Creating User Workareas
M I
L I
Start workarea.PDK_LF15Ai_V0_5_0 script and follow its instructions.
The script will require: 1. Specify Path to the PDK installation folder. 2. Specify Path to the current
R E
working folder. In case, the working directory already exists, the script will update your folder to be
consistent with the new PDK version. 3. Specify Metal option you want to use: (4-, 5- or 6-metal)
4. Specify Cadence or Synopsys environment to use 5. Specify which Ciranova plug-in to use. Please
P
refer to section 3.3.
This script will create two environment template files set.LF.environment.bash and set.LF.environment.csh,
where users may define EDA tools that are necessary for the PDK to work with your software instal-
lations.
First the PDK internal variables MUST be defined:
1. $LF15A_HOME path to the PDK installation directory.
2. $LF15A_OPTION metal flavor name (4metal, 5metal or 6metal)
Second a list of tool related variables must be defined. The template files list the necessary variables.
Please use the files like templates only and update them according to your current software installation
folders. For a detailed list of required variables refer to 4.4.3.

Alternatively, you can create your workarea manually:
1. Change into the directory, you want to use as workarea.
2. Set the environment variable $LF15A_HOME to your PDK installation directory

(e.g. export LF15A_HOME <PDK installation directory>)
3. Set the environment variable $LF15A_OPTION to the metal option you intend to use.
(e.g. export LF15A_OPTION 6metal)
4. Copy the .cdsinit (for Cadence) or .cdesigner.tcl (for Synopsys) from

$LF15A_HOME/tools/user.
To define bindkeys.
5. Copy the cds.lib (for Cadence) or lib.defs (for Synopsys) from $LF15A_HOME/tools/user
or add the following line to your existing file:
INCLUDE $LF15A_HOME/tools/setup/cds.lib respective lib.defs
6. Set the proper tool variables (see 4.4.3).
Y
4.4.3. Defining Environment
A R
The LF15A PDK uses some OS environment variables in the setup files. In order to guarantee the
proper functionality for the LF15A PDK with the customer EDA installation software, the environment
variables defined in the table, shown below, need to be set up.
I N
Note: The Work Area configuration script workarea.PDK_LF15Ai_V0_5_0 creates two files in the
user Work Area directory set.LF.environment.bash and set.LF.environment.csh. which at least
L M
may be useful as template for a personalized environment script.
I
Note: PyCells require Ciranova plug-in. The customer has to setup proper variable. In fact, a plug-in
with ’gcc44x’ in its name MUST be used with Virtuoso. The ’gcc412’ plug-in MUST be used with
R E
Synopsys. Always use the plug-in version delivered within the PDK package! Always use
32-bit plug-in version with 32-bit EDA tools executables and 64-bit plug-in with 64-bit
EDA tools executables.
Variable, Value
P
LF15Ai specific variables
LF15A_HOME, e.g. /opt/tech/
Environment variables
Description
Path to the directory where the LF15Ai

design kit is installed
Used in file
cds.lib,
lib.defs,
assura_tech.lib,
.cdesigner.tcl
LF15A_OPTION, e.g. 6metal Process option; 4metal, 5metal or cds.lib,
6metal; see also fig. 4.2 lib.defs,
assura_tech.lib,
.cdesigner.tcl
continued on next page

Environment variables (continued)

Variable, Value Description Used in file
LF15A_DISPLAY, e.g. true Controls the dispay.drf load mecha- .cdsinit,
nism; value true loads from PDK, false .cdesigner.tcl
(or unset) from work area
LF_PDF_READER_HOME, The path to the pdf reader executable .cdsinit
e.g. /usr/bin
LF_PDF_READER, e.g. acroread The pdf reader executable .cdsinit
Cadence specific variables
CDSHOME, e.g. /opt/cds/ic615 The Cadence DFII installation directory cds.lib
CDS_Netlisting_Mode, Analog Controls how component description for-
mat (CDF) properties are interpreted
during netlisting
DD_USE_LIBDEFS, NO If set to NO DFII applications will not
read or modify lib.defs file and will use
only the cds.lib file
ASSURAHOME, Enables DFII design tools to have access cds.lib
e.g. /opt/cds/assura41_615 to the Assura tools
QRC_HOME, e.g. /opt/cds/ext914 To setup the stand-alone QRC menu in
Virtuoso
Synopsys specific variables
CCDIR, The Synopsys Custom Designer installa- lib.defs,
tion directory
e.g. /opt/synopsys/customdesigner/E-2011.03
Y
autoLoad.file
R
A
Mentor Graphics specific variables
MGC_HOME, The Mentor Graphics Calibre installa- .cdsinit
N
e.g. /opt/ment/cal20101 tion directory
Ciranova plug-in specific variables
CNI_ROOT,
M I
Root path of Ciranova plug-in; select ac-
cording to your DFII installation
CNI_PLAT_ROOT,
I
e.g. $LF15A_HOME/tools/plugins/ciranova_plugin_linux_rhel30_gcc411_32_4.4.2_I6
L
Path for plug-in; select according to your
DFII installation
OA_COMPILER, gcc411
PATH,
R E
e.g. $CNI_ROOT/plat_linux_gcc411_32
Compiler for Ciranova
Search path extension
P
$CNI_PLAT_ROOT/3rd/bin:$CNI_PLAT_ROOT/bin:$CNI_ROOT/bin:$PATH
CNI_LOG_DEFAULT, /dev/null Default plug-in log
PYTHONHOME, Python path for plug-in
$CNI_PLAT_ROOT/3rd
PYTHONPATH, Python specific search path extension
$CNI_ROOT/pylib:$CNI_PLAT_ROOT/lib:$PYTHONPATH
LD_LIBRARY_PATH, Library path extension
$CNI_PLAT_ROOT/3rd/lib:$CNI_PLAT_ROOT/lib:$LD_LIBRARY_PATH
OA_PLUGIN_PATH, Path of OpenAccess plug-in
$CNI_ROOT/quickstart:$OA_PLUGIN_PATH

cmos150 Technology and device library
$LF15A_OPTION
... Some more libraries
myLib Customer’s design library
Figure 4.2.: LF15A technology database graph
4.4.4. PDK usage
1. Change the directory to your Work Area where Virtuoso or Custom Designer will be invoked..
($ cd ~/your/working/directory)
2. Source one of the files set.LF.environment.bash or set.LF.environment.csh to define your
Y
environment).
3. Invoke Virtuoso or Custom Designer from your working folder.
A R
N
4.5. Troubleshooting
4.5.1. Installation
M I
L I
export doesn’t work? Please check the default shell-environment in your OS. If you have shell dif-
ferent from bash like csh /tcsh /ksh please use command setenv instead: setenv CDS_-
R E
Netlisting_Mode Analog.
Layout instances disappeared Please verify Ciranova plug-in version. The plug-in version has to
P
match the specific EDA tool installation. The plug-in with ’gcc44x’ in its name MUST be
used with Virtuoso. Plug-in with ’gcc412’ MUST be used with Custom Designer. Take into
account that 32-bit plug-in version must be used with 32-bit EDA tools executables and
64-bit plug-in with 64-bit EDA tools executables. Moreover Synopsys Custom designer always
requires 64-bit though Virtuoso can be invoked both in 32-/64-bit modes. To change Virtuoso
mode from 32-bit to 64-bit use CDS_AUTO_64BIT Unix variable (e.g. "export CDS_AUTO_-
64BIT=ALL" for all type of executables, Please refer to Cadence documentation for more details).
Please check also your Ciranova plug-in version and OpenAccess database version. For more
details refer to the 3.3 chapter.
cds.lib or lib.defs is missing Please copy the cds.lib from the directory $LF15A_HOME/tools/user
into your working directory for Cadence environment. Please copy lib.defs from the directory
$LF15A_HOME/tools/user into your working folder for Synopsys environment.

4.5.2. Design
The mult parameter doesn’t work Please check .cdsinit if the next string exists
envSetVal("layoutXL" "mfactorNames" ’string "mult m M")
If it’s not there please add this line or copy .cdsinit from the $LF15A_HOME/tools/setup.
Where are the Library Manager and the Display Resource Manager ? You will find them in the Tools
menu within either Virtuoso or Custom Designer.
Can’t see the 3 V and 5 V MOS transistors in Schematic? Please copy the display.drf from the
directory $LF15A_HOME/tools/setup into your working directory.
An wartning message appear when instantiating a device? If the message is like one of of the fol-
lowing ones:
*WARNING* ddMapGetFileViewType: You are trying to run an OA executable on a CDB
library file (...)
*WARNING* ddMapGetFileViewType: You are trying to run a CDB executable on an OA
library file (...)
*WARNING* _deValidateViewType: viewType is nil
You probably have library and DFII versions that are incompatible. This PDK is designed
for OpenAccess based Virtuoso of version 6.1.x. For more detailed information about versions
Y
please refer to chapter 3
You get the next warning in Virtuoso like:
R
*WARNING*: The Pcell super master: <library>/<cell>/layout is not a SKILL super
A
master. The usage of non-SKILL Pcells in Virtuoso is not a supported feature.
N
Please ignore the message. The python-based pcells are provided together with proper Ciranova
I
plug-in that guarantees functionality under Cadence environment.
You get an RCX error message like this:
I
*ERROR* at "capgen": errors found in -p2lvs file
M
You get this error message due to you use wrong flow e.g. Assura LVS - Assura RCX. The RCX
L
is an old tool for layout parasitic extraction we do not support. All our techfiles were compiled
for QRC tool that should be used (Assura LVS-to-QRC flow). Please refer to section 3.3.
Solution:
R E
P
1. Please download the QRC tool from Cadence. For the version, please refer to section 3.3.
2. Setup QRC_HOME shell variable to the installation:

export QRC_HOME = /<path_to_install_dir>/PVE/<tool_version>
3. Update your PATH unix variable:

export PATH=${QRC_HOME}/tools/bin:${QRC_HOME}/tools/dfII/bin:${PATH}
4. Enable QRC:
export QRC_ENABLE_EXTRACTION=1
5. Run Virtuoso. Then you will see the QRC menu item, or QRC RUN button through the
Assura menu.

5. Libraries
5.1. Primitive Library cmos150
5.1.1. MOS Transistors
The MOS transistor device naming follows this rule: amosbc[d]_e (e.g. nmos1v2rvt_3)
a Transistor type n nmos

p pmos
b Device voltage 1v8 1.8 V
3v3 3.3 V
c Device characteristic lvt low Vt
Y
rvt regular Vt
hvt high Vt
d
e
Isolation scheme
Bulk connection
zvt
i
3
zero Vt (native)
Deep NWell isolation
programmable
A R
N
4 by wire
I
The naming and usage for the MOS transistor parameters are given in the following table:
M
I
MOS transistor parameters
Display name Description Model LVS PyCell
Model name
Total width
Finger width
EL Simulator model name

MOS channel width, sum of all fingers
MOS channel width per finger
•
• •
•
R
Length MOS channel length • • •
Number of fingers Number of gate fingers • •
Multiplier
Bulk terminal
DNW terminal
Parameters
Gate contact
P Number of parallel MOS devices
Programmable Bulk connection
Programmable DNW connection
Paramter display choice
Gate contact and connection for multi-
finger MOS
•
•
•
•
•
Gate contact width Gate contact and strap connection width •

Gate contact extra space Extra space for gate strap relative to ini- •
tial placement
Gate contact coverage Gate contact coverage control % •
Gate contact alignment Gate contact alignment control •
Gate contact metal stack Gate contact metal stack, up to METAL4 •
Abutment enable Controls abutment for the MOS ends •

MOS transistor parameters (continued)

MOS left end MOS left end style or dummy •
MOS right end MOS right end style or dummy •
Source/Drain connection Source/Drain connection for multi-finger •
MOS
Source strap width Source connection strap width •
Drain strap width Drain connection strap width •
Source strap extra space Extra space for source strap relative to •
initial placement
Drain strap extra space Extra space for drain strap relative to ini- •
tial placement
Source contact coverage Controls source contact coverage in % •
Drain contact coverage Controls draim contact coverage in % •
Source contact alignment Controls source contact alignment •
Drain contact alignment Controls drain contact alignment •
Source metal stack Source metal stack, up to METAL4 •
Drain metal stack Drain metal stack, up to METAL4 •
Source contact columns Source contact columns, 1 or 2 contacts •
Drain contact columns Drain contact columns, 1 or 2 contacts •
Bulk contact Bulk contact or ring •
Bulk contact space Absolute space between device and con- •
DNW contact
Source juction area
tact
Deep NWell contact or ring
Source juction area •
RY •
A
Drain junction area Drain junction area •
Source STI edge Source STI edge perimeter •
Drain STI edge Drain STI edge perimeter
I N •
In the following two tables the MOS transistors supported by the LF15A PDK are described, along
M
with their models parameters and their respective input ranges.
L I
R E
P

MOS-FET parameters
Device Volt Name Parameter Terminal Model
[V] # names name
NMOS low leak 1.8 nmos1v8hvt_3 l,wf,mult,nf 3,(4) D,G,S,(B)nmos1v8hvt
NMOS low leak 1.8 nmos1v8hvt_4 l,wf,mult,nf 4 D,G,S,B nmos1v8hvt
NMOS isolated low leak 1.8 nmos1v8hvti_3 l,wf,mult,nf 3,(6) D,G,S, nmos1v8hvti
(B,DN,SUB)
NMOS isolated low leak 1.8 nmos1v8hvti_4 l,wf,mult,nf 4,(6) D,G,S,B,nmos1v8hvti
(DN,SUB)
NMOS standard 1.8 nmos1v8lvt_3 l,wf,mult,nf 3,(4) D,G,S,(B)nmos1v8lvt
NMOS standard 1.8 nmos1v8lvt_4 l,wf,mult,nf 4 D,G,S,B nmos1v8lvt
NMOS isolated standard 1.8 nmos1v8lvti_3 l,wf,mult,nf 3,(6) D,G,S, nmos1v8lvti
(B,DN,SUB)
NMOS isolated standard 1.8 nmos1v8lvti_4 l,wf,mult,nf 4,(6) D,G,S,B,nmos1v8lvti
(DN,SUB)
NMOS native 1.8 nmos1v8zvt_3 l,wf,mult,nf 3,(4) D,G,S,(B)nmos1v8zvt
NMOS native 1.8 nmos1v8zvt_4 l,wf,mult,nf 4 D,G,S,B nmos1v8zvt
NMOS 3.3 nmos3v3rvt_3 l,wf,mult,nf 3,(4) D,G,S,(B)nmos3v3rvt
NMOS 3.3 nmos3v3rvt_4 l,wf,mult,nf 4 D,G,S,B nmos3v3rvt
NMOS isolated 3.3 nmos3v3rvti_3 l,wf,mult,nf 3,(6) D,G,S, nmos3v3rvti
(B,DN,SUB)
Y
NMOS isolated 3.3 nmos3v3rvti_4 l,wf,mult,nf 4,(6) D,G,S,B,nmos3v3rvti
(DN,SUB)
NMOS
NMOS
NMOS isolated
5.0
5.0
5.0
nmos5v0rvt_3
nmos5v0rvt_4
nmos5v0rvti_3
l,wf,mult,nf
l,wf,mult,nf
l,wf,mult,nf
4
A R
3,(4) D,G,S,(B)nmos5v0rvt
D,G,S,B nmos5v0rvt
3,(6) D,G,S, nmos5v0rvti
(B,DN,SUB)
NMOS isolated
PMOS low leak

5.0
1.8
nmos5v0rvti_4
pmos1v8hvt_3
I N l,wf,mult,nf
l,wf,mult,nf
4,(6) D,G,S,B,nmos5v0rvti
(DN,SUB)
3,(4) D,G,S,(B)pmos1v8hvt
PMOS
PMOS
PMOS
PMOS
low leak
standard
standard
L I
1.8
1.8
1.8
3.3
pmos1v8hvt_4
pmos1v8lvt_3
pmos1v8lvt_4
pmos3v3rvt_3
M l,wf,mult,nf
l,wf,mult,nf
l,wf,mult,nf
l,wf,mult,nf
4
4
D,G,S,B pmos1v8hvt
3,(4) D,G,S,(B)pmos1v8lvt
D,G,S,B pmos1v8lvt
3,(4) D,G,S,(B)pmos3v3rvt
PMOS
PMOS
PMOS
R E 3.3
5.0
5.0
pmos3v3rvt_4
pmos5v0rvt_3
pmos5v0rvt_4
l,wf,mult,nf
l,wf,mult,nf
l,wf,mult,nf
4 D,G,S,B pmos3v3rvt
3,(4) D,G,S,(B)
4
pmos5v0rvt
D,G,S,B pmos5v0rvt
Device
NMOS low leak

P [V]
1.8
MOS-FET parameters input range
Voltage l [µm] l [µm] wf [µm] wf [µm]
min
0.150
max
10
min
0.320
max
50
nf
min
1
nf
max
100
mult
min
1
mult
max
-
NMOS standard 1.8 0.150 10 0.320 50 1 100 1 -
NMOS native 1.8 0.200 10 1.000 50 1 100 1 -
NMOS 3.3 0.350 10 0.800 50 1 100 1 -
NMOS 5.0 0.800 10 0.800 50 1 100 1 -
PMOS low leak 1.8 0.150 10 0.320 50 1 100 1 -
PMOS standard 1.8 0.150 10 0.320 50 1 100 1 -
PMOS 3.3 0.350 10 0.800 50 1 100 1 -
PMOS 5.0 0.600 10 0.800 50 1 100 1 -

MOS-FET characteristics [L = Lmin ]

Device Name Module Vt Ids BVds Ioff (typ/max) Vds/Vgb (max)
µA
[V] [ /µm] [V] [pA/µm] [V]
1.8V nmos1v8lvt MOS18S 0.5 630 4.0 30/70 2.0
NMOS or
standard MOS18SL
1.8V nmos1v8hvt MOS18L 0.7 490 4.0 2/3 2.0
NMOS low or
leakage MOS18SL
1.8V nmos1v8zvt MOS18S 0.34 650 4.0 850/1200 2
NMOS or
native MOS18SL
3.3V nmos3v3rvt MOS3 or 0.53 460 9.0 3/100 3.7
NMOS MOS35
5.0V nmos5v0rvt MOS5 or 0.75 395 10.0 1/10 6.0
NMOS MOS35
1.8V pmos1v8lvt MOS18S -0.56 -250 -5.1 -2/-70 -2.0
PMOS or
standard MOS18SL
1.8V pmos1v8hvt MOS18L -0.68 -200 -5.0 -0.5/-3 -2.0
PMOS low or
leakage MOS18SL
3.3V
PMOS
5.0V
pmos3v3rvt
pmos5v0rvt
MOS3 or
MOS35
MOS5 or
-0.56
-0.73
-330
-235
-6.8
-9.7
-2/-70
-1/-10
RY -3.7
-6.0
PMOS MOS35
N A
Up to now, there is no difference in transistor models between isolated and not isolated devices.
5.1.2. Bipolar Transistor
M I
L I
The current version of the PDK supports the following bipolar devices.
E
Note: The LF15A bipolar devices have fixed layouts.
R
P
Bipolar transistor parameters
Device Voltage Name Parameter Terminal
[V] # names
NPN 3.3 npn fix 3 E,B,C,(SUB)
PNP 3.3 pnp fix 3 E,B,(C=SUB)
Bipolar transistor characteristics

Device Name Module Vbe hFE
[V]
3.3V NPN npn NISO; MOS3 or 0.641 26.4
MOS35
3.3V PNP pnp MOS3 or MOS35 -0.634 20.1

5.1.3. Diode
The diode naming follows this rule: a[b]cd[e] (e.g. dnppw1v2)
a Device indicator d diode

b Implant np N+
pp P+
c Well nw NWell
pw PWell
d Voltage domain (optional) 1v2 1.2 V
3v3 3.3 V
e Diode to . . . ps p-Substrate
The naming and usage for the diode parameters are given in the following table:
Diode parameters
Model name Simulator model name •
Length Length •
Width Width •
Multiplier Number of parallel bjt devices • •
Y
Style Layout style •
Anode metal stack Anode metal stack, up to METAL4 •
Cathode metal stack
Junction area
Junction perimeter
Cathode metal stack, up to METAL4
Junction area
Junction perimeter
•
•
A R •
•
•
I N
In the following tables the diodes supported by the LF15A PDK are described, along with their models
parameters and their respective input ranges.
Device
N+P-Well
L I Name
dnppwl
Parameter Terminal
l,w,mult
# names M
Diode parameters
2 PLUS,MINUS
Model
name
dnppwl
N+P-Well iso-
lated
P+N-Well
R E dnppwli
dppnwl
l,w,mult
l,w,mult
2 PLUS,MINUS, (NISO,SUB)
2 PLUS,MINUS
dnppwli
dppnwl
N+P-Well
N+P-Well iso-
lated
P+N-Well
NISO-Psub
N-Well-Psub
P dnppw
dnppwi
dppnw
dnipsub
dnwepsub
l,w,mult
l,w,mult
l,w,mult
l,w,mult
l,w,mult
2
2
2
2
2
PLUS,MINUS
PLUS,MINUS, (NISO,SUB)
PLUS,MINUS
PLUS,MINUS
PLUS,MINUS
out of nmos3v3rvt
out of pmos3v3rvt
out of pmos3v3rvt
dnipsub
dnwepsub

Diode parameters input range

Device Name l [µm] l [µm] w [µm] w [µm] mult mult
min max min max min max
N+P-Well dnppwl 0.32 300 0.32 300 1 –
N+P-Well isolated dnppwli 0.32 300 0.32 300 1 –
P+N-Well dppnwl 0.32 300 0.32 300 1 –
N+P-Well dnppw 0.32 300 0.32 300 1 –
N+P-Well isolated dnppwi 0.32 300 0.32 300 1 –
P+N-Well dppnw 0.32 300 0.32 300 1 –
NISO-Psub dnipsub 0.32 – 0.32 – 1 –
N-Well-Psub dnwepsub 0.32 – 0.32 – 1 –
Note: The diodes dnipsub and dnwepsub are only for simulation purpose. A device layout will not
be defined, and by that it will not be included in LVS.
Note: Diodes which were not explicit mentioned as isolated will not work in LVS when placed over
the layer NISO.
5.1.4. MOS Capacitors
The MOS capacitor device naming follows this rule:
acapbc (e.g. ncap1v2rvt)
RY
a MOS capacitor type n
p
ncap
pcap
N A
b
c
Device voltage
Device characteristic
1v2
3v3
lvt
1.2 V
3.3 V
low Vt
M I
L I rvt
hvt
regular Vt
high Vt
E
The naming and usage for the MOS capacitor parameters are given in the following table:
Display name
Model name
Capacitance
Width
Length
PR MOS capacitor parameters
Description
Simulator model name
Approx. calculated capacitance
MOS capacitor channel width
MOS capacitor channel length
Model
•
•
•
LVS
•
•
PyCell
•
•
Multiplier Number of parallel MOS devices • •
Bulk terminal Programmable Bulk connection •
Parameters Paramter display choice
Gate contact Gate contact choice •
Gate contact width Gate contac width •
Gate contact extra space Extra space for gate contact relative •
to initial placement
Gate contact coverage Gate contact coverage control % •
Gate contact alignment Gate contact alignment control •

MOS capacitor parameters (continued)

Gate contact metal stack Gate contact metal stack, up to •
METAL4
Source/Drain connection Source/Drain connection •
Source/Drain strap width Source/Drain connection strap •
width
Source/Drain strap extra space Extra space for source/drain strap •
relative to initial placement
Source/Drain contact coverage Controls source/drain contact cover- •
age in %
Source/Drain contact align- Controls source/drain contact align- •
ment ment
Source/Drain metal stack Source/Drain metal stack, up to •
METAL4
Source/Drain contact columns Source contact columns, 1 or 2 con- •
tacts
Bulk contact Bulk contact or ring •
Bulk contact space Absolute space between device and •
contact
Source juction area Source juction area •
Drain junction area Drain junction area •
Source STI edge
Drain STI edge
Source STI edge perimeter
Drain STI edge perimeter
•
•
RY
A
In the following two tables the MOS capacitors supported by the LF15A PDK are described, along
with their models parameters and their respective input ranges.
Device
M
[V]
Capacitor parameters
Voltage Name Parameter
IN Terminal
# names
MOSCAP-N
MOSCAP-N
MOSCAP-N
L I 1.8
3.3
5.0
ncap1v8hvt l,wf,mult,(cap)
ncap3v3rvt l,wf,mult,(cap)
ncap5v0rvt l,wf,mult,(cap)
2,(3) PLUS,MINUS,(B)
E
MOSCAP-P 3.3 pcap3v3rvt l,wf,mult,(cap) 2,(3) PLUS,MINUS,(B)
Device
MOSCAP-N
MOSCAP-N PR Capacitor parameters input range
Name
ncap1v8hvt
ncap3v3rvt
l [µm] l [µm] w [µm] w [µm]
min max min
like nmos1v8lvt
like nmos3v3rvt
max
mult
min
1
1
mult
max
–
–
MOSCAP-N ncap5v0rvt like nmos5v0rvt 1 –
MOSCAP-P pcap3v3rvt like pmos3v3rvt 1 –
MOSCAP models are taken from the respective MOSFET models.

Capacitor characteristics
Device Name Module Area Cap. Remark
[fF/µm2 ]
MOS Cap 1.8V NMOS ncap1v8hvt any core 9.4 @ −1.8 V, drop 25% at −1.1 V
MOS Cap 3.3V NMOS ncap3v3rvt MOS3 or 4.8 @ −3.3 V, drop 25% at −1.0 V
MOS35
MOS Cap 5.0V NMOS ncap5v0rvt MOS5 or 2.0 @ −5.0 V, drop 25% at −1.2 V
MOS35
MOS Cap 3.3V PMOS pcap3v3rvt MOS3 or 4.9 @ 3.3 V, drop 25% at 1.0 V
MOS35
For the MOS Cap devices the capacity is measured in accumulation. Additionally the value at which
the capacity falls to 75% is given.
Note: The MOSCAPs’ capacitance value in schematic view is an approximated value calculated by
callback at the devices voltage in inversion, since it will change with changing voltage.
5.1.5. Capacitors
The capacitor naming follows this rule: ca (e.g. cmims)
a capacitor type mims single MIM capacitor
RY
A
The naming and usage for the capacitor parameters are given in the following table:
Display name
Model name
Description
Simulator model name
I N
MIM capacitor parameters
Model
•
LVS PyCell
M
Calculated parameter
Capacitance
Width
Length
L I Capacitance value
Capacitor width
Capacitor length
•
•
•
•
•
E
Multiplier Number of parallel cap. devices • •
Capacitor area Capacitor area
R
Capacitor perimeter
Plate capacitance (F/µm2 )
P
Tight top contacts
Bottom plate connection
Capacitor perimeter
Capacitor area capacitance
Top plate contact style
Bottom plate contact style
In the following table the capacitors supported by the LF15A PDK are described, along with their
•
•
models parameters and their respective input ranges.
MIM capacitor parameters

Device Name & Parameter Terminal
Model name # names
Single MIM cmims w,l,mult,(c) 2 T,B
MIM capacitor parameters input range

Model name l [µm] l [µm] w [µm] w [µm] mult mult Ca [fF µm−2 ]
min max min max min max
cmims 5.0 70 5.0 70 1 – –

Capacitor characteristics
Device Name Module Area Cap. Remark
[fF/µm2 ]
MIM cmims MIM 0.98
Note: The MOSCAPs’ capacitance value in schematic view is an approximated value calculated by
callback at the devices voltage in inversion, since it will change with changing voltage.
Note: Please connect the lower MIM pin (B) through METAL_F, then you can connect it to any
metalization level. The pin B is on the metal layer below METAL_F, for 6 metal option it is the
METAL5. The MIM layer lies between these two metal layers.
5.1.6. Resistor
The resistor naming follows this rule: a[b]c[d] (e.g. rnpolyh)
a Device indicator r resistor

b Doping n n doped
p p doped
c Layer met METAL
poly
well
diff
POLY
WELL
DIFF
RY
A
d Sheet resistance indicator [l,m,h,s] for poly resistors, low, medium, high, salicided
[1-7,f] for metal resistors, METAL1. . . METAL7, METALF
I N
The naming and usage for the resistor parameters are given in the following table:
M
Resistor parameters
I
Model name Simulator model name •
Calculated parameter
Resistance
E
Effective resistanceL Single segment resistance value
Combined segments resistance value
•
R
Length Resistor segment length • •
Width Resistor segment width • • •
Multiplier
Netlister
Rsh (W/2)
P
Number of segments
Segment wiring
Matching
Number of parallel resistor devices
Netlister to be used, see note below
Resistor sheet resistance
Number of parallel/series segments
Parallel or series segment wiring
Matching style for two resistor devices
•
•
•
•
•
Segment extra space Extra space between resistor segments •
Metal stack Contact metal stack, up to METAL4 •
Metal top offset +/- Metal offset top contact •
Metal bottom offset +/- Metal offset bottom contact •
Minimum head with Controls the minimum of the resistance •
head

Resistor parameters (continued)

Head contact length Controls the resistance contact length •
RES left end Resistor left end style or dummy •
RES right end Resistor right end style or dummy •
Underlying well Controls the underlying well •
In the following two tables the resistors supported by the LF15A PDK are described, along with their
models parameters and their respective input ranges.
Resistor parameters
Device Name Parameter Terminal
# names
N+poly salicide rnpolys l,w,mult,(res) 2 PLUS,MINUS,(B)
P+poly salicide rppolys l,w,mult,(res) 2 PLUS,MINUS,(B)
P+poly low rppolyl l,w,mult,(res) 2 PLUS,MINUS,(B)
P+poly high rppolyh l,w,mult,(res) 2 PLUS,MINUS,(B)
LTC Poly rnpolylt l,w,mult,(res) 2 PLUS,MINUS,(B)
NWELL rndiff l,w,mult,(res) 2 PLUS,MINUS,(B)
NWELL + STI rnwell l,w,mult,(res) 2 PLUS,MINUS,(B)
Metal 1 rmet1 l,w,mult,(res) 2 PLUS,MINUS,(B)
Metal 2 rmet2 l,w,mult,(res) 2 PLUS,MINUS,(B)
Metal 3
Metal 4
Metal 5
rmet3
rmet4
rmet5
l,w,mult,(res)
l,w,mult,(res)
l,w,mult,(res) Y
2 PLUS,MINUS,(B)
R
2 PLUS,MINUS,(B)
2 PLUS,MINUS,(B)
Metal Final rmetf
N
l,w,mult,(res)
A
2 PLUS,MINUS,(B)
I
Resistor parameters input range
Device Name l [µm] l [µm] l [µm] w [µm] w [µm] mult mult
min relaxed min max min max min max
N+poly salicide
P+poly salicide
P+poly low
P+poly high
L I
rnpolys
rppolys
rppolyl
rppolyh
10
10
5
5
5
5
2
2
M –
–
–
–
1
1
1
1
–
–
–
–
1
1
1
1
–
–
–
–
LTC Poly
NWELL
NWELL + STI
R E rnpolylt
rndiff
rnwell
5
50
50
2
5
5
–
–
–
1
5
5
–
–
–
1
1
1
–
–
–
Metal 1
Metal 2
Metal 3
Metal 4
Metal 5
Metal Final
P rmet1
rmet2
rmet3
rmet4
rmet5
rmetf
5
5
5
5
5
5
0.3
0.3
0.3
0.3
0.3
0.6
–
–
–
–
–
–
0.24
0.24
0.24
0.24
0.24
0.58
40
40
40
40
40
40
1
1
1
1
1
1
–
–
–
–
–
–
Note: The Length limit parameter with options characterized (default) and relaxed. By default,
the length is limited to values accurately covered by the model. In ( relaxed) mode it is possible to
use smaller lengths (see table above). Take into account, that the model is not characterized for the
smaller lengths. The deviation may vary or out of the resistor model’s corners.

5.2. Primitive Library Modeling
5.2.1. Model Usage
Temperature Range
Generally the temperature range considered for modeling is −40 °C < T < 125 °C.
Spectre
The Spectre models have been tested with Spectre 12.11.048.
The model file for Spectre cmos150.scs contains all required model sections and corners, see below.
The Cadence ADE model setup will be done automatically if the provided $LF15A_HOME/tools/setup/.cdsinit
file is used, for details see 4.4. The core models are located in separate files, included in cmos150.scs.
For convenience, if no automatic model setup is used, an include file cmos150_include.scs is pro-
vided and for corner simulations with ADE XL the file cmos150_corners.sdb is available in the
$LF15A_HOME/analog/models/spectre directory.
HSpice
RY
The HSpice models have been tested with HSpice 2013.12-sp1.
N A
I
The model file for HSpice cmos150.lib contains all required model sections, see below. The Synopsys
SAE model setup will be done automatically. The core models are located in separate files, included in
M
cmos150.lib. In HSpice SAE the design variables for Monte Carlo mismatch and for process Monte
L I
Carlo have to be defined to 1 to perform the appropriate Monte Carlo variations. If no Monte Carlo
simulation shall be applied these variables have to be set to 0. Also the option MACMOD equals 1 has
to be set which is required for HSpice MOS transistor subcircuits.
HSpice variable
R E Mismatch
Monte Carlo
Process
P
__1v8hvt_mis__ 1 0
__1v8hvt_pmc__ 0 1
__1v8lvt_mis__ 1 0
__1v8lvt_pmc__ 0 1
__1v8zvt_mis__ 1 0
__1v8zvt_pmc__ 0 1
__3v3rvt_mis__ 1 0
__3v3rvt_pmc__ 0 1
__5v0rvt_mis__ 1 0
__5v0rvt_pmc__ 0 1
__res_mis__ 1 0
__res_pmc__ 0 1
__bjt_pmc__ 0 1
The simulation usage and model corners are shown in the following tables.

Device Simulation usage

1
Corners f Noise Monte Carlo Mismatch Monte Carlo Process
MOS Transistors • • •
MOS Capacitors • • •
Bipolar • •
Diodes
Resistors • • •
MIM Capacitor •
Device Model corners

typical slow n, slow p fast n, fast p fast n, slow p slow n, fast p
MOS low leak 1v8hvt_tt 1v8hvt_ss 1v8hvt_ff 1v8hvt_fs 1v8hvt_sf
MOS standard 1v8lvt_tt 1v8lvt_ss 1v8lvt_ff 1v8lvt_fs 1v8lvt_sf
MOS native 1v8zvt_tt 1v8zvt_ss 1v8zvt_ff
MOS 3.3V 3v3rvt_tt 3v3rvt_ss 3v3rvt_ff 3v3rvt_fs 3v3rvt_sf
MOS 5.0V 5v0rvt_tt 5v0rvt_ss 5v0rvt_ff 5v0rvt_fs 5v0rvt_sf
MOS Capacitors included in the related MOS corner
typical fast slow
Bipolar bjt_tt bjt_ff bjt_ss
Diodes dio_t
typical minimum maximum
Resistors
MIM Capacitor
res_typ
mim_typ
res_min
mim_min
res_max
mim_max
RY
A
PMOS typical
corner
f
I N Monte Carlo Mismatch

Monte Carlo Process
L I
t
s M
R E s t f
NMOS

P Figure 5.1.: Overview of model system
Basic model file structure cmos150.*
# mos monte carlo mismatch and process variation

<mos_type>_mis
parameter
mismatch v a r i a t i o n
<mos_type>_proc
process variation
# mos corner
<mos_type>_tt
parameter

−
→ <mos_type>_mis # include monte carlo mismatch variation
−
→ <mos_type>_proc # include monte carlo process variation
−
→ cmos150_mos_<mos_type >.∗ # include core model f i l e
<mos_type>_<c o r n e r >
parameter
−
→ <mos_type>_mis # include monte carlo mismatch variation
−
→ cmos150_mos_<mos_type >.∗ # include core model f i l e
# r e s i s t o r monte carlo mismatch and process parameter

res_mis
parameter
res_proc
process variation
# r e s i s t o r corner
res_typ
parameter
−
→ res_mis # include monte carlo mismatch variation
−
→ res_proc # include monte carlo process variation
−
→ cmos150_res . ∗
res_<c o r n e r >
# include core model f i l e
RY
A
parameter
−→ res_mis # include monte carlo mismatch variation
−→ cmos150_res . ∗
N
# include core model f i l e
# mimcap monte carlo mismatch and process parameter

I
M
mim_mis
parameter
L I
E
mim_proc
process variation
# mimcap corner
mim_typ
−
parameter
→ mim_mis
−
→ mim_proc
PR # include monte carlo mismatch variation
# include monte carlo process variation
−
→ cmos150_mim . ∗ # include core model f i l e
mim_<c o r n e r >
parameter
−
→ mim_mis # include monte carlo mismatch variation
−
→ cmos150_mim . ∗ # include core model f i l e
# bipolar corner
bjt_<c o r n e r >
parameter
−
→ cmos150_bjt . ∗ # include core model f i l e

# diode corner
dio_<c o r n e r >
parameter
−
→ cmos150_dio . ∗ # include core model f i l e

5.3. HV Library
The section describes LFoundry’s LF15A HV library - cmos150hv, device primitives and models.
LFoundry’s HV library includes a variety of LDMOS transistors.
5.3.1. LDMOS Transistor
amosldbv_c (e.g. nmosld8v_3)
a Transistor type n nmosld

p pmosld
b
c
Voltage level
Additional items
8
40
3
VDS = 8 V
VDS = 40 V
symbol without Sub contact
RY
A
4 symbol with Sub contact
N
The following two tables describe the parameters available for schematic entry and their respective
input range.
M I
LDMOS transistor parameters
I
Device VGS VDS Parameter Terminal Model
[V] [V] # names name
pmosld8v_3
pmosld40v_3
nmosld8v_3
EL 3.3 8.0 wf,mx,my

3.3 40.0 wf,mx
3.3 8.0 wf,mx,my
3 D,G,S
3 D,G,S
3 D,G,S
pmosld8v_3
pmosld40v_3
nmosld8v_3
nmosld40v_3
Device
pmosld8v_3
PR 3.3 40.0 wf,mx
LDMOS transistor parameters input range

wf
min [µm] max [µm] [µm]
5.0 80.0
l*
0.5
3 D,G,S
mx
min max
1 100
nmosld40v_3
1
my
min max
100
pmosld40v_3 5.0 80.0 1.80 1 100 - -
nmosld8v_3 5.0 80.0 0.4 1 100 1 100
nmosld40v_3 5.0 80.0 2.55 1 100 - -
Note: l* is actual poly length but not a gate length!
Note: All LDMOS devices have fixed nf=2. The total W is calculated like wf*nf
Note: The LD MOSFET devices LVS extraction is not supported by Hercules, Please use Calibre-LVS
instead under the Synopsys environment.

5.4. HV Library Modeling
5.4.1. Model Usage
This section provides an overview about HV models, their usage and the model file structure. The HV
model file for Spectre cmos150hv.scs contains all required model sections, see below. The Cadence
ADE model setup is integrated in the library cmos150hv and will be executed automatically.
Note: Hspice model is not avaliable for the current release.
Device Model corners

typical slow n, slow p fast n, fast p fast n, slow p slow n, fast p
LDMOS 8 V tt_mosld8v
LDMOS 40 V tt_mosld40v
Basic model file structure cmos150hv.*
# LDMOS corner
<c o r n e r >_<m o s l d _ v o l t a g e _ c l a s s >

parameter
cmos150hv_mosld . ∗ # include core model f i l e
RY
5.4.2. LDMOS Transistor Model
N A
Device Vth
M
Idsat/WI
LDMOS transistor characteristics
RonW BVdss VDS VGS
pmosld8v_3
L I Vd = 0.1 V
[V]
0.630
µA
@Vd
[ /µm] @ [V]
227 @ 5, 271 @ 8
[W mm]
11.3
[V]
25.0
[V]
8.0
[V]
3.3
pmosld40v_3∗
nmosld8v_3
nmosld40v_3
R E 0.718
0.560
0.540
180 @ 40
497 @ 5, 568 @ 8
398 @ 40
32.0
3.5
11.0
50.0
23.0
50.0
40.0
8.0
40.0
3.3
3.3
3.3
P
Note: Vth calculation by gmmax −
Please refer to figures 5.2, 5.3, 5.4, 5.5.

Vd
2 ..

Figure 5.2.: nmosld8v_3 output characteristics
RY
N A
M I
L I
R E
P
Figure 5.3.: nmosld40v_3 output characteristics

RY
N A
M I
L I
R E Figure 5.4.: pmosld8v_3 output characteristics

RY
N A
M I
L I
R E Figure 5.5.: pmosld40v_3 output characteristics

5.5. Digital Libraries
The library naming follows this rule: lf15adabs (e.g. lf15adhvt9s)
a Transistor characteristic ll 1.8 V low leak

hs 1.8 V standard
b Cell height 9 9 tracks
For detailed information please refer to the documentation within the PDK. It is HTML based, zipped,
and the archives can be found in $LF15A_HOME/digital/<library>/databook_<library>.tgz.
5.5.1. Standard Cell Overview
Naming
Name Description
DFCPS Pos. edge D-Flip-Flop with active low reset, active low set, active high scan
DFCP Pos. edge D-Flip-Flop with active low reset, active low set
DFCS Pos. edge D-Flip-Flop with active low reset, active high scan
DFC Pos. edge D-Flip-Flop with active low reset
Y
DFNC Neg. edge D-Flip-Flop with active low reset
DFPS Pos. edge D-Flip-Flop with active low set, active high scan
DFP
DFS
DF
Pos. edge D-Flip-Flop with active low set
Pos. edge D-Flip-Flop with active high scan
Pos. edge D-Flip-Flop
A R
N
LHCP High enable Latch with active low reset, active low set
I
LHC High enable Latch with active low reset
LHP High enable Latch with active low set
M
LH High enable Latch
I
LNCP Low enable Latch with active low reset, active low set
LNC Low enable Latch with active low reset
LNP
LN
AOI2I1
EL Low enable Latch with active low set

Low enable Latch
AOI21 with A1, A2 inverted
AOI2I2
NAND2I
NAND3I
NAND4I
NOR2I
NOR3I
PR AOI22 with A1, A2 inverted
NAND2 with A1 inverted
NOR2 with A1 inverted
NOR3 with A1 inverted
NOR4I NOR4 with A1 inverted
CLKGATE Clock gating (pos. edge triggered with NAND logic at output)
CLKGATEN Clock gating (neg. edge triggered with NOR logic at output)
CLKGATETST Clock gating with scan (pos. edge triggered with NAND logic at output)
The following tables list the available digital standard cells.
Naming of the cells is <function><variant>_X<driver strength>. For example an inverter with x4

driver strength would be INV_X4, and a four input OR with single driver strength would be OR4_X1.

Buffer / Inverter
Function Variant x0.5 x1 x2 x3 x4 x6 x8 x12 x16 x20 sum
INV (inverter) – • • • • • • • • • 9
BUF (buffer) – • • • • • • • • • 9
CLKINV (clock inverter) – • • • • • • • • • 9
CLKBUF (clock buffer) – • • • • • • • • • 9
Boolean combination
Function Variant x0.5 x1 x2 x3 x4 x6 x8 sum
AND 2 • • • • • • • 7
AND 3, 4 • • • • • • 12
AO 21, 22, 211, 221, 222, 311, 321, 322, 323, 333 • • • • 40
AOI 21, 22, 211, 221, 222, 31, 311, 32, 321, 322, • • • • 52
323, 33, 333
MUX 2 • • • • • • 6
NAND 2, 3, 4 • • • • • • 18
NOR 2, 3, 4 • • • • • • 18
OA 21, 22, 211, 221, 222, 311, 321, 322, 323, 333 • • • • 40
OAI 21, 22, 211, 221, 222, 31, 311, 32, 321, 322, • • • • 52
323, 33, 333
OR 2, 3, 4 • • • • • • 18
XOR 2 • • • • 4
XNOR
AOI2I1
AOI2I2
2
–
–
• •
•
•
•
•
•
RY •
•
•
4
3
3
A
NAND2I – • • • 3
NAND3I – • • • 3
NAND4I
NOR2I
NOR3I
–
–
–
I N •
•
•
•
•
•
•
•
•
3
3
3
M
NOR4I – • • • 3
Function
HA (half adder)
L I Variant
–
Arithmetic
x0.5 x1
•
x2
•
x3 x4 sum
2
FA (full adder)
Function
R E
Variant
–
Flip-flop
• •
x1
•
x2 x4
3
sum
DF
DFS
DFP
DFPS
DFC
–
–
–
–
–
P •
•
•
•
•
•
•
•
•
•
•
•
•
•
•
3
3
3
3
3
DFNC – • • • 3
DFCS – • • • 3
DFCP – • • • 3
DFCPS – • • • 3

Latch
Function Variant x1 x2 x4 sum
LN – • • • 3
LNP – • • • 3
LNC – • • • 3
LNCP – • • • 3
LH – • • • 3
LHP – • • • 3
LHC – • • • 3
LHCP – • • • 3
Clock gate
Function Variant x1 sum
CLKGATE – • 1
CLKGATEN – • 1
CLKGATETST – • 1
Physical
Function Variant x1 x2 x4 x8 x16 x32 x64 sum
ANTENNA (clamp diode) – • 1
FILLCELL – • • • • • • • 7
DCAP – • • • 3
LOGIC0 – • 1
LOGIC1
Function Variant
–
Delay
•
RY x10
1
sum
Del (delay cell) 0.1ns, 1ns, 2ns, 5ns
Tri-state
N A • 4
Function
TBUF (tri-state buffer)
Variant
–
M I x1
•
x2
•
sum
2
I
Note: For the digital library the inherited connection property names are dig_vdd for power and
dig_vss for ground. These may be assigned to other signal names in your design with an instance
L
property (type netSet), for example [@dig_vdd:%:<myDigVdd>] and [@dig_vss:%:<myDigVss>] with
results like in figure 5.6.
E
PR
Figure 5.6.: Example for instance property in schematic
5.5.2. Synopsys Milkyway Library
The Milkyway data format is a unified design storage for usage with Synopsys tools. The digital
standard cell library including the Synopsys database (DB) files and the Milkyway tech file can be
found in $LF15A_HOME/digital/<library>/milkyway. For parasitic extraction with StarRC ™ there
are available the TLUPlus (TLU+) models and ITF (Interconnect Technology File) for corners best,
worst and typical, together with the relevant mapping file. The extraction setup files are located in
$LF15A_HOME/pv/$LF15A_OPTION/starrc/.

Note: The Milkyway library is based on LEF data format and only includes the layout extracts
needed for Place&Route.
5.6. SealRing
The SealRing is located under cmos150 technology library and under Sealring category. The seal ring
structure is used to absorb chip sawing mechanical stress and as barrier to contamination introduced
during sawing process.
The LF15A seal ring in the library cmos150 consists of 4 cells, a corner cell (corner) including an
outer stress relief cell (outer_corner), cells to build the actual ring (sealside and sealside_fill)
and a stress relief cell (stress_relief). An overview is given in fig. 5.7. A cross section of a sealside
cell is shown in fig. 5.8; there VIAs and CONTs with crosshatch pattern are bars instead of single cuts.
• The outer_corner cell is a triangle at the corner used as stress relief cell to prevent damage
due to mechanical stress by sawing process, as this is typically greater at the chip corners.
• The inner stress_relief cell is a trapezoid used to reduce mechanical and thermal stress
during packaging of the chip. LFoundry recommends to use this cell for chips with an edge
length greater than 2000.0 µm or a chip area of over 4.00 mm2 .
RY
• The seal ring cell (sealside) is used to build the ring and the filler cell (sealside_fill) is
A
used to prevent minimum contact and via spacing design rule violations at the intersection to
the corner cell.
I N
• The chip corners are reserved for the placement of the corner cell (95.0 µm edge length) and if
required also for the stress_relief cell (177.5 µm edge length) and have to be empty.
I M
• The distance between the assembly region (outer pad edge) and the inner seal ring edge has to
be 10 µm.
L
R E
P

sealside cell (arrayed)
sealside_fill cell
stress_relief cell
corner cell
10.0 µm
RY
10.0 µm
A
95.0 µm
177.5 µm
I N
Figure 5.7.: Seal ring elements
L I M
METAL_F
R E
P
VIA_F
METAL5
VIA4
METAL4
Chip area
Scribeline
VIA3
METAL3
VIA2
METAL2
VIA1
METAL1
CONT
DIFF
PWELL
Figure 5.8.: Cross section of seal ring

5.7. I/O Libraries
LFoundry offers a general purpose input/output (GPIO) libraries for each voltage domain and metal-
ization flavour supporting all needs of analog-mixed signal products.
Features
• Voltage domains: 1.8 V, 3.3 V, 5.0 V
• Input, output, bi-directional and tri-state
• Pull up and pull down
• Output with open drain / open source; programmable drive strengths (soft by logic input or hard
by wiring); multiple slew rate options (soft by logic input or hard by wiring)
• Level shifter input, Schmitt trigger input
• The ESD architecture will cater for the special needs of mixed-signal products (e.g. separate
Y
analog and digital power supplies)
(including wiring and RF pad)
A R
• For RF I/O the parasitic capacitance of the pad and ESD structures is expected to be 0.2 pF
supply domain.
I N
Note: The ESD structures of the analog INPUTS should NOT connect to any digital/interface power
I
Library Naming and Needed Process Modules
L M
E
The library naming follows this rule: cmos150aIObLib_c (e.g. cmos150pIO1v8hvt)
R
a Layout type p Pad limited
c Core limited
b
c
P
Voltage domain
Transistor characteristic
1v8
3v3
5v0
ll
hs
1.8 V
3.3 V
5.0 V
low leak
standard
In order to have the different libraries available, following process modules have to be selected.
Needed process modules

Library name Process modules
cmos150pIO1v8hvt MOS18L
cmos150pIO3v3hvt MOS18L, MOS3
cmos150pIO5v0hvt MOS18L, MOS5

Overview of Available Cells
Overview of available cells

Cell Function Voltage Max. Current
Domain (see 6.3.4)
1v8_p_ana_io_ll Analog I/O 1.8 V 1.8 mA
1v8_p_anarf_io_ll Analog I/O for RF 1.8 V 4.8 mA
1v8_p_dig_io_. . . _ll Digital I/O 1.8 V
1v8_p_dig_in_ll Digital input 1.8 V
3v3_p_dig_in_ll Digital input 3.3 V
1v8_p_dig_out_. . . _ll Digital output 1.8 V
3v3_p_dig_out_. . . _ll Digital output 3.3 V
1v8_p_vss_core_ac_ll VSS (core) from pad 1.8 V 30 mA
1v8_p_vss_core_gt_ll VSS (core) from pad 1.8 V 30 mA
1v8_p_vss_io_ac_ll VSSA/VSSD from pad 1.8 V 24 mA
3v3_p_vss_io_ac_ll
5v0_p_vss_io_gt_ll
1v8_p_vdd_core_ac_ll
VSSA/VSSD from pad
VSSA/VSSD from pad
VDD (core) from pad
RY
3.3 V
5.0 V
1.8 V
24 mA
24 mA
30 mA
A
1v8_p_vdd_core_gt_ll VDD (core) from pad 1.8 V 30 mA
1v8_p_vdd_io_ac_ll VDDA/VDDD from 1.8 V 24 mA
3v3_p_vdd_io_ac_ll
pad
I
pad
N
VDDA/VDDD from 3.3 V 24 mA
5v0_p_vdd_io_gt_ll
L I
[1v8|3v3|5v0]_p_breaker_io_ll
M
VDDA/VDDD from
pad
Separating any two
voltage domains
5.0 V
any
24 mA
E
[1v8|3v3|5v0]_p_spacer_. . . _[65u|80u]_ll
[1v8|3v3|5v0]_p_corner_[|65u|80u]_ll
iolib_plate. . .
R
Bus spacers
Bus corners
Pad instances
any
any
any
P
Note: For convenience, there are also cells available which contain an I/O cell and a pad. For example,
cell 1v8_p_vss_core_ac_65u_ll contains 1v8_p_vss_core_ac_ll and iolib_plate65.
Note: Generally the . . . _ac_. . . cells have better performance than the . . . _gt_. . . cells. If in doubt
use the . . . _ac_. . . cells.
Migration of Cells from PDK Prior to V2.0.0
Cell replacement table

Old cell (PDK < V2.0.0) New cell (PDK V2.0.0)
iolib_pad_RF_adapter [1v8|3v3|5v0]_p_adapterrf_[65u|80u]_ll
iolib_pad_1v_io 1v8_p_ana_io_[|65u|80u]_ll

Cell replacement table (continued)

Old cell (PDK < V2.0.0) New cell (PDK V2.0.0)
iolib_pad_RF_io [1v8|3v3|5v0]_p_anarf_io_[|65u|80u]_ll
iolib_pad_18v_dig_io_. . . 1v8_p_dig_io_. . . _[|65u|80u]_ll
iolib_pad_18v_dig_in 1v8_p_dig_in_[|65u|80u]_ll
iolib_pad_3v_dig_in 3v3_p_dig_in_[|65u|80u]_ll
iolib_pad_18v_dig_out_. . . 1v8_p_dig_out_. . . _[|65u|80u]_ll
iolib_pad_3v_dig_out_. . . 3v3_p_dig_out_. . . _[|65u|80u]_ll
iolib_pad_1v_vss 1v8_p_vss_core_gt_[|65u|80u]_ll
iolib_pad_1v_vss_ac 1v8_p_vss_core_ac_[|65u|80u]_ll
iolib_pad_1v_vssd_ac 1v8_p_vss_io_ac_[|65u|80u]_ll
iolib_pad_3v_vssd_ac 3v3_p_vss_io_ac_[|65u|80u]_ll
iolib_pad_5v_vssd_gt 5v0_p_vss_io_gt_[|65u|80u]_ll
iolib_pad_1v_vdd 1v8_p_vdd_core_gt_[|65u|80u]_ll
iolib_pad_1v_vdd_ac 1v8_p_vdd_core_ac_[|65u|80u]_ll
iolib_pad_1v_vddd_ac 1v8_p_vdd_io_ac_[|65u|80u]_ll
iolib_pad_3v_vddd_ac 3v3_p_vdd_io_ac_[|65u|80u]_ll
Y
iolib_pad_5v_vddd_gt 5v0_p_vdd_io_gt_[|65u|80u]_ll
iolib_pad_3v_breaker [1v8|3v3|5v0]_p_breaker_io_[|65u|80u]_ll
iolib_spacer_. . .
iolib_corner_. . .
iolib_plate. . .
[1v8|3v3|5v0]_p_spacer_. . . _[65u|80u]_ll
[1v8|3v3|5v0]_p_corner_[|65u|80u]_ll
A R
iolib_plate. . . (in library cmos150_ioLibPlate)
I N
For PDK V2.0.0 the I/O library was enhanced and restructured. Above table may help you in finding
replacement cells for your design.
I M
5.7.1. Pins, Settings and Characteristics for 1.8 V GPIO Cells
L
R E vss_core vdd_core
outen
vss_io vdd_io
P drvstr<2:0>
slewctl
odt_en
pull_ud
pullstr
pad
data_from_core
data_to_core
Figure 5.9.: 1.8 V GPIO terminal overview
Description of pins for 1.8 V GPIO (fig. 5.9)

Pin Pin Type Description
vdd_io Power Supplies 1.8 V power to pad, primary power for GPIO and
drivers

Description of pins for 1.8 V GPIO (fig. 5.9) (continued)

vdd_core Power Supplies 1.8 V core logic
vss_io Ground Substrate and GPIO return
vss_core Ground Core logic ground
outen Input 1.8 V Enables output, high assertion: 1=output enabled, 0=tri-state
driver
odt_en Input 1.8 V Enables on-die termination; high assertion: 1=enabled,
0=disabled; independent of outen and output driver function-
ality
pull_ud Input 1.8 V Determines if on-die termination is connected to power (pull
up) or ground (pull down); 1=pull up; 0=pull down
pullstr Input 1.8 V Determines strength of on-die termination; 1≈5 kW, 0≈50 kW
data_from_core Input 1.8 V Data coming into the GPIO from the core; used to drive the
pad; data_from_core=1, pad=1; data_from_core=0, pad=0;
requires outen to be asserted in order to function
data_to_core Output 1.8 V Receives the signal level at the bond pad and then converts it
to low voltage and sends it to the core; always active
drvstr<2:0> Input 1.8 V 3 bit control bus that sets the DC drive strength of the output
drivers; the details for this bus are in the following table
slewctl Input 1.8 V A 1 bit bus for setting slew rate, 0 is slow and 1 is fast; actual
Y
slew is dependent on drvstr settings and load at pad; this
control though gives the user some level of control over the
pad INOUT
Drive strength
Bond pad to outside world
settings nominal conditions for 1.8 V GPIO

A R
slew rate for a known load and particular drive strength
drvstr<2:0>
setting
000
Iout at Voh =1.4 V
(pull up current)
~3 mA
Iout at Vol =0.4 V
(pull down current)
~4 mA
I N
Comments
001
010
011
L I
~9 mA
~15 mA
~20 mA
~26 mA
~11 mA
~19 mA
~26 mA
~34 mA
M
E
100
101 ~32 mA ~42 mA
R
110 ~38 mA ~50 mA
111 ~44 mA ~58 mA
Input Receiver
P
Due to limitations in sizing of the output drivers, true 3 bit control is not achieved with the pull-up
drive current. Also affected is the fact that drive strength increments are not linear at every step.
Input receiver characteristics for 1.8 V GPIO

Vil Vih
at nominal ~0.5 V ~1.0 V
Slew rate options for 1.8 V GPIO

Slew Rates (cap load=20 pF) Average slew at drvstr(001-111) Slowest at drvstr(000)
0 ~5.5-1.9 ns ~11 ns
1 2-2.5 ns ~10 ns
Because of the very weak current of the lower drive strength setting and the nature of the design, the
lowest drive strength setting makes the slew rate unaffected by the slewctl signal. Please keep in

mind that when using the lowest drive strength setting, the selection of slewctl has little impact. It
is recommended to use slewctl=1 in this case.
vss_core vdd_core vss_io vdd_io

outen
drvstr<3:0>
drvstr33<3:0>
slewctl<1:0> pad
slewctl33<1:0>
odt_en
pull_ud
pullstr
data_from_core
data_to_core
Pin
Pin Type Description
RY
A
drivers
vdd_core
vss_io
Power
Ground
terface
I N
Supplies 1.8 V low voltage power for level shifters and core in-
Substrate and GPIO return

vss_core
outen
odt_en
L I
Ground
Input 1.8 V
Input 1.8 V
M
Not used, feedthrough for multi voltage power supply
Enables output, high assertion: 1=output enabled, 0=tri-state
driver
Enables on-die termination; high assertion: 1=enabled,
pull_ud
R E Input 1.8 V
ality
Determines if on-die termination is connected to power (pull
P
pullstr Input 1.8 V Determines strength of on-die termination; 1≈5 kW, 0≈50 kW
data_to_core Output 1.8 V Receives the signal level at the bond pad and then converts it
to low voltage and sends it to the core; always active
drvstr<3:0> Input 1.8 V 4 bit control bus that sets the DC drive strength of the output
drvstr33<3:0> Input 3.3 V Like drvstr<3:0> but with 3.3 V input level
slewctl<1:0> Input 1.8 V A 2 bit bus for setting slew rate, 00 is the slowest and 11 is
the fastest; actual slew is dependent on drvstr settings and
load at pad; this control though gives the user some level of
control over the slew rate for a known load and particular drive
strength


slewctl33<1:0> Input 3.3 V Like slewctl<1:0> but with 3.3 V input level
pad INOUT Bond pad to outside world
Drive strength settings nominal conditions for 3.3 V GPIO

drvstr<3:0> Iout at Voh =2.7 V Iout at Vol =0.4 V Comments
setting (pull up current) (pull down current)
0000 0 0 Also tri-state output; same as if outen=0
0001 ~5 mA ~1.7 mA
0010 ~10 mA ~3.4 mA
0011 ~15 mA ~5.0 mA
0100 ~20 mA ~12.2 mA
0101 ~25 mA ~13.9 mA
0110 ~30 mA ~15.6 mA
0111 ~35 mA ~17.3 mA
1000 ~35 mA ~24.5 mA PMOS drive is same as 0111 setting
1001 ~40 mA ~26.2 mA
1010 ~45 mA ~27.9 mA
1011 ~50 mA ~29.5 mA
Y
1111 ~50 mA ~41.7 mA
R
PMOS drive is same as 1011 setting
A
N
Input Receiver
M I
Input receiver characteristics for 3.3 V GPIO
Vil Vih
I
at nominal ~1.0 V ~1.78 V
Slew Rates
cap load=20 pF
EL Slew rate options for 3.3 V GPIO

Fastest at drvstr(1111)
1.9 ns
Slowest at drvstr(0001)
~11 ns
PR

drivers
vdd_core Power Supplies 1.8 V low voltage power for level shifters and core in-
terface
vss_io Ground Substrate and GPIO return
vss_core Ground Not used, feedthrough for multi voltage power supply
outen Input 1.8 V Enables output, high assertion: 1=output enabled, 0=tri-state
driver

vss_core vdd_core vss_io vdd_io

outen
drvstr<1:0>
inen pad
odt_en
pull_ud
pullstr
data_from_core
data_to_core

inen Input 1.8 V Enables input receiver: 1=input receiver active, 0=receiver dis-
abled; if disabled, default output for data_to_core is 0
odt_en Input 1.8 V Enables on-die termination; high assertion: 1=enabled,
ality
pull_ud
pullstr
Input 1.8 V
Input 1.8 V
RY
Determines if on-die termination is connected to power (pull
Determines strength of on-die termination; 1≈5.5 kW, 0≈70 kW
A
data_to_core
N
I
Output 1.8 V Receives the signal level at the bond pad and then converts it
to low voltage and sends it to the core; requires inen to be
drvstr<1:0>
pad
L I Input 1.8 V
INOUT
M
asserted, otherwise outputs 0 to core
2 bit control bus that sets the DC drive strength of the output
Bond pad to outside world
R E
When outen is asserted, the 5 V pad driver is active and functioning. With outen deasserted, the
output driver is in a high impedance state.
P
5.0 V GPIO is designed to operate at reasonable data rates under most conditions. The output
is capable of driving under worst case conditions (PVT: slow, 4.5 V, 110 °C) and maximum drive
strength, a 20 pF load at data rates up to 200 MHz.
The input receiver can exceed 200 MHz data rates.
Drive strength settings nominal conditions for 5.0 V GPIO (PVT: typical, 5.0 V, 27 °C)
drvstr<1:0> Ioh at Voh =4.0 V Iol at Vol =0.5 V Comments
00 16.2 mA 9 mA
01 ~24.3 mA ~13.6 mA
10 ~32.4 mA ~18.1 mA
11 ~75.6 mA ~45.3 mA

Drive strength settings hot/slow conditions for 5.0 V GPIO (PVT: slow, 4.5 V, 110 °C)
00 5.3 mA 5.1 mA
01 7.9 mA 7.7 mA
10 10.6 mA 10.3 mA
11 24.6 mA 25.6 mA
Drive strength settings cold/fast conditions for 5.0 V GPIO (PVT: fast, 5.5 V, −30 °C)
00 31.8 mA 13.9 mA
01 47.7 mA 20.9 mA
10 63.6 mA 27.8 mA
11 148.4 mA 69.6 mA
The input receiver is designed to be disabled by the use of inen. The reason is to minimize leakage
current through the receiver during operations where input levels to the pad will not meet the Vil and
Y
Vih levels sufficiently.
5.7.4. Cell Overview
A R
Analog Input/Output
I N
Analog input/output cells features
Cell
1v8_p_ana_io_ll
3v3_p_ana_io_ll
L I M Function
Analog I/O
Analog I/O
Analog I/O
Voltage
1.8 V
3.3 V
5.0 V
E
5v0_p_ana_io_ll
1v8_p_anarf_io_ll Analog I/O for RF 1.8 V
R

VDDA VDDA VDDA
A2 A1 A1
esd_dio_nw_3 esd_dio_nw_3 esd_dio_nw_3
Analog I/O Analog I/O

Rin
B2 B1 B1
esd_dio_pw_3 esd_dio_pw_3 esd_dio_pw_3
VSSA VSSA VSSA
Rin = 200 W (standard in PDK; not RF) Rin = 0 W (skip secondary ESD protection)
ESD junction capacitance
Cj [fF] Cj [fF]
Vio = 0 V Vio = 3.3 V
A1 + B1 452 446
A2 + B2 12 12
A1 + B1 (RF) 70
Figure 5.12.: Simplified circuit of analog input/output cell
Digital Input/Output
Digital input/output cells features and pins
RY
level shifter (1.8 V)
A
data_from_core
slewctl (hard)
slewctl (soft)
data_to_core
drvstr (hard)
drvstr (soft)
I N
pull_str
pull_ud
odt_en
outen
inen
Cell
1v8_p_dig_io_1_ll
1v8_p_dig_io_2_ll
3v3_p_dig_io_1_ll
L I ↔ 3.3 V
M •
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
3v3_p_dig_io_2_ll
3v3_p_dig_io_3_ll
3v3_p_dig_io_4_ll
R E ↔
↔
↔
3.3 V
3.3 V
3.3 V
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
P
5v0_p_dig_io_1_ll
Digital Input
↔ 5.0 V • • • • • • • •
Digital input cells features

Cell level shifter (1.8 V)
1v8_p_dig_in_ll
3v3_p_dig_in_ll ← 3.3 V

VDDD
*) Silicide block extension in drains of output transistors
esd_pmos_3
A1 Rdrain-SB*
I/O (3.3 V)
Rdrain-SB*
esd_nmos_3
VDDD
B1
A2
esd_dio_nw_3
VSSD
Rin = 200 W
input Rin
B2
esd_dio_pw_3
VSSD
ESD/driver junction capacitance
A1 + B1
Cj [fF] Cj [fF]
Vio = 0 V Vio = 3.3 V
2350 2340
RY
A
A2 + B2 12 12
N
Figure 5.13.: Simplified circuit of digital input/output cell
VDDD VDDD
M I
I
A2 A1
esd_dio_nw_3 esd_dio_nw_3
EL B2
Rin
B1
INPUT (3.3 V)
R
esd_dio_pw_3 esd_dio_pw_3
VSSD VSSD
P Rin = 200 W
ESD junction capacitance
Cj [fF] Cj [fF]
Vio = 0 V Vio = 3.3 V
A1 + B1 452 446
A2 + B2 12 12
Figure 5.14.: Simplified circuit of digital input cell

Digital Output
Digital output cells features and pins
level shifter (1.8 V)
data_from_core
slewctl (hard)
slewctl (soft)
drvstr (hard)
drvstr (soft)
outen
Cell
1v8_p_dig_out_1_ll • • • •
3v3_p_dig_out_1_ll → 3.3 V • • • •
3v3_p_dig_out_2_ll → 3.3 V • • • •
3v3_p_dig_out_3_ll → 3.3 V • • • •
VDDD
*) Silicide block extension in drains of output transistors
esd_pmos_3
Y
A1 Rdrain-SB*
R
OUTPUT (3.3 V)
Rdrain-SB*
esd_nmos_3
N A
B1
VSSD
M I
L I ESD/driver junction capacitance
Cj [fF] Cj [fF]
Vio = 0 V Vio = 3.3 V
R E A1 + B1 2350 2340
Figure 5.15.: Simplified circuit of digital output cell
Supply Cells
Cell
P Supply cells features
Function Voltage
1v8_p_vdd_core_ac_ll VDD (core) from pad 1.8 V
1v8_p_vdd_core_gt_ll VDD (core) from pad 1.8 V
1v8_p_vss_core_ac_ll VSS (core) from pad 1.8 V
1v8_p_vss_core_gt_ll VSS (core) from pad 1.8 V
1v8_p_vdd_io_ac_ll VDDA/VDDD from pad 1.8 V
1v8_p_vss_io_ac_ll VSSA/VSSD from pad 1.8 V
3v3_p_vdd_io_ac_ll VDDA/VDDD from pad 3.3 V
3v3_p_vss_io_ac_ll VSSA/VSSD from pad 3.3 V
5v0_p_vdd_io_gt_ll VDDA/VDDD from pad 5.0 V
5v0_p_vss_io_gt_ll VSSA/VSSD from pad 5.0 V

Other Cells
Other cells
Cell Function
[1v8|3v3|5v0]_p_breaker_io_ll Separating any two voltage domains
[1v8|3v3|5v0]_p_adapterrf_[65u|80u]_ll Connecting a RF I/O cell
iolib_plate65 Pad instance of 65 µm (opening size 58 µm)
iolib_plate80 Pad instance of 80 µm (opening size 73 µm)
iolib_plate65_RF RF Pad instance of 65 µm (opening size 58 µm)
iolib_plate80_RF RF Pad instance of 80 µm (opening size 73 µm)
[1v8|3v3|5v0]_p_spacer_. . . _[65u|80u]_ll Bus spacers of different widths (e.g. 9p92 =
b
9.92 µm)
D0
vss_iol vss_ior
D1
Figure 5.16.: Simplified circuit of [1v8|3v3|5v0]_p_breaker_io_ll cell
5.7.5. Power Domain
Overview
RY
N A
Digital and analog domain buses can be separated by breaker cells containing anti-parallel diodes if
required for noise isolation. An example overview using 1.8 V core supply and two separated 3.3 V
I
domains is shown in fig. 5.17. Note that it is preferable to keep a continuous ground bus where possible.
For different digital domains LFoundry recommends continuous ground buses without interruption by
anti-parallel diodes.
M
L I
Note: Between cells of different domains a spacer cell (e.g. 1v8_p_spacer_4p96_65u_ll) or breaker
cell (e.g. 1v8_p_breaker_io_65u_ll) has to be placed. Spacer respective breaker cells of different
R E
voltage domains are identical in layout. Please keep in mind that 1.8 V core domain and 1.8 V driver
domain also count as different domains.
to be used.
P
Note: For connection to RF I/O cells, the [1v8|3v3|5v0]_p_adapterrf_[65u|80u]_ll cells have
Note: For more information, there is a category EXAMPLES within the I/O library including notes and
examples.
Maximum Bus Length
Because metal buses can cause a significant IR drop in case of an ESD event, the effective VDDA/VSSA
bus length within the ESD current path must be limited for analog I/O cell with dual-diode protection.
The maximum permissible bus length depends on the number of stacked bus metal layers.
Following table shows the maximum permissible bus lengths for worst-case ESD stress, i.e. 200 V MM
for the 3 different bus configuration:

for output buffers

in digital I/O
for digital 1.8 V cells and digital
core and supply core auxiliary
for all I/O cells supply for analog core
ore_ to_core ore_to_core _to_c

ore
_to_c
ore
_to_c
ore
_to_c
ore
vdd_c vss_c vdd_io vss_io vdd_io vss_io
VDD vdd_core
ESD ESD
VSS vss_core
VSSD vss_io vss_io VSSA
ESD ESD ESD ESD
VDDD vdd_io vdd_io VDDA
vdd_core_ac vss_core_ac vdd_io_ac vss_io_ac breaker vdd_io_ac vss_io_ac
Figure 5.17.: ESD voltage domain coupling
Pad type
Maximum bus length to next VDDA / VSSA pad
Number of bus metals
1 (METAL_F) 2 (METAL_F, METAL5) 3 (METAL_F, METAL5, METAL4)
RY
A
Analog / 900 µm 1250 µm 1600 µm
Digital input
Analog RF
GPIO
I N
place VDDA / VSSA as close as possible
No limitation for bus length
M
The values above are based on the protection of an input gate within the analog I/O cell without
I
use of any secondary protection. If possible for normal analog operation, it is highly recommended to
L
apply the I/O cell with secondary protection circuit including 200 W decoupling resistor. Please refer
to fig. 5.18.
R E Analog-I/O
Core P Analog-I/O
1500 µm
Core
3000 µm
Vdd Vdd
Distance of analog I/O to next VDDA/VSSA must not exceed 1600 µm with 3 bus metal layer
(METAL_F, METAL5, METAL4)
Figure 5.18.: Examples for maximum bus length between analog-I/O pads

Further Remarks to ESD Protection
1. If junctions are directly connected to the pad, a thorough review of the analog circuit to be
protected is highly recommended. In particular single MOS transistor between two pads (e.g. I/O
and VSSA) are generally critical if exposed to ESD stress. Special precautions must be taken as
described in chapter ??.
2. No gates connected directly to the supplies

If gates are connected to the supplies they should be locally protected with secondary clamps:
a) Rpoly = 2 kW between supply and gate
b) GGNMOS (1.8 V/3.3 V/5.0 V according to the Gate/Supply; with drain extension) between
gate and GND: W=10 µm; L as specified for ESD in NMOS in the corresponding voltage
domain
3. Additional CDM Rbus rule

We should keep in mind that the maximum permissible Rbus resistance considers HBM and
MM stress events only. For CDM stress, in particular the aggressive Rbus rules for 2 kV HBM
could cause dangerous voltage drops. This effect however is highly IC (e.g. size, architecture) and
package dependent and therefore impossible to predict. If CDM is specified, it is recommended to
Y
limited the effective Rbus between the supply clamps to at maximum of approximately Rbus ≈1 W.
Moreover, for Digital and Analog I/Os a maximum Rbus not larger than the ones specified for
200 V MM regarding the supplies should be followed.
A R
4. Care must be exercised regarding the circuit to be protected in analog I/Os. In particular analog
N
I/Os configuration with low / zero I/O resistance and no secondary protection can be critical and
I
must be carefully reviewed.
L I M
R E
P

6. Process Specification
LF15A is a modular 0.15 µm RF CMOS process, offering up to 6 levels of Al plus thick metal (2 -
6 µm), optionally a MIM capacitor, a polyimide passivation and I/O voltages of 1.8 V, 3.3 V and 5.0 V.
6.1. Available Process Options
Core process modules

Module name Masks Description
MOS18L 19 Low leakage 1.8V MOS module with single poly, quad metal
MOS18S 19 Standard 1.8V MOS module with single poly, quad metal
MOS18SL 21 Standard and low leakage 1.8V MOS module with single poly, quad metal
The following add-on modules are actually available.
Add-on Process Modules
RY
Module name
MOS3
MOS5
Add. masks
6
5
Description
3.3V MOS module, additional gate oxide
N
5.0V MOS module, additional gate oxide
A
MOS35
MVGOX
HVGOX
10
1
1 I
3.3V and 5.0V MOS module, two additional gate oxides
3.3V gate oxide (not needed for 3.3V MOS options)
M
5.0V gate oxide (not needed for 5.0V MOS options)
M5
M6
MT
L I 2
4
2
5 metal layers
6 metal layers
Thick metal (2 - 6 µm)
MIM
NISO
LVLDN
R E 1
1
2
Metal insulator metal capacitor
N isolation for PWELL, add. NPN parasitic bipolar transistor
NMOSLD (8V), requires MVGOX
P
LVLDNI 2 Isolated NMOSLD (8V), requires MVGOX, NISO
LVLDP 2 PMOSLD (8V), requires MVGOX, NISO
HVLDN 2 NMOSLD (40V), requires MVGOX
HVLDNI 4 Isolated NMOSLD (40V), requires MVGOX, NISO
HVLDP 3 PMOSLD (40V), requires MVGOX, NISO
OTPNC1 1 OTP memory
6.2. Layer List
Mask layers
Layer Description
DIFF Define active area

Mask layers (continued)

Layer Description
POLY1 Used in PIP capacitor; future option
NISO Isolate PWELL, NPN bipolar transistor
NWELL Common well for PMOS
PWELL Common well for NMOS
P_MVT PMOS threshold adjust for 3.3V
N_MVT NMOS threshold adjust for 3.3V
P_CORE PMOS standard threshold adjust
N_CORE NMOS standard threshold adjust
P_LOWL PMOS low leak threshold adjust
N_LOWL NMOS low leak threshold adjust
HNWELL Future option
HPWELL Future option
DRIFT_N Future option
DRIFT_P Future option
HNC Future option
HPC Future option
MG Future option
CAP Future option
MVT Define 3.3V gate oxide area
Y
NO_LVT Define NOT 1.8V gate oxide area
N_DUALGTE N poly doping
HVT
FLGT
POLY2
Define 16V gate oxid area, future option
Floating gate poly, inverse layer, future option
Transistor gates, resistors
A R
N
POLY2E Future option
I
ESDN Future option
LDD Future option
M
HLDD Future option
I
P_MIN_LVT PMOS extension 1.8V
N_MIN_LVT NMOS extension 1.8V
P_MIN_MVT
N_MIN_MVT
P_MIN_HVT
EL PMOS extension 3.3V

NMOS extension 3.3V
PMOS extension 5.0V
N_MIN_HVT
P_MIN_LD
N_MIN_LD
P_PLUS_LD
N_PLUS_LD
P_PLUS
PR NMOS extension 5.0V
LDMOS
LDMOS
LDMOS
LDMOS
PMOS source/drain
N_PLUS NMOS source/drain
ROM Future option
SALBLOCK Salicide block - defines notsalicided area
CONT Contact to poly and active area
METAL1 Metalization level 1
VIA1 Connect metal 1 and metal 2


Layer Description
P_PLUS_LDH HV-LDMOS
N_PLUS_LDH HV-LDMOS
MIM1 Metal insulator metal capacitor top electrode
MIM2 Future option, used for double MIM
MIM3 Future option, used for triple MIM
VIA_F Final via
METAL_F Final metal
VIA_T Connect METAL_F and METAL_T
METAL_T Thick metal
SIL Open passivation
PIQ Open polyimide; future option
IVD Open inductor passivation; future option
MD Future option
ZMOS Future option
Y
FPRO Future option
MCEL Future option
SIBP
ZEROLAY
PD_NWELL
Future option
Alignment marker, LFoundry reserved layer
NWELL for photo-diodes, future option
A R
N
PD_P_PLUS P-Plus implant (photo-diodes), future option
I
NANO1 Optical filter, future option
M
I
NANO6
NANO7
NANO8
EL Optical filter, future option

Optical filter, future option
Optical filter, future option
NANO9
SNK0
DNWELL
PSUB
NBUFF
NSINK
PR Optical filter, future option
LDMOS, future option
LDMOS
LDMOS
Lateral IGBT
N sinker for BS LDMOS
PSINK P sinker for BS LDMOS
PBURIED LDMOS/lateral IGBT
BSDTI Backside deep trench isolation
BSTSV Backside through silicon via
BSNPLUS Backside N+ source/drain
BSPPLUS Backside P+ source/drain
BSCONT Backside contact
BSMETAL1 Backside metalization level 1


Layer Description
BSSIL Backside open passivation
6.3. General Process Properties
6.3.1. Cross Section
See figure below for a cross section of the full process.
6.3.2. Resistances
Resistance table, contact and via

Device min typ max Unit
CONT 13 20 26 W
VIA1 2.5 4. 7. W
VIAx, x ∈ {2, 3, 4, . . . } 2.5 4. 7. W
Y
VIAF 2.5 4. 7. W
Device
METAL1
METALx, x ∈ {2, 3, 4, . . . }
Resistance table, metal
A
70
70
R
min typ
110
110
max
150
150
Unit
mW/2
mW/2
METALF
METALT
I N 28
1.0
43
1.0
58
1.0
mW/2
mW/2
I
6.3.3. Basic Design Rules
L M
Mask 1
NWELL
R E Mask 2
Basic design rules
Width [µm]
1.5
Spacing [µm]
1.5
P
Active Area 0.32 0.32
Poly Silicon Gate 0.15 0.26
Poly Silicon Gate Contact 0.12
Poly Silicon Gate Active Area 0.14
Contact 0.18 0.3
Metal 1/2/3/4/5 0.24 0.24
Via 1/2/3/4 0.24 0.24
Final Metal 0.58 0.58
Final Via 0.24 0.24
For detailed rules, please refer to the LF15A PDK Technology Description and Design Rules manual.

With thick metal option Simple metal options With MIM option
IVD 9.8 µm εr =3.1
PAS 0.1 µm εr =7.8
≥ 6.0 µm PAS 0.63 µm εr =7.8
PDK_LF15Ai_V0_5_0 / UG
METALT 8.5 µm RMETALT =1.0 mW/2
PAS 0.63 µm εr =7.8
P
IMDF3 0.30 µm εr =4.1
IMDF2 0.63 µm εr =7.8
VIAT 1.83 µm RVIAT =0.054 W
R
IMDF 1.56 µm εr =4.1
3.0 µm
IMDF1 1.73 µm εr =4.1
There for You, Any Time, Every Time
≥ 0.58 µm ≥ 0.58 µm
E
METALF 0.83 µm RMETALF =43 mW/2
L
IMDx 0.945 µm εr =4.1
VIAx 0.575 µm RVIAx =4.0 W
MIMS 0.15 µm
I
0.24 µm
insulator 65 nm
≥ 0.24 µm ≥ 0.24 µm
METALx 0.37 µm RMETALx =110 mW/2
CONFIDENTIAL
M
IMD1 0.945 µm εr =4.1
VIA1 0.575 µm RVIA1 =4.0 W
LFoundry GmbH — http://www.lfoundry.com

0.24 µm
I
≥ 0.24 µm ≥ 0.24 µm
METAL1 0.37 µm RMETAL1 =110 mW/2
ILD1 0.11 µm εr =4.1
N
CONT 0.605 µm RCONT =20 W
PMD 0.7 µm εr =3.9
0.18 µm
PSiN 0.045 µm εr =7.0
≥ 0.15 µm ≥ 0.26 µm ≥ 0.36 µm
POLY2 0.25 µm
A
STI εr =3.9
R
P-substrate εr =11.9 10.5 Ohm cm
Y
56
Figure 6.1.: LF15A process cross section (not to scale)
Cc
Top plate / Plate A Plate B
Cf
Ca
Bottom plate
Figure 6.2.: Interconnect capacitance
6.3.4. Current Density
To avoid electromigration during product life time, do not exceed following current densities.
Current density values

Conductor Maximum DC value
METAL1 . . . METAL5 1.2 mA/µm width
METAL_F 2.5 mA/µm width
METAL_T (6 µm) 5.0 mA/µm width preliminary
VIA1 . . . VIA4, VIA_F 0.16 mA/VIA
CONT to POLY
CONT to DIFF
0.10 mA/CONT
0.10 mA/CONT
RY
A
Note: Values about current densities for POLY resistors are preliminary up to now.
N
Current density values for POLY resistors
I
Device Maximum DC value
rppolyl 0.3 mA/µm width @ width < 30 µm
M
rppolyh 0.08 mA/µm width @ width < 30 µm
I
rnpolylt 0.5 mA/µm width @ width < 30 µm
EL
6.3.5. Interconnect Capacitance Table
R
In the following tables, Ca represents the area capacitance between top and bottom plate, Cf the
P
fringe capacitance between top and bottom plate, and Cc is the coupling capacitance between plates
A and B of the same layer. Please refer to figure 6.2.
Interconnect capacitance table, typical corner

Top plate Bottom plate Ca [aF/µm2 ] Cf [aF/µm]
METAL1 substrate 31.490 52.300
METAL_F substrate 5.830 42.175
METAL1 POLY2 64.030 61.100
METAL2 POLY2 24.390 48.675
METAL3 POLY2 15.010 43.325

Interconnect capacitance table, typical corner (continued)

Top plate Bottom plate Ca [aF/µm2 ] Cf [aF/µm]
METAL4 POLY2 10.815 40.063
METAL5 POLY2 8.435 37.613
METAL_F POLY2 6.545 43.013
METAL2 METAL1 68.860 63.575
METAL3 METAL1 25.050 50.000
METAL4 METAL1 15.260 44.325
METAL5 METAL1 10.935 40.863
METAL_F METAL1 8.115 46.213
METAL3 METAL2 68.870 63.525
METAL4 METAL2 25.060 49.950
METAL5 METAL2 15.265 44.163
METAL_F METAL2 10.520 49.400
METAL4 METAL3 68.870 63.400
METAL5 METAL3 25.080 49.725
METAL_F METAL3 14.810 53.950
METAL5 METAL4 68.860 63.450
METAL_F METAL4 24.570 61.650
METAL_F METAL5 68.150 80.375
Y
Interconnect capacitance table, typical corner
Plates Cc [aF/µm]
METAL1
METAL2
METAL3
30.090
32.470
33.739
A R
N
METAL4 34.567
I
METAL5 35.235
METAL_F 70.451
I M
Note: For Cc the A B plate distance is the interconnect minimum spacing for line width > 40 µm.
L
E
6.4. Process Control
R
Several geometrical and electrical parameters are measured for process control purposes. Electrical
P
measurements are typically performed at T0 = 27 °C (300 K). Coefficients describing the temperature
behavior of parameters are extracted for the temperature range −40 °C < T < 125 °C.
Process control parameters are assigned to one of the following categories.
6.4.1. Judgement Parameters
Judgement parameters are used for wafer selection during the wafer fabrication process. Judgement
parameters are measured on each wafer. In chapter 7.1 these parameters are marked with a } sign.

6.4.2. Information Parameters
Information parameters are provided in order to increase the knowledge about the process. These
parameters do normally not lead to wafer scrap. In chapter 7.1 these are all parameters without the
} sign.
There are several groups of information parameters:
1. The first group of information parameters is measured, identically to the judgement parameters,
on each wafer. These parameters are monitored and substantial abnormalities will be analyzed.
2. The second group of information parameters is not measured on each wafer. This group includes,
for example, the layer thickness values measured during the wafer fabrication process or taken
from SEM images. On some of these parameters internal specs are existing which might lead to
wafer scrap.
3. The third group are the coefficients describing the temperature, voltage and matching behavior
of active and passive devices. This data is updated time by time.
Note: The process control transistor parameters cannot be used for circuit simulation purposes. They
Y
are often extracted from simplified model equations. Special circuit simulation transistor parameters
are provided. Process control transistor parameters may differ from their corresponding circuit simu-
lation parameters.
6.4.3. Wafer Reject Criteria

A R
I N
LFoundry will provide a standard measurement set of judgement parameters at at least 9 sites dis-
M
tributed uniformly across the wafer. At least 2/3 of the measured sites must pass all judgement criteria
I
to consider the tested wafer as pass.
L
R E
P

7. Process Control Parameters
The current release describes control parameters for the MOS transistors and poly silicon resistors,
other parametric test parameters and measured inline parameters will be added in subsequent releases.
Note: The Process Control Parameter are considered as preliminary as the process set up in the fab
is not finally completed.
7.1. Parametric Test
Parameters used for reject judgement are marked with a } sign, all other parameters are for infor-
mation. Please refer to chapter 6.4 for more information about this. For description of measuring
Y
methods please refer to the PCM parameter appendix on page iv.
R
Note: The values for 5 V devices are currently under revision and may change in the next version.
A
7.1.1. Transistors
nmos1v8lvt
I N
PCM
} Vto
Vto
} Vto
Parameter
Short Ch. Vt
L
Long Ch. Vt
I
Narrow Ch. Vt
Name
VT_SNHSW10UL150NNF1
VT_SNHSW10UL10UNF1
VT_SNHSW320NL150NNF1
M Unit
mV
mV
mV
Min
420
220
415
Typ
500
250
490
Max
580
280
565
L × W [µm2 ]
0.15 × 10
10 × 10
0.15 × 0.32
} In2
In2
In2
R E
Sat. Cur. (SC)
Sat. Cur. (LC)
Sat. Cur. (NC)
IDS_SNHSW10UL150NNF1
IDS_SNHSW10UL10UNF1
IDS_SNHSW320NL150NNF1
µA/µm
µA/µm
µA/µm
550
32.2
640
630
36
750
710
39.8
860
0.15 × 10
10 × 10
0.15 × 0.32
} In2
P
Off Cur. IOFFD_SNHSW10UL150NNF1 0.15 × 10
pA/µm 30 70
} Bn4 Breakdown Volt. BVDSS_SNHSW10UL150NNF1 V 4.0 4.3 0.15 × 10
@ IDS = 1 µA
Matching Coeff. Avt mV µm 6

nmos3v3rvt
PCM Parameter Name Unit Min Typ Max L × W [µm2 ]
} Vto Short Ch. Vt VT_SNMVW10UL350NNF1 mV 455 525 595 0.35 × 10
Vto Long Ch. Vt VT_SNMVW10UL10UNF1 mV 475 570 665 10 × 10
} Vto Narrow Ch. Vt VT_SNMVW800NL350NNF1 mV 455 525 595 0.35 × 0.80
} In2 Sat. Cur. (SC) IDS_SNMVW10UL350NNF1 µA/µm 385 460 535 0.35 × 10
In2 Sat. Cur. (LC) IDS_SNMVW10UL10UNF1 µA/µm 37.6 41 44 10 × 10
In2 Sat. Cur. (NC) IDS_SNMVW800NL350NNF1 µA/µm 410 490 570 0.35 × 0.80
} In2 Off Cur. IOFFD_SNMVW10UL350NNF1 pA/µm 3 100 0.35 × 10
} Bn4 Breakdown BVDSS_SNMVW10UL350NNF1 V 9.0 10 0.35 × 10
Volt. @ IDS = 1 µA
nmos5v0rvt
} Vto Short Ch. Vt VT_SNHVW10UL800NNF1 mV 680 755 830 0.80 × 10
Vto Long Ch. Vt VT_SNHVW10UL10UNF1 mV 705 745 785 10 × 10
} Vto Narrow Ch. Vt VT_SNHVW800NL800NNF1 mV 670 745 820 0.80 × 0.80
} In2 Sat. Cur. (SC) IDS_SNHVW10UL800NNF1 µA/µm 345 395 445 0.80 × 10
In2 Sat. Cur. (LC) IDS_SNHVW10UL10UNF1 µA/µm 49.5 55.8 61.5 10 × 10
In2 Sat. Cur. (NC) IDS_SNHVW800NL800NNF1 µA/µm 370 420 470 0.80 × 0.80
Y
} In2 Off Cur. IOFFD_SNHVW10UL800NNF1 pA/µm 1 10 0.80 × 10
} Bn4 Breakdown BVDSS_SNHVW10UL800NNF1 V 10 11.5 0.80 × 10
Volt.
A R @ IDS = 1 µA
N
nmos1v8hvt
I
} Vto Short Ch. Vt VT_SNLLW10UL150NNF1 mV 620 695 770 0.15 × 10
M
Vto Long Ch. Vt VT_SNLLW10UL10UNF1 mV 420 490 560 10 × 10
I
} Vto Narrow Ch. Vt VT_SNLLW320NL150NNF1 mV 625 705 785 0.15 × 0.32
} In2 Sat. Cur. (SC) IDS_SNLLW10UL150NNF1 µA/µm 420 490 570 0.15 × 10
In2
In2
} In2 Off Cur.
EL
Sat. Cur. (LC)
Sat. Cur. (NC)
IDS_SNLLW10UL10UNF1
IDS_SNLLW320NL150NNF1
IOFFD_SNLLW10UL150NNF1
µA/µm
µA/µm
pA/µm
16.5
460
21.5
560
2
26.5
660
3
10 × 10
0.15 × 0.32
0.15 × 10
} Bn4
PR
Breakdown Volt.
Matching Coeff.
BVDSS_SNLLW10UL150NNF1
Avt
V
mV µm
3.9
6
4.3 0.15 × 10
@ IDS = 1 µA

pmos1v8lvt
} Vto Short Ch. Vt VT_SPHSW10UL150NNF1 mV -500 -560 -620 0.15 × 10
Vto Long Ch. Vt VT_SPHSW10UL10UNF1 mV -520 -570 -620 10 × 10
} Vto Narrow Ch. Vt VT_SPHSW320NL150NNF1 mV -525 -585 -645 0.15 × 0.32
} In2 Sat. Cur. (SC) IDS_SPHSW10UL150NNF1 µA /µm -210 -250 -290 0.15 × 10
In2 Sat. Cur. (LC) IDS_SPHSW10UL10UNF1 µA/µm -2.45 -2.85 -3.25 10 × 10
In2 Sat. Cur. (NC) IDS_SPHSW320NL150NNF1 µA/µm -170 -220 -270 0.15 × 0.32
} In2 Off Cur. IOFFD_SPHSW10UL150NNF1 pA/µm -2 -70 0.15 × 10
} Bn4 Breakdown BVDSS_SPHSW10UL150NNF1 V -5.1 -5.6 0.15 × 10
Volt. @ IDS =
1 µA
Matching Co- Avt mV µm 4
eff.
pmos3v3rvt
} Vto Short Ch. Vt VT_SPMVW10UL350NNF1 mV -500 -560 -620 0.35 × 10
Vto Long Ch. Vt VT_SPMVW10UL10UNF1 mV -590 -645 -710 10 × 10
} Vto Narrow Ch. Vt VT_SPMVW800NL350NNF1 mV -500 -560 -620 0.35 × 0.80
} In2 Sat. Cur. (SC) IDS_SPMVW10UL350NNF1 µA/µm -285 -330 -375 0.35 × 10
Y
In2 Sat. Cur. (LC) IDS_SPMVW10UL10UNF1 µA/µm -7.6 -9 -10.4 10 × 10
In2 Sat. Cur. (NC) IDS_SPMVW800NL350NNF1 µA/µm -270 -310 -350 0.35 × 0.80
} In2
} Bn4
Off Cur.
Breakdown
Volt.
IOFFD_SPMVW10UL350NNF1
BVDSS_SPMVW10UL350NNF1
pA/µm
V -6.8
-2
-7.5
A R -70 0.35 × 10
0.35 × 10
@ IDS =
N
1 µA
I
M
pmos5v0rvt
I
} Vto Short Ch. Vt VT_SPHVW10UL600NNF1 mV -655 -725 -795 0.60 × 10
Vto
} Vto
Long Ch. Vt
Narrow Ch.
Vt
EL VT_SPHVW10UL10UNF1
VT_SPHVW800NL600NNF1
mV
mV
-770
-650
-810
-720
-850
-790
10 × 10
0.60 × 0.80
R
} In2 Sat. Cur. IDS_SPHVW10UL600NNF1 µA/µm -195 -235 -275 0.60 × 10
(SC)
In2
In2
} In2
(LC)
(NC)
Off Cur.
P
Sat. Cur.
Sat. Cur.
IDS_SPHVW10UL10UNF1
IDS_SPHVW800NL600NNF1
IOFFD_SPHVW10UL600NNF1
µA/µm
µA/µm
pA/µm
-9.78
-180
-12.83
-225
-1
-15.78
-270
-10
10 × 10
0.60 × 0.80
0.60 × 10
} Bn4 Breakdown BVDSS_SPHVW10UL600NNF1 V -9.7 -10.7 0.60 × 10
Volt. @ IDS =
1 µA
Matching Avt mV µm 14
Coeff.

pmos1v8hvt
} Vto Short Ch. Vt VT_SPLLW10UL150NNF1 mV -605 -680 -755 0.15 × 10
Vto Long Ch. Vt VT_SPLLW10UL10UNF1 mV -640 -690 -740 10 × 10
} Vto Narrow Ch. Vt VT_SPLLW320NL150NNF1 mV -635 -710 -785 0.15 × 0.32
} In2 Sat. Cur. (SC) IDS_SPLLW10UL150NNF1 µA/µm -160 -200 -240 0.15 × 10
In2 Sat. Cur. (LC) IDS_SPLLW10UL10UNF1 µA/µm -1.6 -2.1 -2.6 10 × 10
In2 Sat. Cur. (NC) IDS_SPLLW320NL150NNF1 µA/µm -120 -175 -230 0.15 × 0.32
} In2 Off Cur. IOFFD_SPLLW10UL150NNF1 pA/µm -0.5 -3 0.15 × 10
} Bn4 Breakdown Volt. BVDSS_SPLLW10UL150NNF1 V -5 -5.4 0.15 × 10
@ IDS = 1 µA
7.1.2. Resistors
rnpolys
Rk1 Resistivity RNPOLY_S1_L100_W5 W/2 9 11.5 14 100 × 5
rppolys
PCM
Rk1
Parameter
Resistivity
Name
RPPOLY_S1_L100_W5
Unit Min
W/2 9
Typ
11.5
Max
14
Y
L × W [µm2 ]
100 × 5
R
A
rppolyl
N
Rk1 Resistivity RPPOLY_L1_L50_W10 W/2 303 348 393 50 × 10
PCM Parameter Name

rppolyh
M I
Unit Min Typ Max L × W [µm2 ]
Rk1 Resistivity
I RPPOLY_H1_L50_W10 50 × 10
W/2 1650 2100 2550
PCM
Rk1
Parameter
EL
Resistivity
Name
RNPOLY_LT1_L50_W10
rnpolylt
Unit Min
W/2 119
Typ
134
Max
149
L × W [µm2 ]
50 × 10
PR

8. Physical Verification
8.1. DRC: Design Rule Check
Please refer to LF15A PDK Technology Description and Design Rules for details on design rule check.
8.1.1. Annotations on MIM
The MIM model is defined without any structures below the MIM itself. It is allowed to put devices
or routing lines below, but the model may not work correctly.
Note: We recommend to use MIM_recommended DRC switch to check if there’s routing below MIM
device
RY
8.1.2. Annotations on Resistors
N A
I
The resistor lengths are allowed to be shotter then they are expected by the model range. For more
information refer to the section 5.1.6. To disable DRC warnings for short length resistors please enable
M
theRES_recommended DRC switch.
L I
8.1.3. Annotations on Area Rules
R E
The minimum area rules are not avaliable for Virtuoso DRD functionality, but will be checked by DRC
deck rule. It is true for all metal layers, POLY2 layer and derived layer TAP.
P
8.2. LVS: Layout Versus Schematic
The pycells will work with Assura for LVS & QRC, if the Ciranova plug-in is not installed and
defined. For more information please refer to the chapter 4.4.3.
8.2.1. Stamp Check for Diffusion
The diffStampCheck LVS switch enables an Assura stamp-check. The check highlight if diffusion is
used as connection layer between two METAL1 layers without any parallel metal connection.

Note: The diffStampCheck LVS check is not compatible together with QRC parasitic extraction.
Please disable the one when running textttAssura-LVS-to-QRC flow.
RY
N A
M I
L I
R E
P

9. ESD Information
9.1. ESD Specification
ESD specification
Model Standard Pass level
HBM JESD22-A114 2000 V
MM JESD22-A115 200 V
CDM (see note below)
Note: CDM peak currents are highly dependent on packages. To achieve a 500 V CDM specification
a more conservative design rule for bus resistance and power/ground pad placement must be applied
compared to other ESD standards.
9.2. ESD Rules
RY
9.2.1. ESD Design Requirements
N A
these rules must be fulfilled with additional margin.
M I
Following ESD rules are absolute maximum values. If elements are placed directly in the ESD path
Element
L I Vmax
ESD design requirements
Imax Comments
E
METAL1. . . 5 - 120 mA/W[µm] 2 kV HBM: W ≥ 12 µm; 200 V MM: W ≥ 22 µm
METAL_F - 250 mA/W[µm] 2 kV HBM: W ≥ 6 µm; 200 V MM: W ≥ 11 µm
R
VIA1. . . 4 - 35 mA/VIA 2 kV HBM: ≥ 40; 200 V MM: ≥ 75
VIA_F - mA
33 /VIA 2 kV HBM: ≥ 24; 200 V MM: ≥ 79
CONT
rppolys
rnpolylt
rppolyl
rppolyh
P -
0.61 V/L[µm]
1.26 V/L[µm]
1.78 V/L[µm]
2.8 V/L[µm]
5 mA/VIA
mA
2 kV HBM: ≥ 269; 200 V MM: ≥ 500
15 /W[µm] Make sure to use enough CONT rows
7.5 mA/W[µm] Make sure to use enough CONT rows
9.2.2. Protection Devices
The IOs provided by LFoundry make use of active clamp circuits, gate-grounded NMOS (GGNMOS)
and source-gate shorted PMOS (SGPMOS) devices. GGNMOS and SGPMOS operate in snap-back
mode to protect the core during an ESD event (figure 9.1).

RY
N A
M I
L I
R E Figure 9.1.: Schematic snap-back mode of parasitic bipolar

10. Technology and Reliability Qualification
Our Technology and Reliability Qualification program is based on international technical qualifica-
tion standards. LFoundry follows the procedures and practices based JEDEC JP-001 FOUNDRY
PROCESS QUALIFICATION GUIDELINES.
Level 1 is a pure wafer process qualification intended to find reliability weaknesses by stressing and
testing technology elements. It primarily addresses technology wear out mechanisms on specially
designed test structures.
Level 2 test demonstrate the reliability behaviour of a device for functionality using test vehicle.
Such evaluations are close to customers application and includes test like HTOL, Early Live
tests, Temperature Cycling etc. Level 2 tests might be performed in cooperation with customer
using actual products or using LFoundry test vehicles like SRAM test chips.
RY
N A
M I
L I
R E
10.1. Planned JP001 Level 1 qualification test items for LF15A

Note: Following test items of JP001 Level 1 are not relevant:

8.3 Thermal Cycling Copper Interconnect relevant for copper metallization, only.
Y
8.4 Inter/Intra-metal dielectric integrity required in case of non SIO2 based dielectric, only.
10.3 Plasma Induced Damage (P2ID) are covered by HCI, TDDB, EM . . . test structures.
10.1 QPD (Charge to breakdown) are covered by Oxide TDDB.
A R
N
10.2. Planned JP001 Level 2 qualification test items for LF15A
I
L I M
R E
P

Appendix
RY
N A
M I
L I
R E
P
PDK_LF15Ai_V0_5_0 / UG LFoundry GmbH — http://www.lfoundry.com i

A. Abbreviations
General abbreviations
Short Description
CDE Common Desktop Environment
CDF Component Description Format
CDM Charge Device Model (ESD model)
CIW Command Interpreter Window
CMOS Complementary Metal-Oxide-Semiconductor
DFII Cadence Design Framework II
DFM Design For Manufacturing
DMOS Double Diffused Metal-Oxide-Semiconductor
DRC Design Rule Check
DRD Design Rule Driven editing (on-the-fly DRC)
EDA Electronic Design Automation
EM
ESD
GDSII
Electromigration
Electrostatic Discharge
Graphical Design Station II (file format)
RY
GIDL
HBM
HCI
Gate Induced Drain Leakage
Human Body Model (ESD model)
Hot Carrier Injection
N A
IP
JFET
LSW
Intellectual Property
Junction Field Effect Transistor
Layer Selection Window
M I
LVS
MC
MIM
L I Layout Versus Schematic

Monte-Carlo simulation
Capacitor: Metal-Isolator-Metal
MM
NPN/PNP
NVM
R E Machine Model (ESD model)

Bipolar transistor
Non Volatile Memory
P
PDK Process Design Kit / Process Development Kit
PE Physical Extraction
PIP Capacitor: Poly-Isolator-Poly
QRC Cadence parasitic extraction tool
RCX Assura parasitic extraction tool (not supported by LF15A PDK)
RF Radio Frequency
SOA Safe Operation Area
STI Shallow Trench Isolation
TDDB Time Dependent Dielectric Breakdown
WPE Well Proximity Effect
LFoundry specific abbreviations

Short Description
HS High Speed
PDK_LF15Ai_V0_5_0 / UG LFoundry GmbH — http://www.lfoundry.com ii

LFoundry specific abbreviations (continued)

Short Description
HV High Voltage
HVT High Threshold Voltage
LF LFoundry
LL Low Leak
LP Low Power / Ultra Low Power
LTC Low Temperature Coefficient
LVT Low Threshold Voltage
MLM Multi Layer Mask
MPW Multi Project Wafer
RVT Regular Threshold Voltage
SPW Single Project Wafer
STD Standard Process
TAT Turn Around Time
RY
N A
M I
L I
R E
P
PDK_LF15Ai_V0_5_0 / UG LFoundry GmbH — http://www.lfoundry.com iii

B. PCM parameter description
PCM parameter
Name Area Description
Vto all Threshold Voltage
VDS =0.05 V / −0.05 V (n-channel / p-channel); VSUB =0 V;
VGS is sweeped and IDS is measured;
VTH is extracted with gmmax -method from IDVG with (- Vdlin 2 ) correction (Five
points on the curve are used to construct a best-fit line)
Bn4 all Breakdown Voltage
VGS =0 V; VSUB =0 V; IDS =100 nA/µm / −100 nA/µm (n-channel / p-channel device)
Ca1 0.0 V Capacitance Measurement
VDC =0 V; f =100 kHz; VSS =50 mV
Ca1 1.8 V Capacitance Measurement
VDC =1.8 V / −1.8 V; f =100 kHz; VSS =50 mV
Ca1
Ca1
3.3 V
5.0 V
Capacitance Measurement
VDC =3.3 V / −3.3 V; f =100 kHz; VSS =50 mV
Capacitance Measurement
RY
Hfe PNP
VDC =5.0 V / −5.0 V; f =100 kHz; VSS =50 mV
Current Gain
N
β = IICB ; IC is measured at IB =10 nA; IB =0.1 µA; IB =1 µA
A
Hfe NPN Current Gain
I
β = IICB ; IC is measured at IB =10 nA; IB =0.1 µA; IB =1 µA
M
I
In2 1.8 V Saturation Current
VDS =VGS =1.8 V / −1.8 V (n-channel / p-channel); VSUB =0 V;
In2 3.3 V
EL Normalization: µA/µm
Saturation Current
VDS =VGS =3.3 V / −3.3 V (n-channel / p-channel); VSUB =0 V;
R
Normalization: µA/µm
In2 5.0 V Saturation Current
In2
In2
1.8 V
3.3 V
P VDS =VGS =5.0 V / −5.0 V (n-channel / p-channel); VSUB =0 V;
Normalization: µA/µm
Off Current
VDS =1.8 V / −1.8 V (n-channel / p-channel); VGS =VSUB =0 V;
Normalization: pA/µm
Off Current
In2 5.0 V Off Current
PDK_LF15Ai_V0_5_0 / UG LFoundry GmbH — http://www.lfoundry.com iv

PCM parameter (continued)

Name Area Description
Rd1 Poly Sheet Resistance
VRES across resistance is 1.0 V, current IRES is measured;
Normalization: W/2
Rd1 Metal Sheet Resistance
IRES =0.2 mA is forced through resistor VRES is measured;
Normalization: mW/2
Rk1 Poly Sheet Resistance (with Kelvin method)
IRES =0.1 mA is forced through resistor; VRES is measured at different connection;
L is resistor length in µm; W is resistor width in µm;
RS = VIRES
RES
·WL
Normalization: W/2
Rk1 Metal Sheet Resistance (with Kelvin method)
IRES =0.1 mA is forced through resistor; VRES is measured at different connection;
L is resistor length in µm; W is resistor width in µm;
RS = VIRES
RES
·WL
Normalization: mW/2
RY
N A
M I
L I
R E
P
PDK_LF15Ai_V0_5_0 / UG LFoundry GmbH — http://www.lfoundry.com v

C. iPDK supported devices
iPDK supported devices

EDA Tool Vendor Metal Option
Device Name Cadence Synopsys 6 Metal 5 Metal 4 Metal
MOS
nmos3v3rvt_3 • • • • •
nmos3v3rvt_4 • • • • •
nmos5v0rvt_3 • • • • •
nmos5v0rvt_4 • • • • •
nmos1v8lvt_3 • • • • •
nmos1v8lvt_4 • • • • •
nmos1v8lvti_3 • • • • •
nmos1v8lvti_4 • • • • •
nmos1v8hvt_3 • • • • •
nmos1v8hvt_4
nmos1v8zvt_3
nmos1v8zvt_4
•
•
•
•
•
•
•
•
•
•
•
•
RY •
•
•
A
pmos3v3rvt_3 • • • • •
pmos3v3rvt_4 • • • • •
pmos5v0rvt_3
pmos5v0rvt_4
pmos1v8lvt_3
•
•
•
•
•
•
I N •
•
•
•
•
•
•
•
•
pmos1v8lvt_4
pmos1v8hvt_3
pmos1v8hvt_4
Bipolar
L I
•
•
•
•
•
•
M •
•
•
•
•
•
•
•
•
E
npn • • • • •
pnp • • • • •
Diodes
dnipsub
dnwepsub
dnppw
dnppwl
dppnw
PR •
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
dppnwl • • • • •
Capacitors
ncap3v3rvt • • • • •
ncap5v0rvt • • • • •
ncap1v8hvt • • • • •
pcap3v3rvt • • • • •
cmims • • • • •
PDK_LF15Ai_V0_5_0 / UG LFoundry GmbH — http://www.lfoundry.com vi

iPDK supported devices (continued)

EDA Tool Vendor Metal Option
Device Name Cadence Synopsys 6 Metal 5 Metal 4 Metal
Resistors
rmet1 • • • • •
rmet2 • • • • •
rmet3 • • • • •
rmet4 • • • •
rmet5 • • •
rmetf • • • • •
rnpolylt • • • • •
rnpolys • • • • •
rndiff • • • • •
rnwell • • • • •
rppolyh • • • • •
rppolyl • • • • •
rppolys • • • • •
Miscellaneous
break • • • •
make • • • •
LDMOS
nmosld40v_3 • • • •
nmosld8v_3
pmosld40v_3
pmosld8v_3
•
•
•
•
•
•
•
•
•
RY •
•
•
N A
M I
L I
R E
P
PDK_LF15Ai_V0_5_0 / UG LFoundry GmbH — http://www.lfoundry.com vii

D. List of Figures
3.1. EDA tool vendors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.2. LF15A Cadence Mixed-Signal design flow . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3. LF15A Synopsys Mixed-Signal design flow . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1. File structure of PDK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.2. LF15A technology database graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1. Overview of model system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.2. nmosld8v_3 output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3. nmosld40v_3 output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.4. pmosld8v_3 output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.5. pmosld40v_3 output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.6. Example for instance property in schematic . . . . . . . . . . . . . . . . . . . . . . . . 35
5.7. Seal ring elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.8. Cross section of seal ring . . . . . . . . . . . . . . . . . . . . .
5.9. 1.8 V GPIO terminal overview . . . . . . . . . . . . . . . . . .
.
.
.
.
.
.
.
.
.
RY.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
37
40
42
5.12. Simplified circuit of analog input/output cell . . . . . . . . .
N
5.13. Simplified circuit of digital input/output cell . . . . . . . . .
.
.
.
.
.
.
A
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
44
46
47
M I
5.14. Simplified circuit of digital input cell . . . . . . . . . . . . . .
5.15. Simplified circuit of digital output cell . . . . . . . . . . . . .
5.16. Simplified circuit of [1v8|3v3|5v0]_p_breaker_io_ll cell .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
47
48
49
L I
5.17. ESD voltage domain coupling . . . . . . . . . . . . . . . . . .
5.18. Examples for maximum bus length between analog-I/O pads
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
50
50
E
6.1. LF15A process cross section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.2. Interconnect capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
PR
9.1. Schematic snap-back mode of parasitic bipolar . . . . . . . . . . . . . . . . . . . . . . 67
PDK_LF15Ai_V0_5_0 / UG LFoundry GmbH — http://www.lfoundry.com viii

E. Document History
Version Date Modifications

0.5.0 2014-12-18 Digital libraries recharacterization, SALBLOCK DR update
0.4.0 2014-12-05 spice models update, iso mosfets roll-back
0.2.0 2014-07-04 preliminary external release
0.1.X 2014-02-14 preliminary internal release
For details please refer to the LF15A PDK Release Notes.
RY
N A
M I
L I
R E
P
PDK_LF15Ai_V0_5_0 / UG LFoundry GmbH — http://www.lfoundry.com ix

LF15Ai User Guide V0 5 0

Transféré par

Informations du document

Copyright

Formats disponibles

Partager ce document

Partager ou intégrer le document

Options de partage

Avez-vous trouvé ce document utile ?

Ce contenu est-il inapproprié ?

Droits d'auteur :

Formats disponibles

LF15Ai User Guide V0 5 0

Transféré par

Droits d'auteur :

Formats disponibles

PDK_LF15Ai_V0_5_0

2. LF15A Technology description 2

PDK_LF15Ai_V0_5_0 / UG LFoundry GmbH — http://www.lfoundry.com II

5.7.5. Power Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

7. Process Control Parameters 60

B. PCM parameter description iv

C. iPDK supported devices vi

D. List of Figures viii

PDK_LF15Ai_V0_5_0 / UG LFoundry GmbH — http://www.lfoundry.com III

LFoundry is the foundry of choice because it:

• promotes specialized manufacturing technologies and a world-class engineering organization.

• supplies a monthly capacity of more than 40k, on 200mm, wafers.

requests from its customers.

• is reliable and flexible.

PDK_LF15Ai_V0_5_0 / UG LFoundry GmbH — http://www.lfoundry.com 1

2. LF15A Technology description

The major process features include:

• n/p-well formation and channel enhancement;

PDK_LF15Ai_V0_5_0 / UG LFoundry GmbH — http://www.lfoundry.com 2

3.1. General information

• PDK name and version

PDK_LF15Ai_V0_5_0 / UG LFoundry GmbH — http://www.lfoundry.com 3

3.3. EDA Environment

This PDK is checked to work with the following EDA environment:

Stream Release Tool Usage

PDK_LF15Ai_V0_5_0 / UG LFoundry GmbH — http://www.lfoundry.com 4

PDK_LF15Ai_V0_5_0 / UG LFoundry GmbH — http://www.lfoundry.com 5

Analog Mixed-Signal Digital

n Spectre Virtuoso Incisive

Figure 3.2.: LF15A Cadence Mixed-Signal design flow

PDK_LF15Ai_V0_5_0 / UG LFoundry GmbH — http://www.lfoundry.com 6

Analog Mixed-Signal Digital

t Custom Designer ICC-CD IC

Figure 3.3.: LF15A Synopsys Mixed-Signal design flow

PDK_LF15Ai_V0_5_0 / UG LFoundry GmbH — http://www.lfoundry.com 7

4.1. Naming convention

PDK_LF15Ai_V0_5_0 / UG LFoundry GmbH — http://www.lfoundry.com 8

Figure 4.1.: File structure of PDK

PDK_LF15Ai_V0_5_0 / UG LFoundry GmbH — http://www.lfoundry.com 9

4.4.1. Installing the PDK

File name Description

Alternatively, you can extract the PDK archive manually:

First the PDK internal variables MUST be defined:

1. $LF15A_HOME path to the PDK installation directory.

2. $LF15A_OPTION metal flavor name (4metal, 5metal or 6metal)

PDK_LF15Ai_V0_5_0 / UG LFoundry GmbH — http://www.lfoundry.com 10

Alternatively, you can create your workarea manually:

1. Change into the directory, you want to use as workarea.

2. Set the environment variable $LF15A_HOME to your PDK installation directory

4. Copy the .cdsinit (for Cadence) or .cdesigner.tcl (for Synopsys) from

6. Set the proper tool variables (see 4.4.3).

Path to the directory where the LF15Ai

PDK_LF15Ai_V0_5_0 / UG LFoundry GmbH — http://www.lfoundry.com 11

Environment variables (continued)

PDK_LF15Ai_V0_5_0 / UG LFoundry GmbH — http://www.lfoundry.com 12

cmos150 Technology and device library

... Some more libraries

myLib Customer’s design library

Figure 4.2.: LF15A technology database graph

4.4.4. PDK usage

2. Source one of the files set.LF.environment.bash or set.LF.environment.csh to define your

3. Invoke Virtuoso or Custom Designer from your working folder.

PDK_LF15Ai_V0_5_0 / UG LFoundry GmbH — http://www.lfoundry.com 13

You get the next warning in Virtuoso like:

Basic model file structure cmos150hv.*