EE227 Final Study Guide

By: Jitendra Thummar

Email: jitendrathummar@yahoo.co.in

1 MOS transistor theory

1.1 Current Equations
1.1.1 If VG=2.5V, VS=2V, VD=1V, VB=0V, and VT=0.5V is the NMOS transistor off, in
linear mode, or in saturation.
Ans. Vs= Min (Vs, Vd)= 1V
Vd= Max (Vs, Vd)= 2V
Vgs= Vg – Vs= 1.5V
Vds= Vd – Vs= 1V
Vgs – Vt= 1V As Vds = Vgs – Vt, Transistor is in saturation.
Id= K’n (W/2L) (Vgs - Vt) 2
Take values of K’n, W & L from given datasheet. Assume the data that is not given
and evaluate equation. Mention all your assumption in answer sheet.
1.1.2 Using the device parameters given in the table, what Width of N transistor is
required with a L=2u device to get 1 ma current flow with VGS=2V and VDS=1.8V.
Ans. A) Use required parameters from given datasheet. Assume not given parameters.
B) Calculate Vgs–Vt & check if Vgs – Vt =< Vds.
If so, use Id = K’ (W/2L) (Vgs-Vt) 2
Else, use Id = K’ (W/L) [(Vgs – Vt).Vds - (Vds2 /2)]
1.2 CMOS Inverters and gates
Ans.
1.3 Design a CMOS function implementing Z=ABC+D+EF matching a standard
inverter. For example….
………. Design a CMOS logic function implementing ABC+D+EF using a single inverter. Show the
sizes of all transistors assuming the W/L of a reference inverter is 2/.25 for the N and 7/.25 for the P.
Ans.
2 CMOS Schmidt Trigger

2.1 Design a VM type Schmitt trigger with trip points of 1.3V and 1.5V. Assume all
transistor have L=0.24u. Assume 1st N device has Wni=.72u. Assume all L’s are
0.24u. Show devices on schematic.
Ans.
2.2 Design a NMOS style Schmitt trigger with trip points of 1.2V and 1.4V.
Ans.
3 Wires

3.1 How is capacitance estimated in deep sub-micron? What are the two
components?

Ans. Area capacitance and fringe capacitance are two components of the capacitance in
deep submicron. By adding total area and total fringe capacitances, total capacitance is
estimated in deep sub-micron.

3.2 Calculate the capacitance for a given piece of layout for the HP process.
3.3 Calculate the capacitance for a given piece of layout to several layers.
Ans.
4 Passive devices
4.1 Draw a typical poly-poly capacitor layout. Why are fingers included?
Ans. Poly has high resistivity. By including multiple fingers, number of contacts between
metal and poly is increased, so resistance is reduced, resulting in lower value of RC time
constant. This allows use of capacitor in high frequency application.

4.2 What are sources of “Stray” capacitance in capacitors?

Ans. Capacitances with upper layer, capacitance with lower layer and fringe capacitance
with the same layer are the sources of “Stray” capacitance in capacitors i.e. for ploy layer,
poly to metal, poly to substrate and poly-poly fringe capacitances are the sources of stray
capacitance.
4.3 Design a matched set of 3 capacitors with ratios 1:2:3. Show a layout with all
required symmetries to correct for gradients.
Ans.

4.4 Why is diffusion capacitor not often used?

Ans. It varies wildly with voltage. It has very high value of temperature coefficient. It picks
up Noise.

4.5 How close can capacitors be matched?

Ans. Up to 0.1%.

4.6 What are 3 common layers used to construct resistors?

Ans. Poly, well and diffusion.

4.7 Draw a layout example of two matched well resistors of 20k ohms each.
Ans.

4.8 Why are guard rings placed around well and diffusion resistors?
Ans. To prevent coupled noise from substrate.
4.9 Why are guard rings good around capacitors?
Ans. To prevent coupled noise from surrounding.

4.10 What is the FT of a transistor W=20u, L=1u KP’=110u Vgs=1.25V Vt=.55V?

Ans. There is nothing like Transition Frequency for MOS because it switches very fast. It
is defined only for BJT and other transistors.

5 GM related things
5.1 Why should be Gm be kept high in a Low noise amplifier?
Ans. Gain of the amplifier is given by Av = Gm. RL. Thermal noise in the circuit increases
with the increase in resistance. For the same gain requirement, as value of Gm increases
required value of RL decreases and so noise in the circuit does. Thus, higher value of Gm
is desirable in low noise amplifier.

5.2 What value of Gm should be used to obtain an amplifier with a gain of 10 when
RL is 10k ohms?
Ans. Given data: Av=10, RL = 10 K ohms.
Av = Gm. RL
Gm = 1 m mho.

5.3 Design a transistor with L=1u B’=KP=110u and Id=750ua and a GM of 10-3
Ans. Use Gm = (2 K’ (W/L) Id) ½
5.4 What assumptions are made for small signal operation?
Ans. 1) Straight line approximation or in other words constant slop around quiescent point
(Vgsq, Idsq).
2) Vgs varies within 10 % of Vdd.

5.5 If an amplifier is designed with a 10u/2u transistor, what will be the gain using a
10k ohm resistor assuming B’=K’=120u. Set the idle voltage (No input) at
Vdd/2=1.25V.
Ans. Use equation, Vidle = Vdd - Id.RL, to find Id.
Use equation, Id= K’ (W/2L) (Vbias - Vth) 2, to find Vbias.
Use equation, Gm= (2.K’.(W/L).Id) ½, to find Gm.
In all equations assume W and L, if not given.
6 Special Purpose Digital circuits
6.1 Draw schematics for a Mono stable multi-vibrator using a resistor and capacitor.
Ans.

6.2 Draw schematics for a Mono stable multi-vibrator using gates and invertors.
Ans.

6.3 Draw schematics for a Mono stable multi-vibrator which generates a pulse on
both rising and falling edges of the input.
Ans.
6.4 Draw schematics of an Astable multi-vibrator using a single resistor and
capacitor.
Ans.

6.5 Draw schematics of an Astable multi-vibrator using only digital circuits.

Ans.

6.6 How can the pulse width of a Mono-stable multi-vibrator be changed?

Ans. By changing RC time constant or changing inverter delay, depending on the
structure used to realize the circuit.

6.7 Draw a logic diagram for a circuit that will produce a 3ns wide pulse every 11 ns.
Assume logic with a 1ns delay. You may use invertors and NAND gates only.
Ans.
6.8 Calculate the C value for a Mono-stable multi-vibrator which will have a pulse of
5us with a 50k ohm resistor. (Hint: V(t) = Vdd [1- e-t/RC ] for an RC circuit with a step
input). Assume the digital logic is static CMOS with a Vm=Vdd/2=1.25V
Ans.

6.9 Draw schematics for a voltage doubling circuit using NMOS transistors.
Ans.

7 Misc
7.1 Why is layout important in Mixed signal design?
Ans. A) We can not control precise values of the components, so we perform matching of
their values by taking ratios of the values. To precisely maintain ratios against process and
temperature variations, and noise, symmetric arrangement is required in layout.
B) In mixed signal designs currents are very high, so preventing problem of metal
migration is also important by making wider paths.
C) Because mixed signal designs have both analog and digital sections on the same chip,
it is necessary to prevent noise generated by digital section to couple with analog section.

Meeting all the above given requirements is the part of layout. Thus layout is important in
mixed signal design.

7.2 How are devices matched in Mixed signal design?

Ans. By taking ratios of device values and maintaining precise values of ratios by
symmetric arrangement in layout, devices are matched in mixed signal design.

7.3 Why are device ratios used instead of device values in mixed signal design?
Ans. We don’t know absolute values of devices. And it is easier to maintain ratios
constant against process and temperature variations, and noise. So, we use device ratios
instead of device values.

7.4 Why must the number of invertors in a ring oscillator be odd?

Ans. In ring oscillator output of one inverter is given to the input of next inverter as shown
in fig. below. If number of inverters is even, it put all the inverters in one stable state and
hence no oscillation occurs. To prevent this stable state condition in oscillator, number of
inverters is kept odd.

7.5 How can a ring oscillator be started and stopped? What logic elements are
added?
Ans. Ring oscillator can be started and stopped by adding logic elements as given in fig
below.

7.6 Over what Vgs range is designing with Gm normally valid?

Ans. Vth<Vgs<(Vds+Vth) and maximum variation of Vgs should be 10% of Vdd, so that
straight line approximation remains valid.

8 PLLs
8.1 Draw the block diagram for a PLL and explain each circuit function
Ans.

VCO (Voltage Controlled Oscillator): Converts i/p voltage in to output frequency.

Do: Divides o/p frequency of VCO by Do to allow phase frequency detector to work at
slower frequency.
Dr: Divides i/p reference frequency by Dr to allow phase frequency detector to work at
slower frequency.
PFD (Phase Frequency Detector): Gives error up and down pulses proportional to
difference in phase and frequency of its two input signals.
Charge Pump: Converts up and down signals given by PFD in to o/p current.
Filter: It averages current variation of charge pump and coverts in smooth o/p voltage,
which controls VCO o/p frequency.

8.2 Given a PLL with 12 bit Y and Z dividers, and a restriction on Z that it can range
from 4005 to 4009. Find the best value of Y and Z (Smallest error) to generate a
VCO frequency of 14.775MHz when FREF is 6.277MHz. Compute all results to 1Hz
resolution. Assume Z is the VCO divider
Ans. Use equation fosc = (Do/Dr)*fref. Whr, Do= VCO divider; Dr= Reference divider

8.3 Draw Oscillator circuits:

Ans.

8.3.1 Current Starved

 8.3.2 Relaxation

8.3.3 Schmitt Trigger with RC

8.4 Size transistors in a current starved Oscillators

Ans.

8.5 For a Schmidt oscillator find the value for C that will result in a frequency of 2.35
MHz with a resistance of 12k ohms. Assuming the Schmitt trigger Vtl=1.1 and
Vth=1.3V.
Ans.
8.6 Draw logic schematics for programmable counter(s).
Ans.
8.7 What is the trade off between stability, capture time, and jitter.
Ans. As capture time becomes smaller, stability degrades and jitter increase. And
opposite is also true.

8.8 Show how a PLL can be used to remove clock skew from a clock distribution
network.
Ans. By inserting clock distribution network between VCO output and Do block as shown
in given fig.

8.9 Draw the schematics for an XOR, 3 state PFD, and 5 state PFD.
Ans.
8.10 What are the differences between a data capture PLL, and a frequency
synthesizer PLL?
Ans. In data capture PLL only phase shift of the clock and data needs to be locked.
Frequency of data is assumed to be constant. Ex-or can lock phase very well with 90’
phase shift, which is desirable in digital circuits.
In frequency synthesizer PLL both frequency and phase needs to be locked. Ex-or
can not detect difference in frequency so 3 or more state PFD is required.

8.11 When should an XOR PD be used?

Ans. When only phase detection is required, i.e. data capture PLL.

8.12 What is Kvco, Kpd and how are they determined?

Ans. Kvco: gain of the VCO stage. It’s unit is MHz/volt.
Kpd: gain of the phase detector stage. It’s given by eq. Kpd = Ipump/(2*π)

8.13 What is the natural frequency of a PLL?

Ans. Wn = [ {Kpd * Kvco}/{N * C1}] ½ , Kpd = Ipump/(2*π), ξ= (Wn*R*C1)/2
Wn is a free running frequency, which is also known as natural frequency of PLL.

9 DLLs
9.1 How is a DLL different from a PLL?
9.2 Draw the block diagram for a DLL
9.3 How can a clock pulse of arbitrary position and width be
created using DLLs?
9.4 How can oscillators be designed with DLLs to generate higher
frequencies than the reference frequency?
9.5 Draw the schematics for a DLL delay block
9.6 What are the advantage of DLL referenced delay elements in a
opochip?
9.7 What are 5 applications of DLL referenced delay elements?
9.8 Does the number of DLL delay elements need be odd?

10 Current sources and sinks and references

10.1 Draw schematics for a current mirror.
Ans.

10.2 Why are cascade transistors used?

Ans. It reduces λ and hence, increases output resistance and reduces dependence of o/p
current on voltage variation.

10.3 Design a current reference using a single resistor

10.4 Draw the schematic diagram for a band gap voltage reference.
Ans.
10.5 How can a band gap voltage reference be used with an external resistor to
provide a precision current reference?
Ans.

10.6 Design a current mirror that will provide 3X the current Out vrs. Current in.
Ans.

10.7 How can currents be added and subtracted?

Ans.
10.8 Design a 3 transistor voltage divider providing Vdd/3 and 3/4Vdd using only N
transistors. Calculate device sizes assuming 100ua flows in the divider.
Ans.
11 Amplifiers
11.1 What conditions must be met for amplifier stability?
Ans. Gain must be less than unity at phase shift 180’ or higher.

11.2 Draw schematics for a source coupled pair amplifier.

11.3 What is the large scale transconductance of a differential pair?

Ans. Transconductance is approximated as constant only for small signal model. So, large
scale transconductance of a differential pair dose not exist.

11.4 For the following schematic of an amplifier, What is VMAX on input A when
A=B if Iss=190ua, Vdd=2.5V, W1,W2=22u/3u W3,4=72u/2u and W5=19u/3u? Assume
k’p=140u.

Vdd

m5

Vbias Iss

m1 m2
A B

m3 m4

Gnd

Ans.

11.5 What is CMRR (CMR) ?

Ans. It stands for Common Mode Rejection Ratio. It is a measure of an ability of the
differential amplifier to cancel out common mode voltages at its input terminals.

11.6 What is a source cross coupled pair amplifier? What are the benefits of it’s
use? Draw schematics.
11.7 What are the benefits of a current source loaded amplifier?
Ans. It gives same gain for both, true and compliment outputs. Here, gain depends on
λ.Id. λ varies very less with W & L. So, we can choose any width and length such that
circuit works.

11.8 Why cascaded current source loads are an improvement? What is a major
disadvantage of cascaded loads?
Ans. Cascaded current source load gives very high output resistance and hence very high
gain. But it reduces maximum output swing.

11.9 Draw the schematics for a current differential amplifier.

Ans.

11.10 What is a rail to rail amplifier? How can it be realized?

Ans. The amplifier that gives full output swing from Vdd to Vss is known as rail to rail
amplifier.
11.11 Draw schematics for an operational amplifier, and show where compensation
should be placed.
Ans.

11.12 What is the condition for stability in an OP Amp? How is the value of a
compensation capacitor calculated? What phase margins are traditional for
compensation?
Ans. To ensure stability in an Op-amp, gain must be less than unity at 180’ or higher
phase shift of o/p w.r.t. i/p.
We do not calculate the value of compensation capacitor but we choose arbitrarily
one and iterate several times until best performance is achieved.
PM is generally enough between 40’ to 60’ but to compensate for temperature and
process variations it is advisable to keep it around 80’ to 90’.

11.13 What is IOS?

Ans. IOS stands for Input Offset Voltage. It is measure of matching between two i/ps of
the opamp. It is the voltage difference that must be applied between two i/p terminals to
set o/p voltage at zero.

11.14 What is PSSR?

Ans. PSSR is another name of Power supply rejection ratio. It is measure of the ability of
the Op-amp to reject noise of the power supply voltage.

11.15 What is slew rate?

Ans. Slew rate is defined as the maximum rate of change of output voltage.

11.16 Why is a resistor added to a compensation network? What impact does it

have on the phase frequency plot?
Ans. Resistor is added to compensation network to shift zero near to high frequency
second pole. It improves phase margin and unity gain frequency of the op-amp.
11.17 What is an “instrumentation” amplifier? Draw schematics for a typical circuit.
Ans. An amplifier that dose not give loading effect to source is called instrumentation
amp. Schematic is shown in below fig.

11.18 What is “gain boosting” how can it be performed?

Ans. Method of increasing gain is called gain boosting. It is achieved by connecting
number of amplifiers in series (cascading).

12 Non Linear mixed signal circuits

12.1 Draw schematics for a comparator. Calculate device sizes. Show modifications
for a clocked comparator.
Ans.

a. Comparator
 b. Clocked Comparator.

12.2 How can adaptive biasing be used to improve the comparator?

Ans.

12.3 How can circuits be implemented that perform the ln,exp, square, and square
root functions?
Ans.

12.4 How can ln and exp functions be used to perform multiplication?

Ans.

12.5 How can square law circuits be used to perform multiplication?

Ans.
12.6 What must be done to the length to ensure the transistors approach the square
law curves?
Ans. Length should be increased.

12.7 Why are decision circuits used in comparators?

Ans. To make decision process very fast and efficient, we use decision circuit with
positive feedback.

12.8 Why is a two stage comparator used in most circumstances?

Ans. To reduce effect of kickback noise on inputs.

12.9 How is a clocked comparator implemented? Draw a typical schematic.

Ans.
12.10 What are the benefits of a clocked comparator over a static comparator?
Ans. Static comparator takes continuous decision, so very large voltage difference
between both the inputs is required to invert decision.
In clocked comparators, during decision phase it takes decision and during reset
phase it brings both the o/ps at same potential, so even a small difference between i/ps
can be sensed in next decision phase.
In short, clocked comparators have better speed and resolution than static one.

12.11 Draw circuits for a 2 input low voltage differential based CML circuit.
Ans.

12.12 What are the benefits and disadvantages of low voltage logic?
Ans. Low voltage circuits have lower power consumption resulting in lower heat
generation; hence on chip device density can be increased. So, small device sizes can be
implemented.
Noise signal doesn’t get any smaller so SNR degrades. And circuit design becomes
complex because of noise problem.

12.13 Draw schematics for voltage doublers, and negative voltage generators.
Ans.

12.14 How can a MOSFET replace a diode in rectification circuits?

Ans. By shorting drain and gate of the MOSFET as shown in below fig.

12.15 Draw the circuit for a peak detector circuit. How can a decay time constant be
added?
Ans.
13 Data converters
13.1 Why do converters have sample and hold circuits? What is the importance of
aperture time?
Ans. Converters have comparator array. During decision of the comparator, its i/p should
remain constant. To meet this requirement S/H is put before comparator array. It also
correct for clock skew in comparators. S/H offers very small capacitive load to i/p & drives
large capacitor of comparators.

13.2 Design a resistor string DAC.

Ans.

13.3 Design a R-2R D/A converter

Ans.
13.4 Design a switched capacitance D/A
Ans.

13.5 Design a switched capacitance A/D

Ans.
13.6 Design a current mode D/A converter
Ans.

13.7 Design a flash A/D converter

Ans.
13.8 Design a charge scaling D/A converter
Ans.

13.9 What is a Thermometer code? How is it important to D/A design?

Ans. A 2N bit representation of N-bit digital word in which only one bit changes if data is
incremented or decremented by 1, is called thermometer code. It reduces glitch power.

13.10 What is a pipelined A/D converter? Draw a block diagram.

Ans. In algorithmic ADC, instead of using one ADC with feedback, we can use multiple
algorithmic ADCs in pipeline, such as analog o/p is given to i/p of next ADC as shown in
given fig. Each stage will give one digital bit.
13.11 Why are multiple pipelined A/D converters combined?
Ans. To get very high conversion speed, multiple pipelined ADCs are combined.

13.12 How does an over sampling or Delta Sigma A/D work. Draw a block diagram.
Ans.

13.13 Why are fully differential circuits typically used in SC ADCs? What problems
do they overcome?
Ans. It removes error on o/p due to charge injection. It cancels common mode voltages,
so gives better noise cancellation. It removes error due to parasitic capacitance.

13.14 How are compensated and self calibrating ADCs typically constructed?
Illustrate with a block diagram.
Ans.

13.15 What voltage could a N bit converter discern if the Vdd is 2.5V, and N=10?
Ans. Voltage= Vdd/2N.

13.16 What is DNL?

Ans. DNL is defined as the deviation of the vertical step between adjacent o/p from its
ideal values.

13.17 What is INL?

Ans. INL is defined as the maximum deviation of the ADC transfer curve from a straight
line connecting its end points.

13.18 What is Gain Error?

Ans. The difference between ideal and actual gains is called gain error.

13.19 What is SNR?

Ans. SNR is the ratio of signal power to noise power. For better performance higher SNR
is desirable.

13.20 What is ENOB? How is it determined?

Ans. ENOB stands for Effective Number Of Bits. It is defined as
ENOB = SFDR/6.02 dB/bit, SFDR = Spurious Free Dynamic Range.

13.21 What does monotonic increasing mean?

Ans. Non-decreasing output with i/p codes is called monotonic increasing.

13.22 Why are guard rings included in D/A and A/D designs?
Ans. To prevent noise generated by digital section to be coupled with analog section.
In converters clock is the major source of noise, so it is required to shield it in order to
prevent its noise to be coupled with substrate.

13.23 What is glitch energy?

Ans. Energy contained in the glitch is called glitch energy.

14 I/O Buffers
14.1 Draw an ESD circuit. Explain how it works.
Ans. The diodes D1 & D2 are used as clamping devices, which clamp the i/p from
Vdd+Vd to Vss-Vd values. If the i/p increases above that value, the diodes turn on
allowing the access voltage to go to Vdd or Vss. As D1 and D2 turn on time is high, it
allows high frequency i/p to go through. So, we have a RC circuit to slow i/p. D3 and D4
diodes are used as cap.

14.2 Why is guard rings used in I/O design? Draw the latch up devices, and show
their origin on a chip view.
Ans. Guard rings are used in I/O design to prevent latch up. The latch up circuit is created
in CMOS devices as shown in fig. The resistors so created generate a positive feedback
which latches up a CMOS device. So, GR are used around the R’s to limit current. GR are
added to buffers driving o/p buffers, too.

14.3 Size transistors for output drive requirements. Design for multiple drive
strengths.
Ans.

14.4 Show how Tri-state can be implemented in I/O design.

Ans.

14.5 How is large cross over current eliminated in I/O design?

Ans. Cross over current is generated in I/O buffer when there is a switching between
NMOS and PMOS. During this period, both of them are momentarily on, which allows
large current to flow between Vdd and Vss. This can be avoided by driving them
separately such that they are not on at the same time as shown in fig.(b).
 Fig.a

Fig.b

14.6 How is high speed buffers implemented? Why are driving fixed impedances
important?
Ans. It is important to drive fixed impedance to avoid reflections at buffer.
14.7 What is SWR? How does it impact buffer design?
Ans. SWR stands for Standing Wave Ratio. It is defined as the ratio of the maximum
amplitude to the minimum amplitude of a standing wave.

14.8 Why must high speed busses be terminated in a characteristic impedance?

Ans. To prevent reflections generated by ends of high speed busses.

14.9 Show schematics for a two wire high speed driver.

Ans.
14.10 Show schematics for a high speed receiver.
Ans.

14.11 How is common mode voltage injected in a differential driver?

Ans.
14.12 What functions do mixers, scramblers, bit stuffers perform in an I/O system?
Why are they needed?
Ans. Mixers: They perform signal multiplication and thus it shifts input frequency by
reference frequency i.e. fin+fref & fin-fref.
Scramblers: They encode n bit input data to m bit o/p data (m>n) in such a way that o/p
data freq. stays at desired frequency range.
Bit Stuffers: It stuffs unique bits in data to maintain desired data width while keeping its
frequency in required range.

Basically all of them are used to shift data frequency to desired range.

14.13 What is the purpose of 4/5 or 8/10 recoding?

Ans. Both of these recoding are used to shift data frequency in desired range so that it
dose not fall in notch range of i/o buffer.

14.14 How can non-data control codes be transmitted and detected?

Ans. By recoding we get some good bit patterns that never occur in data. We can use
them as control codes. And as it is not used in data, it can be easily detected.

14.15 What are the purpose of idle or sync patterns in high speed I/O?
Ans. PLL has a finite capture time. So we need to send some idle or Sync pattern, to lock
PLL before sending data.

14.16 How are good sync patterns determined?

Ans. By using recoding and identifying good bit patterns that are not used for data, good
sync patterns are determined.
14.17 Why must I/O operation be delayed after starting a high speed channel? What
operations take time to perform?
Ans. First idle pattern is sent to lock PLL in center of the data. 3-5 Sync packets are sent
to indicate start of data. Then control patterns are sent. After that data is sent. Because of
the above procedure I/O operation must be delayed after starting a high speed channel.

14.18 Why is data often sent in 32 or 64 bit units over high speed I/O systems?
Ans. Data is broken in packets of 32 or 64 bits and sent on multiple channels to enable
low frequency I/O operation, while maintaining same data operation speed.

14.19 Why is data grouped into “packets” in many high speed I/O systems?
Ans. Look ans. 14.18

14.20 Why are high speed I/O systems typically not bidirectional? What happens if
the signal direction is reversed?
Ans. PLL takes time to be locked every time the data direction is reversed. That slows
down the speed of operation which is not possible in high speed operation. If data
direction is reversed suddenly, it will result in data loss.

14.21 How is clock information transmitted in high speed I/O systems? What are the
benefits and disadvantages of separate clock transmission?
Ans. In high speed I/O systems, clock information is transmitted on separate line. It allows
low frequency clock transmission. Clock and data have to be aligned properly.

14.22 What impact does I/O buffer resonance have on high speed I/O design?
Ans. There is a notch in I/O buffer frequency response at resonance. Therefore, we have
to maintain data frequency above resonance frequency of I/O buffer to prevent data loss,
which requires recoding of the data.

15 Current mode analog

15.1 Draw schematics for current mode circuits that add, subtract, multiply, and
divide.
Ans.
15.2 Draw schematics for a current mode integrator.
Ans.

15.3 Draw schematics for a current mode inverter and 2 input NOR gate.
Ans.

15.4 Draw schematics for a current mode comparator.

Ans.
15.5 Why is cascade devices used in current mode circuits?
Ans. To reduce effect of λ on the results. It gives higher gain and output resistance, and
makes current less dependent on change in voltage.

15.6 How can an amplifier be used to reduce drain voltage variations?

Ans.

15.7 What are bias currents? Why are they used? Show examples.
Ans. Bias currents are the fixed currents applied to the circuit, which are used to offset o/p
current to a fixed value.
15.8 What are advantages of SC circuits over Switched Current (SI) circuits?
Ans. SC circuits are more accurate. Capacitor ratios match up to 0.1 % while transitor
matches up to 5 %. Capacitance has very small value of temperature coefficient.

15.9 What are advantages of SI circuits over SC circuits?

Ans. It takes very small area as compared to SC. It is very fast as compared to SC
because capacitor charge-discharge takes finite time. SI circuit can be made to operate at
very small voltages.

15.10 Why are switched current circuits typically faster than switched capacitor
circuits?
Ans. Charge-discharge process of capacitor takes finite time, so switched current is
typically faster than switched capacitor circuits.

15.11 How can digital current source matching be implemented? Draw a circuit to
illustrate.
Ans. Instead of making current sources of different values, we make minimum value
current and use them in parallel to get desired current value.

15.12 Why is current mode analog interesting in future very deep submicron
processes? What fundamental limits can it help overcome?
Ans. In deep submicron processes voltages are very small. So voltage mode operation
will suffer from very poor SNR. So it will help to overcome problem of SNR as well as Vt.

15.13 Size transistors for a current mode analog device designed to operate at a
given supply voltage.
Ans.

16 Switched Capacitor circuits

16.1 Draw circuits for a SC resistor equivalent
Ans.

16.2 What is the benefit of a SC resistor over a poly resistor?

Ans. More accurate. Very small size. Device value can be changed without changing
physical dimensions. Temperature independent.

16.3 How can the resistance of a SC resistor be made larger?

Ans. SC resistor value is given by R = (1/fC). By decreasing value of switching frequency
f, value of R can be made larger.

16.4 How can the capacitor size of a given SC resistor value be made smaller?
Ans. R= 1/fc. For given value of resistance, cap size can be decreased, by increasing
switching frequency such that R remains unchanged.

16.5 For a given resistance and frequency, calculate a SC capacitance size.

Ans. R= 1/fc
16.6 Calculate SC RC single pole circuit values at a given frequency.
Ans. Fc= 1/(2πRC).

16.7 How can a SC resistor be made to have a negative value?

Ans.

16.8 How can differential circuits cancel parasitic capacitance?

Ans. Fully differential SC circuits are built with one circuit and horizontally flipped over
duplicate. So, error in voltage due to parasitic capacitance is same on both the terminals.
Due to its ability to cancel common mode voltage, differential circuits cancel parasitic
capacitance.

16.9 What switching rates are typical for a SC circuit?

Ans. 100 to 1000 times the maximum input frequency.

16.10 What is the equation for a simple SC resistor?

Ans. R=1/fc.

16.11 How can the frequency response of a SC filter be changed without altering
any physical devices?
Ans. By changing value of RC time constant, response of filter can be changed. In SC
circuit by changing switching frequency, value of R can be changed. And thus response of
SC filter can be changed without altering any physical devices.

16.12 Draw the circuit for a charge mode integrator and explain how it works.
Ans. 1) At the starting of operation, rst is closed to discharge C2.
2) Switches ϕ1 and ϕ2 are not overlapping.
3) First ϕ1comes and charge Q1=Vin.C1 is put on C1.
4) Then ϕ2 comes and whole charge on C1 is transferred to C2. C2 holds the charge
during next ϕ1. And C1 gets new charge.
5) And this cycle continues. Here C2 works as a charge accumulator. Thus integration
operation is performed.
16.13 Draw the circuit for a charge mode voltage multiplier and explain how it
works.
Ans. 1) In ϕ1, Q1=C.Vin is put on C. and C/M is discharged at the same time.
2) During ϕ2 whole charge on C is transferred to C/M.

Now voltage across C/M becomes, Vout = -Q1/(C/M) = - C.Vin.M/C = -M.Vin

Here, inversion in polarity is because charge on C is given to inverting terminal of
the opamp.

16.14 Draw the circuit for a resistive SC amplifier, and explain how it works.
Ans.
16.15 Why are output S/H circuits often required in charge mode switched capacitor
circuits?
Ans. In some SC circuits o/p is required to reset during certain phase. To prevent this to
appear at o/p, o/p is sampled by S&H circuit before o/p of SC circuit takes undesired value
and holds it until next valid o/p comes.

16.16 How can digital capacitor matching be implemented? Draw schematics of an

example to illustrate.
Ans. Capacitors can be matched by breaking them in smaller pieces and arranging them
symmetrical manner.