ECE 351 Table of Contents PDF

ECE 351 NOTES & TEST Questions
Table of Contents

April 2
April 4
April 9
April 11
April 16
1. 4 to 1 mux using dataflow description
2. 4 to 1 mux using data flow with conditional operator
3. 4 bit full adder using dataflow statements
4. Diagram and verilog code for 4 bit ripple counter
5. Edge triggered d flip flop made of 3 SR latches
6. Edge triggered t flip flop that toggles every second
7. Definition of testbench and notes on testbench purpose
8. Not everything in behavioral is synthesizable. You don’t synthesize testbenches
9. Behavioral models 2 structured procedures. Initial & always statements. Observations.
10. Syntax for initial statements.
11. Example of initial statement keywords in sequential block
12. Example of initial statement and timing
13. Description of always statement. Operates in continuous loop. Very important.
14. Reg variables only assigned value when declared or inside initial or always statement.
15. Always statement example with timing.
16. Always statement example showing timing
17. Two kinds of assignments, blocking and non-blocking, syntax and details.
18. Example of blocking and non-blocking statements used.
19. Rules for blocking and non-blocking assignments
20. Example showing a #delay on a line by itself. Shows expressions with delays.

April 18
1. Midterm 1 study guide
2. Timing controls with initial and always statements and delays as variables
3. More examples of delays being saved into variable names
4. Delays with blocking and non-blocking statements. Shows timing results
5. Writing testbenches, gives syntax, blocking and non-blocking example
6. Final case showing timing from non-blocking example with timing output.
7. Generate specific timing using a non-blocking assignment.
8. Summary of blocking assignments, non-blocking assignments, and delays
9. Event control using the @ symbol. Level and edge triggered control
10. Edge triggered events with posedge and negedge keywords
11. Regular event control example with posedge and negedge controls.
12. Example showing event controls being operated on with the ‘or’ operator
13. Event control example with level sensitive latch and asynchronous reset.
14. Example of event control using the * (star) operator as a wildcard
15. 2 examples of conditional statements and a nested if-else-if statement.
16. Another example of conditional and if-else statements
17. Syntax for the case statement in verilog
18. Example showing keywords used for the case statement in verilog
19. 4 to 1 mux example with a case statement
20. Variations of the case statement including casez and casex
21. Example comparing case and casex.
22. Another example showing the usage of casex
23. Full module example showing a demultiplexer with case statement using x and z.
24. Definition of loop types in verilog. While, for, repeat, and forever. Syntax in verilog.
25. Large example showing the while loop being used.
26. Short example showing a for loop in an initial statement used as a counter.

April 23
1. Long example of a while loop being used
2. Short for loop example again.
3. Syntax for repeat loop shown
4. Short example of repeat loop used as a counter
5. Two examples of the forever loop being used.
6. Example showing 2 reg values, or variables, being synchronized
7. Definition of parallel blocks. Notes on parallel blocks and fork and join keywords.
8. Example of a sequential and a parallel block side by side. Uses fork and join keywords.
9. 4 to 1 mux example with always statement and case statement.
10. Behavioral 4 bit counter example with always statement and posedge and negedge.
11. Finite state machines example diagrams for mealy and moore.
12. Example showing a bitstream that is being modified with a finite state machine
13. Long example of a moore finite state machine.
14. Block diagram showing how a mealy state machine works.
15. Long example of a mealy finite state machine.
16. Short explanation of doing one hot encoding for a FSM or finite state machine.
17. Tasks and Functions, description. Declared in the module that they are used in.
18. Good table showing the differences between tasks and functions. Input, output, inout

April 25
1. Tasks, definition and properties, syntax for using. Tasks called from initial or always
2. Notes on tasks. Default type is reg. Ports in modules vs ports in tasks. What operates on
3. Direct operation on reg variables example. Tasks called and task template shown.
4. Input and output arguments example using tasks. Uses connection by position.
5. Another note on tasks. Keyword automatic makes the task re-entrant
6. re-entrant , automatic, task example
7. Description of what can and cannot be in a function.
8. Function syntax is described and return values discussed.
9. Example of function used with a function template and register to store values.
10. Basic example showing how a function is called by a module.
11. Example with a module that contains a function for a parity calculation.
12. Example for a left-right shift register. Uses a function and a function template.

April 30
1. Usual way of doing assignments is LHS = RHS. Override these existing assignments with
procedural continuous assignments. Two types, assign/deassign and force/release.
2. Assign and Deassign constructs now bad coding style. Use force and release instead.
3. Example using force and release to force a particular value at a time interval.
4. Example showing how to force and release nets.
5. Large example showing force and release of a net in a testbench with timing output
6. Large example showing force and release of a reg in a testbench with timing output
7. Module instance parameter values. Can reuse modules with these. HDLs allow it.
8. Example showing the use of module instance parameter values.
9. More examples showing the use of parameters in modules.
10. Timescales in simulations. Shows the syntax and notes on how timescales work.
11. Example of timescales being used.
12. $dislay, $monitor, $strobe how to use each and what they do in your code.
13. Example using the $strobe
14. Opening a file in Verilog. Closing a file in Verilog.
15. Example showing how to write to files in Verilog.
16. Example showing how to initialize memory using the $readmemb and $display
17. Example for a 3-bit adder reading from a file using $readmemb
18. Value Change Dump files (VCD), Verilog source level debugger. Definition.
19. Block diagram showing debugging and analysis of the simulation with a VCD file.
20. Example showing how a VCD file is created using the $dumpfile, $dumpall, $dumpvars
21. Other VCD file system tasks. $dumplimit, $dumpvars
22. Example with timing for $dumpvars
23. Another long example with timing for $dumpvars.

May 2
1. Definition of project. Definition of wizard. In reference to a synthesizer.
2. Definition for synthesize. Converting a high level description into a netlist.
3. Block diagram of the basic computer aided logic synthesis process. With feedback loop
4. Table showing what Verilog HDL constructs are used in logic synthesis.
5. All delays are ignored, simulation results do not equal synthesized results.
6. Block diagram showing logic synthesis flow from RTL to gates.
7. ASIC synthesis block diagram. Description of ASIC library standard cells and macros
8. Large diagram of the standard cell design
9. Example of comparator with smallest propagation delay possible. (tpd) Area and tpd are
inversely proportional.
10. Chart showing the area of the fabric used for designs with high speed.
11. RTL description example for a magnitude comparator.
12. Example showing the use of library cells
13. A gate level schematic for a magnitude comparator.
14. Example verilog program for a magnitude level comparator.
15. Example showing a gate level description for the magnitude comparator.
16. Example showing the magnitude comparator using a library.
17. Timing verification. Used to check the gate level netlist for timing constraints.
18. Design checkout or proof. 70% of design effort is now in verification.
19. Managing complexity. Always separate the datapath from the control path.
20. Structure the data path. Notes on how to do this. Identify control points, functional units
have control/status signals (coded control points)
21. Determine a control strategy. FSM example of a counter. Block diagram for this.
22. Determine reset strategy. What gets initialized and what is the initial value. Notes.
23. GREENWOODS FIRST LAW, Always design before coding.

May 7
1. Definition of partitioning. Process of dividing design into modules. Design hierarchy
2. Example showing partitioning of an ALU. Easier to optimize small bit circuitry.
3. Example showing vertical partitioning of a 4-bit ALU. Easier to optimize individual
functions.
4. General rules for partitioning. Definition of critical paths, slowest combinational logic
path between registers.
5. Continued notes on critical paths. Potentially sharable resources should be in the same
path. Example showing the sharing of resources.
6. Keep modules as small as possible
7. Simple module using input and output only
8. Simple module using blocking assignment and gate results.
9. Simple module using non-blocking assignment and gate results
10. Another module using non-blocking assignments and the gate results
11. Example showing a bit shift and the resulting gates
12. Another bit shift example with gate output
13. Example module with gate output using bit arrays. (constant bit select)
14. Non constant bit-select example. Shows output of a multiplexer.
15. Example of a module that outputs a decoder.
16. Example of a module that outputs a mux or multiplexer
17. If-then-else code synthesizes as a multiplexer with example code
18. Latch inference with 2 examples of why it happens
19. Example code for latch inference, bad
20. Example code that eliminates latch inference with gate output
21. Another example of avoiding latch inference using a pre-assignment
22. Example of avoiding latch inference using a full_case synthesis directive
23. Example of when using a synthesis full_case makes more sense
24. Example code showing no full_case used and gate output
25. Example code showing full_case used and better gate output
26. Priority encoder using an if-else statement
27. Priority encoder using a case statement
28. Priority encoder using a synthesis directive
29. Example of gate output if an if statement is used in a loop
30. LAW for when to use blocking and non-blocking assignments. Blocking for
combinational logic, non-blocking for sequential logic.
31. Example showing blocking assignments used and gate output
32. Same example showing non-blocking assignments and why they need some sort of
storage when used this way.
33. Example and schematics for using blocking and non-blocking with posedge. Shows
different results.
34. Block diagram for modules with assumed clock periods.

May 9
1. Lattice general coding styles for FPGA
2. Lattice design partitioning
3. Lattice state encoding methodologies for state machines
4. Lattice state encoding methodologies for state machines
5. Lattice Coding styles for FSM
6. Lattice Coding styles for FSM
7. Lattice using pipelining in designs
8. Example showing pipelining and the timing results. This is why registered outputs are
useful.
9. More details on the timing after using registers on the outputs. Shows speedup
10. Lattice coding styles with if-then-else notes. Talks about latch inference.
11. Lattice FPGA synthesis libraries
12. Lattice implementing multiplexers, clock dividers
13. More clock dividers
14. Lattice register control signals and clock enable
15. Lattice set and reset
16. Lattice use PIC features. Moving registers or latches into input/output cells
17. Lattice bidirectional IO and other IO types. Specifying IO types and locations
18. Lattice implementation of memory.
19. Lattice preventing logic replication and limited fanout
20. Xilinx basic HDL coding video. See slides from videos section.
21. Instantiation vs inference. Definitions and advantages/disadvantages.

May 14
1. Diagram of 2-4 decoder with output polarity control
2. Diagram of 8x4 rom that can be used to build the decoder.
3. Any boolean equation can be implemented with an appropriate size memory chip. LUT
(look up table) is defined. Shows ROM diagram
4. Diagram of the FPGA fabric, configurable logic blocks (CLB) IO pad
5. Logic synthesis slides - VHDL description and circuit netlist
6. Logic synthesis slides - circuit netlist, devices used and their interconnections
7. Logic synthesis slides - mapping of the netlist
8. Logic synthesis slides - placing of the netlist on the fabric
9. Logic synthesis slides - routing if the interconnects on the fabric. Programmable
connections.
10. XILINX Spartan FPGAs Datasheet - introduction
11. XILINX Spartan FPGAs Datasheet - general overview
12. XILINX Spartan FPGAs Datasheet - Logic functional description, CLBs, function
generators
13. XILINX Spartan FPGAs Datasheet - flip flops latches clock input, clock enable set/reset
14. XILINX Spartan FPGAs Datasheet - CLB signal flow control, control signals, Input/output
blocks
15. XILINX Spartan FPGAs Datasheet - continued IO blocks
16. XILINX Spartan FPGAs Datasheet - IO blocks signal path
17. XILINX Spartan FPGAs Datasheet - output buffer and pullup pulldown networks
18. XILINX Spartan FPGAs Datasheet - set/reset independent clocks, clock enables routing
channel description
19. XILINX Spartan FPGAs Datasheet - routing channels diagram
20. XILINX Spartan FPGAs Datasheet - double length lines, long lines, IO routing, Global nets
and buffers.
21. XILINX Spartan FPGAs Datasheet - CLB routing channels, CLB interface, Programmable
switch matrices with good diagrams.
22. XILINX Spartan FPGAs Datasheet - Advanced features, distributed RAM, memory
configuration, single port mode, RAM signals.
23. XILINX Spartan FPGAs Datasheet - on-chip oscillator, Global set and reset (GSR), Global
3 state (GTS), boundary scan,
24. XILINX Spartan FPGAs Datasheet - Data register and instruction set with boundary scan
diagram.
25. XILINX Spartan FPGAs Datasheet -
29. Intellectual property definitions. IP, soft IP, Hard IP
30. Sources of IP, user, vendor supplied IP, and 3rd party IP
31. XILINX binary counter datasheet - Vendor supplied IP
32. XILINX binary counter datasheet- Vendor supplied IP
33. Lattice encoder decoder datasheet - Vendor supplied IP
37. Art Silicon - 3rd party IP example
43. Art Silicon - 3rd party IP example - how to used in your HDL code
44. Art Silicon - 3rd party IP example - generator and checker
54. XILINX Video Slides - Title
55. XILINX Video Slides -benefits of using IP cores
56. XILINX Video Slides - types of cores
57. XILINX Video Slides - Vendor core options
58. XILINX Video Slides - 3rd party IP core options
59. XILINX Video Slides - sample functions you can get
60. XILINX Video Slides - Core generator software system (GUI)
61. XILINX Video Slides - customize window
62. XILINX Video Slides - datasheets
63. XILINX Video Slides - Generate or purchase a core
64. Wrapper files, how they are used to call an IP core to use in your program.
65. IMPORTANT, you don't synthesize wrapper files.
66. XILINX Video Slides - Summary of slide deck

May 16
Fpga implementation
How to use ip cores or other IP in your designs
Datasheet on configurable logic blocks
28. Distributed RAM
31. Inferring block RAM in a Xilinx fpga.;
37. Implementation in BRAM
42. To infer ROM in BRAM, you must register either the output or the address.
45. Finite state machines in block RAM (BRAM)
47 LUT structure minimizing flip flop complexity. How to infer an SRL 16 input LUT
May 23 (NOT PRINTED!!! LOOK AT THE PDF)
Synplicity FPGA synthesis - not covered on final
Page 85 gets into virtex and tcl scripts
87 gets into using tcl scripts to try different clock frequencies.

May 28
1. How to configure an FPGA for xilinx. How do I program those flash memories if they are
soldered to a board? Use JTAG. Indirect programming of BPI PROMs with VIRTEX 5
application note
2. Definition of FPGA image - a binary file that’s the programming data for the FPGA. There
is a note with what is contained in the image. Config bitstream, programming bitstream,
and bitstream.
3. Datasheet showing sizes of flash chips required for different bitstreams
4. Diagram showing how FPGAs are programmed with a PCB and mode pins
5. Datasheet of configuring FPGAs from a SPI serial flash
6. JTAG - joint test action group. JTAG programming of FPGAs. Always provide a JTAG
interface on any FPGA design.
7. Boundary scan register diagram
8. Block diagram showing programming with boundary scan registers
9. Virtex tap controller pins needed for JTAG programming
10. Diagram Showing test logic and state transitions.A state diagram for the TAP controller.
TMS is the FSM input
11. TAP controller step description datasheet.
12. Platform cable USB II datasheet. Also called “Downloaded cabes” device used for
programming FPGAs and PROMs
13. Goes through page 18
19. Indirect programming of BPI PROMs with Virtex 5 FPGAs.
20. Need a special IP module downloaded to the FPGA. THis IP converts JTAG instructions
into the command/control signals needed to program the flash memory. After
downloading the bitstream, the FPGA will read the flash to configure itself.
21. Lattice SPI serial flash programming using ispJTAG on Lattice ECP/EC FPGAs
22. Configuration codes
23. SPI serial flash interface, pinout, ispJTAG interface.
24. Downloaded Header pinout
25. Hardware schematic for connecting the ispJTAG connector FPGA and serial flash
26. How to include the SPI interface in the FPGA design.
27. Sample code for including the SPI interface in your FPGA design.

May 30
Pages 1-20 are the Virtex 5 configuration guide. Page 1 has a good table of contents for this
datasheet guide.

21. Global timing constraints powerpoint
22. Shows the effects of timing constraints. Mapping of FPGA showing where the design is
located on the fabric. With global timing constraints and without global timing
constraints. Shows I/O vs internal timing differences.
23. Timing constraints define your performance objectives. Timing constraints define your
timing objectives. Unrealistic timing constraints will cause the tools to stop. After
implementing review the post place and routing static timing report to determine if your
objectives were met.
24. Path endpoints are - IO pads, synchronous elements like FFs latches Rams DSP slices
SRLs etc. Path endpoints do NOT include LUTs nets or any other asynchronous
elements
25. Creating timing constraints, step 1 create groups of path endpoints. Step 2 specify a
timing requirement between the groups. Global timing constraints use a default grouping
of path endpoints which makes it easy to constrain your design.
26. Period Constraint covers paths between synchronous elements on a single clock
domain. Shows example with FF and CLK
27. Period constraint - uses most accurate timing information. Considers clock skew
between the source and destination flip flops. Synchronous elements clocked on the
negative clock edge. Unequal clock duty cycles. Clock input jitter the implementation
tool uses this to place and route design.
28. Examples of period constraint and timing
29. Clock input jitter - xilinx tool allows for setting tolerance of clock jitter
30. Offset in/out constraints - shows diagram with what is included for both in and out
offset constraints
31. Offset in/out constraints with formula for calculating the clock delay and total effective
input and output delay
32. Offset constraints reporting example. Shows the timing analyzer output.
33. Apply your knowledge question with paths constrained by different clock signals.
Diagram shows the design.
34. Launching the constraints editor.
35. Entering a Period constraint
36. Multiple UCF files
37. Period constraint options
38. Entering Offset constraints
39. APPLY your knowledge question - Given the diagram, what would you put in the
constraints editor so the system would run at 100MHz?
40. Answer shows the timing needed to do this.
41. Summary slide - performance expectations are communicated with timing constraints,
the period constraint covers delay paths between synchronous elements, the offset IN
constraint covers delay paths from input pins to synchronous elements, the offset OUT
constraint covers delay paths from synchronous elements to output pins, use the
constraints editor to create timing constraints.
42. Verification diagram. What is verification - design meets functional intent. Timing
closure is proof that the design meets the timing restrictions. Test is proof that the
design is manufactured without flaws. EDA vendors claim that 70% of design effort is
now verification.
43. Timing closure definition. - Timing closure is a process whose purpose is to make sure
that after PAR (Place and route) all timing constraints (register setup and hold times)
have all been met.
44. Timing closure document from Xilinx
45. Diagram - flow chart showing all the steps involved in timing closure
46. Max performance ratings of different FPGA lines
47. Performance estimates shows a formula for calculating the delay. Talks about logic
levels and if you have more of them it impacts the speed of your design.
48. Performance estimates showing another formula for this. Talks about the 50/50 rule for
performance.
49. Performance estimates - most experienced designers design at 2 logic levels
50. Pin planning showing images of a designs usage of the FPGA fabric
51. Using the core generator - cores are optimized componentes, increase design
performance
52. Diagrams of placement with and without global timing constraints
53. Timing constraints define your performance objectives. Unrealistic constraints cause the
tools to stop. Review the post place and route static timing report to determine if your
objectives were met.
54. Timing constraints - the period constraint defines the max allowable internal delay
between two synchronous elements, the offset in constraint covers your input pin to
synchronous element delay paths. The offset out constraint covers your synchronous
element to output pin delay paths.
55. Analyzing post place and route timing. Many factors that contribute to timing errors like
poor micro architecture, neglecting synchronous design rules or using incorrect HDL
coding style, poor synthesis results (too many logic levels), inaccurate or incomplete
timing constraints, poor logic mapping or placement. - Each root cause has a different
solution, rewrite HDL code, ensure that synthesis constraints are correct and use proper
synthesis options, add path specific timing constraints, resynthesize or reimplement
with different software options. Correct interpretation of timing reports can reveal the
most likely cause.
56. Case 1 timing report example
57. Answer
58. Poor placement solutions - Increase placement effort level (or overall effort level), PAR
extra effort or smartXplorer, area constraints with the PlanAhead tool
60. Answer
61. High Fanout solutions - most likely solution is to duplicate the source of the high fanout
net.
63. Answer
64. Too many logic levels solutions - implementation tools cannot do much to improve
performance. The netlist must be altered to reduce the amount of logic between flip
flops
65. Diagrams showing replacement of registers to reduce fanout
66. Synthesis options that can help you obtain your performance and area objectives.
Timing driven synthesis, FSM extraction, Retiming, register duplication, hierarchy
management, resource sharing, physical optimization.
67. Timing closure is a design activity not an automatic activity. Summary of timing closure
skills and strategies.

Jun 4
1. Scripting VS system programming languages - designed to handle different things.
System programming language designed to manipulate complex data structures and
algorithms. Scripting languages designed to manipulate data, like read a file or an I/O
device
2. System program language compiled, scripting language is interpreted. Examples of both
kinds of languages. Definition of tcl scripts. Tool Command Language. Called tickle. TK
is a toolkit for creating graphical I/Fs
3. Tcl is the predominate scripting language in the EDA field. Built in commands for doing
file I/O, procedures for controlling tasks (synthesis, PAR, etc.), Xilinx has adopted Tcl as
the native scripting language for Vivado.
4. From MACos type tclsh in a command window. Basic syntax for Tcl shown here.
5. Continued Tcl script syntax
6. Other features of Tcl - control structures, storage manipulation, I/O, manipulate lists,
arrays, wait for events. Definition of script - an ASCII file containing a sequence of Tcl
commands.(*, tcl extension)
7. Project vs Non-project - Project mode is GUI based, automatically manages the design,
project file and directory is created ON DISK, source files copied to the directory, results
automatically stored, only default reports are stored,
8. NON-project mode - Tcl based, you manage the design process, compiler type
performance, only writes what you specify to disk, you determine what reports are
generated.
9. In NON-project mode, if you modify HDL code, must rerun the script file. Any reports
must be explicitly stored (timing). Parameter and implementation options invoked with
Tcl commands. You can save design checkpoints at any stage of the process.
10. Table summarizes features between project and non-project mode
11. Diagram showing how to use GUI in project mode - different Tcl commands for adding
files in project vs non-project mode
12. Tcl glob command - glob returns a list of things that match some pattern. Example
given.
13. Xilinx non-project mode Tcl script example - long
14. Launching the Vivado design suite Tcl Shell and tools using a batch Tcl script.
15. Computers are ubiquitous - information processing examples (word processor
spreadsheets) Control examples (household appliances, automobiles, aircraft)
16. Computers are either visible (pc’s laptops, mainframes) or Non-visible (embedded
systems running embedded software) Definition of embedded system - A computer
system completely enclosed inside the physical system in controls. End user is not
aware that a computer is present.
17. Characteristics of embedded systems - limited computing power, memory, power size
weight constraints etc.
18. Embedded vs desktop computer sales.
19. Useless picture
20. Microblaze - a full-blown microprocessor that is IP from Xilinx. This is a microprocessor
that is fully implemented in the FPGA fabric.

Slides From Videos

Midterm 1
1. Which of the following are synthesizer inputs
Verilog program source files, user constraint files, component library files (all of the
above)
2. One of your fellow students says “netlists are technology independent” do you agree
Yes
3. Consider the following partial program. Which of the following is correct
xor(y,a,b);
and(a,b,c);
or(r,y,c);
r = ((c . b)xor_symbol b) + c
4. What is the purpose of simulation
To verify the design meets functional specifications
5. Which of the following is preferred when instantiating modules
Connection by name
6. Consider the following partial program. What is the problem with it?
re-Declarations must be the same size as the original declaration
7. An EDIF file is
A netlist file
8. Parameter statements are used to declare variables and assign them values at run time
False, it assigns them values at compile time
9. How are values assigned to net variables
With continuous assignment statements and when driven by module output.
10. The purpose of HDL is
To describe a digital design that can be synthesized
11. Instantiation
NONE OF THE FOLLOWING (is only done in test benches, can only be done as a part of a
port list, is not used in gate level of abstraction modules)
12. When does the LHS of a continuous assignment statement update
Everytime a variable on the RHS changes value
13. Suppose A = 4’b1101. What is the value of Y?
Assign Y = A >>2;
4’b0011
14. Which of the following accurately describes the RTL model
The model shows data movement and no details about the control structure
15. Design flow refers to
All of the steps involved in going from a specification to a programmed devise
16. RTL coding refers to what level of abstraction
Dataflow and behavioral, not gate level.
17. The output of one module is connected to the input of another module. Which of the
following declarations are correct.
The output ports can be reg or net
18. Suppose A = 4’b1010, B = 4’b110z. Y is the result of a binary operation on A and B. If Y
= 1, which of the following was the most likely operation
&
19. Let A = 4’h2 and B = 1’b0. What is the value of V = {{A}, 2{B}, {A}}
NONE of the ABOVE, 10’b0010_000001, 16’b0010_00000000_0010, 16’d22
20. notif0 describes
A tri-state inverting buffer with an active low control

Midterm 2
1. An if -else- statement is synthesized as
A multiplexer
2. What does partitioning a design do?
Divides a design into modules
3. A VCD file
Can contain timestamped signal transitions of selected signals during a simulation
4. Blocking assignments are recommended for combinational logic
TRUE
5. Which of the following prevents priority logic from being synthesized
A case statement with a parallel_case synthesis directive
6. Which of the following is true with respect to tasks
They can contain event controls and they do not require arguments.
7. You want to display a specific signal value everytime it changes. You should use
$monitor
8. Which of the following are not synthesizable
Case_equality statements
9. One of your fellow classmates says “initial statements are always synthesizable” do
you agree
NO
10. Which of the following is recommended coding style?
Register, the module outputs, use connection by name whenever possible, write module
templates to support module instance parameter overriding
11. Lattice Semiconductor recommends FSMs be
One-hot encoded if the number of states is large
12. Why is it recommended that module outputs be registered
It simplifies the timing analysis
13. Consider the following code segment:
And U11(y,b,a);
Initial
Begin
A = 1’b0;
B = 1’b1;
#5 force A = 1’b1
#7 release A;
#8 $finish;
end
When does y = 1?
Between 5 and 12 time units
14. When is the system task $readmemh used for
Reading hex data from files
15. What causes latch inference
Using a variable on the RHS of an expression before it is given a value, using an
incomplete if-then-else statement, and using a case statement where not all possible
values of the case statement argument are assigned a value. (ALL OF THE ABOVE)
16. Functions and tasks declared in one module are globa. That is they can be called in any
module in the design.
FALSE, they are not global
17. It is often the case that simulation results do not equal synthesis results. Why not?
#delay statements are ignored by synthesizers, synthesis directives cannot be simulated
18. When using a case statement to code one hot finite state machines a default statement
can prevent latch inference, but that method is not recommended. What is a better way
to prevent latch inference?
Use the full_case synthesis directive
19. FPGA manufacturers recommended whenever possible that modules be inferred rather
than instantiated. Why?
This makes the design reusable. More portable to another design or FPGA.
20. Why is it good practice to code modules to support instantiation via model instance
parameter values
The modules are easier to be reused in future designs.

Midterm 2.2
1. An if-then else statement is synthesized as
A multiplexer
2. What does partitioning a design do
3. A VCD file
Can contain timestamped signal transitions of selected signals during a simulation
4. Blocking assignments are recommended for combinational logic
TRUE
5. 3rd Party IP
Is IP sold by a company that does not manufacture FPGA’s
6. Which of the following is true with respect to tasks
They can contain event control, they do not require arguments
7. When you pass timing closure then your design
Successfully meets all of the timing constraints
8. Which of the following are not synthesizable
Case equality statements
9. One of your fellow classmates says “using #delays in your modules will make the
description technology dependent when synthesized” do you agree
NO
10. Which of the following is recommended coding style
Register the module outputs, use connection by name whenever possible, write module
templates to support module instance parameter overriding. (All of the above).
11. Lattice semiconductor recommends FSMs be
One hot encoded if the number of states is large
12. Why is it recommended that module outputs be registered
It simplifies timing analysis
13. One of your fellow students says “simulation often do not match synthesized results”
do you agree
AGREE
14. Consider the following code segment. When does Y = 1?
Xor U11(y,b,a);
Initial
b = 0;
initial
Begin
a<= 1’b0;
b<= #5 ~a;
End
5 time units
15. Hard IP exists only as an HDL description
FALSE
16. When is the system task $readmemb used for
Reading binary data from files
17. What causes latch inference
Using a variable on the RHS of an expression before it is given a value, using an
incomplete if-then-else statement, using a case statement where not all possible values
of the case statement argument are assigned a value (all of the above
18. Functions declared in one module are global. That is they can be called in any module
in the design
FALSE
19. Which of the following methods will infer block RAM in a Xilinx FPGA
Register the memory read address, *or register the output data register*
20. Synthesis directives
Are instructions to the synthesizer

Final exam Practice
1. An if - else statement synthesizes as
Multiplexer
2. What does a partitioning do?
3. A VCD file contains
Timestamped signal changes during simulation
4. Why is it good practice to code modules to support model instance parameter values?
Promotes Module reuse
5. One -Hot encoded FSMs are faster than fully- encoded FSMs
True
6. Which of the following is NOT provided with 3rd party IP?
HDL source code
7. Which of the following prevents synthesizing priority logic?
Parallel case synthesis directive
8. Which of the following provides more comprehensive synthesis/PAR reports?
Non project mode synthesis
9. How is FPGA configuration done in hand-held medical instruments?
SPI flash memory
10. Which of the following limits inferrance of hard IP?
Using asynchronous resets
11. Which of the following helps resolve period timing constraints violations?
Pipelining
12. Which of the following is not synthesizable?
Case Equality
13. Which of the following does not require inputs?
Task statements
14. What causes period constraint violations?
Excessive logic levels
15. What are synthesis directives
Instructions to the synthesizer
16. Why is it recommended module outputs be registered
It simplifies timing analysis
17. Which of the following is recommended in all FPGA designs
Provide a JTAG interface
18. Continuous assignment statements always synthesis as what
Combinational Logic
19. What does completing timing closure mean?
The design is temporally correct
20. Functions defined in one module can be called in another module
False

Homework Questions and Answers
Homework 1
1) What is a netlist?
An ASCII file that describes the components used in a design and how they are
interconnected.

2) Why is an HDL program technology independent?
The HDL only describes the circuit’s functionality. The synthesizer takes the HDL as input
but also a component library as input. The synthesizer does the technology mapping.

3) What is the purpose of simulation?
To determine the function (behavior) of a circuit described by an HDL for specified inputs.

4) Briefly describe the 3 inputs to a synthesizer.
he HDL describes the circuit to be synthesized. The component library indicates what
components are available for the design. The user constraint file indicates any design
restrictions/constraints such as timing, pinouts, etc.

5) What is a design flow?
t is the process to take a design from a specification to production of a programmed part.
The design flow identifies all of the steps required to do that.

6) What is the difference between the syntax and semantics of a program statement?
Syntax tells you the rules for creating valid program statements. The semantics tells you the
meaning of a syntactically correct statement.

7) Express 93 decimal as an 8-bit binary string using the Verilog syntax.
’b01011101 or 8’B01011101. I will also accept 8’d93 or 8’D93

Homework 3
module fsm(clk, reset, in1, out1);
input clk, reset, in1;
output out1;
reg [2:0] state, nextState;
parameter A=0, B=1, C=2, D=3, E=4;
always @(posedge clk)
begin
case(state}
A: if (in1) begin nextState = D; out1 = 0; end
else begin nextState = B; out1 = 0; end
B: if (in1) begin nextState = C; out1 = 1; end
C: if (in1) begin nextState = D; out1 = 0; end
else begin nextState = E; out1 = 1; end
D: if (in1) begin nextState = D; out1 = 0; end
else begin nextState = E; out1 = 1; end
E: if (in1) begin nextState = C; out1 = 1; end
endcase
end
always @(posedge clk or reset)
if (!reset)
begin
state = A; out1=0;
end
else state = nextState;
endmodule

Homework 5
ECE 351 HW #5 (due 11 May)
1) Briefly explain what “latch inference” means.
The inadvertent inclusion of a latch in a circuit that does not require one to implement.
2) What are two ways latch inference occurs. How can you prevent it from occurring?
complete if-then-else statements; use defaults with case statements; use full_case synthesis
directives (only 2 needed)
3) What is a synthesis directive?
an instruction to a synthesizer. It does not generate synthesizable circuitry.
4) Describe the difference between hard IP and soft IP.
hard IP is an on-chip hardware resource. Soft IP is an HDL file.
5) What is the difference between “inferring a module” and “instantiating” a module?
instantiation tells the synthesizer specific circuitry/devices are to be incorporated in the design.
inferring “suggests” that a synthesizer include specific circuitry/devices but it is not required in
the final circuit.
6) It is recommended that module outputs be registered. Why?
It simplifies the timing analysis by allowing you to only rely on the combination logic that has
the longest propagation delay for a given data path.

Homework 6
1) Consider the following code:

always @(A) if (A < 10) Y = 0;
else if (A > 10 & A <= 15) Y = 1;

Assume A can assume a value between -2 and +22. Why would a synthesizer believe a latch is
necessary?

Since there are values for A between -2 and 22 that are not defined in the code example, the
synthesizer will create a latch to hold the last value that was valid. Otherwise it wouldn’t know
what to put on the output. It creates a latch to avoid this situation.

(2 points) The if statement updates the value of Y based on a new value of A. Since updates
are not specified for all A values, the synthesizer infers you want to keep the old Y value. A
latch is included to retain the old Y valu

2) What are three ways of preventing latch inference in case statements?

1. Include a default case in the case statement
2. Use a full_case synthesis directive
3. Pre-assign a value so there is always a known state.

(2 points) provide a value always assigned before executing the case statement; use a
synthesis directive; use a default statement in the case statem

3) Why should module outputs be registered?

Module outputs should be registered to help with timing. It makes it easier to determine timing
between modules.

(2 points) Registering the outputs makes the design synchronous, which makes it easier to
estimate the timing. (Synchronous designs are always easier to analyze for timin

4) Consider the following module: Edit the code so the module has a registered output.

module U1(in1, in2, y, clk);
input in1, in2, clk;
output y; reg y;
reg s;
always @(posedge clk)
s = in1 ^ in2;

y = ~s;
endmodule

5) Consider the following Verilog code. Show what would most likely be synthesized.

if (A)
y=1;
else if (B)
y=2;
else if (C)
y=3;
else if (D)
y=4;
else
y=0;

6) Rewrite the code from the previous problem as a case statement. Show what would be
synthesized if the parallel_case synthesis directive is used.

case(select)
A: y=1;
B: y=2;
C: y=3;
D: y=4
default: y=0;
endcase

Homework 7
1. (2 points) 3rd party IP provides three files: a netlist; a behavioral wrapper; and a file
showing the instantiation syntax. What is the purpose of the behavioral wrapper?
it is used to support HDL simulation.
2. (2 points) Why are black boxes synthesized?
There needs to be a "placeholder" in the netlist produced by the synthesizer for 3rd party IP (or
some vendor supplied IP). The netlist from the core is then input to the PAR tool along with the
synthesizer's netlist.
3. (2 poiints) Xilinx recommends control signals in modules be coded so they are active high.
Why?
A LUT is required to invert the control signal if it has to be active-low. Thus making the control
signals active-high preserves LUTs.
4. (2 points) In a Xilinx FPGA, what is a control set? What does it contain?
A control set is a set of control signals (e.g., enables, selection lines, reset, etc) that are bundled
together to use for all registers within a CLB.
5. (2 points) Xilinx says designs with asynchronous resets may use excess LUTs and registers.
Briefly explain why.
There are many acceptable answers to this problem. Some involve multicycle circuits. Any
reasonable explanation will be accepted.
That said, the most obvious reason is using an asynchronous reset precludes using hard IP. For
example, a FSM can be implemented in block RAM. But block RAM can't support asynchronous

Homework 8
1) (5 points) You have a timing problem. Looking at the timing report you see that one
particular net delay is considerably larger than the other net delays. However, the fanouts
are all roughly the same. What is the most likely problem and how would you solve it?
The most likely problem is a routing problem. That is this is a relatively long net in the design.
The solution will probably require launching the PAR tool and try different routing options to see
if the length of this net can be reduced.

2) (5 points) You have a timing problem. Looking at the timing report you see that a period
constraint has been violated. There are two possible solutions:
(a) retiming the data path, or
(b) manually pipelining the data path. Explain how each solution addresses the timing
problem.
This is a period constraint violation. Both pipelining and retiming change the propagation delay
of the data path between register pairs. However, they do this in different ways. In retiming, you
move logic blocks to different locations so they are enclosed by a different pair of registers.
Equivalently, you can move the register location to a different place in the the datapath. In
pipelining, you “break up” consecutive logic blocks by adding additional registers.
Put another way, retiming moves the location of the registers but the number of registers is still
the same. Conversely, in pipelining you add additional registers. See the attached two figures to
see the difference.

Quiz Questions from Online
1. What do the following acronyms mean?
HDL - Hardware description language
ASIC - Application specific integrated circuit
ASSP - Application specific standard product
RTL - Register Transfer Level
2. What property must all verilog programs have
They must be synthesizable
3. What are the three inputs to a synthesizer
Parts or component library, HDL, User constraints
4. What is a testbench
A file containing the input test signals (or vectors) used during a circuit simulation
5. What does instantiation do?
It creates a module instance
6. What is the basic building block in verilog?
A module
7. What is the difference between syntax and semantics of a programming language
statement?
Syntax refers to the rules of how to construct valid program statements. Semantics
refers to the meaning or interpretation of a syntactically correct program statement.
8. What are the three inputs to a synthesizer?
HDL file, library of components, and user constraints
9. What type of operator is used in the following partial verilog statement. A = B # C
Binary
10. What is the gate primitive?
A predefined verilog module. These modules describe basic logic gate functions.
11. What are the two ways of connecting Verilog modules?
By position and by name
12. Draw a schematic of the circuit described by the following verilog module
See quiz 2 for an example
13. What are two ways of assigning a value to a net variable?
Drive it with a module output or with a continuous assignment statement.
14. What does the following partial verilog program do?
Computes bitwise AND of two 6-bit variables. See quiz 3 for the code and full answer.
15. Draw a schematic of the following verilog code.
See quiz 3 for the diagram and code.
16. What does the following verilog program do?
Whenever a positive edge is seen on the variable ‘A’ or ‘B’, the value of ‘Y’ is updated with
the value of ‘A’ left-shined by 2 bits.
17. What are the semantics of the following Verilog code? XYZ #(1,22) ABC();
A module XYZ is instantiated with the first two parameter values in the module template
overriden by the values of 1 and 22.
18. Explain the difference between ports in modules and port tasks.
Ports in modules are used for interfacing signals, ports in tasks are used to pass values
19. How many bits are in the return value for the following function?
9, see quiz 4 for the code.
20. What is the assignment delay for the code below?
`timescale 10us/1fs
Assign #22 A=B*C;
220 microseconds
21. What two keywords are associated with parallel blocks?
Fork and Join
22. Briefly define the term timing closure.
Timing closure means a design meets all timing requirements.
23. One way to manage complexity in a design is to separate the control path from the data
path. What is the purpose of these two paths?
The data path operates or processes input data. The control path provides the necessary
command, control and status signals needed by the devices in the data path. (in other
words, the control path contains the control points)
24. Describe how a FSM can implement a control strategy
Each FSM state output is a control point. As the FSM processes inputs it makes state
transitions. The sequence of state transitions generates a sequence of control points for
the data path.
25. Why is it good practice to have a reset strategy?
Devices in both the data path and the control path must be initialized properly. The reset
strategy defines what gets initialized and what that initial state is.
26. What does the syntax “(01)” signify in a UDP?
An input signal makes a 0 -> 1 transition.
27. What information is contained in a VCD file?
Time stamped switching information on signals in a design recorded during a simulation
28. FPGAs are often soldered on a PCB, which fixes which pins are used for I/O. How is the
synthesizer informed of these pin assignments so the FPGA can be properly
programmed?
Pin assignments are provided by the user either manually during the synthesis process
or via a user constraint file.
29. How do ports in modules differ from ports in tasks?
Ports in tasks are used to pass values. Ports in modules are signals used for interfacing.
30. How do you make a task re-entrant?
After the keyword “task” you put the keyword “automatic”
31. What is IP (in the context of HDL programing)?
Reusable modules of functionality. In other words, any verilog module is IP.
32. What is the best way to synthesize memory in FPGAs?
Use memory primitives (IP) furnished by the FPGA vendor.
33. What is latch inference?
Undesirable latches in the synthesized design cause by poor coding syntax. In other
words, the “poor syntax” INFERS that latches should be in the design -- even when they
are not necessary.
34. When is it better to use an if-then-else syntax instead of a case syntax?
Use if-then-else when the number of choices are 2 or less. Otherwise, use the case
statement.
35. The Spartan-6 FPGA CLBs just like all other FPGAs, but also contains several blocks of
special purpose circuitry. What is one of them?
DSP slices, Memory controller blocks, endpoint blocks for PCI express, serial
transceivers.
36. What does latch inference mean?
Latch inference means a synthesizer has added unnecessary latches to a circuit. The
circuit could be built strictly with combinational logic.
37. List three ways to program an FPGA.
From a parallel boot memory device, from a serial peripheral interface (SPI) flash
memory, from a microprocessor, via the JTAG port.
38. What does the term “Design flow” refer to?
The steps required to take a design from a specification (or HDL description) to a
synthesized part.
39. What is the most common programming language used for FPGA scripts
Tcl or Tool Command Language
40. What are the two ways of creating FPGA scripts?
Write it directly using a text editor, or save the results of a synthesis run
41. What are the 4 signals you must have for a JTAG interface?
TMS, TDI, TDO, and TCK
42. What is 3rd party IP?
IP that is not created by the user or by the FPGA vendor
43. How does pipelining differ from retiming?
Pipelining inserts additional registers into a data path. Retiming only repositions
registers in the datapath, no new registers are added.
44. Suppose your company is designing a new product line that wil include a very
sophisticated ASIC. What role does FPGA prototyping play in the ASIC design process?
FPGA prototypes allow software (that ultimately will run on the ASIC) to be developed,
tested and validated before the ASIC hardware design is finished. This greatly shortens
the ASIC design time.
45. What is design flattening?
Design flattening is the removal of portions of a design hierarchy by the synthesizer to
promote optimization.

ECE 351 Table of Contents PDF

Transféré par

Informations du document

Titre original

Copyright

Formats disponibles

Partager ce document

Partager ou intégrer le document

Options de partage

Avez-vous trouvé ce document utile ?

Ce contenu est-il inapproprié ?

Droits d'auteur :

Formats disponibles

ECE 351 Table of Contents PDF

Transféré par

Droits d'auteur :

Formats disponibles

ECE 351 NOTES & TEST Questions

Vous aimerez peut-être aussi