7/12/2018 VLSI Design Overview and Questionnaires: FPGA Interview Questions and Answers

VLSI Design Overview and Questionnaires

This blog provides an overview of various practical concepts related to Synthesis, STA, Low Power, FPGA which are use
We also try to cover the practical questionnaires related to these topics which are asked in the interviews of product/ser
semiconductor companies.

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FPGA Interview Questions and Answers OCV

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Chip
1. What is FPGA ?

Total P
ANS : FPGA - Field Programmable Gate Array.
Share and Learn It is a device with programmable ‘logic blocks’ and programmable ‘interconnects’. Logic 5 1
blocks contain LUTs and CLBs which used to implement mathema cal or logical func ons and
Edusaksham Professional VLSI interconnect join them to make large design. It uses external memory to store the Blog A
interconnec on informa on. This informa on can be changed and device can be
► 201
reprogrammed by prototype designer.
▼ 201

2. Draw the general structure of FPGA ? ► S

ANS : FPGA - Basically it consists of programmable ‘Logic Blocks’ and ‘Interconnects’. ▼ M

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hold (3) setup (3) Follo

block ram (2) distributed
ram (2) synthesis report (2)
Search
ASIC flow (1) Backend (1) CLB and LUT
(1) Clock Delay (1) Clock Tree Delay (1) D
flip flop timing analysis (1) DC (1) DCM
(1) DRC and LVS (1) Design constraints
Logic Blocks contains CLB (Configurable Logic Block) and each CLB contain some LUTs (Look- Follow
(1) Design environments (1) FPGA
Up-Table) and other logic.
prototyping (1) FPGA vs ASIC (1)
Email
Frontend (1) Glitch (1) Global Buffers (1)
Hard and Soft Processor Core (1) 3. Explain CLB’s and LUT’s of FPGA ?
Incremental optimization (1) Jitter (1) ANS : Logic Blocks primarily contain programmable CLBs and LUTs. Popula
LBIST and MBIST (1) PLL and DLL (1)
1. CLB (Configurable Logic Block) - These are the main logic resource for implemen ng
RAM HDL coding technique (1) RC (1)
OCV
RTL2GDSI (1) Skew (1) Synthesis (1)
sequen al as well as combinatorial circuits. A CLB elements contains a pair of ‘slices’.
(Ad
Synthesis flow (1) Uncertainty (1) aocv (1) They don’t have direct connec on to each other. Each slice has contain independent Vari
asic synthesis vs fpga synthesis (1) clock carry chain.
gating (1) combinatorial logic (1) Mul
contamination delay (1) depth based ocv
2. LUT (Look Up Table) - Each Slice contains four or six input look-up-table (LUT), storage You
(1) distance based ocv (1) early path (1) elements, mul plexers and carry logic. These element are used to provide logic,
FPG
edif (1) edn (1) emulation platform (1) arithme c and ROM func ons. Some slice contains addi onal func ons like Distributed Que
examples of setup and hold (1) fast to slow RAM and shi ing data 32-bit. Ans
(1) hold violation (1) late path (1) low-
power (1) mcp (1) metastability (1) modal Syn
coverage (1) multicycle (1) netlist 4. Steps for FPGA Prototyping ? -AP

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7/12/2018 VLSI Design Overview and Questionnaires: FPGA Interview Questions and Answers
simulation (1) ocv (1) on chip variations ANS : Find the FPGA prototyping design flow in following link.
Fron
(1) pre silicon validation (1) precision (1)
h p://www.design4silicon.com/p/fpga-related.html Info
set_multicycle_path (1)
to S
set_timing_derate (1) setup and hold (1)
setup and hold time (1) setup violation (1)
5. What are the differences between FPGA and ASIC also give pros and cons ?
Bac
slow to fast (1) synplify pro (1) ANS : FPGAs (Field Programmable Gate Arrays) and ASICs (Applica on Specific Integrated - Sy
Gen
Circuits) both have their advantages. FPGA’s are reprogrammable but costly where ASIC’s are
non-programmable and applica on specific but cheap. Let’s look Bas
FPGA Advantages Hol

1. Field Reprogrammable Bitstream can be uploaded remotely. Bas

Hol
2. Simple design cycle Tool take care of rou ng, placement and ming.
Hig
3. Faster me to market No layout, masking or fabrica on needed.
Bas
Hol
ASIC Advantages
1. Full custom capability Device is manufactured with design specs.

2. Lower unit cost Generally cost is lower due to mass produc on.

6. What is Synthesis ?
ANS : Synthesis is the process of transla ng HDL code into gates. Synthesis tools take HDL
code and gives gate level netlist output for selected device. Please go through following link
for more informa on-
h p://www.design4silicon.com/2016/01/fpga-synthesis.html

7. List of synthesizable and non-synthesizable constructs ?

ANS : Please go through following link for synthesizable and non-synthesizable constructs
informa on-
h p://www.design4silicon.com/2016/02/front-end-informa on-design-to-simula on.html

8. What is DRC and difference between DRC and LVS ?

ANS : DRC : Design Rule Check
In ASIC there are some sets of rules which depends on technology used to design. Means
some sets of parameters which decide where the mask should be placed, connected and
routed in the layout. This check has responsibility of design to work a er fab process.
In FPGA, tool (like vivado) check the correctness of the design before synthesis, which is also
said DRC check.
LVS : Layout Versus Schema c
DRC ensure that layout conforms the rule required for faultless fabrica on. But it is not
guaranteed layout contain same circuit you desire to fab. Here the LVS check required. This
process matches the netlist extracted from layout versus the original schema c or circuit.

9. What is stuck at ZERO Means ?

ANS : Some me in ASIC due to some fault any node will permanent e to either ‘0’. This is
called Stuck at ZERO error. Similarly stuck at ONE error. To check this error we need to provide
some testability in RTL.
It generally not appears in FPGA prototyping, these are tested hardware which are
programmed by bit file not fabricated so probability of error is less.

10. What is DFT and do it require in FPGA prototyping ?

ANS : DFT : Design for Testability.
Check the toggling of each flop in the design and eliminate the manufacturing error like stuck
at ‘0’ or ‘1’, DFT process is used. Apart from the func onal logic DFT logic are also added in
design and pa erns are generated so that we can test the manufacturing defects a er it
come from fab. Scan chain, MBIST and LBIST are the part of this test.

11. What are MBIST and LBIST in DFT ?

ANS : BIST : Built in Self Test.
Two most common method for DFT tes ng are Logic BIST (LBIST) and Memory BIST (MBIST).
LBIST is design for tes ng random logic, which use pseudo random pa ern generator (PRPG)
to generate input pa ern and mul ple input signature register (MISR) for obtaining the
response of the device for there input pa ern. An incorrect MISR output indicate the defect
in the device.

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MBIST is design for tes ng memory, which use various algorithm to test memory by wri ng,
reading and comparing. MBIST check following faults in memories
a. Stuck-at Fault
b. Transi on Fault
c. Coupling Fault
d. Neighborhood Pa ern Sensi ve Fault
e. Address Decoding Fault.
“March” Algorithm is most common algorithm used in industry.

12. What are the differences between FPGA and CPLD ?

ANS : FPGA : Field Programmable Gate Array.
CPLD : Complex Programmable Logic Device.
Func on of both the devices are same but difference in
1. Capacity : Normally CPLD has less capacity than FPGA.
2. Image Storage : CPLD can bootup by itself but FPGA has large boot image and it fetches
image from SRAM.
3. Features : CPLD only provide gates but FPGA also provides hard blocks like Block RAM,
DSP, Microprocessor etc. which make FPGA more suitable for embedded systems.

13. What is DCM, Why the are used ?

ANS : DCM : Digital Clock Manager
DCM is an electronic component which uses the feedback path to maintain the clock signal
despite normal varia on in opera ng temperature and voltage. The output of DCM gives
clock with minimum skew with high fanout, because it uses global buffer for high fanout.

14. What are differences between DLL and PLL ?

ANS : DLL : Delay Lock Loop
PLL : Phase Lock Loop
These are two technique to minimize the clock skew.
1. PLL use voltage-controlled-oscillator (VCO) whereas DLL use delay line.
2. PLLs are hybrid analog and digital whereas DLLs are all digital.
3. DLL have step errors but hybrid PLL does not have it.
4. DLL have less clock skew than PLL.

15. What are the different modes of programming the FPGA ?

ANS : There are many modes of programming the FPGA.
1. SRAM via JTAG or programmable cable.
2. Flash.
3. USB and SD-Card.

16. What is constraint file and why we use it ?

ANS : Constraint file required for make design as per your requirements, like there is need to
take out some signals to par cular pins of FPGA eg. JTAG or define clocks as false path or
mul -cycle path. More can find from -
h p://www.design4silicon.com/2016/04/user-constraint-file-fpga.html

17. Name the FPGA manufacture companies ?

ANS : FPGA Companies
1. Xilinx (~50%)
2. Altera (~40%)
3. La ce Semiconductor
4. Microsemi (Actel)
5. QuickLogic

18. What is the difference between ‘Hard Processor Core’ and ‘Soft Processor Core’ ?
ANS : Generally FPGA are categorized in following two ways in terms of design.
1. Hard Processor Core - Some part of FPGA has fixed blocks like processor core and some
common standard IPs. Li le space for other logic implementa on.

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a. Capable of work on high speed due to be er op miza on.

b. But have fixed configura on and can not be altered.
2. So Processor Core - Full FPGA can be used for logic. User need to implement so
processor core if required.
a. Can be easily modified and have more logic.
b. But limited in terms of speed of the fabric.

19. How you can know the maximum allowable operating frequency of your design ?
ANS : Maximum allowable frequency is limit by ‘Setup Viola on’ in FPGA design. Timing
report generated for the given clock frequency. If minimum ‘Slack’ between two flops is
posi ve then we can decrease the me period by that amount or increase the frequency.

20. How you can increase the operating frequency of the design in FPGA ?
ANS : There are following ways which might use to increase the opera ng frequency of the
design
1. Check ming cri cal path and op mized it.
2. Proper design constraint and ming constraint.
3. Pipeline structure.

21. What is minimum and maximum frequency of DCM in Spartan-3 and Virtex-5 series
FPGA ?
ANS : Minimum and maximum frequency of DCM in
1. Spartan-3 : 24 MHz to 248 MHz
2. Virtex-5 : up to 550 Mhz

22. Can CLB configured as a RAM ?

ANS : In Xilinx CLB has two slices which is Slice-L and Slice-M. Func on generators (LUTs) in
Slice-M can be implemented as a synchronous RAM called distributed RAM. Mul ple LUTs in
Slice-M can be combined in various ways to store large amount of data.

23. What is Global Buffers, give some example ?

ANS : Global Buffer - Distribute the high fanout signals throughput.
In Xilinx FPGA there are many types of global buffers available like BUFG, BUFGMUX, BUFGCE
etc. Different FPGA has limited global buffers and apart from tool user can explicitly use them
also by using constraint file.

24. Is there is any way to use the design in FPGA which has ‘setup violation’ ?
ANS : Setup viola on accrue if net delay between flops are greater than Time period of the
clock. So if we can increase the me period of clock such that it is greater than or equal to net
delay then we can use that same FPGA design. Increase the me period means decrease in
frequency so by lowering the clock frequency can make design work.

25. Is there is any way to use the design in FPGA which has ‘hold violation’ ?
ANS : Hold viola on accrue when path delay is less than the hold me of the flop. So by
adding some path delay we can use the design. But that path delay should not exceed the
me period of clock.

26. What is ‘contamination delay’ in sequential circuit and difference with propagation
delay ?
ANS : Contamina on Delay (Tcd) : Minimum me that the logic gate will change the output
based on change in input.
Propaga on Delay (Tpd) : Maximum me that the logic gate will change the output based on
change in input.

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27. Which are the different reports we need to look while FPGA prototyping ?
ANS : At different phase of FPGA prototyping following report are generated
1. Synthesis report a er synthesis.
2. Place & Route and
3. Timing report a er Place and route or bit file genera on.

28. Which primary information are need to look in above reports ?

ANS : Following main informa on need to look in synthesis report
1. Signals or registers which are op mized or prune.
2. Latches in the design.

Following informa on need to look in P&R and ming report

1. Setup and Hold Viola on.
2. Are the clock constraints applied properly.
3. False path and mul cycle path.
4. Gate count.

29. What are different type of RAMs in FPGA and how we can use them ?
ANS : Xilinx FPGA provides two op ons for crea ng memories for storing data.
1. Distributed Memory : Array of register.
2. Block Memory : Dedicated memory.
When synthesis tool synthesize the RTL then it can use any memory depends on your coding.
Before move on to coding style first see the difference between them.
a. When it require to make small data memory, like small buffers or registers then use
distributed memory.
b. When it require to store large amount of data, like data message buffers or large lookup
table then use block memory. This memory is limited and depends on FPGA series.
We should not use distributed memory for storing large amount of data because it use large
number of logic cells/flops to make register and will take large number of registers to make
memory.
//Let’s see the verilog code for configure block RAM
module B_RAM (clk, addr, we, data_in, data_out);
input clk, we ;
input [1:0] addr ;
input [15:0] data_in ;
output [15:0] data_out ;

reg [15:0] mem [3:0] ;

reg [15:0] data_r ;

assign data_out = data_r ;

always @ (posedge clk) begin
if (we) begin
mem [addr] <= data_in ;
end
data_r <= mem [addr] ;
end
endmodule
NOTE : Ini aliza on the RAM separately.

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30. What is the difference between ‘reg’ and ‘wire’ ?
ANS : In HDL language ‘wire’ is which connects two nodes, it can not store data and used for
designing combina onal logic.
Whereas ‘reg’ can store the value and drive strength. It can use for modeling both
combina onal and sequen al logic. Reg data type can be ini al and always block.

31. What is different type of ‘timing verification’ ?

ANS : There are two type ming verifica on -
1. Dynamic ming
2. Sta c Timing

32. What does ‘timescale 1ns/1ps’ signifies ?

ANS : Timescale specify the me unit and precision of a module. It is wri en as
mescale me_unit_base / precision_base
From above example ‘ mescale 1ns/1ps’, the base of me unit is in nanosecond and base of
precision is in picosecond. Time unit is amount of me a delay #1 represents and precision is
how many decimal points of precision to use rela ve to the me unit.

33. Different Debug tools used in FPGA design debugging ?

ANS : Each FPGA Tool manufacturing company will also make some tools for debugging like
1. Chipscope - Xilinx
2. Protolink - Synopsis
3. On-Chip Debugging - Altera

34. What is ‘Emulation’ and difference from ‘FPGA platform’ ?

ANS : Emula on word sound similar to simula on and work similar to that also. In simula on
compiler break the code into nodes and calculate the value of each node at each clock edge.
Emula on pla orm is actually group of processors which make can separate thread for each
node. It work on synthesized design. Emula on pla orm is a hardware so we can connect
debugger and other peripherals with it.
It is similar to FPGA but have following differences
1. Capacity : Emula on Pla orm has very large capacity compare to FPGA. You can
emulate full Soc in emula on pla orm.
2. Speed : Emula on pla orm work on KHz to few MHz whereas FPGA work on 10 to 100
MHz. So FPGA are 100 mes faster than Emula on.
3. Debug : Emula on pla orm gives facility to take waveform dump at any me at any
trigger condi on, but FPGA you need to add extra logic plus select the signal previously
which we want to check.
4. Force : In emula on we can force any value to any signal but in FPGA we can not do this.
5. Timing : In FPGA we need to do Place and Route a er synthesis but in Emula on
pla orm we need not to do P&R.

35. What is the difference between ‘rtl simulation’ and ‘netlist simulation’ ?
ANS : In simula on compiler do and don’t do the following opera on
1. Do the syntax check
2. Don’t op mize the code
3. Don’t synthesize the code means non-synthesizable construct can be use in simula on,
eg. delay, ini al, fork join etc.
4. Do break the code into nodes and calculate the value of each node for each clock edge.
So as your design increases, number of nodes increases and hance take more me to
run complete simula on. Also it dumps the waveform for each clock edge.
5. Don’t change the signal name.
In RTL simula on, tool compile the code and determine the nodes and dump the value of
each nodes at each clock cycle. Whereas netlist generate a er the synthesis in which RTL
code is op mized and change into gate level. This increase the number of nodes and take
more me in simula on compared to RTL simula on.

36. Which one of following is not synthesizable VHDL statement  ?

a. ‘case’
b. ‘wait until’
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c. ‘wait for’
d. ‘generate’
ANS : ”wait for” is non synthesizable.
Under process ‘wait un l’ is synthesizable.

at 12:35 PM

Labels: block ram, CLB and LUT, contamination delay, DCM, distributed ram, DRC and LVS, emulation platform,
FPGA vs ASIC, Global Buffers, Hard and Soft Processor Core, LBIST and MBIST, netlist simulation, PLL and DLL

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