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2–1 Implementation using NAND gates: We can write the XOR logical expression A B + A B using
double negation as
AB+AB = AB+AB
= AB AB
From this logical expression, we can derive the following NAND gate implementation:
A B
Implementation using NOR gates: We can write the XOR logical expression as
AB+AB = AB+AB
= A + B + A + B
From this logical expression, we can derive the following NOR gate implementation:
1
2 Chapter 2
A B
2–2 Implementation using NAND gates: We can write the exclusive-NOR logical expression A B +
A B using double negation as
AB+A B = AB + AB
= AB AB
From this logical expression, we can derive the following NAND gate implementation:
A B
Chapter 2 3
Implementation using NOR gates: We can write the exclusive-NOR logical expression as
AB+A B = AB+AB
= A + B + A + B
From this logical expression, we can derive the following NOR gate implementation:
A B
Alternative Implementations:
Alternatively, we can derive the following NAND implementation by modifying the logic circuit
in Figure 2.1 by adding an output inverter:
A B
4 Chapter 2
Similarly, we derive the following NOR implementation by modifying the logic circuit in Fig-
ure 2.2 by deleting the output inverter:
A B
2–3 A NOT gate can be implemented by holding one input at ‘1’ as shown below:
A
A
2–4 By keeping one input at ‘0’, we can turn an XOR gate into a buffer that passes input to output as
shown below:
A
A
It is clear from this and the last exercise that by controlling one input (call it control input), we can
turn an XOR gate into either an inverter or a buffer. If the control input is ‘1’, the XOR gate acts
as an inverter; if the control input is ‘0’, it acts as a buffer.
2–5 We can write the AND logical expression (A B) using double negation as
AB = AB
= A + B
A + B = A + B
= A B
2–7 The two transistors are in series. V out is low only when both transistors are turned on. This
happens only when both V in1 and Vin2 are high as shown below:
As in the text, when we interpret low as ‘0’ and high as ‘1’, it implements the NAND function.
2–8 In this example, the two transistors are in parallel. V out is low when any of the two transistors are
turned on. This happens when either V in1 or Vin2 (or both) is high as shown below:
As in the text, when we interpret low as ‘0’ and high as ‘1’, it implements the NOR function.
2–9 We assume that input A has 50% weight. The truth table is shown below:
6 Chapter 2
A B C F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
BC
BC
A 00 01 11 10
0 0 0 1 0
1 1 1 1 1
A + BC
A
B
C
2–10 We assume that input A has the veto power. The truth table is shown below:
A B C F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Chapter 2 7
The sum-of-products expression for F can be simplified by replicating the term (A B C) as shown
below:
F = ABC + ABC + ABC
= ABC + ABC + ABC + ABC
= AC + AB
= A(B + C)
You can also use the Karnaugh map method to derive the same logical expression.
The following logic circuit implements this function:
A
B
C
2–11 (a) x x = x
Let us start with x and show that it is equivalent to x x.
x = x1 Identity)
(
= x (x + x) (Complement)
= (x x) + (x x) (Distribution)
= (x x) + 0 (Complement)
= x x (Identity )
(b) x + x = x
Let us start with x and show that it is equivalent to x + x (very similar to the last exercise).
x = x+0 Identity)
(
= x + (x x) (Complement)
= (x + x) (x + x) (Distribution)
= (x + x) 1 (Complement)
= x + x (Identity )
(c) x 0 = 0
As in the previous examples, we start with the right hand side (0) and show that it is equivalent to
8 Chapter 2
x 0.
0 = xx Complement)
(
= x (x + 0) (Identity )
= (x x) + (x 0) (Distribution)
= 0 + (x 0) (Complement)
= x 0 (Identity )
(d) x + 1 = 1
This is the dual of the last exercise.
1 = Complement)
x + x (
= x + (x 1) (Identity )
= (x + x) (x + 1) (Distribution)
= 1 (x + 1) (Complement)
= x + 1 (Identity )
= 0
(x y) + (x + y) = xy + x (y + y) + y (x + x)
= xy + x y+ xy + y x+yx
= (x y + x y) + (x y + y x)
= (x y + x y) + (x y + y x)
= y + y
= 1
= 0
Chapter 2 9
(x + y)
+ (x y) = x( y + y) + y (x + x)
+ (x y)
= xy + xy+yx + yx + xy
= x(y + y + y) + x (y + y)
= x + x
= 1
A B C
A B C A + B + C
0 0 0 1 1
0 0 1 1 1
0 1 0 1 1
0 1 1 1 1
1 0 0 1 1
1 0 1 1 1
1 1 0 1 1
1 1 1 0 0
OR version: A + B + C = A B C
The truth table below verifies the OR version.
A B C A + B + C A B C
0 0 0 1 1
0 0 1 0 0
0 1 0 0 0
0 1 1 0 0
1 0 0 0 0
1 0 1 0 0
1 1 0 0 0
1 1 1 0 0
2–15 From the 3-input NAND gate shown in Figure 2.23b, we can see that each additional input needs
an inverter and a 2-input NAND gate. Since we implement the inverter with a 2-input NAND gate
as well, we need two 2-input NAND gates for each additional input. Thus, for an n input NAND
gate, we need
1 + 2( n 2)
10 Chapter 2
1 + 2(8 2) = 13 gates
Since there are four gates in the 7400 chip, we need four 7400 chips.
2–16 (a)
(x + y) (x + y) = (x y) xy (de Morgon’s law)
= 0
(b)
x + yx = x (1 + y) + yx
= x + xy + yx
= x + y (x + x)
= x + y
(c)
AB AB = (A + B) (A + B)
= AA + AB + BA + BB
= A B + AB
A B C F
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
Sum-of-products form:
ABC + A BC + ABC + ABC
Product-of-sums form:
(A + B + C) (A + B + C) (A + B + C) (A + B + C)
Chapter 2 11
2–18 We start with the product-of-sums expression and derive the sum-of-products expression.
(A + B + C) (A + B + C) (A + B + C) (A + B + C)
= (A + A B + A C + A B + B C + A C + B C) (A + B + C) (A + B + C)
= (A B C + A B C + A B + A B C + B C + A B C + A C + A B C) (A + B + C)
2–20 We start with the product-of-sum expression and derive the other expression.
(A + B + C ) (A + B + C) (A + B + C) (A + B + C)
= (A + A B + A C + B + B C + A C + B C) (A + B + C) (A + B + C)
= (A + A B + A C + A B C + A C + A B C + A B + A B C + A B C + B C) (A + B + C)
(A + B + C) (A + B + C) (A + B + C) (A + B + C)
= (A + A B + A C + A B + B C + A C + B C) (A + B + C) (A + B + C)
= (A B C + A B C + A B + A B C + B C + A B C + A C + A B C) (A + B + C)
Solution:
= A C (B + B) + A CD + AB C + ABD + AC + A BCD
= (A C + A C) + A CD + AB C + ABD + A BCD
= A + A CD + A (1 + C D) + AB C + A (1 + B C) +
ABD + A (1 + B D) + A BCD + A (1 + B C D)
= A + CD + B C + BD + BCD
2–24 We need a 7-input XOR gate to derive the parity bit. We can construct 1 7-input XOR using 2-input
XOR gates as shown below:
A0
A1
A2
A3 P
A4
A5
A6
2–25
= BD + A B C (D + D) + A B D (1 + C)
= BD + ABC + ABD
A B C F
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
= C(A + A)
= C
Clearly, we just need one inverter to implement this simplified logical expression.
A B C D F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
CD
AB 00 01 11 10
00 1 0 0 0
01 1 0 0 0
11 1 0 0 0
10 1 0 0 0
CD
A BCD
p BCD
p
ABCD
p BCD
p
ABCD
p ACD
p
Chapter 2 15
A B C D F
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
CD
AB 00 01 11 10
00 0 0 0 0
01 0 1 1 1
11 0 0 0 0
10 1 1 0 1
ABD + ABC + A BD + A BC = A B (C + D) + A B (C + D)
A
B
C
D
A
B
C
D
Column 1 Column 2
— ABD
ABCD
p ABC
A BCD
p A BD
A BCD
p A BC
ABCD
p
ABCD
p
A BCD
p
Step 2:
N
ABD
N
A BC
N
A
AB
BD
C
N
Chapter 2 17
ABD + ABC + A BD + A BC = A B (C + D) + A B (C + D)
A B C D F
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 1
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0
CD
AB 00 01 11 10
00 0 0 0 1
01 1 1 0 0
11 1 0 0 1
10 0 0 1 0
A
B
C
A
B
D
B
C
A
D
Column 1 Column 2
— —
AB CD A BC
BCD
A BCD
p ABD
A BCD
p
ABCD
p
ABCD
ABCD
p
Step 2:
ABC N
BCD
N
A BD
N
A BCD
ABCD
N
Chapter 2 19