Chapter One

Part II
Instruction Sets & Instruction cycle

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 Contents
• Instruction set
• Elements of Instruction
• Instruction set design Issues
• Addressing modes
• Types of Instructions
• Instruction Cycle

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 Instruction set
• The complete collection of instructions that are
understood by a CPU
• The instruction set is also the machine description that a
hardware designer must understand to design a correct
implementation of the computer
• Serves as an interface between software and
hardware.
• Machine language: binary representation of
operations and (addresses of) arguments
• Assembly language: mnemonic representation
OP A,B,C (meaning A <- OP(B,C))

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 Elements of Instruction
• Operation code (opcode)-mnemonic code
• Source operand reference
• Destination operand reference
• Next instruction reference

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Example of simple Instruction format
using two addresses

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 Instruction Set Design Issues
• Where are operands stored?
• How many explicit operands are there?
• How is the operand location specified?
• What type & size of operands are supported?
• What operations are supported?
• Number of CPU registers available
• Which operations can be performed on which registers

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 Importance of Registers
– Registers are much faster than memory (even cache)
• Register values are available immediately
• When memory isn’t ready, processor must wait (“stall”)
– Registers are convenient for variable storage
• More compact code since small fields specify registers
compared to memory addresses
– Two types of registers
– General purpose & specific purpose

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 Addressing modes
• Addressing modes are method of referencing
the operands
• The most common addressing techniques are
– Immediate
– Direct
– Indirect
– Register
– Register indirect

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 Immediate Addressing mode
• Operand is part of instruction
• Operand = address field
• Example
• ADD 5
• No memory reference to fetch data
• Fast

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 Direct Addressing
• Address field contains address of operand
• Effective address (EA) = address field (A)
• e.g., ADD A
– Look in memory at address A for operand
• Single memory reference to access data

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 Indirect Addressing
• Look in A, find address [A] and look there for
operand
• E.g. ADD [A]
• Multiple memory accesses to find operand
• Hence, slower

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 Register Addressing
• Operand is held in register named in address
field
• Very small address field needed
– Shorter instructions
• No memory access
• Very fast execution
• Availability of Multiple registers helps
performance

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 Register indirect addressing
• Operand is in memory cell pointed to by
contents of register R
• One fewer memory access than indirect
addressing

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 Instruction Types
• Data movement instructions
• Arithmetic instructions
• Logical instructions
• Branch instructions
• Control instructions

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 Data Transfer/movement
• Data transfer Instructions include: Store, load,
exchange, move, clear, set, push, pop
• Specifies: source and destination
• Example
• LDA 2000H; load the data in memory location
2000H to accumulator
• MOV R1,R2; move the data in register R2 to
Register R1

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 Input/output Instructions
• Example
• IN 02H; transfer the data at port 02H to Ac.
• OUT 02H; transfer the data in Ac. through 02H

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 Arithmetic
• Arithmetic instructions include Add, Subtract,
Multiply, Divide
• May also include
– Absolute (|a|)
– Increment (a++)
– Decrement (a--)
– Negate (-a)
• Example: ADD A,B....A=A+B

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 Logical
• Bitwise operations/instructions: AND, OR,
NOT, XOR, TEST, CMP, SET
• Example: AND A, B; A=A AND B
• Shifting and rotating functions
– arithmetic right shift: division
– arithmetic left shift: multiplication

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 Branch instructions

– Alter the normal flow of control from executing the next

instruction in sequence
– Br Loc, Brz Loc2 ---unconditional or conditional branches

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 Control instruction
• No operation (NOP) or stop execution (HLT)

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 Example: write an assembly code for
Y=(A-B)/[(C+(D*E))]
Implicit second address, usually a register
(accumulator, AC)
LOAD D
MUL E
ADD C
STOR Y
LOAD A
SUB B
DIV Y
STOR Y
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 Using two addresses

One address doubles as operand and result

– Reduces length of instruction
MOV Y,A
SUB Y,B
MOV T,D
MUL T,E
ADD T,C
DIV Y,T

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 Instruction Cycle
• A program in the memory consists of a
sequence of instructions
• Program is executed in the computer by going
through a cycle for each instruction
• Each instruction cycle in turn is subdivided in
to a sequence of sub cycles or phases

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Instruction Cycle…

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 Fetch and Decode
• Program counter, PC is loaded with the
address of the first instruction in the program
• Sequence counter SC is cleared to 0, providing
a decoded timing signal T0
• After each clock pulse, SC is incremented by
one so that timing signals go through a
sequence T0, T1, T2

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micro operations for fetch & decode
phases

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 Instruction cycle…
• Decode IR[12-14] -identify type of instruction
• Decoder out put D7 is equal to 1 when the
operation code is 111
• If D7=1 register reference instruction;
otherwise memory reference Instruction

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