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VLSI LABORATORY

Department Of Electronics and


Communication Engineering

Paavai College of Engineering


Pachal,Namakkal

VLSI LAB SYLLABUS


SL. No. Experiments
Cycle-I Design and simulation of Combinational Logic Circuit using VHDL
1 Adder
2 Multiplexer and Demultiplexer
3 Encoder and Decoder
4 Multiplier
Cycle-II Design and simulation of Sequential logic circuit using VHDL
1 Flip Flops
2 Counter
3 Shift registers
Cycle-III CMOS Circuit design using Multisim (DC and Transient Analysis)
1 CMOS Inverter
2 CMOS NAND and NOR Gates
3 CMOS D Latch
Cycle-IV FPGA Implementation
1 4 bit Adder
2 Real Time Clock

TOOLS USED: Modelsim, Xilinx ISE and Multisim.

EX.No:1
DATE : ADDER
AIM:
To Simulate VHDL Program for Adder Using ModelSim SE 6.0a tool and verify the
output.
APPARATUS REQUIRED:
1. EDA Tool: ModelSim SE 6.0a
2. PC : WINDOWS OS

PROCEDURE:

1. Double click on ModelSim SE 6.0a icon in the Desktop.


2. Click file New  Source Verilog.
3. Type the program in the work space window.
4. Save the program as .v extension in Work.
5. Go to Compile  Type file name  Compile  Done.
6. Go to Simulate Start SimulationWorkSelect Filename Ok.
7. Go to View Debug WindowObjects.
8. Force the input by right clicking the input variables
9. Select all the variablesRight clickAdd To WaveSelected Signals.
10. Go to Simulate RunRun 100ps.
11. Then verify the output.

PROGRAM:
Half Adder(VHDL) using dataflow:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity halfadder is
port ( a,b : in std_logic;
sum, carry : out std_logic);
end halfadder;

architecture behavioral of halfadder is


begin
sum<= a xor b;
carry<= (a and b);
end behavioral;
Full Adder(VHDL) using dataflow:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fulladder is
port ( a,b,c : in std_logic;
sum, carry : out std_logic);
end fulladder;

architecture behavioral of fulladder is


begin
sum<= a xor b xor c;
carry<= (a and b) or (b and c) or (a and c);
end behavioral;

Half Adder(VHDL) using structural:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity and1 is
port ( a : in std_logic;
b : in std_logic;
y : out std_logic);
end and1;

architecture behavioral of and1 is


begin
y<= a and b;
end behavioral;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity xor1 is
port ( a : in std_logic;
b : in std_logic;
y : out std_logic);
end xor1;
architecture behavioral of xor1 is
begin
y<= a xor b;
end behavioral;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity halfadder is
port ( a,b : in std_logic;
sum, carry : out std_logic);
end halfadder;

architecture behavioral of halfadder is

component xor1
port(a,b: in std_logic; y: out std_logic);
end component;

component and1
port(a,b: in std_logic; y: out std_logic);
end component;

begin
x1: xor1 port map(a,b,sum);
a1: and1 port map(a,b,carry);

end behavioral;

Full Adder(VHDL) using structural:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity and1 is
port ( a : in std_logic;
b : in std_logic;
y : out std_logic);
end and1;

architecture behavioral of and1 is


begin
y<= a and b;
end behavioral;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity or1 is
port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end or1;

architecture behavioral of or1 is


begin
y<= a or b or c;
end behavioral;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity xor1 is
port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic);
end xor1;
architecture behavioral of xor1 is
begin
y<= a xor b xor c;
end behavioral;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fulladder is
port ( a, b, c : in std_logic;
sum, carry : out std_logic);
end fulladder;

architecture behavioral of fulladder is


component xor1
port(a,b,c: in std_logic; y: out std_logic);
end component;
component and1
port(a,b: in std_logic; y: out std_logic);
end component;
component or1
port(a,b,c: in std_logic; y: out std_logic);
end component;
signal y1,y2,y3:std_logic;
begin
x1: xor1 port map(a,b,c,sum);
a1: and1 port map(a,b,y1);
a2: and1 port map(b,c,y2);
a3: and1 port map(c,a,y3);
o1: or1 port map(y1,y2,y3,carry);
end behavioral;

ECE DEPARTMENT
PERFORMANCE 25
RECORD 15
VIVA-VOCE 10
TOTAL 50

RESULT:
Thus the half adder and full adder program using ModelSim SE 6.0a was stimulated and
output was verified.

EX.No:2
DATE : Multiplexer and Demultiplexer
AIM:
To Simulate VHDL Program for Multiplexer and Demultiplexer Using ModelSim SE
6.0a tool and verify the output.
APPARATUS REQUIRED:
1. EDA Tool: ModelSim SE 6.0a tool
2. PC:WINDOWS OS

PROCEDURE:

1. Double click on ModelSim SE 6.0a icon in the Desktop.


2. Click file New  Source Verilog.
3. Type the program in the work space window.
4. Save the program as .v extension in Work.
5. Go to Compile  Type file name  Compile  Done.
6. Go to Simulate Start SimulationWorkSelect Filename Ok.
7. Go to View Debug WindowObjects.
8. Force the input by right clicking the input variables
9. Select all the variablesRight clickAdd To WaveSelected Signals.
10. Go to Simulate RunRun 100ps.
11. Then verify the output.

PROGRAM:
2 to 1 MUX (VHDL) using dataflow:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity mux 2 to 1 is
port ( i1,i2,s : in std_logic;
y : out std_logic);
end mux 2 to 1;

architecture behavioral of mux 2 to 1 is


begin

y<=(not(s) and i1) or (s and i2);


end behavioral;

4 to 1 MUX (VHDL) using dataflow:


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity mux 4 to 1 is
port ( i1,i2,i3,i4,s1,s2 : in std_logic;
y : out std_logic);
end mux 4 to 1;

architecture behavioral of mux 4 to 1 is

begin

y<=(not(s1) and not(s2) and i1) or (not(s1) and (s2) and i2) or (s1 and not(s2) and i3) or
(s1 and s2 and i4);

end behavioral;

8 to 1 MUX (VHDL) using Behavioral:


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity mux 8 to 1 is
port(a : in std_logic_vector(7 downto 0);
sel : in std_logic_vector(2 downto 0);
y : out std_logic);
end mux 8 to 1;

architecture behavioral of mux 8 to 1 is

begin
process(sel,a)
begin
case sel is
when"000"=>
y<=a(0);
when"001"=>
y<=a(1);
when"010"=>
y<=a(2);
when"011"=>
y<=a(3);
when"100"=>
y<=a(4);
when"101"=>
y<=a(5);
when"110"=>
y<=a(6);
when"111"=>
y<=a(7);
when others=>
end case;
end process;
end behavioral;

1 to 2 DEMUX (VHDL) using dataflow:


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity demux 1 to 2 is
port ( i, s : in std_logic;
y1,y2 : out std_logic);
end demux 1 to 2;

architecture behavioral of demux 1 to 2 is

begin
y1<= i and (not(s));
y2<= i and s;

end behavioral;
1 to 4 DEMUX (VHDL) using dataflow:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity demux 1 to 4 is
port ( i,s1,s0 : in std_logic;
y1,y2,y3,y4 : out std_logic);
end demux 1 to 4;

architecture behavioral of demux 1 to 4 is

begin

y1<= i and (not(s1)) and (not(s0));


y2<= i and (not(s1)) and ((s0));
y3<= i and (s1) and (not(s0));
y4<= i and (s1) and (s0);

end behavioral;

1 to 8 DEMUX (VHDL) using dataflow:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity demux 1 to 8 is
port ( i,s0,s1,s3 : in std_logic;
y1,y2,y3,y4,y5,y6,y7,y8 : out std_logic);
end demux 1 to 8;

architecture behavioral of demux 1 to 8 is

begin
y1<= i and (not(s2)) and (not(s1)) and (not(s0));
y2<= i and (not(s2)) and (not(s1)) and (s0);
y3<= i and (not(s2)) and (s1) and (not(s0));
y4<= i and (not(s2)) and (s1) and (s0);
y5<= i and (s2) and (not(s1)) and (not(s0));
y6<= i and (s2) and (not(s1)) and (s0);
y7<= i and (s2) and (s1) and (not(s0));
y8<= i and (s2) and (s1) and (s0);
end behavioral;

ECE DEPARTMENT
PERFORMANCE 25
RECORD 15
VIVA-VOCE 10
TOTAL 50

RESULT:
Thus the Multiplexer and Demultiplexer program using ModelSim SE 6.0a was
stimulated and output was verified.

EX.No:3
DATE : Encoder and Decoder
AIM:
To Simulate VHDL Program for Encoder and Decoder Using ModelSim SE 6.0a tool and
verify the output.

APPARATUS REQUIRED:
3. EDA Tool: ModelSim SE 6.0a tool
4. PC:WINDOWS OS

PROCEDURE:

12. Double click on ModelSim SE 6.0a icon in the Desktop.


13. Click file New  Source Verilog.
14. Type the program in the work space window.
15. Save the program as .v extension in Work.
16. Go to Compile  Type file name  Compile  Done.
17. Go to Simulate Start SimulationWorkSelect Filename Ok.
18. Go to View Debug WindowObjects.
19. Force the input by right clicking the input variables
20. Select all the variablesRight clickAdd To WaveSelected Signals.
21. Go to Simulate RunRun 100ps.
22. Then verify the output.

PROGRAM:

2 to 4 Decoder:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity decoder 2 to 4 is
port ( e,i1,i2 : in std_logic;
o1,o2,o3,o4 : out std_logic);
end decoder 2 to 4;
architecture behavioral of decoder 2 to 4 is
begin
o1<= e and (not i1) and (not i2);
o2<= e and (not i1) and i2;
o3<= e and i1 and (not i2);
o4<= e and i1 and i2;

end behavioral;

3 to 8 Decoder:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity decoder 3 to 8 is
port ( e,i1,i2,i3 : in std_logic;
o1,o2,o3,o4,o5,o6,o7,o8 : out std_logic);
end decoder 3 to 8;

architecture behavioral of decoder3 to 8 is


begin
o1<= e and (not i1) and (not i2) and (not i3);
o2<= e and (not i1) and (not i2) and i3;
o3<= e and (not i1) and i2 and (not i3);
o4<= e and (not i1) and i2 and i3;
o5<= e and i1 and (not i2) and (not i3);
o6<= e and i1 and (not i2) and i3;
o7<= e and i1 and i2 and (not i3);
o8<= e and i1 and i2 and i3;
end behavioral;

2 to 4 Encoder:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity encoder 2 to 4 is
port ( i1,i2,i3,i4 : in std_logic;
o1,02 : out std_logic);
end encoder 2 to 4;

architecture behavioral of encoder 2 to 4 is


begin
o1<=(not (i1) and (i3) and not (i2) and not(i1)) or (i4 and not(i3) and not (i2) and not (i1));
o2<=(not (i4) and not(i3) and (i2) and not(i1)) or (i4 and not(i3) and not (i2) and not (i1));

end behavioral;

ECE DEPARTMENT
PERFORMANCE 25
RECORD 15
VIVA-VOCE 10
TOTAL 50

RESULT:
Thus the Encoder and Decoder program using ModelSim SE 6.0a was stimulated and
output was verified.

EX.No:4
DATE : Multiplier
AIM:
To Simulate VHDL Program for Multiplier Using ModelSim SE 6.0a tool and verify the
output.

APPARATUS REQUIRED:
5. EDA Tool: ModelSim SE 6.0a tool
6. PC:WINDOWS OS

PROCEDURE:

23. Double click on ModelSim SE 6.0a icon in the Desktop.


24. Click file New  Source Verilog.
25. Type the program in the work space window.
26. Save the program as .v extension in Work.
27. Go to Compile  Type file name  Compile  Done.
28. Go to Simulate Start SimulationWorkSelect Filename Ok.
29. Go to View Debug WindowObjects.
30. Force the input by right clicking the input variables
31. Select all the variablesRight clickAdd To WaveSelected Signals.
32. Go to Simulate RunRun 100ps.
33. Then verify the output.

PROGRAM:
Unsigned 8 x 4 bit Multiplier:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity mult is
port(A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(3 downto 0);
RES : out std_logic_vector(11 downto 0));
end mult;
architecture archi of mult is
begin
RES <= A * B;
end archi;

ECE DEPARTMENT
PERFORMANCE 25
RECORD 15
VIVA-VOCE 10
TOTAL 50

RESULT:
Thus the Multiplier program using ModelSim SE 6.0a was stimulated and output was
verified.

EX.No:5
DATE : Flip Flops
AIM:
To Simulate VHDL Program for Flip Flops Using ModelSim SE 6.0a tool and verify the
output.

APPARATUS REQUIRED:
1. ModelSim SE 6.0a tool
2. PC:XP/WINDOWS

PROCEDURE:

1. Double click on ModelSim SE 6.0a icon in the Desktop.


2. Click file New  Source Verilog.
3. Type the program in the work space window.
4. Save the program as .v extension in Work.
5. Go to Compile  Type file name  Compile  Done.
6. Go to Simulate Start SimulationWorkSelect Filename Ok.
7. Go to View Debug WindowObjects.
8. Force the input by right clicking the input variables
9. Select all the variablesRight clickAdd To WaveSelected Signals.
10. Go to Simulate RunRun 100ps.
11. Then verify the output.
PROGRAM:

DFF(VHDL) using Behavioral:


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dff is
port ( d,res,clk : in std_logic;
q : out std_logic);
end dff;

architecture behavioral of dff is


begin
process(clk)
begin
if(res='0') then q<='0';
elsif clk'event and clk='1'
then q<=d;
end if;
end process;
end behavioral;

JKFF(VHDL) using Behavioral:


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity jkff is
port(j,k,clk,reset : in std_logic;
q,qn : out std_logic);
end jkff;

architecture behavioral of jkff is


signal ff:std_logic;
begin
process(j,k,clk,reset)
variable jk:std_logic_vector(1 downto 0);
begin
jk:=j&k;
if(reset='0')then ff<='0';
elsif(clk'event and clk='1')then
case jk is
when"01"=>ff<='0';
when"10"=>ff<='1';
when"11"=>ff<=not(ff);
when others=>ff<=ff;
end case;
end if ;
end process;
q<=ff;
qn<=not(ff);
end behavioral;

SRFF(VHDL) using Behavioral:


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity srff is
port (s,r,clk : in std_logic;
q,qb : buffer std_logic);
end srff;

architecture behavioral of srff is

begin
q<= not((r and clk) or qb);
qb<= not((s and clk) or q);

end behavioral;

TFF(VHDL) using Dataflow:


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity tff is
port ( t,clk : in std_logic;
q : out std_logic);
end tff;

architecture behavioral of tff is


begin
q<= (t and clk);
end behavioral;

ECE DEPARTMENT
PERFORMANCE 25
RECORD 15
VIVA-VOCE 10
TOTAL 50

RESULT:
Thus the Flip Flops using ModelSim SE 6.0a was stimulated and output was verified.
EX.No:6
DATE :
COUNTER
AIM:
To Simulate VHDL Program for Counter Using ModelSim SE 6.0a tool and verify the
output.

APPARATUS REQUIRED:
1. ModelSim SE 6.0a tool
2. PC:XP/WINDOWS

PROCEDURE:

1. Double click on ModelSim SE 6.0a icon in the Desktop.


2. Click file New  Source Verilog.
3. Type the program in the work space window.
4. Save the program as .v extension in Work.
5. Go to Compile  Type file name  Compile  Done.
6. Go to Simulate Start SimulationWorkSelect Filename Ok.
7. Go to View Debug WindowObjects.
8. Force the input by right clicking the input variables
9. Select all the variablesRight clickAdd To WaveSelected Signals.
10. Go to Simulate RunRun 100ps.
11. Then verify the output.

PROGRAM:

UP COUNTER(VHDL) using Behavioral:


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity upcounter is
port ( clk,clr : in std_logic;
q : inout std_logic_vector (2 downto 0));
end upcounter;
architecture behavioral of upcounter is

begin
process(clk)

variable temp: std_logic_vector (2 downto 0):="000";


begin
if (rising_edge (clk)) then
if clr='0' then
case temp is
when "000"=>temp:="001";
when "001"=>temp:="010";
when "010"=>temp:="011";
when "011"=>temp:="100";
when "100"=>temp:="101";
when "101"=>temp:="110";
when "110"=>temp:="111";
when "111"=>temp:="000";
when others=>temp:="000";
end case;
else
temp:="000";
end if;
end if;
q<=temp;
end process;

end behavioral;

DOWN COUNTER(VHDL) using Behavioral:


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity downcounter is
port ( clk,clr : in std_logic;
q : inout std_logic_vector (2 downto 0));
end downcounter;

architecture behavioral of downcounter is

begin
process(clk)
variable temp: std_logic_vector (2 downto 0):="000";
begin

if (rising_edge (clk)) then


if clr='0' then
case temp is
when "000"=>temp:="111";
when "111"=>temp:="110";
when "110"=>temp:="101";
when "101"=>temp:="100";
when "100"=>temp:="011";
when "011"=>temp:="010";
when "010"=>temp:="001";
when "001"=>temp:="000";
when others=>temp:="000";
end case;
else
temp:="000";
end if;
end if;
q<=temp;
end process;

end behavioral;

BCD Counter(VHDL) using Behavioral:


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity bcd is
port ( clk,clr : in std_logic;
q : inout std_logic_vector (3 downto 0));
end bcd;

architecture behavioral of bcd is

begin
process(clk)

variable temp: std_logic_vector (3 downto 0):="0000";


begin
if (rising_edge (clk)) then
if clr='0' then
case temp is
when "0000"=>temp:="0001";
when "0001"=>temp:="0010";
when "0010"=>temp:="0011";
when "0011"=>temp:="0100";
when "0100"=>temp:="0101";
when "0101"=>temp:="0110";
when "0110"=>temp:="0111";
when "0111"=>temp:="1000";
when "1000"=>temp:="1001";
when others=>temp:="0000";
end case;
else
temp:="0000";
end if;
end if;
q<=temp;
end process;

end behavioral;

Synchronous mod- 4 counter using Behavioral:


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity syn4 is
port ( clk,rst : in std_logic;
q : inout std_logic_vector (2 downto 0));
end syn4;

architecture behavioral of syn4 is

begin
process(clk)

variable temp: std_logic_vector (2 downto 0):="000";


begin
if (rising_edge (clk)) then
if rst='0' then
case temp is
when "000"=>temp:="001";
when "001"=>temp:="010";
when "010"=>temp:="011";
when others=>temp:="000";
end case;
else
temp:="000";
end if;
end if;
q<=temp;
end process;

end behavioral;

Sequence counter using Behavioral:


Sequence: 01357

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity seq is
port ( clk,clr : in std_logic;
q : inout std_logic_vector (2 downto 0));
end seq;

architecture behavioral of seq is

begin
process(clk)

variable temp: std_logic_vector (2 downto 0):="000";


begin

if (rising_edge (clk)) then


if clr='0' then
case temp is
when "000"=>temp:="001";
when "001"=>temp:="011";
when "011"=>temp:="101";
when "101"=>temp:="111";
when others=>temp:="000";
end case;
else
temp:="000";
end if;
end if;
q<=temp;
end process;

end behavioral;

ECE DEPARTMENT
PERFORMANCE 25
RECORD 15
VIVA-VOCE 10
TOTAL 50

RESULT:
Thus the Counter program using ModelSim SE 6.0a was stimulated and output was
verified.
EX.No:7
DATE : SHIFT REGISTERS

AIM:
To Simulate VHDL Program for Shift Registers Using ModelSim SE 6.0a tool and verify
the output.

APPARATUS REQUIRED:

1. ModelSim SE 6.0a tool


2. PC:XP/WINDOWS

PROCEDURE:

12. Double click on ModelSim SE 6.0a icon in the Desktop.


13. Click file New  Source Verilog.
14. Type the program in the work space window.
15. Save the program as .v extension in Work.
16. Go to Compile  Type file name  Compile  Done.
17. Go to Simulate Start SimulationWorkSelect Filename Ok.
18. Go to View Debug WindowObjects.
19. Force the input by right clicking the input variables
20. Select all the variablesRight clickAdd To WaveSelected Signals.
21. Go to Simulate RunRun 100ps.
22. Then verify the output.

PROGRAM:

REGISTER:
library ieee;
use ieee.std_logic_1164.all;

entity reg is
port(clk : in std_logic;
input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(15 downto 0);
ld : in std_logic) ;
end reg;
architecture behavioral of reg is
begin
generic_register: process(clk, input, ld)
begin
if (rising_edge(clk)) then
if (ld = '1') then
output <= input ;
end if ;
end if ;
end process ;
end behavioral ;

8-bit Shift Register with Positive-Edge Clock, Serial In, and


Serial Out:
library ieee;
use ieee.std_logic_1164.all;

entity siso is
port(C, SI : in std_logic;
SO : out std_logic);
end siso;

architecture archi of siso is


signal tmp: std_logic_vector(7 downto 0);

begin
process (C)
begin
if (C'event and C='1') then
for i in 0 to 6 loop
tmp(i+1) <= tmp(i);
end loop;
tmp(0) <= SI;
end if;
end process;
SO <= tmp(7);
end archi;
8-bit Shift Register with Positive-Edge Clock, Serial In,
and Parallel Out:

library ieee;
use ieee.std_logic_1164.all;

entity sipo is
port(C, SI : in std_logic;
PO : out std_logic_vector(7 downto 0));
end sipo;

architecture archi of sipo is


signal tmp: std_logic_vector(7 downto 0);

begin
process (C)
begin
if (C'event and C='1') then
tmp <= tmp(6 downto 0) & SI;
end if;
end process;
PO <= tmp;
end archi;

ECE DEPARTMENT
PERFORMANCE 25
RECORD 15
VIVA-VOCE 10
TOTAL 50

RESULT:
Thus the Shift Registers program using ModelSim SE 6.0a was stimulated and output
was verified.
EX.No:8
DATE : CMOS INVERTER

AIM:
To Design CMOS Inverter Using Multisim Software and verify the output.

APPARATUS REQUIRED:
1. Multisim Software
2. PC:XP/WINDOWS

Inverter Circuit:
DC Operating Point:

ECE DEPARTMENT
PERFORMANCE 25
RECORD 15
VIVA-VOCE 10
TOTAL 50

RESULT:
Thus the CMOS Inverter is Designed using Multisim and output was verified.
EX.No:9
DATE : CMOS NAND and NOR Gates

AIM:
To Design CMOS NAND and NOR Gates Using Multisim Software and verify the
output.

APPARATUS REQUIRED:
3. Multisim Software
4. PC:XP/WINDOWS

NAND Gate Circuit:


DC Operating Point:

NOR Gate Circuit:


DC Operating Point:

ECE DEPARTMENT
PERFORMANCE 25
RECORD 15
VIVA-VOCE 10
TOTAL 50

RESULT:
Thus the CMOS NAND and NOR Gates is Designed using Multisim and output was
verified.
EX.No:10
DATE : CMOS D Latch

AIM:
To Design CMOS D Latch using Multisim Software and verify the output.

APPARATUS REQUIRED:
5. Multisim Software
6. PC:XP/WINDOWS

D Latch with NAND Gate Circuit:


Circuit:

DC Operating Point:
ECE DEPARTMENT
PERFORMANCE 25
RECORD 15
VIVA-VOCE 10
TOTAL 50

RESULT:
Thus the CMOS D Latch is Designed using Multisim and output was verified.
EX.No:11
DATE : 4 BIT ADDER
AIM:
To Study the synthesis of a VHDL Program Using tools in XILINX ISE 8.2i Software.

APPARATUS REQUIRED:
1. XILINX ISE 8.2i tool
2. PC:XP/WINDOWS

PROCEDURE:

1. Double click on XILINX ISE 8.2i icon in the Desktop.


2. Click file New project  Enter the project name & Location, Select top level source
type as HDL. Click NEXT.
3. In the device property window select the details:
4. Click NextNEXTNEXTFINISH.
5. Click Project  New source  Select Verilog module, Enter the file Name
NEXTNEXT  FINISH.
6. Type program in the work space window.
7. Save the program.
8. Double click the synthesis XST in the process window.
9. Click view RTL schematic in the synthesis XST.
10. Click view Technology schematic in the synthesis XST.
11. Verify the schematic diagram.

PROGRAM:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity fadd4 is
port(a,b : in std_logic_vector(3 downto 0);
cin : in std_logic;
s : out std_logic_vector(3 downto 0);
cout : out std_logic);
end fadd4;
architecture structural of fadd4 is
component fulladd
port(a,b,cin : in std_logic;
sum,cout : out std_logic);
end component;
signal c1,c2,c3: std_logic;
begin

a0: fulladd port map (a(0),b(0),cin,s(0),c1);


a1: fulladd port map (a(1),b(1),c1,s(1),c2);
a2: fulladd port map (a(2),b(2),c2,s(2),c3);
a3: fulladd port map (a(3),b(3),c3,s(3),cout);

end structural;

ECE DEPARTMENT
PERFORMANCE 25
RECORD 15
VIVA-VOCE 10
TOTAL 50

RESULT:
Thus the 4 Bit Adder program using XILINX ISE 8.2i Software was stimulated and
output was verified.
EX.No:12
DATE : Real Time Clock
AIM:
To Study the synthesis of a VHDL Program Using tools in XILINX ISE 8.2i Software.

APPARATUS REQUIRED:
3. XILINX ISE 8.2i tool
4. PC:XP/WINDOWS

PROCEDURE:

12. Double click on XILINX ISE 8.2i icon in the Desktop.


13. Click file New project  Enter the project name & Location, Select top level
source type as HDL. Click NEXT.
14. In the device property window select the details:
15. Click NextNEXTNEXTFINISH.
16. Click Project  New source  Select Verilog module, Enter the file Name
NEXTNEXT  FINISH.
17. Type program in the work space window.
18. Save the program.
19. Double click the synthesis XST in the process window.
20. Click view RTL schematic in the synthesis XST.
21. Click view Technology schematic in the synthesis XST.
22. Verify the schematic diagram.

PROGRAM:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity rtc_im is
port(reset,clk_4m,load,control:in std_logic;
rtc_seg:out std_logic_vector(7 downto 0);
rtc_dis:out std_logic_vector(5 downto 0));
end rtc_im;

architecture behavioral of rtc_im is


signal tc,tc1,tc2,tc3,tc4,tc5,tc6,enable:std_logic;
signal sec1,sec2,min1,min2,hr1,hr2: std_logic_vector(3 downto 0);
signal sec1_rg:std_logic_vector(3 downto 0);
signal sec2_rg:std_logic_vector(3 downto 0);
signal min1_rg:std_logic_vector(3 downto 0);
signal min2_rg:std_logic_vector(3 downto 0);
signal hr1_rg:std_logic_vector(3 downto 0);
signal hr2_rg:std_logic_vector(3 downto 0);
signal pulsegen:std_logic_vector(21 downto 0);
signal sel:std_logic_vector(2 downto 0);
signal mout:std_logic_vector(3 downto 0);
signal sgout:std_logic_vector(7 downto 0);
signal dis_sig:std_logic_vector(5 downto 0);
signal cnk2:std_logic_vector(2 downto 0);
begin
--*************************** pulse generator ******************
p0:process(reset,clk_4m,pulsegen)
begin
if (reset = '1') then
pulsegen <= "0000000000000000000000";
elsif rising_edge (clk_4m) then
if (pulsegen = "1111010000100100000000") then
pulsegen <= "0000000000000000000000";
else
pulsegen <= pulsegen + 1;
end if;
end if;
end process;
---------- enable signal to generate 1-sec pulse for sec1 counter

enable <= '1' when pulsegen = "1111010000100100000000" else --enable signal for sec1
counter
'0';
--************************ second_cntr1 *************************
p1:process (reset,clk_4m,sec1_rg,enable,load) --decade counter
begin
if (reset = '1') then
sec1_rg <= "0000";
elsif load = '1' then
sec1_rg <= "0100";

elsif rising_edge(clk_4m) then


if (enable = '1') then
if (sec1_rg = "1001")then
sec1_rg <= "0000";
else
sec1_rg <= sec1_rg + 1;
end if;
end if;
end if;
sec1 <= sec1_rg;
end process ;
-----------------------tc signal to start sec2 counter----------------------------------
tc <= '1' when (sec1_rg = "1001") and (enable = '1') else --signal for sec2 counter
'0';
--************************* second_cntr2 ***********************

p2:process (reset,clk_4m,sec2_rg,tc,load) --sec2 counter for reading upto 59 sec


begin
if (reset = '1') then
sec2_rg <= "0000";
elsif (load = '1') then
sec2_rg <= "0100";
elsif rising_edge(clk_4m) then
if (tc = '1') then
if (sec2_rg = "0101")then
sec2_rg <= "0000";
else
sec2_rg <= sec2_rg + 1;
end if;
end if;
end if;
sec2 <= sec2_rg;
end process;
-----------------------------tc1 signal to start min1 counter------------------------
tc1 <= '1' when (sec2_rg = "0101") and (tc = '1') else
'0' ;
--************************ minute_cntr1 *************************
p3:process(reset,clk_4m,min1_rg,tc1,load) -- min1 counter
begin
if (reset = '1') then
min1_rg <= "0000";
elsif load = '1' then
min1_rg <= "0100";
elsif rising_edge(clk_4m) then
if (tc1 = '1') then
if (min1_rg = "1001")then
min1_rg <= "0000";
else
min1_rg <= min1_rg + 1;
end if;
end if;
end if;
min1 <= min1_rg;
end process;
--------------------------tc2 signal to start min2 counter----------------------------
tc2 <= '1' when (min1_rg ="1001") and (tc1 = '1') else --pulse for min2 counter
'0';
--************************ minute_cntr2 *************************
p4:process(reset,clk_4m,min2_rg,tc2,load) --min2 counter
begin
if (reset = '1') then
min2_rg <= "0000";
elsif load = '1' then
min2_rg <= "0100";
elsif rising_edge(clk_4m) then
if (tc2 = '1') then
if (min2_rg = "0101")then
min2_rg <= "0000";
else
min2_rg <= min2_rg + 1;
end if;
end if;
end if;
min2 <= min2_rg;
end process;
--------------------------tc3 signal to start hr1 counter----------------------------------
tc3 <= '1' when (min2_rg ="0101") and (tc2 = '1') else
'0';
--************************ hour_cntr1 *************************
p5:process(reset,clk_4m,hr1_rg,tc3,load,control,tc6,tc5) --hr1 counter
begin
if (reset = '1') then
hr1_rg <= "0000";
elsif (load = '1') then
hr1_rg <= "0001";
elsif rising_edge(clk_4m) then
if control = '1' then
if (tc5 = '1') then
hr1_rg <= "0000";
else
if (tc3 = '1') then
if (hr1_rg = "1001")then
hr1_rg <= "0000";
else
hr1_rg <= hr1_rg + 1;
end if;
end if;
end if;
else
if (tc6 = '1') then
hr1_rg <= "0001";
else
if (tc3 = '1') then
if (hr1_rg = "1001")then
hr1_rg <= "0000";
else
hr1_rg <= hr1_rg + 1;
end if;
end if;
end if;
end if;
end if;
hr1 <= hr1_rg;
end process;
---------------------tc4 signal to start hr2 counter--------------------------
tc4 <= '1' when (hr1_rg ="1001") and (tc3 = '1') else
'0';
------------------------tc5 signal to reset at 23:59:59--------------------------
tc5 <= '1' when (hr2_rg ="0010")and (hr1_rg ="0011") and (tc3 = '1') else
'0';
-----------------------------tc6 signal to reset at 11:59:59---------------
tc6 <= '1' when (hr2_rg = "0001") and (hr1_rg = "0010") and (tc3 = '1') else
'0';
--************************ hour_cntr2 *************************
p6:process(reset,clk_4m,hr2_rg,tc4,load,control) --hr2 counter
begin
if (reset = '1') then
hr2_rg <= "0000";
elsif load = '1' then
hr2_rg <= "0000";
elsif rising_edge(clk_4m) then
if (control = '1') then
if (tc5 = '1') then
hr2_rg <="0000";
else
if (tc4 = '1') then
if (hr2_rg = "0010")then
hr2_rg <= "0000";
else
hr2_rg <= hr2_rg + 1;
end if;
end if;
end if;
else
if (tc6 = '1') then
hr2_rg <="0000";
else
if (tc4 = '1') then
if (hr2_rg = "0001")then
hr2_rg <= "0000";
else
hr2_rg <= hr2_rg + 1;
end if;
end if;
end if;
end if;
end if;
hr2 <= hr2_rg;
end process;
p14:process(reset, pulsegen(9))
begin
if (reset = '1') then
cnk2 <= "000";
elsif rising_edge(pulsegen(9)) then
if (cnk2 = "101") then
cnk2 <= "000";
else
cnk2 <= cnk2 + 1;
end if;
end if;
end process;
mout <= sec1 when cnk2 = "000" else
sec2 when cnk2 = "001" else
min1 when cnk2 = "010" else
min2 when cnk2 = "011" else
hr1 when cnk2 = "100" else
hr2 when cnk2 = "101";
--********hgfedcba****************************
sgout <= "11000000" when mout = "0000" else
"11111001" when mout = "0001" else
"10100100" when mout = "0010" else
"10110000" when mout = "0011" else
"10011001" when mout = "0100" else
"10010010" when mout = "0101" else
"10000010" when mout = "0110" else
"11111000" when mout = "0111" else
"10000000" when mout = "1000" else
"10011000" when mout = "1001" else
"11111111" ;
dis_sig <= "111110" when cnk2 = "000" else
"111101" when cnk2 = "001" else
"111011" when cnk2 = "010" else
"110111" when cnk2 = "011" else
"101111" when cnk2 = "100" else
"011111" ;--when cnk2 = "101" ;
rtc_seg <= not sgout;
rtc_dis <= not dis_sig;
end behavioral;

ECE DEPARTMENT
PERFORMANCE 25
RECORD 15
VIVA-VOCE 10
TOTAL 50

RESULT:
Thus the Real time clock program using XILINX ISE 8.2i Software was stimulated and
output was verified.