CoSc-2043: Microprocessor and Assembly Language

Chapter 2: 8086 Microprocessor and its Architecture

2.0 INTRODUCTION
 A processor is the logic circuitry that responds to and processes the basic instructions
that drives a computer. The processor is the computer’s brain.
 The processor (CPU) in a personal computer or embedded in small devices is often
called a microprocessor.
 Microprocessor is a program-controlled device, which fetches the instructions from
memory, decodes and executes the instructions. Most microprocessors are single- chip
devices.
 Microprocessor speed depends on the Data Bus width.
 A common way of categorizing microprocessors is by the number of bits that ALU can
work with at a time.

2.1 8086 MICROPROCESSOR

The concept of 8086’s principles and structures is very useful to understanding any other
advanced Intel microprocessors
 It is the first 16- bit microprocessor released by Intel in 1978.
 It’s ALU, internal registers work with 16 bit binary word. It means 16-bit numbers are
directly processed by 8086.
 It has 16-bit data bus, so it can read data or write data to memory or I/O ports either 16-
bits or 8-bits at a time.
 It has 20 bit address bus (20 address lines), so it can address up to 220 = 1048576 = 1M
bytes of memory locations (words i.e. 16-bit numbers are stored in consecutive memory
locations).
 Due to the 1 Mbytes memory size multiprogramming is made feasible as well as several
multiprogramming features have been incorporated in 8086 design.
 8086 includes few features, which enhance multiprocessing capability (it can be used
with math coprocessors like 8087, I/O processor 8089 etc.)
 It provides 14, 16-bit registers.
 It has multiplexed address and data bus (AD0- AD15 and A16 – A19) like 8085 due to
which the pin count is reduced considerably.
 Operates on +5v supply and single phase (single line) clock frequency (Clock is
generated by separate peripheral chip 8284).
 8086 comes with different versions. 8086 runs at 5 MHz, 8086-2 runs at 8 MHz, 8086-
1 runs at 10 MHz.
 It comes in 40-pin configuration with HMOS technology having around 29,000
transistors in its circuitry.
 Higher Throughput (Speed) is achieved by a concept called pipelining. It can prefetch
up to 6 instruction bytes from memory and queues them in order to speed up.
 8086 is designed to operate in two modes, Minimum mode and Maximum mode.
o The minimum mode is selected by applying logic 1 to the MN / MX# input pin.
This is a single microprocessor configuration.
o The maximum mode is selected by applying logic 0 to the MN / MX# input pin.
This is a multi- microprocessors configuration.

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2.2 The 8086 MICROPROCESSOR ARCHITECTURE

 8086 has two blocks: Bus Interface Unit (BIU) and Execution Unit (EU).
 The BIU performs all bus operations such as instruction fetching, reading and writing
operands for memory and calculating the addresses of the memory operands. The
instruction bytes are transferred to the instruction queue.
 EU executes instructions from the instruction system byte queue.
 Both units operate asynchronously to give the 8086 an overlapping instruction fetch
and execution mechanism which is called as Pipelining. This results in efficient use of
the system bus and system performance.
 BIU contains Instruction queue, Segment registers, Instruction pointer and Address
adder.
 EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register,
Flag register.

Figure 1.6: The architecture of 8086 microprocessor.

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Bus Interface Unit (BIU)

BIU provides a full 16 bit bidirectional data bus and 20 bit unidirectional address bus. The bus
interface unit is responsible for performing all external bus operations. Specifically it has the
following functions:
 Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation
and Bus control.
 The BIU uses a mechanism known as an instruction stream queue to implement pipeline
architecture (pipelining).
 This queue permits prefetch of up to six bytes of instruction code. Whenever the
instruction queue is not full, and it has room for at least two more bytes and at the same
time the EU is not requesting it to read or write operands from memory, the BIU fetches
the next sequential instruction of the program.
 These prefetching instructions are held in its FIFO queue (instruction queue). With its
16 bit data bus, the BIU fetches two instruction bytes in a single memory cycle.
 After a byte is loaded at the input end of the queue, it automatically shifts up through
the FIFO to the empty location nearest the output.
 The EU accesses the queue from the output end. It reads one instruction byte after the
other from the output of the queue.
 If the BIU is already in the process of fetching an instruction when EU request it to read
or write operands from memory or I/O, the BIU first completes the instruction fetch bus
cycle before initiating the operand read / write cycle.
 The BIU also contains a dedicated adder which is used to generate the 20 bit physical
address. This address is formed by adding an appended 16 bit segment address and a
16 bit offset address.
o For example: The physical address of the next instruction to be fetched is
formed by combining the current contents of the code segment CS register and
the current contents of the instruction pointer IP register.
 The BIU is also responsible for generating bus control signals such as those for memory
read or write and I/O read or write.

Execution Unit (EU)

 The Execution unit is responsible for decoding and executing all instructions.
 The EU extracts instructions from the top of the queue in the BIU, decodes them,
generates operands if necessary, passes them to the BIU and requests it to perform the
read or write bus cycles to memory or I/O and perform the operation specified by the
instruction on the operands.
 During the execution of the instruction, the EU tests the status and control flags and
updates them based on the results of executing the instruction.
 If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted
to top of the queue.
 When EU executes a branch or jump instruction, it transfers control to a location
corresponding to another set of sequential instructions.
 Whenever this happens, the BIU automatically resets the queue and then begins to fetch
instructions from this new location to refill the queue.

2.3 REGISTER ORGANIZATION OF 8086

The 8086 microprocessor has a total of 14 registers that are accessible to the programmer. It is
divided into four groups. They are:
 Four General purpose registers

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 Four Index/Pointer registers

 Four Segment registers
 Two Other registers

2.3.1 General purpose registers

Figure 1.7: General purpose registers.

The AX, BX, CX, and DX registers can be considered as two 8-bit registers, a High byte and
a Low byte. This allows byte operations and compatibility with the previous generation of 8-
bit processors, the 8080 and 8085.

Accumulator Register (AX)

 Consists of two 8-bit registers AL and AH, which can be combined together and used
as a 16-bit register AX.
 AL in this case contains the low order byte of the word, and AH contains the high- order
byte.
 The I/O instructions use the AX or AL for inputting / outputting 16 or 8 bit data to or
from an I/O port.
 Multiplication and Division instructions also use the AX or AL.

Base Register (BX)

 Consists of two 8-bit registers BL and BH, which can be combined together and used
as a 16-bit register BX.
 BL in this case contains the low-order byte of the word, and BH contains the high- order
byte.
 This is the only general purpose register whose contents can be used for addressing the
8086 memory.
 All memory references utilizing this register content for addressing use DS as the
default segment register.
 BX register usually contains a data pointer used for based, based indexed or register
indirect addressing.

Counter Register (CX)

 Consists of two 8-bit registers CL and CH, which can be combined together and used
as a 16-bit register CX.
 When combined, CL register contains the low order byte of the word, and CH
contains the high-order byte.
 Count register can be used in Loop, shift/rotate instructions and as a counter in string
manipulation.

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Data Register (DX)

 Consists of two 8-bit registers DL and DH, which can be combined together and used
as a 16-bit register DX.
 When combined, DL register contains the low order byte of the word, and DH contains
the high-order byte.
 Data register can be used as a port number in I/O operations. In integer 32-bit multiply
and divide instruction the DX register contains high-order word of the initial or
resulting number.

2.3.2 Index or Pointer Registers

These registers can also be called as Special Purpose registers.

Figure 1.8: Index or Pointer Registers.

Stack Pointer (SP) is a 16-bit register pointing to program stack, i.e. it is used to hold the
address of the top of stack. The stack is maintained as a LIFO with its bottom at the start of the
stack segment (specified by the SS segment register). Unlike the SP register, the BP can be
used to specify the offset of other program segments.
Base Pointer (BP) is a 16-bit register pointing to data in stack segment. It is usually used by
subroutines to locate variables that were passed on the stack by a calling program. BP register
is usually used for based, based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register used for indexed, based indexed and register indirect
addressing, as well as a source data address in string manipulation instructions. Used in
conjunction with the DS register to point to data locations in the data segment.
Destination Index (DI) is a 16-bit register used in conjunction with the ES register in string
operations. DI is used for indexed, based indexed and register indirect addressing, as well as a
destination data address in string manipulation instructions. In short, Destination Index and SI
Source Index registers are used to hold address.

2.3.3 Segment Registers

Most of the registers contain data/instruction offsets within 64 KB memory segment. There are
four different 64 KB segments for instructions, stack, data and extra data in memory. To specify
where in 1 MB of processor memory these 4 segments are located, the processor uses four
segment registers.

Figure 1.9: Segment Registers.

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Code Segment (CS) Register

 Its a16-bit register contains the base or start address of the 64KB current code segment
of memory.
 IP contains the distance or offset from this address to the next instruction byte to be
fetched.
 BIU computes the 20-bit physical address by logically shifting the contents of CS 4-
bits to the left and then adding the 16-bit contents of IP.
 That is, all instructions of a program are relative to the contents of the CS register
multiplied by 16 and then offset is added provided by the IP.

Data Segment (DS) Register

 Its a16-bit register contains the address of 64KB segment with program data.
 Operands for most instructions are fetched from this segment.
 The 16-bit contents of the Source Index (SI) or Destination Index (DI) or a 16-bit
displacement are used as offset for computing the 20-bit physical address.

Stack Segment (SS) Register

 Its a16-bit register contains the address of 64KB segment with program stack. By
default, the processor assumes that all data referenced by the stack pointer (SP) and
base pointer (BP) registers is located in the stack segment.
 The 20-bit physical stack address is calculated from the Stack Segment (SS) and the
Stack Pointer (SP) for stack instructions such as PUSH and POP.
 In based addressing mode, the 20-bit physical stack address is calculated from the Stack
segment and the Base Pointer (BP).

Extra Segment (ES) Register

 Its a16-bit register, points to the extra segment in which data (in excess of 64K pointed
to by the DS) is stored.
 String instructions use the ES and DI to determine the 20-bit physical address for the
destination.

2.3.4 Other Registers of 8086

The other two registers of 8086 are:
 Instruction Pointer (IP)
 Instruction Queue
 Flag Register

Instruction Pointer (IP)

 Its a16-bit register, always points to the next instruction to be executed within the
currently executing code segment.
 So, this register contains the 16-bit offset address pointing to the next instruction code
within the 64KB of the code segment area.
 Its content is automatically incremented as the execution of the next instruction takes
place.

Instruction queue
 A group of First-In-First-Out (FIFO) in which up to 6 bytes of instruction code are pre
fetched from the memory ahead of time.

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 This is done in order to speed up the execution by overlapping instruction fetch with
execution.
 This mechanism is known as pipelining.

Flag Register
 Flag register contains a group of status bits called flags that indicate the status of the
CPU or the result of arithmetic operations. There are two types of flags:
o Status flags which reflect the result of executing an instruction. The programmer
cannot set/reset these flags directly.
o Control flags enable or disable certain CPU operations. The programmer can
set/reset these bits to control the CPU's operation.
 Nine individual bits of the flag register are used as control flags (3 of them) and status
flags (6 of them). The remaining 7 are not used.
 A flag can only take on the values 0 and 1. We say a flag is set if it has the value 1.The
status flags are used to record specific characteristics of arithmetic and of logical
instructions.

Control Flags
There are three control flags
1. Direction Flag (D): Affects the direction of moving data blocks by such instructions
as MOVS, CMPS and SCAS. The flag values are 0 = up and 1 = down and can be
set/reset by the STD (set D) and CLD (clear D) instructions.
2. Interrupt Flag (I): Indicates whether or not system interrupts can occur. Interrupts are
actions initiated by hardware block such as input devices that will interrupt the normal
execution of programs. The flag values are 0 = disable interrupts or 1 = enable interrupts
and can be manipulated by the CLI (clear I) and STI (set I) instructions.
3. The Trap Flag (T): Determines whether or not the CPU is halted after the execution
of each instruction. When this flag is set (i.e. = 1), the programmer can single step
through his program to debug any errors. When this flag = 0 this feature is off. This
flag can be set by the INT 3 instruction.

Status Flags
There are six status flags
1. Carry Flag (C): This flag is set when there is an end carry in an addition operation or
there is an end borrows in a subtraction operation. A value of 1 = carry and 0 = no carry.
2. Overflow Flag (O): This flag is set when the result of a signed arithmetic operation is
too large to fit in the destination register (i.e. when an overflow occurs). Overflow can

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occur when adding two numbers with the same sign. A value of 1 = overflow and 0 =
no overflow.
3. Sign Flag (S): This flag is set when the result of an arithmetic or logic operation is
negative. This flag is a copy of the MSB of the result (i.e. the sign bit). A value of 1 =
negative and 0 = positive.
4. Zero Flag (Z): This flag is set when the result of an arithmetic or logic operation is
equal to zero. A value of 1 means the result is zero and a value of 0 means the result is
not zero.
5. Auxiliary Carry Flag (A): This flag is set when an operation causes a carry from bit 3
to bit 4 (or a borrow from bit 4 to bit 3) of an operand. A value of 1 = carry and 0 = no
carry.
6. Parity Flag (P): This flags reflects the number of 1’s in the result of an operation. If
the number of 1’s is even its value = 1 and if the number of 1’s is odd then its value =
0.

2.4 PIN DIAGRAM OF 8086

The 8086 Microprocessor is available in different clock rates and packaged in a 40 pin
configuration
The 8086 operates in single processor or multiprocessor configuration to achieve high
performance. The pins serve a particular function in minimum mode (single processor mode)
and other function in maximum mode configuration (multiprocessor mode).

Figure 1.10: PIN Diagram of 8086.

The 8086 signals can be categorized in three groups.

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 The first are the signal having common functions in minimum as well as maximum
mode.
 The second are the signals which have special functions for minimum mode
 The third are the signals having special functions for maximum mode.

2.4.1 Pin Description

AD15-AD0 (address/data bus multiplexed):
 When AD lines are used to transmit memory address the symbol A is used instead of
AD, for example A0-A15.
 When data are transmitted over AD lines the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.
o memory address or I/O port no : whenever ALE = 1 (ALE: Address Latch
Enable)
o data : whenever ALE = 0

A19/S6-A16/S3 (address/status bus multiplexed): High order addresses bus. These are
multiplexed with status signals

BHE (Active Low)/S7 (Output):

 Bus High Enable/Status
 It is used to enable data onto the most significant half of data bus, D8-D15. 8-bit device
connected to upper half of the data bus use BHE (Active Low) signal. It is multiplexed
with status signal S7.

RD (Read):
 This signal on Active low indicates the processor is performing memory or I/O read
operation.
 It is an output signal. It is active when low.

READY: This is the acknowledgement from the slow device or memory that they have
completed the data transfer.
 μp enter into wait states and remain idle : READY = 0
 no effect on the operation of μp : READY = 1

INTR (interrupt request):

 This is a triggered input. This is sampled during the last clock cycles of each instruction
to determine the availability of the request.
 If any interrupt request is pending, the processor enters the interrupt acknowledge cycle.
This can be internally masked by resulting the interrupt enable flag. This signal is active
high and internally synchronized.

TEST:
 This input is examined by a ‘WAIT’ instruction.
 If the TEST pin goes low, execution continue, else the processor remains in an idle
state.

CLK- Clock Input: The clock input provides the basic timing for processor operation and bus
control activity. It’s an asymmetric square wave with 33% duty cycle.

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The following pin functions are for the minimum mode operation of 8086.
In the minimum mode of operation the microprocessor does not associate with any
coprocessors and cannot be used for multiprocessor systems.

M/IO - Memory/IO: This is a status line.

 When it is low, it indicates the CPU is having an I/O operation, and when it is high, it
indicates that the CPU is having a memory operation.
INTA - Interrupt Acknowledge: This signal is used as a read strobe for interrupt acknowledge
cycles. i. e. when it goes low, the processor has accepted the interrupt.
ALE - Address Latch Enable: This output signal indicates the availability of the valid address
on the address/data lines, and is connected to latch enable input of latches. This signal is active
high.
DT/R - Data Transmit/Receive: This output is used to decide the direction of data flow
through the transceivers (bidirectional buffers). When the processor sends out data, this signal
is high and when the processor is receiving data, this signal is low.
DEN - Data Enable: This signal indicates the availability of valid data over the address/data
lines. It is used to enable the transceivers (bidirectional buffers) to separate the data from the
multiplexed address/data signal.
HOLD, HLDA- Acknowledge: When the HOLD line goes high; it indicates to the processor
that another master is requesting the bus access. The processor, after receiving the HOLD
request, issues the hold acknowledge signal on HLDA pin, in the middle of the next clock cycle
after completing the current bus cycle.

The following pin functions are applicable for maximum mode operation of 8086.
S2, S1, and S0 – Status Lines: These are the status lines which reflect the type of operation,
being carried out by the processor. These become active during T4 of the previous cycle and
active during T1 and T2 of the current bus cycles.
LOCK: This output pin indicates that other system bus master will be prevented from gaining
the system bus, while the LOCK signal is low. The LOCK signal is activated by the ‘LOCK’
prefix instruction and remains active until the completion of the next instruction. When the
CPU is executing a critical instruction which requires the system bus, the LOCK prefix
instruction ensures that other processors connected in the system will not gain the control of
the bus.

2.5 MEMORY SEGMENTS OF 8086

Computer memory consists of an ordered sequence of storage units (8-bits called bytes), each
with its own address.
 8086’s memory is bytes-addressable, which means that each byte has its own address,
e.g. if A is the address of a word (16 bits), then A is actually the address of the first byte
(bits 0-7) of the word, A+1 is the address of the second byte (bits 8-15) of the word,
and A+2 is the address of the next word.
 Memory address space: (MAS): 220= 1, 048, 576= 1M bytes (address space: 0 - 220- 1,
i.e.00000 - FFFFF: in hexadecimal)
 Map of the memory address space (MAS) - The whole MAS is organized by a 216 * 24
matrix: there are 216 paragraphs, each of which with 16 (24) bytes.

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Figure 1.11: Map of the memory address space (MAS) of 8086 microprocessor.

Segments and Offsets

 All real (physical or absolute) memory addresses must consist of a segment address
plus an offset address. The segment address, located within one of the segment
registers, defines the beginning address of any 64K-byte memory segment.
 The offset address selects any location within the 64K byte memory segment. Segments
in the real mode always have a length of 64K bytes.
 In the real mode, each segment register is internally appended with a 0H on its rightmost
end. This forms a 20-bit memory address, allowing it to access the start of a segment.
 The microprocessor must generate a 20-bit memory address to access a location within
the first 1M of memory. For example, when a segment register contains 1200H, it
addresses a 64K-byte memory segment beginning at location 12000H. Likewise, if a
segment register contains 1201H, it addresses a memory segment beginning at location
12010H. Because of the internally appended 0H, real mode segments can begin only
at a l6-byte boundary in the memory system. This l6-byte boundary is often called a
paragraph.
 Because a real mode segment of memory is 64K in length, once the beginning address
is known, the ending address is found by adding FFFFH. For example, if a segment
register contains 3000H, the first address of the segment is 30000H, and the last address
is 30000H + FFFFH or 3FFFFH.
 The offset address, which is a part of the address, is added to the start of the segment to
address a memory location within the memory segment. For example, if the segment
address is 1000H and the offset address is 2000H, the microprocessor addresses
memory location 12000H.
 The segment and offset address is sometimes written as 1000:2000 for a segment
address of 1000H with an offset of 2000H.
 Segments are < or = 64K and can overlap. Note that the Code segment is < 64K since
0FFFFFH is the highest address.

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Offset Registers for Various Segments: The following Table provides a summary of the
offset registers that can be used with the four segment registers of the 8086/8088:

Segment Register CS DS ES SS
Offset Register IP SI, DI, BX SI, DI, BX SP, BP

The Code Segment

 The offset is given by the IP for the Code Segment.
 Instructions are always fetched using the CS register

The Data Segment

 Data is usually fetched with respect to the DS register.
 The effective address (EA) is the offset.
 The EA depends on the addressing mode.

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2.5 ADDRESSING MODES OF 8086/8088

 Addressing mode indicates a way of locating data or operands in a register or a memory
location. Every instruction of a program has to operate on a data.
 The different ways in which a source operand is denoted in an instruction are known as
addressing modes.
 The general addressing modes of 8086 microprocessor can be classified as:
1. Data Addressing Modes
2. Program-Memory Addressing Modes
3. Stack-Memory Addressing Modes

Instruction, Opcode and Operand

An instruction is an elementary operation that the processor can accomplish. Instructions are
stored in the main memory, waiting to be processed by the processor. An instruction has two
fields:
 Operation code (opcode) represents the action that the processor must execute. It is a
single instruction can be executed by the CPU. In assembly language mnemonic form
an opcode is a command such as MOV or ADD or JMP.
Example:
MOV AX, 1000H ; MOV is the opcode
; AX (register) is an operand

Operand defines the parameters of the action. Operands are manipulated by the opcode. It can
be data or a memory address. In this example, the operands are the register AX and the value
1000H.

2.5.1 Data Addressing Modes

8086/8088 provide a seven Data Addressing Modes:
1. Register Addressing
2. Immediate Addressing
3. Direct Addressing
4. Register Indirect Addressing
5. Base–Plus–Index Addressing
6. Register Relative Addressing
7. Base Relative–Plus–Index Addressing

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Register Addressing Mode

 Transfers a copy of a byte or word from the source register or memory location to the
destination register or memory location
 Use of registers to hold the data to be manipulated.
 Source and destination registers must have the same size
 Memory is not accessed when this addressing mode is executed
Example:
o MOV BX, DX ; copy the contents of DX into BX
o MOV ES, AX ; copy the contents of AX into ES
o ADD AL, BH ; add the contents of BH to contents of AL

Immediate Addressing Mode

 Transfers the source, an immediate byte or word of data, into the destination register or
memory location
 The source operand is a constant
 The operand comes immediately after the opcode. For this reason, this addressing mode
executes quickly
 Immediate addressing mode can be used to load information into any of the registers
except the segment registers and flag registers.

Example:
MOV AX, 2550H ; move 2550H into AX
MOV CX, 625 ; load the decimal value 625 into CX
MOV BL, 40H ; load 40H into BL

 The data must first be moved to a general-purpose register and then to the segment
register.
Example:
MOV AX, 2550H
MOV DS, AX
MOV DS, 0123H ; illegal instruction!

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Direct Addressing Mode

 Moves a byte or word between a memory location and a register.
 The data is in some memory location(s) and the address of the data in memory comes
immediately after the instruction. This address is the offset address.

Example:
MOV AX, [2400] ; move contents of DS:2400H into AX

 The physical address is calculated by combining the contents of offset location 2400
with DS

Example:
Find the physical address of the memory location and its contents after the execution of
the following, assuming that DS = 1512H.
MOV AL, 3BH
MOV [3518], AL
Solution:
 First 3BH is copied into AL,
 Then in line two, the contents of AL are moved to logical address DS:3518 which is
1512:3518.
 Shifting DS left and adding it to the offset gives the physical address of 18638H
(15120H + 3518H = 18638H).
 After the execution of the second instruction, the memory location with address 18638H
will contain the value 3BH.

Register Indirect Addressing Mode

 Transfers a byte or word between a register and a memory location addressed by an
index or base register
 The address of the memory location where the operand resides is held by a register
 The registers used for this purpose are SI, DI, and BX

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 They must be combined with DS in order to generate the 20-bit physical address.

Example:
MOV AX, [BX] ; moves into AX the contents of the memory location pointed to by
DS:BX, 1000:1234

 The physical address is calculated as

1000x10+1234=11234H

 The same rules apply when using register SI or DI.

Example:
MOV CL, [SI] ; move contents of DS:SI into CL
MOV [DI], AH ; move contents of AH into DS:DI

Example:
Assume that DS = 1120, SI = 2498, and AX = 17FE. Show the contents of memory
locations after the execution of
MOV [SI], AX ; move contents of AX into DS:SI

Solution:
 The contents of AX are moved into memory locations with logical address DS:SI and
DS:SI + 1;
 The physical address starts at DS (shifted left) + SI = 13698. According to the little
endian convention,
 Low address 13698H contains FE, the low byte,
 High address 13699H will contain 17, the high byte.

Base-Plus-Index Addressing Mode

 Transfers a byte or word between a register and the memory location addressed by a
base register (BP or BX) plus an index register (DI or SI).
 Combining based and indexed addressing modes. One base register and one index
register are used.
Examples:
MOV [BX+DI], CL ; move contents of CL into DS:BX+DI
 Physical Address = DSx10 + BX+DI

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CoSc-2043: Microprocessor and Assembly Language

MOV CH, [BX+SI] ; move contents of the DS:BX+SI into CH

 Physical Address = DSx10 + BX+SI

MOV AH, [BP+DI] ; move contents of the SS:BP+SI into AH

 Physical Address = SSx10 + BP+DI

MOV [BP+SI], AL ; move contents of AL into SS:BP+SI

 Physical Address = SSx10 + BP+SI

Register Relative Addressing Mode

 Moves a byte or word between a register and the memory location addressed by an
index or base register plus a displacement.
 The data in a segment of memory are addressed by adding the displacement to the
contents of a base or an index register (BP, BX, DI, or SI).
Examples:
MOV AX, [BX+4] ; move contents of DS:BX+4 into AX
 Physical Address = DSx10 + BX+4

MOV CH, [SI+5] ; move contents of the DS:SI+5 into CH

 Physical Address = DSx10 +SI+5

MOV AH, [DI+1] ; move contents of the DS:DI+1 into AH

 Physical Address = DSx10 + DI+1

MOV [BP+2], AL ; move contents of AL into SS:BP+2

 Physical Address = SSx10 + BP+2

Example:
Assume that DS = 4500, SS = 2000, BX = 2100, SI = 1486, DI = 8500, BP= 7814, and
AX = 2512. Show the exact physical memory location where AX is stored in each of
the following. All values are in hex.
1- MOV [BX+20], AX
2- MOV [SI+10], AX
3- MOV [DI+4], AX
4- MOV [BP+12], AX
Solution:
Physical Address = segment reg. x 10 + (offset reg.) + displacement

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CoSc-2043: Microprocessor and Assembly Language

1- DS:BX+20 location 47120 = (12) and 47121 = (25)

2- DS:SI+10 location 46496 = (12) and 46497 = (25 )
3- DS:DI+4 location 4D504 = (12) and 4D505 = (25)
4- SS:BP+12 location 27826 = (12) and 27827 = (25)

Base Relative-Plus-Index Addressing Mode

 The base relative-plus-index addressing mode is similar to the base-plus-index
addressing mode, but adds a displacement besides using a base register and an index
register to form the memory address.
 This type of addressing mode often addresses a two-dimensional array of memory data.
 The data in a segment of memory are addressed by adding the displacement to the
contents of a base and an index register (BP, BX, DI, or SI).
Examples:
MOV [BX+DI+1], AX ; move contents of AX into DS:BX+DI+1
 Physical Address = DSx10 + BX+DI+1H

MOV AX, [BX+SI+10] ; move contents of the DS:BX+SI+10 into AX

 Physical Address = DSx10 + BX+SI+10H

MOV AH, [BP+DI+3] ; move contents of the SS:BP+SI+3 into AH

 Physical Address = SSx10 + BP+DI+3H

MOV [BP+SI+6], AL ; move contents of AL into SS:BP+SI+6

 Physical Address = SSx10 + BP+SI+6

MOV AX, FILE[BX+DI] ; move contents of the DS:FILE+BX+DI into AX

 Physical Address = DSx10 + BX+DI+FILE

MOV LIST[BP+SI+4], DH ; move contents of DH into SS:LIST+BP+SI+4

 Physical Address = SSx10 +LIST+ BP+SI+4

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2.5.2 Program-Memory Addressing Modes

 Program memory-addressing modes, used with the JMP and CALL instructions.
 These three addressing forms are introduced in the next chapter using the JMP
instruction to illustrate their operation.

2.5.3 Stack-Memory Addressing Modes

 The stack plays an important role in all microprocessors.
 It holds data temporarily and stores return addresses for procedures.
 The stack memory is a LIFO (last-in, first-out) memory, which describes the way that
data are stored and removed from the stack.
 Data are placed onto the stack with a PUSH instruction and removed with a POP
instruction.
 The CALL instruction also uses the stack to hold the return address for procedures and
a RET (return) instruction to remove the return address from the stack.

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